TW201735363A - 奈米線半導體元件及其製造方法 - Google Patents

奈米線半導體元件及其製造方法 Download PDF

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TW201735363A
TW201735363A TW105127931A TW105127931A TW201735363A TW 201735363 A TW201735363 A TW 201735363A TW 105127931 A TW105127931 A TW 105127931A TW 105127931 A TW105127931 A TW 105127931A TW 201735363 A TW201735363 A TW 201735363A
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nanowire
substrate
source region
semiconductor device
layer
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TW105127931A
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肖德元
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上海新昇半導體科技有限公司
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Abstract

在本發明提供的奈米線半導體元件及其製造方法中,通過在PMOS源極區和NMOS源極區上分別形成高電洞遷移率的第一奈米線和高電子遷移率的第二奈米線,從而提高奈米線半導體元件的性能。

Description

奈米線半導體元件及其製造方法
本發明與半導體製造領域相關,特別是一種奈米線半導體元件及其製造方法。
在過去的四十年裡,微電子工業發展一直遵循著摩爾定律。為了跟上摩爾定律的脚步,人們不斷地縮小半導體元件的特徵尺寸。當前,半導體元件的物理尺寸已到極限,通過縮小物理尺寸來提高性能已經非常困難。
為此,業內設計開發了各種新型的半導體元件以適應市場需求,例如奈米線場效應電晶體(Nanowire Field-Effect Transistor,簡稱NWFET)。NWFET的結構中具有一維奈米線通道,由於量子限制效應,通道內載子遠離表面分佈,故載子輸運受表面散射和通道橫向電場影響小,可以獲得較高的遷移率。另一方面,NWFET具有較小尺寸的通道並且通常採用圍閘結構,閘極可以從多個方向對所述通道進行調製,從而增強閘極的調控能力,改善閾值特性。因此NWFET可以很好地抑制短通道效應,使場效應電晶體的尺寸得以進一步縮小。同時,由於NWFET利用自身的細通道和圍閘結構改善了閘極調控能力,因此緩解了減薄閘介電層厚度的需 求,進而減小閘極的漏電流。基於以上優勢,NWFET已經越來越受到科技研發人員的關注。
然而,在實際的製造和使用過程中發現,現有的奈米線半導體元件的性能比較差,還不能滿足市場要求。如何進一步提升奈米線半導體元件的性能仍是本領域技術人員亟待解決的技術問題。
本發明的目的在於提供一種奈米線半導體元件及其製造方法,以解決現有技術中奈米線半導體元件的性能差的問題。
為解決上述問題,本發明提供一種奈米線半導體元件的製造方法,所述奈米線半導體元件的製造方法包括:提供一基板,所述基板包括NMOS源極區和PMOS源極區;進行第一次選擇性磊晶生長製程,以在所述NMOS源極區中形成多邊形結構的第一奈米線;進行第二次選擇性磊晶生長製程,以在所述PMOS源極區中形成多邊形結構的第二奈米線;通過蝕刻製程去除部分基板,使得所述第一奈米線懸空於所述基板的上方;對所述第一奈米線進行氧化退火處理;以及在所述基板、第一奈米線和第二奈米線上依次形成閘介電層和閘極層。 可選的,在所述的奈米線半導體元件的製造方法中,在進行第一次選擇性磊晶生長製程,以在所述NMOS源極區中形成多邊形結構的第一 奈米線之前,提供一基板之後,還包括:在所述基板上形成隔離結構。
可選的,在所述的奈米線半導體元件的製造方法中,進行第一次選擇性磊晶生長製程,以在所述NMOS源極區中形成多邊形結構的第一奈米線的過程包括:在所述基板和隔離結構上形成圖形化的第一硬幕罩層,所述第一硬幕罩層中具有第一通孔,所述第一通孔的底部暴露出部分NMOS源極區的基板;通過第一次選擇性磊晶生長製程在所述第一通孔暴露出的基板上形成多邊形結構的第一奈米線;以及去除所述第一硬幕罩層。
可選的,在所述的奈米線半導體元件的製造方法中,進行第二次選擇性磊晶生長製程,以在所述PMOS源極區中形成多邊形結構的第二奈米線的過程包括: 在所述基板、隔離結構以及第一奈米線上形成圖形化的第二硬幕罩層,所述第二硬幕罩層中具有第二通孔,所述第二通孔的底部暴露出部分PMOS源極區的基板;對所述第二通孔暴露出的基板進行濕式蝕刻以形成凹陷;通過第二次選擇性磊晶生長製程在所述凹陷上形成多邊形結構的第二奈米線;以及去除所述第二硬幕罩層。
可選的,在所述的奈米線半導體元件的製造方法中,對所述第一奈米線進行氧化退火處理的過程包括: 對所述第一奈米線進行熱氧化;通過濕式蝕刻製程去除所述第一奈米線表面的氧化層;以及在氫氣環境中對所述第一奈米線的進行高溫退火。
可選的,在所述的奈米線半導體元件的製造方法中,所述第一奈米線和第二奈米線採用的材料均為III-V族半導體材料。
可選的,在所述的奈米線半導體元件的製造方法中,所述第一奈米線採用的材料為鍺,所述第二奈米線採用的材料為銦鎵砷。
本發明還提供一種奈米線半導體元件,所述奈米線半導體元件包括:基板,所述基板包括PMOS源極區和NMOS源極區;形成於所述PMOS源極區上的第一奈米線;形成於所述NMOS源極區上的第二奈米線;完全包圍所述第一奈米線並部分包圍所述第二奈米線的閘介電層和閘極層。
可選的,在所述的奈米線半導體元件中,所述第一奈米線的長度範圍在2奈米到50奈米之間,所述第一奈米線的直徑範圍在2奈米到5奈米之間。
可選的,在所述的奈米線半導體元件中,所述第一奈米線為鍺奈米線,所述鍺奈米線的截面形狀為圓形、橢圓形或棱形。
所述第二奈米線為銦鎵砷奈米線,所述第二奈米線的截面形狀為多邊形。
可選的,在所述的奈米線半導體元件中,所述第一奈米線中鍺的含量範圍在65%到100%之間。
可選的,在所述的奈米線半導體元件中,所述閘介電層為高 介電係數介電層,所述閘介電層採用的材料為Al2O3或TiSiOx; 所述閘極層為金屬層,所述閘極層採用的材料為TiN、NiAu或CrAu中的任意一種。
綜上所述,在本發明提供的奈米線半導體元件及其製造方法中,通過在PMOS源極區和NMOS源極區上分別形成高電洞遷移率的第一奈米線和高電子遷移率的第二奈米線,從而提高奈米線半導體元件的性能。
200‧‧‧奈米線半導體元件
210‧‧‧基板
210a‧‧‧PMOS源極區
210b‧‧‧NMOS源極區
220‧‧‧隔離結構
230‧‧‧第一硬幕罩層
230a‧‧‧第一通孔
240‧‧‧第一奈米線
250‧‧‧第二硬幕罩層
250a‧‧‧第二通孔
260‧‧‧第二奈米線
270‧‧‧閘介電層
280‧‧‧閘極層
第1圖是本發明實施例的奈米線半導體元件的製作方法的流程圖;第2圖至第12圖是本發明實施例的奈米線半導體元件的製作過程的結構示意圖。
以下結合附圖和具體實施例對本發明提出的奈米線半導體元件及其製造方法作進一步詳細說明。根據下面說明和權利要求書,本發明的優點和特徵將更清楚。需說明的是,附圖均採用非常簡化的形式且均使用非精准的比例,僅用以方便、明晰地輔助說明本發明實施例的目的。
請參考第1圖,其為本發明實施例的奈米線半導體元件的製作方法的流程圖。如第1圖所示,所述奈米線半導體元件的製造方法包括:S10:提供一基板,所述基板包括NMOS源極區和PMOS源極區;S11:進行第一次選擇性磊晶生長製程,以在所述NMOS源極區上形成多邊形結構的第一奈米線;S12:進行第二次選擇性磊晶生長製程,以在所述PMOS源極區上形成多邊形結構的第二奈米線; S13:通過蝕刻製程去除部分基板,使得所述第一奈米線懸空於所述基板的上方;S14:對所述第一奈米線進行氧化退火處理;S15:在所述基板、第一奈米線和第二奈米線上依次形成閘介電層和閘極層280。
第2~12圖為本發明實施例的奈米線半導體元件的製作過程的結構示意圖,請參考第1圖所示,並結合第2~12圖,詳細說明本發明提出所述奈米線半導體元件的製作方法:首先,如第2圖所示,提供一基板210,所述基板210包括圖形化的NMOS源極區210b和PMOS源極區210a。
接著,如第3圖所示,在所述基板210上形成氧化物層並採用化學機械研磨去除多餘的氧化物層,以形成隔離結構220,所述隔離結構220的頂部與所述基板210的頂部大致齊平。
然後,進行第一次選擇性磊晶生長製程,以在所述PMOS源極區210a上形成多邊形結構的第一奈米線240。形成第一奈米線240的具體過程包括:步驟一:在所述基板210和隔離結構220上形成圖形化的第一硬幕罩層230,所述第一硬幕罩層230中具有第一通孔230a,所述第一通孔230a的底部暴露出部分PMOS源極區210a的基板210;步驟二:通過第一次選擇性磊晶生長製程在所述第一通孔230a暴露出的基板210上形成多邊形結構的第一奈米線240;步驟三:去除所述第一硬幕罩層230。
如第4圖所示,執行步驟一之後,在所述基板210和隔離結構220的上面形成有圖形化的第一硬幕罩層230,位於所述PMOS源極區210a的部分第一硬幕罩層230被蝕刻掉了,形成了第一通孔230a,所述第一通孔230a的底部暴露出所述基板210。
如第5圖所示,執行步驟二之後,形成了多邊形結構的第一奈米線240,所述第一奈米線240與所述PMOS源極區210a的基板210相接觸。
之後,進行第二次選擇性磊晶生長製程,以在所述NMOS源極區210b上形成多邊形結構的第二奈米線260。形成第二奈米線260的具體過程包括:步驟一:在所述基板210、隔離結構220以及第一奈米線240的上面形成圖形化的第二硬幕罩層250,所述第二硬幕罩層250中具有第二通孔250a,所述第二通孔250a的底部暴露出部分NMOS源極區210b的基板210;步驟二:對所述第二通孔250a暴露出的基板210進行濕式蝕刻以形成凹陷212;步驟三:通過第二次選擇性磊晶生長製程在所述凹陷212上形成多邊形結構的第二奈米線260;步驟四:去除所述第二硬幕罩層250。
如第6圖所示,執行步驟一之後,在所述基板210、隔離結構220以及第一奈米線240的上面形成了圖形化的第二硬幕罩層250,位於所述NMOS源極區210b的部分第二硬幕罩層250被蝕刻掉了,形成了第二通孔250a,所述第二通孔250a的底部暴露出所述基板210。
如第7圖所示,對所述第二通孔250a暴露出的基板210進行蝕 刻之後,所述基板210中形成了凹陷212。優選的,所述凹陷212的截面形狀為V型,所述蝕刻製程採用的蝕刻液為四甲基氫氧化銨(TMAH)或KOH。
如第8圖所示,執行步驟三之後,在所述V型凹陷212上形成了多邊形結構的第二奈米線260,所述第二奈米線260所述第二奈米線260與所述NMOS源極區210b的基板210相接觸。
之後,通過第二次蝕刻製程去除部分隔離結構220和基板210,使得所述第一奈米線240懸空於所述基板210的上方。所述第二次蝕刻製程採用的蝕刻液為四甲基氫氧化銨(TMAH)。
如第9圖所示,第二次蝕刻製程之後,所述第一奈米線240懸空於所述基板210的上方,即所述第一奈米線240與所述基板210不接觸。
此後,對所述第一奈米線240進行氧化退火處理。對所述第一奈米線240進行氧化退火處理的具體過程包括:步驟一:對所述第一奈米線240進行熱氧化;步驟二:通過濕式蝕刻製程去除所述第一奈米線240表面的氧化層;步驟三:在氫氣環境中,對所述第一奈米線240的進行高溫退火。
如第10圖所示,在氧化退火處理過程中,鍺矽進行氧化濃縮,使得所述第一奈米線240的鍺濃縮形成鍺奈米線,氧化和濕式蝕刻使得所述鍺奈米線具有更光滑的表面,氧化退火處理之後,所述第一奈米線240(即鍺奈米線)的截面形狀由多邊形變為圓形、橢圓形或棱形。
最後,在所述基板210、第一奈米線240和第二奈米線260上依次形成閘介電層270和閘極層280。
如第11圖所示,在所述基板210、隔離結構220、第一奈米線 240以及第二奈米線260上形成閘介電層270之後,所述閘介電層270覆蓋在所述基板210、隔離結構220、第一奈米線240以及第二奈米線260的表面上。
如第12圖所示,在所述閘介電層270上形成閘極層280之後,所述閘極層280完全包圍所述第一奈米線240,同時包圍所述第二奈米線260大部分的表面。
所述閘介電層270的形成製程可以是原子層沉積(ALD)製程、金屬有機化合物化學氣相沉積(MOCVD)製程或化學氣相沉積(CVD)製程或其他現有的製程技術。所述閘極層280的形成製程可以是原子層沉積(ALD)製程、金屬有機化合物化學氣相沉積(MOCVD)製程或分子束磊晶(MBE)製程或其他現有的製程技術。
至此,形成了所述奈米線半導體元件200。所述奈米線半導體元件200的PMOS源極區210a上形成有鍺奈米線,NMOS源極區210b上形成有銦鎵砷奈米線。由於,所述鍺奈米線(Ge)具有較高的電洞遷移率,所述銦鎵砷奈米線(InGaAs)具有較高的電子遷移率,因此所述奈米線半導體元件200的性能得以提高。
對奈米線半導體元件而言,奈米線的製作是其關鍵製程,直接關係到奈米線半導體元件的性能。現有的鍺奈米線的製作過程通常包括:首先,形成具有矽核的奈米線;接著,通過氧化退火處理,使鍺向中心聚集以形成鍺奈米線。然而,由於內核中矽的含量較高,因此提高鍺奈米線中鍺含量的製程難度較大。所形成的奈米線半導體元件中,奈米線的鍺含量較低,對半導體元件的性能造成了不利影響。
本實施例中,鍺奈米線在製作過程中不需要先形成具有矽核 的奈米線,直接利用鍺進行磊晶生長,後續氧化退火處理後所形成的鍺奈米線具有較高的鍺含量。
實驗證明,所述奈米線半導體元件200中第一奈米線240的鍺含量在65%到100%之間,明顯高於現有的鍺奈米線的鍺含量(通常在50%以下)。由此可見,採用所述奈米線半導體元件的製造方法製作的半導體元件,能夠有效地提升元件性能。
相應的,本發明還提供一種奈米線半導體元件。請參考第12圖,其為本發明實施例的奈米線半導體元件的結構示意圖。如第12圖所示,所述奈米線半導體元件包括:基板210,所述基板210包括PMOS源極區210a和NMOS源極區210b;:形成於所述PMOS源極區210a上的第一奈米線240;形成於所述NMOS源極區210b上的第二奈米線260;完全包圍所述第一奈米線240並部分包圍所述第二奈米線260的閘介電層270和閘極層280。
具體的,所述第一奈米線240和第二奈米線260分別形成於所述基板210的PMOS源極區210a和NMOS源極區210b,所述閘介電層270形成於所述基板210、第一奈米線240和第二奈米線260上,所述閘極層280形成於所述閘介電層270上。所述第一奈米線240被所述閘介電層270與閘極層280完全包圍,所述第二奈米線260中位於隔離結構220上方的區域也被所述閘介電層270與閘極層280包圍。
其中,所述閘介電層270為高介電係數(HIGH k)介電層。例如,所述閘介電層270的材料為Al2O3或TiSiOx。採用高電係數材料製作閘介電層270,能夠提高奈米線半導體元件的電學性能。所述閘極層280為金屬電極層,所述閘極層280採用的材料為TiN、NiAu或CrAu中的一種。
所述第一奈米線240和第二奈米線260採用的材料為III-V族半導體材料,所述III-V族半導體材料包括矽、矽鍺、碳化矽或鍺。優選的,所述第一奈米線240採用的材料為鍺(Ge),所述第二奈米線260採用的材料為銦鎵砷(InGaAs)。
所述第一奈米線240的截面形狀為圓形,所述第二奈米線260的截面形狀為多邊形。優選的,所述第二奈米線260的截面形狀為邊長數大於或等於五的多邊形。
優選的,所述第一奈米線240的長度範圍在2奈米到50奈米之間,所述第一奈米線240的直徑範圍在2奈米到5奈米之間。
綜上可見,在本發明實施例提供的奈米線半導體元件及其製造方法中,通過在PMOS源極區和NMOS源極區上分別形成高電洞遷移率的第一奈米線和高電子遷移率的第二奈米線,從而提高奈米線半導體元件的性能。
上述僅為本發明的優選實施例而已,並不對本發明起到任何限制作用。任何所屬技術領域的技術人員,在不脫離本發明的技術方案的範圍內,對本發明揭露的技術方案和技術內容做任何形式的等同替換或修改等變動,均屬未脫離本發明的技術方案的內容,仍屬於本發明的保護範圍之內。
S10~S15‧‧‧製程步驟

Claims (12)

  1. 一種奈米線半導體元件的製造方法,包括:提供一基板,所述基板包括NMOS源極區和PMOS源極區;進行第一次選擇性磊晶生長製程,以在所述NMOS源極區中形成多邊形結構的第一奈米線;進行第二次選擇性磊晶生長製程,以在所述PMOS源極區中形成多邊形結構的第二奈米線;通過蝕刻製程去除部分基板,使得所述第一奈米線懸空於所述基板的上方;對所述第一奈米線進行氧化退火處理;以及在所述基板、第一奈米線和第二奈米線上依次形成閘介電層和閘極層。
  2. 如權利要求1所述的奈米線半導體元件的製造方法,其中在進行第一次選擇性磊晶生長製程,以在所述NMOS源極區中形成多邊形結構的第一奈米線之前,提供一基板之後,還包括:在所述基板上形成隔離結構。
  3. 如權利要求2所述的奈米線半導體元件的製造方法,其中進行第一次選擇性磊晶生長製程,以在所述NMOS源極區中形成多邊形結構的第一奈米線的過程包括:在所述基板和隔離結構上形成圖形化的第一硬幕罩層,所述第一硬幕罩層中具有第一通孔,所述第一通孔的底部暴露出部分NMOS源極區的基板;通過第一次選擇性磊晶生長製程在所述第一通孔暴露出的基板上形成多邊形結構的第一奈米線;以及去除所述第一硬幕罩層。
  4. 如權利要求2所述的奈米線半導體元件的製造方法,其中進行第二次選擇性磊晶生長製程,以在所述PMOS源極區中形成多邊形結構的第二奈米線的過程包括:在所述基板、隔離結構以及第一奈米線上形成圖形化的第二硬幕罩 層,所述第二硬幕罩層中具有第二通孔,所述第二通孔的底部暴露出部分PMOS源極區的基板;對所述第二通孔暴露出的基板進行濕式蝕刻以形成凹陷;通過第二次選擇性磊晶生長製程在所述凹陷上形成多邊形結構的第二奈米線;以及去除所述第二硬幕罩層。
  5. 如權利要求1所述的奈米線半導體元件的製造方法,其中對所述第一奈米線進行氧化退火處理的過程包括:對所述第一奈米線進行熱氧化;通過濕式蝕刻製程去除所述第一奈米線表面的氧化層;以及在氫氣環境中對所述第一奈米線的進行高溫退火。
  6. 如權利要求1所述的奈米線半導體元件的製造方法,其中所述第一奈米線和第二奈米線採用的材料均為III-V族半導體材料。
  7. 如權利要求6所述的奈米線半導體元件的製造方法,其中所述第一奈米線採用的材料為鍺,所述第二奈米線採用的材料為銦鎵砷。
  8. 一種奈米線半導體元件,包括:基板,所述基板包括PMOS源極區和NMOS源極區;形成於所述PMOS源極區上的第一奈米線;形成於所述NMOS源極區上的第二奈米線;完全包圍所述第一奈米線並部分包圍所述第二奈米線的閘介電層和閘極層。
  9. 如權利要求8所述的奈米線半導體元件,其中所述第一奈米線的長度範圍在2奈米到50奈米之間,所述第一奈米線的直徑範圍在2奈米到5奈米之間。
  10. 如權利要求8所述的奈米線半導體元件,其中所述第一奈米線為鍺奈米線,所述鍺奈米線的截面形狀為圓形、橢圓形或棱形;所述第二奈米線為銦鎵砷奈米線,所述第二奈米線的截面形狀為多邊形。
  11. 如權利要求10所述的奈米線半導體元件,其中所述第一奈米線中鍺的含量範圍在65%到100%之間。
  12. 如權利要求8所述的奈米線半導體元件,其中所述閘介電層為高介電係數介電層,所述閘介電層採用的材料為Al2O3或TiSiOx;所述閘極層為金屬層,所述閘極層採用的材料為TiN、NiAu或CrAu中的任意一種。
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