TW201724452A - 具有對位標記的積體電路晶粒及其形成方法 - Google Patents

具有對位標記的積體電路晶粒及其形成方法 Download PDF

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Publication number
TW201724452A
TW201724452A TW105129728A TW105129728A TW201724452A TW 201724452 A TW201724452 A TW 201724452A TW 105129728 A TW105129728 A TW 105129728A TW 105129728 A TW105129728 A TW 105129728A TW 201724452 A TW201724452 A TW 201724452A
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Taiwan
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integrated circuit
alignment mark
die
circuit die
layer
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TW105129728A
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English (en)
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陳憲偉
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台灣積體電路製造股份有限公司
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Publication of TW201724452A publication Critical patent/TW201724452A/zh

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Abstract

一種具有對位標記的積體電路晶粒及其形成方法。方法包括在基板上形成元件。在基板和元件上方形成多個接觸墊。與形成多個接觸墊同時，在基板和元件上方形成一個或多個對位標記。

Description

具有對位標記的積體電路晶粒及其形成方法
本發明的實施例是關於一種積體電路元件，且特別是有關於一種具有對位標記的積體電路晶粒及其形成方法。
半導體元件用於許多電子應用，諸如個人電腦、手機、數位相機和其他電子設備。通常，藉由在半導體基板上方相繼沉積絕緣層或介電層、導電層和半導體材料層，並使用微影蝕刻圖案化各個材料層以在材料層上形成電路構件和元件來製造半導體元件。通常，在單個半導體晶圓上製造數十或數百個積體電路。藉由沿著切割線切割積體電路將單個晶粒單一化。然後，將單個的晶粒單獨封裝在多晶片模組中，或封裝在其他類型的封裝中。
由於許多電子元件(例如，電晶體、二極體、電阻、電容等)的積體密度的不斷提高，半導體工業經歷了快速發展。大體上，該積體密度的改進源自最小特徵尺寸的不斷減小(例如，縮小半導體製程節點至小於20 nm節點)，其允許將更多的元件整合到給定的區域中。由於最近對微型化、更高速度和更大頻寬以及更低功耗和延遲的需求不斷增長，因此亟需用於半導體晶粒的更小和更具創造性的封裝技術。
隨著半導體技術進一步發展，諸如三維積體電路(3DIC)的堆疊式半導體元件出現，並成為進一步減小半導體元件的物理尺寸的有效替代物。在堆疊式半導體元件中，在不同半導體晶圓上製造諸如邏輯、記憶體、處理器電路等的主動電路。可將兩個或多個半導體晶圓安裝或堆疊在另一個半導體晶圓的頂部以進一步減小半導體元件的外觀尺寸。堆疊式封裝(POP)元件是一種三維積體電路，其中晶粒被封裝並接著與另一個或多個封裝的晶粒一起被封裝。
一種方法，包括：在基板上形成元件；在所述基板和所述元件上方形成多個接觸墊；以及與形成所述多個接觸墊同時，在所述基板和所述元件上方形成一個或多個對位標記。
以下公開內容提供了許多不同的實施例或實例以實現本發明的不同特徵。下面將描述元件和佈置的特定實例以簡化本發明。當然這些僅僅是實例並不旨在限定本發明。例如，在下面的描述中第一特徵在第二特徵上方或者在第二特徵上的形成可以包括第一特徵和第二特徵以直接接觸方式形成的實施例，也可以包括額外的特徵可以形成在第一和第二特徵之間，使得第一特徵和第二特徵可以不直接接觸的實施例。此外，本發明可以在各實施例中重複參考標號和/或字元。這種重複僅是為了簡明和清楚，其自身並不表示所論述的各個實施例和/或配置之間的關係。
而且，為便於描述，在此可以使用諸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空間相對術語，以描述如圖所示的一個元件或特徵與另一個（或另一些）元件或特徵的關係。除了圖中所示的方位外，空間相對術語旨在包括元件在使用或操作中的不同方位。裝置可以以其他方式定向（旋轉90度或在其他方位上），而本文使用的空間相對描述符可以同樣地作相應的解釋。
在具體地討論繪示出的實施例之前，一般地討論一些實施例的某些有利特徵和方面。下面描述具有對位標記的各個積體電路晶粒以及形成這種積體電路晶粒的方法。此外，下面描述使用積體電路晶粒形成積體電路封裝的方法。藉由形成具有一個或多個對位標記的積體電路晶粒，在形成積體電路封裝時可減少或避免積體電路晶粒的不期望的偏移或旋轉。而且，可減少或避免由於未對位所致的積體電路晶粒的損壞。
圖1A至圖4B是根據一些實施例的製造具有對位標記的積體電路晶粒期間的各個製程步驟的俯視圖和剖面圖，其中，“A”圖代表俯視圖且“B”圖代表沿著相應的“A”圖的B-B’線截取的剖面圖。
參考圖1A以及1B，其繪示出藉由切割線(scribe lines，亦稱為dicing lines或dicing streets)103隔開的具有晶粒區101的工件100的部分。如下文更詳細地描述的，將沿著切割線103切割工件100以形成單個的積體電路晶粒(諸如圖5中繪示出的積體電路晶粒500)。在一些實施例中，工件100包括基板105，位於基板105上的一個或多個主動和/或被動元件111以及位於基板105上方的一個或多個金屬化層113。在一些實施例中，基板105可由矽形成，儘管它還可由諸如矽、鍺、鎵、砷的其他第III族、第IV族和/或第V族元素及其組合形成。基板105還可為絕緣體上有矽(SOI)的形式。絕緣體上有矽基板可包括在絕緣體層(例如，埋入式氧化物等)上方形成的半導體材料層(例如，矽、鍺等)，所述半導體材料層在矽基板上形成。此外，可使用的其他基板包括多層基板、梯度(gradient)基板、混合定向(hybrid orientation)基板、其任意組合等。在其他實施例中，基板105可包括諸如氧化矽、氧化鋁等的介電材料或其組合。
在一些實施例中，一個或多個主動和/或被動元件111(由圖1B中的單個電晶體表示)可包括諸如電晶體、電容、電阻、二極體、光二極體、熔斷器等的各種n-型金屬氧化物半導體(NMOS)和/或p-型金屬氧化物半導體(PMOS)元件。在一些實施例中，積體電路晶粒可為分離式半導體元件晶片(有時稱為表面安裝元件(SMD)或整合型被動元件(IPD))。在這種實施例中，基板105可包括諸如二階電路(RLC circuit)、電容、電感、變壓器、平衡-不平衡轉換器、微波線、共面波導管等的各種元件，並且可實質上沒有主動元件。
一個或多個金屬化層113可包括在基板105上方形成的層間介電層(ILD)/金屬間介電層(IMD)。例如，可藉由諸如旋轉塗佈方法、化學氣相沉積(CVD)、電漿增強型化學氣相沉積(PECVD)等或其組合的本領域已知的任何合適的方法，由諸如磷矽酸鹽玻璃(PSG)、硼磷矽酸鹽玻璃(BPSG)、氟矽玻璃(FSG)、SiOxCy、旋塗玻璃、旋塗聚合物、碳化矽材料、其混合物、其複合物、其組合等的低介電係數介電材料形成層間介電層/金屬間介電層。在一些實施例中，例如，可使用鑲嵌製程、雙重鑲嵌製程等在層間介電層/金屬間介電層中形成內連線。在一些實施例中，內連線可包括銅、銅合金、銀、金、鎢、鉭、鋁等。在一些實施例中，內連線可在基板105上形成的一個或多個主動和/或被動元件111之間提供電性連接。
進一步參考圖1A以及圖1B，在一些實施例中，晶粒區101的俯視圖及隨之在切割工件100之後形成的積體電路晶粒的俯視圖可在旋轉90º、180º和/或270º時幾何對稱。然而，晶粒區101及隨之在切割工件100之後形成的積體電路晶粒在旋轉90º、180º和/或270º時在功能上可不對稱。這種積體電路晶粒的不對稱性可由積體電路晶粒中的各個主動和/或被動元件的不對稱排列所致。因此，可在每個積體電路晶粒上形成一個或多個對位標記以識別期望的積體電路晶粒的方向。
在一些實施例中，在一個或多個金屬化層113上方形成接觸墊107和對位標記109。可藉由一個或多個金屬化層113將接觸墊107電性連接至一個或多個主動和/或被動元件111，同時可將對位標記109與一個或多個主動和/或被動元件111電性絕緣。在一些實施例中，接觸墊107和對位標記109可包括諸如鋁、銅、鎢、銀、金等的導電材料或其組合。在一些實施例中，例如，可使用物理氣相沉積(PVD)、原子層沉積(ALD)、電化學鍍、無電電鍍等或其組合在基板105和一個或多個主動和/或被動元件111上方形成導電材料。隨後，將導電材料圖案化以形成接觸墊107和對位標記109。因此，接觸墊107和對位標記109可具有相同厚度。在一些實施例中，可使用微影蝕刻技術將導電材料圖案化。通常，微影蝕刻技術包括沉積光阻材料(未繪示出)，隨後照射(曝光)和顯影光阻材料以去除光阻材料的部分。剩餘的光阻材料保護諸如接觸墊107和對位標記109的導電材料的下層材料免受諸如蝕刻的隨後的製程步驟的影響。可將諸如反應性離子蝕刻(RIE)或其他乾式蝕刻、等向性或非等向性濕式蝕刻的適當的蝕刻製程或任何其他適當的蝕刻或圖案化製程應用於導電材料以去除導電材料的暴露的部分並且形成接觸墊107和對位標記109。在導電材料為鋁的一些實施例中，可使用80%磷酸、5%硝酸、5%乙酸和10%去離子水(DI)的混合物蝕刻導電材料。隨後，例如，可使用灰化製程和隨後的濕式清潔製程去除光阻材料。如下面更詳細地描述的，在接觸墊107上將形成連接結構。
在繪示出的實施例中，接觸墊107的俯視形狀為矩形，且對位標記109的俯視形狀為L形多邊形。然而，在其他實施例中，接觸墊107的俯視形狀可為圓形、橢圓形或諸如三角形、正方形的多邊形等，且對位標記109的俯視形狀可為圓形、橢圓形或諸如三角形、正方形、矩形的多邊形等。在一些實施例中，接觸墊107和對位標記109的俯視形狀可能相似。在其他實施例中，接觸墊107和對位標記109的俯視形狀可能不同。
參考圖2A以及圖2B，在基板105、接觸墊107和對位標記109上方形成保護層201。在一些實施例中，保護層201可包括諸如聚苯並惡唑(PBO)、聚醯亞胺(PI)、苯並環丁烯(BCB)等的可光圖案化介電材料的一個或多個層，並且可使用旋轉塗佈製程等形成。可使用與光阻材料類似的微影蝕刻方法將這種可光圖案化介電材料圖案化。在其他實施例中，保護層201可包括諸如氮化矽、氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜磷矽酸鹽玻璃(BPSG)等的非可光圖案化介電材料的一個或多個層，並且可使用化學氣相沉積(CVD)、物理氣相沉積、原子層沉積、旋轉塗佈製程等或其組合形成保護層201。
隨後，在保護層201中形成開口203以暴露接觸墊107。在一些實施例中，其中，保護層201由可光圖案化介電材料形成，可使用與光阻材料類似的微影蝕刻方法將保護層201圖案化。在其他實施例中，其中，保護層201由非可光圖案化介電材料形成，在保護層201上方形成光阻材料(未繪示出)。隨後，照射(曝光)和顯影光阻材料以去除光阻材料的部分。隨後，例如，使用適當的蝕刻製程去除保護層201的暴露部分以形成開口。在保護層201由氧化矽形成的一些實施例中，例如使用緩衝的氫氟酸(HF)將保護層201蝕刻。在保護層201由氮化矽形成的其他實施例中，例如使用熱磷酸(H3 PO4 )將保護層201蝕刻。隨後，例如可使用灰化製程和隨後的濕式清潔製程將光阻材料去除。
參考圖3A以及圖3B，在一些實施例中，在保護層201上以及在開口203的底部和側壁中形成種子層301。種子層301可包括銅、鈦、鎳、金等或其組合，並且可使用電化學鍍製程、原子層沉積、物理氣相沉積、濺鍍等或其組合形成種子層301。在一些實施例中，在種子層301上方形成犧牲層303。在犧牲層303中形成開口305以暴露設置在開口203中的種子層301的部分。在犧牲層303包括光阻材料的一些實施例中，可使用適當的微影蝕刻方法將犧牲層303圖案化。如下文更詳細描述的，將在開口203和305中形成連接結構。
參考圖4A以及圖4B，在開口203和305中形成連接結構401。在一些實施例中，使用電化學鍍製程、化學鍍製程、原子層沉積、物理氣相沉積等或其組合以諸如銅、鋁、鎳、金、銀、鈀等或其組合的導電材料填充開口203和305以形成導電柱401A。在一些實施例中，連接結構401還可包括覆蓋層401B，覆蓋層401B可形成在導電柱401A的頂部。覆蓋層401B可包括焊料、鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金等或其組合並且可藉由鍍製程等形成。在完成連接結構401的形成之後，將犧牲層303去除。在一些實施例中，其中，犧牲層303包括光阻材料，例如，可使用灰化製程和隨後的濕式清潔製程將犧牲層303去除。隨後，例如，使用適當的蝕刻製程將種子層301的暴露部分去除。種子層301的剩餘的部分還可稱為球底金屬層(UBM)301。在其他實施例中，連接結構401可為焊球、可控塌陷晶片連接(C4)凸塊、球柵陣列(BGA)球、微凸塊、化學鍍鎳鈀-浸金技術(ENEPIG)形成的凸塊等。在連接結構401為焊料凸塊的一些實施例中，可藉由諸如蒸發、電鍍、印刷、焊料轉移、植球等的常用方法首先形成焊料層來形成連接結構401。一旦形成焊料層，可實施迴焊以將材料成型為期望的凸塊形狀。
在繪示出的實施例中，連接結構401的俯視形狀為圓形。然而，在其他實施例中，連接結構401的俯視形狀可為橢圓形或諸如三角形、正方形的多邊形等。此外，在繪示出的實施例中，晶粒區101包括二十個接觸墊(諸如接觸墊107)、二十個連接結構(諸如連接結構401)、一個對位標記(諸如對位標記109)和一個保護層(諸如保護層201)。本領域具通常知識者將知，保護層、接觸墊、對位標記和連接結構的數量僅提供用於說明的目的而並非限制本發明的實施例的範圍。在其他實施例中，取決於隨後形成的積體電路晶粒的設計要求，晶粒區101可包括適當數量的保護層、接觸墊、對位標記和連接結構。
進一步參考圖4A以及圖4B，沿著切割線103將工件100切割以形成單個的積體電路晶粒。在一些實施例中，例如可使用蝕刻、切割、雷射剝蝕等或其組合將工件100切割。隨後，為了進一步加工，可測試各個積體電路晶粒以識別已知良好晶粒(KGD)。如下面更詳細地描述的，積體電路晶粒將用於形成積體電路封裝。
圖5是根據一些實施例的在切割工件100之後形成的積體電路晶粒500的俯視圖。在繪示出的實施例中，對位標記109的俯視形狀為L形多邊形。僅為了例示的目的，提供了圖5中繪示出的對位標記109的特定方向。在其他實施例中，當以俯視觀察時，可將對位標記109旋轉期望的角度。在一些實施例中，積體電路晶粒500的第一側面可具有約0.5 mm和約3.0 mm之間的第一寬度W1 ，且積體電路晶粒500的第二側面可具有約0.5 um和約3.0 um之間的第二寬度W2 。在一些實施例中，連接結構401可具有約35 um和約55 um之間的第三寬度W3 。在一些實施例中，對位標記109的第一最長側面(平行於積體電路晶粒500的第一側面)可具有約W1 /20和約W1 /10之間的長度L1 ，對位標記109的第二最長側面(平行於積體電路晶粒500的第二側面)可具有約W2 /20和約W2 /10之間的長度L2 ，對位標記109的第一最短側面(平行於積體電路晶粒500的第一側面)可具有約L1 /2和約L1 /3之間的長度L3 ，對位標記109的第二最短側面(平行於積體電路晶粒500的第二側面)可具有約L2 /2和約L2 /3之間的長度L4 。在一些實施例中，對位標記109和最近的連接結構401之間的距離L5 可大於或等於W3 /2。
圖6是根據一些實施例的積體電路晶粒600的俯視圖。在一些實施例中，可使用與上述參考圖1A至圖4B描述的材料和方法類似的材料和方法形成積體電路晶粒600，其中，使用類似的標號標記類似的元件，並且此處不重複描述。在一些實施例中，可在積體電路晶粒600的角形成對位標記601，並且以俯視觀察，對位標記601可具有三角形狀。在一些實施例中，可使用與上述參考圖1A至圖1B描述的對位標記109的材料和方法類似的材料和方法形成對位標記601，並且此處不重複描述。僅為了例示的目的，提供圖6中繪示出的對位標記601的特定方向。在其他實施例中，當以俯視觀察時，可將對位標記601旋轉期望的角度。在一些實施例中，積體電路晶粒600的第一側面可具有約0.5 mm和約3 mm之間的第一寬度W1 ，且積體電路晶粒600的第二側面可具有約0.5 mm和約3 mm之間的第二寬度W2 。在一些實施例中，連接結構401可具有約35 um和約55 um之間的第三寬度W3 。在一些實施例中，對位標記601的第一側面(平行於積體電路晶粒600的第一側面)可具有約W1 /20和約W1 /10之間的長度L6 ，且對位標記601的第二側面(平行於積體電路晶粒600的第二側面)可具有約W2 /20和約W2 /10之間的長度L7 。在一些實施例中，對位標記601和最近的連接結構401之間的距離L8 可大於或等於W3 /2。
圖7是根據一些實施例的積體電路晶粒700的俯視圖。在一些實施例中，可使用與上述參考圖1A至圖4B描述的材料和方法類似的材料和方法形成積體電路晶粒700，其中，使用類似的標號標記類似的元件，並且此處不重複描述。在一些實施例中，可在積體電路晶粒700的相對的角形成第一對位標記701和第二對位標記703。在一些實施例中，可使用與上述參考圖1A至圖1B描述的對位標記109的材料和方法類似的材料和方法形成第一對位標記701和第二對位標記703，並且此處不重複描述。在一些實施例中，第一對位標記701和第二對位標記703的俯視形狀為L-形多邊形。僅為了例示的目的，提供圖7中繪示出的第一對位標記701和第二對位標記703的特定方向。在其他實施例中，當以俯視觀察時，可將第一對位標記701和第二對位標記703旋轉期望的角度。在一些實施例中，積體電路晶粒700的第一側面可具有約0.5 mm和約3 mm之間的第一寬度W1 ，且積體電路晶粒700的第二側面可具有約0.5 mm和約3 mm之間的第二寬度W2 。在一些實施例中，連接結構401可具有約35 um和約55 um之間的第三寬度W3 。在一些實施例中，第一對位標記701的第一最長側面(平行於積體電路晶粒700的第一側面)可具有約W1 /20和約W1 /10之間的長度L9 ，第一對位標記701的第二最長側面(平行於積體電路晶粒700的第二側面)可具有約W2 /20和約W2 /10之間的長度L10 。第一對位標記701的第一最短側面(平行於積體電路晶粒700的第一側面)可具有約L9 /2和約L9 /3之間的長度L11 ，且第一對位標記701的第二最短側面(平行於積體電路晶粒700的第二側面)可具有約L10 /2和約L10 /3之間的長度L12 。在一些實施例中，第二對位標記703的第一最長側面(平行於積體電路晶粒700的第一側面)可具有約W1 /20和約W1 /10之間的長度L14 ，第二對位標記703的第二最長側面(平行於積體電路晶粒700的第二側面)可具有約W2 /20和約W2 /20之間的長度L15 ，第二對位標記703的第一最短側面(平行於積體電路晶粒700的第一側面)可具有約L14 /2和約L14 /3之間的長度L16 ，且第二對位標記703的第二最短側面 (平行於積體電路晶粒700的第二側面)可具有約L15 /2和約L15 /3之間的長度L17 。在一些實施例中，第一對位標記701和最近的連接結構401之間的距離L13 可大於或等於W3 ，且第二對位標記703和最近的連接結構401之間的距離L18 可大於或等於W3 /2。
圖8繪示出根據一些實施例形成具有對位標記的積體電路晶粒(諸如積體電路晶粒500、600和/或700)的方法800的流程圖。方法從步驟801開始，其中，如上述參考圖1A以及圖1B描述的，在工件(諸如工件100)上方形成接觸墊(諸如接觸墊107)和對位標記(諸如對位標記109)。在步驟803中，如上述參考圖2A至圖4B描述的，在接觸墊上方形成連接結構(諸如連接結構401)。在步驟805中，如上述參考圖4A以及圖4B描述的，將工件切割成單個的積體電路晶粒。
圖9至圖13是根據一些實施例的在積體電路封裝的製造期間的各個示例性製程步驟的剖面圖。如下面更詳細地描述的，積體電路晶粒(例如，分別在圖5至圖7中繪示出的積體電路晶粒500、600和700)將用於形成積體電路封裝(諸如圖12中繪示出的積體電路封裝1215)。本領域具通常知識者將理解，僅為了例示的目的提供下面描述的製程步驟，並且可使用任何適當的封裝方法封裝積體電路晶粒。
首先參考圖9，在一些實施例中，在載板901上方形成離形層903，並在離形層903上方形成一個或多個介電層905以開始形成積體電路封裝。在一些實施例中，載板901可由石英、玻璃等形成，並且提供隨後的操作的力學支撐。在一些實施例中，離形層903可包括光熱轉換(LTHC)材料、UV膠等，並且可使用旋轉塗佈製程、印刷製程、層壓製程等形成。在離形層903由光熱轉換材料形成的一些實施例中，當暴露於光時，離形層903部分地或完全地喪失它的黏合強度，並且可從隨後形成的結構的背面容易地去除載板901。在一些實施例中，可使用與上述參考圖2A以及圖2B描述的保護層201的材料和方法類似的材料和方法形成一個或多個介電層905，並且此處不重複描述。
進一步參考圖9，在一個或多個介電層905上形成導電通孔907。在一些實施例中，可在導電通孔907和一個或多個介電層905之間***種子層(未繪示出)。在一些實施例中，可使用與分別參考圖3A至圖4B描述的種子層301和導電柱401A類似的材料和方法形成種子層和導電通孔907，此處不重複描述。
參考圖10，使用膠層1001將積體電路晶粒1003連接至一個或多個介電層905。在一些實施例中，例如，使用拾取和放置裝置將積體電路晶粒1003放置在一個或多個介電層905上。在其他實施例中，可手動地或使用任何其他適當方法將積體電路晶粒1003放置在一個或多個介電層905上。在一些實施例中，膠層1001可包括光熱轉換材料、UV膠、晶粒黏著膜等，並且膠層1001可使用旋轉塗佈製程、印刷製程、層壓製程等形成。
在一些實施例中，將積體電路晶粒1003安裝至一個或多個介電層905使得晶粒接觸件1005和對位標記1007面對遠離一個或多個介電層905或者處於一個或多個介電層905的遠端。晶粒接觸件1005提供與在積體電路晶粒1003上形成的電路的電性連接。晶粒接觸件1005可在積體電路晶粒1003的主動側面上形成，或者可在背面上形成並且包括通孔。晶粒接觸件1005還可包括在積體電路晶粒1003的第一側面和第二側面之間提供電性連接的通孔。在一些實施例中，晶粒接觸件1005可包括銅、鎢、鋁、銀、金、錫、其組合等。在一些實施例中，可使用與上述參考圖1A至圖4B描述的接觸墊107和對位標記109類似的材料和方法形成晶粒接觸件1005和對位標記1007，此處不重複描述。如上所述，一個或多個對位標記的使用具有許多優點。例如，當將積體電路晶粒1003安裝在一個或多個介電層905上時，可減少或避免積體電路晶粒1003的不期望的偏移或旋轉。而且，可減少或避免由未對位所致的積體電路晶粒1003的損壞。
參考圖11，在載板901上方以及在積體電路晶粒1003和導電通孔907的上方和周圍形成封裝膠材1101。在一些實施例中，封裝膠材1101可包括諸如環氧化物、樹脂、可模製聚合物等的模塑膠體。可在模塑膠體實質上是液體時將其塗覆，然後藉由諸如環氧化物或樹脂中的化學反應將模塑膠體固化。在其他實施例中，模塑膠體可為紫外(UV)或熱固化聚合物，所述聚合物以能夠設置在積體電路晶粒1003和導電通孔907周圍以及之間的凝膠或可塑固體的形式塗覆。
進一步參考圖11，在一些實施例中，使用CMP製程、磨削製程等或其組合將產生的結構平坦化。在一些實施例中，實施平坦化製程直至暴露積體電路晶粒1003的晶粒接觸件1005。在一些實施例中，導電接觸件1005的頂面與導電通孔907和封裝膠材1101的頂面實質上共面。
參考圖12，在積體電路晶粒1003、導電通孔907和封裝膠材1101上方形成一個或多個重佈線(RDL)1201。在一些實施例中，重佈線1201包括一個或多個介電層1203和設置在一個或多個介電層1203內的一個或多個導電特徵1205。在一些實施例中，可使用與上述參考圖10描述的介電層905類似的材料和方法形成一個或多個介電層1203，此處不重複描述。在一些實施例中，一個或多個導電特徵1205可包括銅、鎢、鋁、銀、金等或其組合，並且可使用電化學鍍製程、化學鍍製程、原子層沉積、物理氣相沉積等或其組合形成。
進一步參考圖12，在重佈線1201上方形成電性連接至重佈線1201的球底金屬層(UBM)1207。在一些實施例中，可形成穿過一個或多個介電層1203的最頂介電層(未單獨繪示出)的一組開口以暴露重佈線1201的一個或多個導電特徵1205。在一些實施例中，球底金屬層1207可包括諸如鈦層、銅層和鎳層的多層導電材料。然而，本領域具通常知識者將認識到，有適於形成球底金屬層1207的材料和層的許多適當排列，諸如鉻/鉻-銅合金/銅/金的排列、鈦/鈦鎢/銅的排列或銅/鎳/金的排列。可用於球底金屬層1207的任何適當的材料或材料層完全旨在包括在本發明的實施例的範圍內。在一些實施例中，在一些球底金屬層1207上方形成電性連接至這些球底金屬層1207的連接結構1209。在一些實施例中，可使用與上述參考圖4A以及圖4B描述的連接結構401類似的材料和方法形成連接結構1209，此處不重複描述。
進一步參考圖12，在重佈線1201上方安裝積體電路晶粒1211，並且積體電路晶粒1211電性連接至重佈線1201。在一些實施例中，積體電路晶粒1211的連接結構1213用於將積體電路晶粒1211連接至球底金屬層1207，同時積體電路晶粒1211的對位標記1217用於在重佈線1201上方適當地對位積體電路晶粒1211。在一些實施例中，積體電路晶粒1211可能與積體電路晶粒500、600和/或700(參見圖5至圖7)類似，並且可使用與上述參考圖1A至圖4B描述的那些方法類似的方法形成，此處不重複描述。在一些實施例中，可使用分別與參考圖1A至圖4B描述的連接結構401和對位標記109類似的材料和方法形成連接結構1213和對位標記1217，此處不重複描述。在一些實施例中，例如使用拾取和放置裝置將積體電路晶粒1211放置在重佈線1201上。在一些實施例中，拾取和放置裝置可使用積體電路晶粒1211的對位標記1217以在重佈線1201上方適當地對位積體電路晶粒1211。藉由使用對位標記1217，可減少或避免積體電路晶粒1211的不期望的偏移或旋轉。而且，可減少或避免由未對位所致的積體電路晶粒1211的損壞。在其他實施例中，可手動地或使用任何其他適當方法將積體電路晶粒1211放置在重佈線1201上。在繪示出的實施例中，積體電路晶粒1211為分離式半導體元件晶片。然而，在其他實施例中，積體電路晶粒1211可為提供期望的功能性的任何適當的積體電路晶粒。
在一些實施例中，在重佈線1201上方安裝積體電路晶粒1211之後，將產生的結構從載板901分離並切割以形成單個的積體電路封裝1215。在一些實施例中，可藉由切割、雷射剝蝕方法等將產生的結構切割。隨後，為了進一步加工，可測試各個積體電路封裝1215以識別已知良好封裝(KGP)。
圖13繪示出藉由延伸穿過一個或多個介電層905中的開口的工件1303與積體電路封裝1215的接合製程以形成堆疊式半導體元件1300。在一些實施例中，工件1303可為封裝、一個或多個晶粒、印刷電路板(PCB)、封裝基板、***層等。在工件1303為封裝的一些實施例中，堆疊式半導體元件1300為疊層封裝(PoP)元件。在工件1303為晶粒的其他實施例中，堆疊式半導體元件1300為封裝上晶片(CoP)元件。在一些實施例中，可使用與上述參考圖3A至圖4B描述的連接結構401的材料和方法類似的材料和方法形成連接結構1305，此處不重複描述。在一些實施例中，在參考圖12描述的切割製程之前，可將工件1303接合至積體電路封裝1215。
進一步參考圖13，可注入底部填充材料(未繪示出)或者可以其他方式在工件1303和積體電路封裝1215之間的空間以及連接結構1305周圍形成底部填充材料。例如，底部填充材料可為在各個結構之間分配的液體環氧化物、可變形凝膠、矽橡膠等，然後將底部填充材料固化至變硬。此外，該底部填充材料可用於減少對連接結構1305的損壞以及保護連接結構1305。
進一步參考圖13，在一些實施例中，可使用連接結構1209將堆疊式半導體元件1300接合至工件1301。在一些實施例中，工件1301可能與工件1303類似並且此處不重複描述。在繪示出的實施例中，工件1301是印刷電路板(PCB)。
圖14繪示出根據一些實施例的形成積體電路封裝的方法1400的流程圖。方法1400從步驟1401開始，其中，如上述參考圖9描述的，在載板(諸如載板901)上方形成一個或多個介電層(諸如一個或多個介電層905)。隨後，如上述參考圖9描述的，在一個或多個介電層上方形成導電通孔(諸如導電通孔907)。在步驟1403中，如上述參考圖10描述的，將第一晶粒(諸如積體電路晶粒1003)連接至一個或多個介電層。在步驟1405中，如上述參考圖11描述的，形成封裝膠材(諸如封裝膠材1101)以封裝導電通孔和第一晶粒。在步驟1407中，如上述參考圖12描述的，在封裝的第一晶粒和導電通孔上方形成一個或多個重佈線(諸如重佈線1201)。在步驟1409中，如上述參考圖12描述的，在一個或多個重佈線上方形成連接結構(諸如連接結構1209)。在步驟1411中，如上述參考圖12描述的，將第二晶粒(諸如積體電路晶粒1211)安裝在一個或多個重佈線上。在步驟1413中，如上述參考圖12描述的，將產生的結構從載板分離並切割以形成單個的積體電路封裝(諸如積體電路封裝1215)。
根據一個實施例，方法包括在基板上形成元件。在基板和元件上方形成多個接觸墊。與形成多個接觸墊同時，在基板和元件上方形成一個或多個對位標記。
在上述方法中，更包括：將所述基板切割以形成晶粒，所述晶粒具有至少一個對位標記；使用所述至少一個對位標記將所述晶粒與工件對位；以及將所述晶粒連接至所述工件。
在上述方法中，更包括：將所述基板切割以形成晶粒，所述晶粒具有至少一個對位標記；使用所述至少一個對位標記將所述晶粒與工件對位；以及將所述晶粒連接至所述工件，其中，所述晶粒是分離式半導體元件晶片。
在上述方法中，更包括：將所述基板切割以形成晶粒，所述晶粒具有至少一個對位標記；使用所述至少一個對位標記將所述晶粒與工件對位；以及將所述晶粒連接至所述工件，其中，所述工件包括多個封裝的晶粒和位於所述多個封裝的晶粒上的一個或多個重佈線，所述晶粒連接至所述一個或多個重佈線，所述一個或多個重佈線***在所述多個封裝的晶粒和所述晶粒之間。
在上述方法中，其中，形成所述多個接觸墊和所述一個或多個對位標記包括：在所述基板和所述元件上方沉積導電層；以及將所述導電層圖案化以形成所述多個接觸墊和所述一個或多個對位標記。
在上述方法中，更包括在所述多個接觸墊上形成連接結構。
在上述方法中，其中，所述一個或多個對位標記與所述元件電性絕緣。
根據另一個實施例，方法包括在基板上形成元件。在基板和元件上方形成一個或多個金屬化層。在一個或多個金屬化層上形成導電層。將導電層圖案化以形成多個接觸墊和一個或多個對位標記，一個或多個對位標記與元件電性絕緣。
在上述方法中，更包括在所述多個接觸墊和所述一個或多個對位標記上方形成保護層，所述保護層覆蓋所述一個或多個對位標記的整個頂面。
在上述方法中，更包括：將所述基板單一化以形成單一化的晶粒，所述單一化的晶粒具有至少一個對位標記；使用所述至少一個對位標記將所述單一化的晶粒與工件對位；以及將所述單一化的晶粒連接至所述工件。
在上述方法中，更包括：將所述基板單一化以形成單一化的晶粒，所述單一化的晶粒具有至少一個對位標記；使用所述至少一個對位標記將所述單一化的晶粒與工件對位；以及將所述單一化的晶粒連接至所述工件，其中，所述工件包括多個封裝的晶粒和位於所述多個封裝的晶粒上的一個或多個重佈線，所述單一化的晶粒連接至所述一個或多個重佈線，所述一個或多個重佈線***在所述單一化的晶粒和所述多個封裝的晶粒之間。
在上述方法中，更包括：將所述基板單一化以形成單一化的晶粒，所述單一化的晶粒具有至少一個對位標記；使用所述至少一個對位標記將所述單一化的晶粒與工件對位；以及將所述單一化的晶粒連接至所述工件，其中，所述單一化的晶粒為分離式半導體元件晶片。
在上述方法中，更包括在所述多個接觸墊上形成連接結構。
在上述方法中，其中，當以俯視觀察時，所述一個或多個對位標記的每個都具有多邊形形狀。
根據另一個實施例，半導體元件包括基板、位於基板上的元件和位於基板和元件上方的介電層。半導體元件更包括位於介電層上的接觸墊和位於介電層上的第一對位標記，第一對位標記與元件電性絕緣，接觸墊和第一對位標記由相同材料形成，接觸墊和第一對位標記處於相同的層級。
在上述半導體元件中，更包括：保護層，位於所述介電層上，所述接觸墊和所述第一對位標記***在所述介電層和所述保護層之間。
在上述半導體元件中，其中，所述接觸墊和所述第一對位標記具有相同厚度。
在上述半導體元件中，其中，所述第一對位標記位於所述基板的第一角。
在上述半導體元件中，其中，所述第一對位標記位於所述基板的第一角，所述半導體元件更包括：第二對位標記，位於所述介電層上，所述第二對位標記位於所述基板的第二角，所述第二角與所述第一角相對。
在上述半導體元件中，其中，當以俯視觀察時，所述第一對位標記具有多邊形形狀。
上面論述了若干實施例的特徵，使得本領域具通常知識者可以更好地理解本發明的各個方面。本領域具通常知識者應該理解，他們可以很容易地使用本發明作為基礎來設計或更改其他用於達到與本文所介紹實施例相同的目的和/或實現相同優點的製程和結構。本領域具通常知識者也應該意識到，這些等效結構並不背離本發明的精神和範圍，並且在不背離本發明的精神和範圍的情況下，可以進行多種變化、替換以及改變。
100、1301、1303‧‧‧工件
101‧‧‧晶粒區
103‧‧‧切割線
105‧‧‧基板
107‧‧‧接觸墊
109、601、701、703、1007、1217‧‧‧對位標記
111‧‧‧主動和/或被動元件
113‧‧‧金屬化層
201‧‧‧保護層
203、305‧‧‧開口
301‧‧‧種子層
303‧‧‧犧牲層
401、1209、1213、1305‧‧‧連接結構
401A‧‧‧導電柱
401B‧‧‧覆蓋層
500、600、700、1003、1211‧‧‧積體電路晶粒
800、1400‧‧‧方法
801、803、805、1401、1403、1405、1407、1409、1411、1413‧‧‧步驟
901‧‧‧載板
903‧‧‧離形層
905、1203‧‧‧介電層
907‧‧‧導電通孔
1001‧‧‧膠層
1005‧‧‧晶粒接觸件
1101‧‧‧封裝膠材
1201‧‧‧重佈線
1205‧‧‧導電特徵
1207‧‧‧球底金屬層
1215‧‧‧積體電路封裝
1300‧‧‧堆疊式半導體元件
L1、L2、L3、L4、L6、L7、L8、L9、L10、L11、L12、L14、L15、L16、L17‧‧‧長度
L5、L13、L18‧‧‧距離
W1‧‧‧第一寬度
W2‧‧‧第二寬度
W3‧‧‧第三寬度
圖1A至圖4B是根據一些實施例的在具有對位標記的積體電路晶粒的製造期間的各個製程步驟的俯視圖和剖面圖。 圖5是根據一些實施例的積體電路晶粒的俯視圖。 圖6是根據一些實施例的積體電路晶粒的俯視圖。 圖7是根據一些實施例的積體電路晶粒的俯視圖。 圖8繪示出根據一些實施例的形成具有對位標記的積體電路晶粒的方法的流程圖。 圖9至圖13是根據一些實施例的在積體電路封裝的製造期間的各個製程步驟的剖面圖。 圖14繪示出根據一些實施例的形成積體電路封裝的方法的流程圖。
100‧‧‧工件
101‧‧‧晶粒區
103‧‧‧切割線
105‧‧‧基板
107‧‧‧接觸墊
109‧‧‧對位標記

Claims (1)

  1. 一種方法，包括： 在基板上形成元件； 在所述基板和所述元件上方形成多個接觸墊；以及 與形成所述多個接觸墊同時，在所述基板和所述元件上方形成一個或多個對位標記。
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