TW201717261A - A stretchable form of single crystal silicon for high performance electronics on rubber substrates - Google Patents

A stretchable form of single crystal silicon for high performance electronics on rubber substrates Download PDF

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TW201717261A
TW201717261A TW105135576A TW105135576A TW201717261A TW 201717261 A TW201717261 A TW 201717261A TW 105135576 A TW105135576 A TW 105135576A TW 105135576 A TW105135576 A TW 105135576A TW 201717261 A TW201717261 A TW 201717261A
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約翰Ａ 羅傑斯
姜達榮
孫玉剛
艾坦尼 米納德
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美國伊利諾大學理事會
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Abstract

In an aspect, the present invention provides stretchable, and optionally printable, components such as semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed, and related methods of making or tuning such stretchable components. Stretchable semiconductors and electronic circuits preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention are adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

Description

用在橡膠基板上高效能電子組件之可延伸形式之單晶矽 Single crystal germanium in an extendable form of high performance electronic components for use on rubber substrates

本發明係關於用在橡膠基板上高效能電子組件之可延伸形式之單晶矽。 The present invention relates to a single crystal crucible in an extendable form of a high performance electronic component for use on a rubber substrate.

自1994年一印製的全聚合物電晶體之第一次演示以來，人們對在塑膠基板上包含可撓性積體電子裝置之一潛在的新類別電子系統產生了巨大的興趣。[Garnier,F.,Hajlaoui,R.,Yassar,A.及Srivastava,P.,Science，第265卷，第1684-1686頁]近來，大量研究已針對發展新的用於可撓性塑性電子裝置之導體、介電質及半導體元件之溶液可處理材料。然而，可撓性電子裝置領域中之進步不僅由新的溶液可處理材料的發展來驅動，而且由新裝置組件幾何形態、高效裝置及裝置組件處理方法及可應用於塑膠基板之高解析度圖案化技術所驅動。預期此等材料、裝置組態及製造方法將在迅速出現之新型可撓性積體電子裝置、系統及電路中起到關鍵作用。 Since the first demonstration of a fully polymerized transistor printed in 1994, there has been a great interest in the potential new class of electronic systems that include flexible integrated electronic devices on plastic substrates. [Garnier, F., Hajlaoui, R., Yassar, A. and Srivastava, P., Science, Vol. 265, pp. 1684-1686] Recently, a large number of studies have been directed to the development of new flexible plastic electronic devices. Solutions of conductors, dielectrics, and semiconductor components can process materials. However, advances in the field of flexible electronic devices have not only been driven by the development of new solution-processable materials, but also by new device component geometries, high-efficiency devices and device component processing methods, and high-resolution patterns that can be applied to plastic substrates. Driven by technology. It is expected that such materials, device configurations and manufacturing methods will play a key role in the rapid emergence of new flexible integrated electronic devices, systems and circuits.

對可撓性電子裝置領域之興趣是由此技術提供之若干重要優勢而引起。首先，塑膠基板材料之機械耐用性提供不易損壞及/或不易受到由機械應力引起之電子效能降級的電子裝置。其次，此等基板材料之固有的可撓性允許將其整合為許多形狀，從而提供不可能藉由脆 性的習知的基於矽之電子裝置來提供的大量有用裝置組態。最後，溶液可處理組件材料與塑膠基板之組合使得藉由能在大基板面積上以低成本產生電子裝置之連續、高速、印製技術的製造成為可能。 Interest in the field of flexible electronic devices is caused by several important advantages provided by this technology. First, the mechanical durability of the plastic substrate material provides an electronic device that is less susceptible to damage and/or less susceptible to degradation in electronic performance caused by mechanical stress. Second, the inherent flexibility of these substrate materials allows them to be integrated into many shapes, thereby providing the impossibility of A large number of useful device configurations provided by the sophisticated electronic devices. Finally, the combination of solution processable component materials and plastic substrates makes it possible to manufacture continuous, high speed, printing techniques that can produce electronic devices at low cost over large substrate areas.

然而，呈現良好電子效能之可撓性電子裝置之設計及製造存在若干顯著挑戰。首先，用於製造習知的基於矽之電子裝置的已良好發展的方法與大部分塑膠材料不相容。舉例而言，諸如單晶矽或鍺半導體之傳統的高品質無機半導體組件通常藉由在某些溫度(>攝氏1000度)下生長薄膜來處理，該等溫度顯著超過大部分塑膠基板的熔融或分解溫度。另外，大部分無機半導體在允許基於溶液之處理及傳送之適宜溶劑中本質地不可溶。其次，儘管許多非晶系矽、有機或混合有機-無機半導體可相容地併入塑膠基板中，且可在相對較低溫度下處理，但是此等材料不具有能提供具有良好電子效能之積體電子裝置之電子性質。舉例而言，具有由此等材料製造之半導體元件的薄膜電晶體顯示出比互補的基於單晶矽之裝置低大約三個數量級之場效應遷移率。作為此等侷限性之結果，可撓性電子裝置目前限於無需高效能的特定應用，諸如用於具有非發射性像素之主動矩陣平板顯示器之開關元件中及發光二極體中。 However, the design and manufacture of flexible electronic devices that exhibit good electronic performance present several significant challenges. First, well-developed methods for fabricating conventional germanium-based electronic devices are incompatible with most plastic materials. For example, conventional high quality inorganic semiconductor components such as single crystal germanium or germanium semiconductors are typically processed by growing a film at certain temperatures (> 1000 degrees Celsius) that significantly exceed the melting of most plastic substrates or Decomposition temperature. In addition, most inorganic semiconductors are substantially insoluble in suitable solvents that allow for solution based processing and delivery. Second, although many amorphous germanium, organic or hybrid organic-inorganic semiconductors are compatiblely incorporated into plastic substrates and can be processed at relatively low temperatures, such materials do not have the ability to provide products with good electronic performance. The electronic properties of bulk electronic devices. For example, thin film transistors having semiconductor elements fabricated from such materials exhibit field effect mobility that is about three orders of magnitude lower than complementary single crystal germanium based devices. As a result of these limitations, flexible electronic devices are currently limited to specific applications that do not require high performance, such as in switching elements for active matrix flat panel displays having non-emissive pixels and in light emitting diodes.

在擴展塑膠基板上的積體電子裝置之電子效能能力方面已獲得進步以將其適用性擴展至一更廣泛範圍之電子應用。舉例而言，已出現若干新型薄膜電晶體(TFT)設計，其與塑膠基板材料上之處理相容且顯示出顯著高於具有非晶系矽、有機或混合有機-無機半導體元件之薄膜電晶體之裝置效能特性。一類更高效能之可撓性電子裝置係基於藉由對非晶系矽薄膜之脈衝雷射退火而製造之多晶矽薄膜半導體元件。雖然此類可撓性電子裝置提供增強之裝置電子效能特性，但是對脈衝雷射退火之使用限制了此等裝置製造的容易性及靈活性，進而顯著增加了成本。另一有希望之新型更高效能之可撓性電子裝置是使用 諸如奈米線、奈米帶、奈米微粒及奈米碳管之溶液可處理奈米級材料作為若干宏觀電子及微電子裝置中之主動功能性組件之裝置。 Advances have been made in expanding the electronic performance capabilities of integrated electronic devices on plastic substrates to extend their applicability to a wider range of electronic applications. For example, several new thin film transistor (TFT) designs have emerged that are compatible with processing on plastic substrate materials and exhibit significantly higher film transistors than amorphous germanium, organic or hybrid organic-inorganic semiconductor devices. Device performance characteristics. A class of higher performance flexible electronic devices are based on polycrystalline germanium thin film semiconductor devices fabricated by pulsed laser annealing of amorphous germanium films. While such flexible electronic devices provide enhanced device electronic performance characteristics, the use of pulsed laser annealing limits the ease of manufacture and flexibility of such devices, thereby significantly increasing cost. Another promising new and more efficient flexible electronic device is used Solutions such as nanowires, nanobelts, nanoparticles, and carbon nanotubes can process nanoscale materials as devices for active functional components in a number of macroelectronic and microelectronic devices.

離散單結晶奈米線或奈米帶之使用已被評估為於塑膠基板上提供顯示增強裝置效能特性之可印刷電子裝置的一可能之手段。Duan等人描述具有複數個作為半導體通道之可選擇性定向之單結晶矽奈米線或CdS奈米帶的薄膜電晶體設計[Duan,X.,Niu,C,Sahl,V.,Chen,J.,Parce,J.,Empedocles,S.及Goldman,J.,Nature，第425卷，第274-278頁]。該等作者報告一據稱可與塑膠基板上之溶液處理相容之製造過程，其中具有少於或等於150奈米之厚度的單結晶矽奈米線或CdS奈米帶被分散於溶液中，且使用流量定向對準方法將其組裝於一基板之表面上以產生薄膜電晶體之半導體元件。由該等作者提供之一光學顯微圖暗示所揭示之製造過程製備了呈大體上平行取向且間隔約500奈米至約1000奈米的多個奈米線或奈米帶之單層。儘管該等作者報告了個別奈米線或奈米帶之相對高的本質場效應遷移率(119cm2 V-1 s-1)，但是總的裝置場效應遷移率近來已被判定為比由Duan等人報告之本質場效應遷移率值小"大約兩個數量級"。[Mitzi,D.B,Kosbar,L.L.,Murray,C.E.,Copel,M.Afzali,A.,Nature，第428頁，第299-303頁]。此裝置場效應遷移率比習知單結晶無機薄膜電晶體之裝置場效應遷移率低若干數量級，且可能係歸因於使用Duan等人揭示之方法及裝置組態進行對準、緊密封裝及電接觸離散奈米線或奈米帶中的實際挑戰。 The use of discrete single crystal nanowires or nanobelts has been evaluated as a possible means of providing a printable electronic device on a plastic substrate that exhibits enhanced device performance characteristics. Duan et al. describe a thin-film transistor design with a plurality of selectively oriented single crystal tantalum nanowires or CdS nanobelts as semiconductor channels [Duan, X., Niu, C, Sahl, V., Chen, J ., Parce, J., Empedocles, S. and Goldman, J., Nature, Vol. 425, pp. 274-278]. The authors report a manufacturing process that is said to be compatible with solution processing on a plastic substrate in which a single crystal tantalum nanowire or CdS nanobelt having a thickness of less than or equal to 150 nanometers is dispersed in solution. And it is assembled on the surface of a substrate using a flow direction alignment method to produce a semiconductor element of a thin film transistor. One of the optical micrographs provided by the authors suggests that the disclosed fabrication process produces a single layer of multiple nanowires or nanoribbons in substantially parallel orientation and spaced from about 500 nanometers to about 1000 nanometers. Although the authors report the relatively high intrinsic field effect mobility of individual nanowires or nanoribbons ( 119 cm 2 V -1 s -1 ), but the total device field-effect mobility has recently been determined to be "about two orders of magnitude smaller" than the intrinsic field-effect mobility value reported by Duan et al. [Mitzi, DB, Kosbar, LL, Murray, CE, Copel, M. Afzali, A., Nature, page 428, pages 299-303]. The field effect mobility of this device is several orders of magnitude lower than that of the conventional single crystal inorganic thin film transistor, and may be due to alignment, tight packaging, and electricity using the method and device configuration disclosed by Duan et al. Contact the actual challenges in discrete nanowires or nanobelts.

亦已探索了將奈米晶體溶液用作多晶系無機半導體薄膜之先驅體，以將其作為在塑膠基板上提供呈現更高裝置效能特性之可印刷電子裝置之手段。Ridley等人揭示一溶液處理製造方法，其中具有約2奈米尺寸之硒化鎘奈米晶體溶液在塑膠相容溫度下被處理以提供場效應電晶體之半導體元件。[Ridley,B.A.,Nivi,B.及Jacobson,J.M., Science，第286卷，746-749(1999)]該等作者報告一方法，其中在硒化鎘奈米晶體溶液中的低溫晶粒生長提供包含數百奈米晶體之單晶區域。雖然Ridley等人報告了相對於具有有機半導體元件之比較裝置的改良之電子性質，但是藉由此等技術達成的裝置遷移率(1cm2 V-1 s-1)比習知單結晶無機薄膜電晶體之裝置場效應遷移率低若干數量級。藉由Ridley等人之裝置組態及製造方法所達成之場效應遷移率的限制可能是由在個別奈米微粒之間建立之電接觸產生的。詳言之，對用以穩定奈米晶體溶液及防止凝聚之有機端基的使用可阻止在鄰近奈米微粒之間建立良好電接觸，此種良好電接觸對於提供高裝置場效應遷移率係必要的。 Nanocrystalline crystal solutions have also been explored as precursors for polycrystalline inorganic semiconductor thin films as a means of providing printable electronic devices that exhibit higher device performance characteristics on plastic substrates. Ridley et al. disclose a solution processing process in which a cadmium selenide crystal crystal solution having a size of about 2 nanometers is processed at a plastic compatible temperature to provide a semiconductor element of a field effect transistor. [Ridley, BA, Nivi, B. and Jacobson, JM, Science, Vol. 286, 746-749 (1999)] The authors report a method in which low temperature grain growth in cadmium selenide nanocrystals provides A single crystal region containing hundreds of nanometer crystals. Although Ridley et al. report improved electronic properties relative to comparison devices having organic semiconductor components, device mobility achieved by such techniques ( The field effect mobility of the device of 1 cm 2 V -1 s -1 ) is several orders of magnitude lower than that of the conventional single crystal inorganic thin film transistor. The limitation of field effect mobility achieved by Ridley et al.'s device configuration and fabrication methods may be due to electrical contact established between individual nanoparticles. In particular, the use of organic end groups to stabilize the nanocrystal solution and prevent agglomeration prevents the formation of good electrical contact between adjacent nanoparticles, which is necessary to provide high device field-effect mobility. of.

儘管Duan等人及Ridley等人提供用於在塑膠基板上製造薄膜電晶體之方法，所描述之裝置組態係包含諸如電極、半導體及/或介電質的機械剛性裝置組件之電晶體。選用具有良好機械性質之塑膠基板可提供能在延伸或扭曲定向中工作的電子裝置，然而，預期此種形變會在個別剛性電晶體裝置組件上產生機械應力。此機械應力可導致對個別組件之損傷，例如，裂紋，且亦可降級或中斷裝置組件之間的電接觸。 While Duan et al. and Ridley et al. provide methods for fabricating thin film transistors on plastic substrates, the device configurations described are those comprising mechanically rigid device components such as electrodes, semiconductors, and/or dielectrics. The use of a plastic substrate having good mechanical properties provides an electronic device that can operate in an extended or twisted orientation, however, such deformation is expected to create mechanical stress on the individual rigid transistor device components. This mechanical stress can cause damage to individual components, such as cracks, and can also degrade or interrupt electrical contact between device components.

此外，由Duan等人、Ridley等人及其他人發展之基於塑膠基板之電子系統是否提供對於許多重要裝置應用(包括可撓性感測器陣列、電子紙，及可佩帶電子裝置)為必要的機械延伸性並不明朗。雖然此等團隊展示了有能力承受由撓曲引起之變形的電子裝置，但是此等基於塑膠基板之系統不可能進行可觀的延伸而無損傷、機械失效或裝置效能之顯著降級。因此，此等系統不可能承受由膨脹或壓縮引起之變形，或承受等形覆蓋高度起伏之表面(諸如具有大曲率半徑的彎曲表面)所要求之變形。 In addition, the electronic substrate based on plastic substrates developed by Duan et al, Ridley et al. and others provide the necessary machinery for many important device applications, including flexible sensor arrays, electronic paper, and wearable electronic devices. The extensibility is not clear. While such teams have demonstrated electronic devices capable of withstanding deformation caused by deflection, such plastic substrate-based systems are unlikely to undergo considerable extension without damage, mechanical failure, or significant degradation in device performance. Thus, such systems are unlikely to withstand the deformation caused by expansion or compression, or the deformation required to conform to a surface that is highly undulating, such as a curved surface having a large radius of curvature.

如上述，預期可撓性電子裝置領域中之進步會在若干重要新技 術及已有技術中起到關鍵作用。然而，可撓性電子裝置技術之此等應用之成功極大地取決於新材料、裝置組態及用於製造在撓曲、變形及彎曲構形中展示良好電子、機械及光學性質的積體電子電路及裝置之商業上可行的製造途徑之持續發展。特定言之，需要在延伸或收縮構形中展示有用之電子及機械性質的高效能、可機械延伸的材料及裝置組態。 As mentioned above, it is expected that advances in the field of flexible electronic devices will be in several important new technologies. And the prior art plays a key role. However, the success of such applications of flexible electronic device technology is highly dependent on new materials, device configurations, and integrated electronics used to fabricate good electronic, mechanical, and optical properties in flexure, deformation, and bending configurations. The continued development of commercially viable manufacturing routes for circuits and devices. In particular, high performance, mechanically extensible materials and device configurations that exhibit useful electronic and mechanical properties in an extended or collapsed configuration are required.

本發明提供可延伸半導體及可延伸電子裝置、裝置組件及電路。如本文所使用，術語"可延伸"指材料、結構、裝置及裝置組件能承受應變而無破裂或機械失效。本發明之可延伸半導體及電子裝置係可延伸的，且因此能至少在某種程度上延伸及/或壓縮而無損壞、機械失效或裝置效能之顯著降級。較佳用於某些應用的本發明之可延伸半導體及電子電路為可撓性的(除了為可延伸的之外)，且因此能顯著伸長、撓曲，彎曲或進行沿一或多個軸之其他變形。 The present invention provides extendable semiconductors and extendable electronic devices, device components and circuits. As used herein, the term "extensible" means that the materials, structures, devices, and device components are capable of withstanding strain without cracking or mechanical failure. The extendable semiconductor and electronic devices of the present invention are extensible and, therefore, extend and/or compress at least to some extent without damage, mechanical failure, or significant degradation in device performance. The extensible semiconductor and electronic circuits of the present invention, which are preferred for certain applications, are flexible (except for being extensible) and are therefore capable of significantly elongating, flexing, bending or performing along one or more axes Other variants.

本發明之有用的可延伸半導體及電子裝置能伸長、壓縮、扭曲及/或膨脹而無機械失效。另外，本發明之可延伸半導體及電子電路即使當承受顯著應變(諸如大於或等於約0.5%，較佳1%且最好為2%的應變)時亦展示良好電子效能。可撓性的可延伸半導體及電子裝置、裝置組件及電路當處於撓曲、彎曲及/或變形狀態時亦顯示良好的電子效能。因為本發明之可延伸半導體元件及可延伸電子裝置、裝置組件及電路在撓曲、延伸、壓縮或變形的裝置定向中可提供有用之電子性質及機械耐用性，所以其適合廣泛範圍的裝置應用及裝置組態。 Useful extendable semiconductor and electronic devices of the present invention are capable of elongating, compressing, twisting, and/or expanding without mechanical failure. Additionally, the extendable semiconductor and electronic circuits of the present invention exhibit good electronic performance even when subjected to significant strain, such as greater than or equal to about 0.5%, preferably 1%, and most preferably 2% strain. Flexible extensible semiconductor and electronic devices, device components, and circuits also exhibit good electrical performance when in a flexed, bent, and/or deformed state. Because the extendable semiconductor components and extendable electronic devices, device components, and circuits of the present invention provide useful electronic properties and mechanical durability in device orientation for flexing, extending, compressing, or deforming, they are suitable for a wide range of device applications. And device configuration.

本發明之可延伸及/或可撓性半導體亦可(視情況)為可印刷的，且(視情況)可包含複合半導體元件，其具有一可操作地與其他結構、材料及/或裝置組件(諸如介電材料及層、電極及其他半導體材料及層)連接之半導體結構。本發明包括具有可延伸及/或可撓性半導體之廣 泛範圍之可延伸及/或可撓性電子及/或光電子裝置，包括(但不限於)電晶體、二極體、發光二極體(LED)、有機發光二極體(OLED)、雷射器、微機電裝置及奈米機電裝置、微流體裝置及奈米流體裝置、記憶體裝置，及系統層級積體電子電路(諸如互補邏輯電路)。 The extendable and/or flexible semiconductor of the present invention may also (as appropriate) be printable, and (as appropriate) may comprise a composite semiconductor component having an operatively associated with other structures, materials and/or device components A semiconductor structure (such as a dielectric material and layers, electrodes, and other semiconductor materials and layers). The invention includes a wide range of extendable and/or flexible semiconductors Extensive range of extendable and/or flexible electronic and/or optoelectronic devices including, but not limited to, transistors, diodes, light emitting diodes (LEDs), organic light emitting diodes (OLEDs), lasers , microelectromechanical devices and nanoelectromechanical devices, microfluidic devices and nanofluid devices, memory devices, and system level integrated electronic circuits (such as complementary logic circuits).

在一個態樣中，本發明提供當處於撓曲、膨脹、壓縮、彎曲及/或變形狀態中時可提供有用之功能性質之可延伸半導體元件。如本文所使用，表述"半導體元件"及"半導體結構"在本文中等同地使用且泛指任何半導體材料、組合物或結構，且特別包括高品質單晶及多晶半導體、經由高溫處理製造之半導體材料、摻雜半導體材料、有機及無機半導體及具有一或多種額外半導體組份及/或非半導體組份(諸如，介電層或材料及/或導電層或材料)的複合半導體材料及結構。 In one aspect, the present invention provides an extendable semiconductor component that provides useful functional properties when in a flexed, expanded, compressed, bent, and/or deformed state. As used herein, the expression "semiconductor element" and "semiconductor structure" are used equally herein and generally refer to any semiconductor material, composition or structure, and particularly include high quality single crystal and polycrystalline semiconductor, manufactured by high temperature processing. Semiconductor materials, doped semiconductor materials, organic and inorganic semiconductors, and composite semiconductor materials and structures having one or more additional semiconductor components and/or non-semiconductor components such as dielectric layers or materials and/or conductive layers or materials .

本發明之可延伸半導體元件包含一具有一支撐表面之可撓性基板及一具有一曲線內表面(例如，由該半導體結構之一彎曲構形提供的一曲線內表面)之半導體結構。在此實施例中，該半導體結構之至少一部分曲線內表面與該可撓性基板之支撐表面結合。具有本發明中有用之曲線內表面之例示性半導體結構包含彎曲結構。在本文中，"彎曲結構"指一具有由施加力而導致之曲線構形之結構。本發明中之彎曲結構可具有一或多個折疊區域、凸起區域及/或凹入區域。舉例而言，本發明中有用之彎曲結構可以一捲曲構形、一皺褶構形、一翹棱構形及/或一波狀(意即波形)組態來提供。 The extensible semiconductor component of the present invention comprises a flexible substrate having a support surface and a semiconductor structure having a curved inner surface (e.g., a curved inner surface provided by a curved configuration of the semiconductor structure). In this embodiment, at least a portion of the curved inner surface of the semiconductor structure is bonded to the support surface of the flexible substrate. An exemplary semiconductor structure having an inner surface of a curve useful in the present invention comprises a curved structure. As used herein, "curved structure" refers to a structure having a curved configuration resulting from the application of a force. The curved structure of the present invention may have one or more folded regions, raised regions, and/or recessed regions. For example, the curved structure useful in the present invention can be provided in a crimped configuration, a pleated configuration, a wavy configuration, and/or a wavy (ie, waveform) configuration.

彎曲結構(諸如具有曲線內表面之可延伸彎曲半導體結構及電子電路)可與諸如聚合物及/或彈性基板之可撓性基板以一其中該彎曲結構承受應變的構形來結合。在某些實施例中，該彎曲結構(諸如一彎曲帶狀結構)承受等於或小於約30%之應變，在較佳用於某些應用之實施例中承受等於或小於約10%的應變，及/或在較佳用於某些應用之實施例中承受等於或小於約1%之應變。在某些實施例中，該彎曲結 構(諸如一彎曲帶狀結構)承受選自約1%至約30%之範圍之應變。 A curved structure, such as an extensible curved semiconductor structure having a curved inner surface and an electronic circuit, can be combined with a flexible substrate such as a polymer and/or an elastic substrate in a configuration in which the curved structure is strained. In certain embodiments, the curved structure (such as a curved ribbon structure) is subjected to a strain of equal to or less than about 30%, and is subjected to strains equal to or less than about 10% in embodiments preferred for certain applications, And/or withstand strains equal to or less than about 1% in embodiments preferred for certain applications. In some embodiments, the curved knot The structure, such as a curved ribbon structure, is subjected to strains selected from the range of from about 1% to about 30%.

在一有用之實施例中，具有一曲線內表面之半導體結構包含一至少部分地與該支撐可撓性基板結合的可轉移半導體元件。在本文中，"可轉移半導體元件"係一能例如經由沈積技術、印刷技術、圖案化技術及/或其他材料轉移方法自一供體表面轉移至一受體表面之半導體結構。本方法中有用之可轉移半導體元件、複合物及裝置包括(但不限於)可印刷半導體元件。 In a useful embodiment, a semiconductor structure having a curved inner surface includes a transferable semiconductor component at least partially bonded to the support flexible substrate. As used herein, a "transferable semiconductor component" is a semiconductor structure that can be transferred from a donor surface to a receptor surface, for example, via deposition techniques, printing techniques, patterning techniques, and/or other material transfer methods. Transferable semiconductor components, composites, and devices useful in the present methods include, but are not limited to, printable semiconductor components.

適用之可撓性基板包括(但不限於)聚合物基板、塑膠基板及/或彈性基板。舉例而言，在一實施例中，本發明包含一經轉移且結合至一預應變之彈性基板之可轉移、且(視情況)可印刷之半導體元件。本發明之此態樣中的有用之轉移方法包括印刷技術，如接觸印刷或溶液印刷。彈性基板之隨後鬆弛在該可轉移且(視情況)可印刷之半導體元件上產生一應變，從而導致(例如經由該半導體元件之彎曲及/或翹曲)該曲線內表面之形成。 Suitable flexible substrates include, but are not limited to, polymer substrates, plastic substrates, and/or elastic substrates. For example, in one embodiment, the invention comprises a transferable, and optionally a printable, semiconductor component that is transferred and bonded to a pre-strained elastomeric substrate. Useful transfer methods in this aspect of the invention include printing techniques such as contact printing or solution printing. Subsequent relaxation of the elastic substrate creates a strain on the transferable (as appropriate) printable semiconductor component, resulting in the formation of the inner surface of the curve (e.g., via bending and/or warping of the semiconductor component).

在某些實施例中，製造(例如如上述)具有曲線內表面之半導體元件，且隨後將其自用於產生其曲線表面之彈性基板轉移至一不同可撓性基板且將其與該不同可撓性基板結合。本發明之此態樣之有用實施例包括一可轉移且(視情況)可印刷之半導體結構，其包含具有曲線內表面之彎曲半導體帶、線、條、碟片、小板、方塊、柱或圓柱，該內表面具有一皺褶、翹棱及/或波形組態。然而，本發明包括可延伸半導體，其中該半導體元件未經由印刷構件而提供至該可撓性基板及/或其中該半導體元件係不可印刷的。 In some embodiments, a semiconductor component having a curved inner surface is fabricated (eg, as described above) and subsequently transferred from a flexible substrate used to create its curved surface to a different flexible substrate and is otherwise flexible The substrate is bonded. Useful embodiments of this aspect of the invention include a transferable and (as appropriate) printable semiconductor structure comprising curved semiconductor strips, wires, strips, discs, plates, cubes, columns or columns having curved inner surfaces The cylinder has a corrugated, ribbed and/or wavy configuration on the inner surface. However, the invention includes an extendable semiconductor wherein the semiconductor component is not provided to the flexible substrate via a printing member and/or wherein the semiconductor component is unprintable.

本發明包括可延伸半導體，該等可延伸半導體包含具有由單一可撓性基板支撐之曲線內表面之單一半導體元件。或者，本發明之可延伸半導體包含複數個可延伸半導體元件，該等可延伸半導體元件具有由單一可撓性基板支撐之曲線內表面。本發明之實施例包括可延伸 半導體元件之陣列或圖案，該等可延伸半導體元件具有由單一可撓性基板支撐的曲線內表面。可選擇地，該陣列或圖案中之可延伸半導體元件具有良好界定的、預選擇之實體尺寸、位置及相對空間取向。 The present invention includes extendable semiconductors comprising a single semiconductor component having a curved inner surface supported by a single flexible substrate. Alternatively, the extendable semiconductor of the present invention comprises a plurality of extensible semiconductor elements having curved inner surfaces supported by a single flexible substrate. Embodiments of the invention include extendable An array or pattern of semiconductor elements having curved inner surfaces supported by a single flexible substrate. Optionally, the extendable semiconductor component in the array or pattern has a well defined, pre-selected physical size, location, and relative spatial orientation.

本發明亦包括可延伸電子裝置、裝置組件及/或電路，其包含一或多個可延伸半導體結構，及額外積體裝置組件，諸如電觸點、電極、導電層、介電層，及/或額外半導體層(例如，摻雜層，P-N接面等等)。在此實施例中，可延伸半導體結構及額外積體裝置組件係可操作地耦合，以便提供選擇之裝置功能性，且可彼此電接觸或絕緣。在某些有用之實施例中，額外積體裝置組件(及該(等)可延伸半導體)之至少一部分或所有部分具有曲線內表面，該等曲線內表面係由可撓性基板之支撐表面來支撐，且提供於一彎曲結構中，例如一具有捲曲、波形、翹棱及/或皺褶構形之彎曲結構。額外積體裝置組件及可延伸半導體之曲線內表面可具有大體上相同或不同的輪廓形狀。本發明包括實施例，其中可延伸裝置組件係經由展示本質可延伸性之金屬互連件或亦具有波形、皺褶、彎曲及/或翹棱構形之金屬互連件來互連。 The invention also includes an extendable electronic device, device assembly and/or circuit comprising one or more extendable semiconductor structures, and additional integrated device components, such as electrical contacts, electrodes, conductive layers, dielectric layers, and/or Or an additional semiconductor layer (eg, doped layer, PN junction, etc.). In this embodiment, the extendable semiconductor structure and the additional integrated device components are operatively coupled to provide selected device functionality and are electrically or insulative to each other. In certain useful embodiments, at least a portion or all of the additional integrated device components (and the extendable semiconductor) have curved inner surfaces that are supported by the support surface of the flexible substrate. Supported and provided in a curved structure, such as a curved structure having a curled, wavy, ribbed and/or pleated configuration. The curved inner surface of the additional integrated device assembly and the extendable semiconductor can have substantially the same or different contour shapes. The present invention includes embodiments in which the extendable device components are interconnected via metal interconnects that exhibit substantial extensibility or metal interconnects that also have a wavy, wrinkled, curved, and/or raised configuration.

額外積體裝置組件之曲線內表面組態係藉由諸如捲曲、波形、翹棱及/或皺褶組態之電子裝置的一總體上彎曲結構提供於某些實施例中。在此等實施例中，彎曲結構使此等裝置即使當承受顯著應變時也能展示良好電子效能，諸如當處於延伸、壓縮及/或彎曲組態時保持與一半導體元件之導電性或絕緣性。可延伸電子電路可使用與如此處描述之彼等用以製造可延伸半導體元件之技術類似的技術來製造。舉例而言，在一實施例中，包括一可延伸半導體元件之可延伸裝置組件係獨立製造且然後互連。或者，一包含半導體之裝置可以一平坦組態來製造，且隨後處理所得平坦裝置以提供一總體上彎曲的裝置結構，其具有某些或所有裝置組件之曲線內表面。 The curved inner surface configuration of the additional integrated device assembly is provided in certain embodiments by a generally curved structure of an electronic device such as a crimp, wave, rib, and/or wrinkle configuration. In such embodiments, the curved structure enables such devices to exhibit good electrical performance even when subjected to significant strain, such as maintaining electrical or insulating properties with a semiconductor component when in an extended, compressed, and/or curved configuration. . Extensible electronic circuits can be fabricated using techniques similar to those described herein for fabricating extensible semiconductor components. For example, in one embodiment, an extendable device component including an extendable semiconductor component is fabricated separately and then interconnected. Alternatively, a device comprising a semiconductor can be fabricated in a flat configuration and the resulting planar device can then be processed to provide a generally curved device structure having curved inner surfaces of some or all of the device components.

本發明包括可延伸電子裝置，該等電子裝置包含具有由單一可撓性基板支撐之曲線內表面之單一電子裝置。或者，本發明包括可延伸電子裝置陣列，該等陣列包含複數個可延伸電子裝置或裝置組件，每一者具有由單一可撓性基板支撐之曲線內表面。可選擇地，本發明之裝置陣列中之可延伸電子裝置具有良好界定的、預選擇之實體尺寸、位置及相對空間取向。 The present invention includes extendable electronic devices including a single electronic device having a curved inner surface supported by a single flexible substrate. Alternatively, the invention includes an array of extendable electronic devices comprising a plurality of extendable electronic devices or device components, each having a curved inner surface supported by a single flexible substrate. Alternatively, the extendable electronics in the array of devices of the present invention have well defined, pre-selected physical dimensions, locations, and relative spatial orientations.

在本發明之某些實施例中，半導體結構或電子裝置之曲線內表面係由一彎曲結構來提供。本發明之半導體及/或電子裝置之彎曲結構及曲線內表面可具有提供可延伸性及/或可撓性的任何輪廓形狀，包括(但不限於)以至少一個凸起區域、至少一凹入區域或至少一個凸起區域與至少一個凹入區域之一組合為特徵之輪廓形狀。本發明中有用之輪廓形狀包括在一個或兩個空間維度上變化之輪廓形狀。使用具有一內表面(其具有在多個空間維度上展示週期或非週期變化之輪廓形狀)之彎曲結構有助於提供能在包括正交的方向之多個方向上延伸、壓縮、撓曲或進行其他變形之可延伸半導體及/或電子裝置。 In some embodiments of the invention, the curved inner surface of the semiconductor structure or electronic device is provided by a curved structure. The curved structure and curved inner surface of the semiconductor and/or electronic device of the present invention may have any contour shape that provides extensibility and/or flexibility, including but not limited to, at least one raised region, at least one recessed The region or at least one raised region is combined with one of the at least one recessed region as a characteristic contour shape. Contour shapes useful in the present invention include contour shapes that vary in one or two spatial dimensions. The use of a curved structure having an inner surface that exhibits a periodic or aperiodic profile shape in multiple spatial dimensions helps provide extension, compression, flexing, or the ability to extend in multiple directions including orthogonal directions. Other variants of extendable semiconductors and/or electronic devices.

有用之實施例包括由彎曲半導體結構及/或電子裝置提供的曲線內表面，該等彎曲半導體結構及/或電子裝置具有包含複數個凸起及凹入區域之構形，例如以波形組態提供之凸起與凹入區域之交替圖案。在一實施例中，可延伸及/或可撓性半導體元件或電子裝置之曲線內表面，或(視情況)整個截面組件具有以大體上週期波形或者大體上非週期波形為特徵之輪廓形狀。在本文中，週期波形可包含任何兩維或三維維度波形，包括(但不限於)一或多個正弦波、方波、Aries函數、高斯(Gaussian)波形、洛仁子(Lorentzian)波形，或此等波形之組合。在另一實施例中，半導體或電子裝置之曲線內表面，或(視情況)整個截面組件具有由複數個具有較大振幅及寬度之非週期翹棱組成的輪廓形狀。在另一實施例中，半導體或電子裝置之曲線內表面，或 (視情況)整個截面組件具有由週期波形及複數個非週期翹棱組成的輪廓形狀。 Useful embodiments include curved inner surfaces provided by curved semiconductor structures and/or electronic devices having configurations including a plurality of raised and recessed regions, such as provided in a waveform configuration An alternating pattern of raised and recessed areas. In one embodiment, the curved inner surface of the extendable and/or flexible semiconductor component or electronic device, or (as appropriate) the entire cross-sectional component has a contoured shape characterized by a substantially periodic waveform or a substantially non-periodic waveform. In this context, the periodic waveform may comprise any two- or three-dimensional dimensional waveform including, but not limited to, one or more sine waves, square waves, Aries functions, Gaussian waveforms, Lorentzian waveforms, or the like. A combination of equal waveforms. In another embodiment, the curved inner surface of the semiconductor or electronic device, or (as appropriate) the entire cross-sectional assembly has a contoured shape comprised of a plurality of non-periodic warps having a large amplitude and width. In another embodiment, the curved inner surface of the semiconductor or electronic device, or (As appropriate) The entire cross-section assembly has a contour shape consisting of a periodic waveform and a plurality of non-periodic warps.

在一實施例中，本發明之可延伸半導體元件或電子裝置包含一彎曲結構，諸如一具有沿其長度及(視情況)寬度之至少一部分擴展的一週期或非週期波形構形之彎曲帶狀結構。舉例而言，本發明包括彎曲結構，該等彎曲結構包括具有一週期在約1微米與100微米之間且振幅在約50奈米與約5微米之間的正弦波構形之彎曲帶狀結構。彎曲結構可以其他週期波形構形提供，諸如沿此等結構之至少一部分長度及/或寬度擴展之方波及/或高斯波形。包含彎曲帶狀結構之可延伸及可撓性半導體元件及可延伸電子裝置可沿著沿該半導體帶之長度擴展的軸(諸如沿該曲線內表面之第一波形方向擴展之軸)膨脹、壓縮、彎曲及/或變形，且(視情況)可沿一或多個其他軸(諸如沿該等彎曲結構及曲線內表面之其他波形方向擴展之軸)膨脹、壓縮、彎曲及/或變形。 In one embodiment, the extendable semiconductor component or electronic device of the present invention comprises a curved structure, such as a curved ribbon having a periodic or aperiodic waveform configuration extending along at least a portion of its length and, optionally, the width. structure. By way of example, the present invention includes curved structures comprising a curved ribbon structure having a sinusoidal configuration with a period between about 1 micrometer and 100 micrometers and an amplitude between about 50 nanometers and about 5 micrometers. . The curved structure may be provided in other periodic waveform configurations, such as a square wave and/or a Gaussian waveform extending along at least a portion of the length and/or width of the structures. The extensible and flexible semiconductor component and the extendable electronic device comprising the curved strip structure are expandable and compressible along an axis extending along the length of the semiconductor strip, such as an axis extending along a first waveform of the inner surface of the curved surface. , curved and/or deformed, and (as appropriate) may expand, compress, bend and/or deform along one or more other axes, such as an axis extending along the curved structures and other directions of the inner surface of the curved surface.

在某些實施例中，本發明之此態樣之半導體結構及電子裝置的構形當受到機械應力或被施加力時會改變。舉例而言，具有波形或翹棱構形之彎曲半導體結構及電子裝置之週期及/或振幅可回應於所施加機械應力及/或力而改變。在某些實施例中，此改變構形之能力提供了可延伸半導體結構及電子電路膨脹、壓縮、撓曲、變形及/或彎曲而無顯著機械損傷、破裂或實質性的電子性質及/或電子裝置效能之降低的能力。 In some embodiments, the configuration of the semiconductor structure and electronic device of this aspect of the invention may change when subjected to mechanical stress or when a force is applied. For example, the period and/or amplitude of a curved semiconductor structure and electronic device having a wavy or warped configuration may vary in response to applied mechanical stress and/or force. In some embodiments, the ability to modify the configuration provides for extensible semiconductor structures and electronic circuits to expand, compress, flex, deform, and/or bend without significant mechanical damage, cracking, or substantial electronic properties and/or The ability to reduce the performance of electronic devices.

該半導體結構及/或可延伸電子裝置之曲線內表面可連續地結合至該支撐表面(意即在沿該曲線內表面之大體上所有點(例如約90%)處結合)。或者，該半導體結構及/或可延伸電子裝置之曲線內表面可間斷地與該支撐表面結合，其中該曲線內表面在沿該曲線內表面的所選點處與該支撐表面結合。本發明包括實施例，其中該半導體結構或電子裝置之曲線內表面與該可撓性基板在離散點處結合，且在該內表面 與該可撓性基板之間的離散的結合點之間該內表面具有一曲線構形。本發明包括具有一內表面之彎曲半導體結構及電子裝置，該內表面與該可撓性基板在離散點處結合，其中該等離散的結合點藉由未與該可撓性基板直接結合之翹棱區域而彼此隔離。 The curved inner surface of the semiconductor structure and/or the extendable electronic device can be continuously bonded to the support surface (i.e., bonded at substantially all points (e.g., about 90%) along the inner surface of the curve). Alternatively, the curved inner surface of the semiconductor structure and/or the extendable electronic device can be intermittently bonded to the support surface, wherein the curved inner surface is bonded to the support surface at selected points along the inner surface of the curve. The invention includes an embodiment wherein a curved inner surface of the semiconductor structure or electronic device is bonded to the flexible substrate at discrete points, and the inner surface The inner surface has a curved configuration between discrete bonding points with the flexible substrate. The present invention includes a curved semiconductor structure having an inner surface and an electronic device bonded to the flexible substrate at discrete points, wherein the discrete bonding points are not directly bonded to the flexible substrate The edges are isolated from each other.

在本發明之某些可撓性半導體及/或可撓性電子裝置中，僅半導體結構或電子裝置之內表面以一曲線構形提供。或者，本發明包括以一彎曲構形提供之可延伸半導體及可延伸電子裝置，其中該彎曲半導體結構或電子裝置之整個截面組件以一曲線構形提供，諸如波形、皺褶、翹棱或捲曲構形。在此等實施例中，該曲線構形擴展穿過該半導體結構或電子裝置之至少一部分的整個厚度。舉例而言，本發明之可延伸半導體包括具有波形、皺褶、翹棱及/或捲曲組態之彎曲半導體帶或條。本發明亦包括組合物或電子裝置，其中整個半導體結構或電子裝置，或該半導體結構或電子裝置之至少大部分以一曲線構形提供，諸如波形、皺褶或彎曲構形。 In some flexible semiconductor and/or flexible electronic devices of the present invention, only the inner surface of the semiconductor structure or electronic device is provided in a curved configuration. Alternatively, the invention includes an extendable semiconductor and extendable electronic device provided in a curved configuration, wherein the entire cross-sectional assembly of the curved semiconductor structure or electronic device is provided in a curved configuration, such as a wave, wrinkles, ridges or curls Configuration. In such embodiments, the curved configuration extends through the entire thickness of at least a portion of the semiconductor structure or electronic device. For example, the extensible semiconductor of the present invention includes a curved semiconductor strip or strip having a wavy, wrinkled, warped, and/or crimped configuration. The invention also includes compositions or electronic devices in which the entire semiconductor structure or electronic device, or at least a majority of the semiconductor structure or electronic device, is provided in a curved configuration, such as a wavy, wrinkled or curved configuration.

在某些實施例中，該波形、翹棱及/或可延伸構形提供了一種調節本發明之組合物、材料及裝置之性質的適用性的途徑。舉例而言，半導體之遷移率及其觸點之性質至少部分地取決於應變。本發明中空間變化的應變有助於以有利的方式調節材料及裝置性質。如另一實例，在波導中之空間變化之應變引起空間變化之折射率性質(經由彈光效應)，其亦可有利地用於不同類型光柵耦合器。 In certain embodiments, the waveform, warp and/or extendable configuration provides a means of adjusting the suitability of the properties of the compositions, materials and devices of the present invention. For example, the mobility of a semiconductor and the nature of its contacts depend, at least in part, on strain. The spatially varying strain in the present invention helps to adjust the material and device properties in an advantageous manner. As another example, the spatially varying strain in the waveguide causes spatially varying refractive index properties (via the bounce effect), which may also be advantageously used for different types of grating couplers.

可延伸半導體結構及/或電子裝置之內表面與可撓性基板的外表面之間的結合可使用任何可提供機械上有用之系統的組合物、結構或結合機制來提供，該機械上有用之系統應能承受延伸及/壓縮移位而無機械失效或電子性質及/或效能之顯著降級且(視情況)能撓曲移位而無機械失效或電子性質及/或效能的顯著降級。該半導體結構及/或電子裝置與該可撓性基板之間的有用之結合提供了當處於多種延伸、壓 縮及/或撓曲組態或變形時展示有益的電子性質之機械穩固結構。在本發明之此態樣之一實施例中，該半導體結構及/或電子裝置之內表面之至少一部分與該可撓性基板的外表面之間之結合係藉由該半導體結構或電子裝置與該可撓性基板之外表面之間的共價及/或非共價鍵結來提供。此等結構中有用之例示性結合機制包括使用該半導體結構或電子裝置與該可撓性基板之外表面之間的凡得瓦爾力交互作用、偶極-偶極交互作用及/或氫鍵結交互作用。本發明亦包括實施例，其中結合係藉由該半導體結構或電子裝置與該可撓性基板之外表面之間的一黏接或層壓層、塗層或薄膜來提供。有用之黏接層包括(但不限於)金屬層、聚合物層、部分聚合化聚合物前驅層，及複合材料層。本發明亦包括使用具有一化學改質之外表面之可撓性基板，以便利(例如)具有置於其外表面上之複數個羥基基團的可撓性基板(諸如聚合物基板)與半導體元件或電子裝置之結合。本發明包括可撓性半導體及電子電路，其中該半導體結構或電子電路整體或部分地囊封於一囊封層或塗層中，諸如一聚合物層。 The bond between the inner surface of the extendable semiconductor structure and/or electronic device and the outer surface of the flexible substrate can be provided using any composition, structure or bonding mechanism that provides a mechanically useful system that is useful in mechanical use. The system should be able to withstand extension and/or compression displacement without mechanical failure or significant degradation of electronic properties and/or performance and (as appropriate) flexural displacement without mechanical failure or significant degradation of electronic properties and/or performance. The useful combination of the semiconductor structure and/or electronic device with the flexible substrate provides for a variety of extensions, pressures A mechanically stable structure that exhibits beneficial electronic properties when shrunk and/or flexed or deformed. In an embodiment of this aspect of the invention, the bonding between at least a portion of the inner surface of the semiconductor structure and/or the electronic device and the outer surface of the flexible substrate is performed by the semiconductor structure or electronic device Covalent and/or non-covalent bonding between the outer surfaces of the flexible substrate is provided. Exemplary binding mechanisms useful in such structures include van der Waals interaction, dipole-dipole interaction, and/or hydrogen bonding between the semiconductor structure or electronic device and the outer surface of the flexible substrate. Interaction. The invention also includes embodiments in which bonding is provided by a bonded or laminated layer, coating or film between the semiconductor structure or electronic device and the outer surface of the flexible substrate. Useful bonding layers include, but are not limited to, metal layers, polymer layers, partially polymerized polymer precursor layers, and composite layers. The invention also includes the use of a flexible substrate having a chemically modified outer surface to facilitate, for example, a flexible substrate (such as a polymer substrate) and a semiconductor having a plurality of hydroxyl groups disposed on an outer surface thereof. A combination of components or electronic devices. The present invention includes flexible semiconductors and electronic circuits in which the semiconductor structure or electronic circuit is wholly or partially encapsulated in an encapsulation layer or coating, such as a polymeric layer.

該半導體結構或電子裝置之實體尺寸及組合物至少部分地影響本發明之可延伸半導體元件的總體機械及電子性質。如本文所使用，術語"薄"指一結構具有一小於或等於約100微米之厚度，且對於某些應用較佳為小於或等於約50微米之厚度。諸如薄半導體帶、小板及條或薄膜電晶體之薄半導體結構或電子裝置之使用在某些實施例中係重要的，以便利諸如波形、捲曲或彎曲曲線內表面之曲線內表面之形成，從而提供能延伸、收縮及/或撓曲而無損傷、機械失效或電子性質的顯著降級之構形。諸如薄可印刷半導體結構之薄半導體結構及電子裝置之使用對包含諸如單晶及/或多晶無機半導體的脆性半導體材料之可延伸半導體及可延伸電子裝置尤其有用。在一有用之實施例中，該半導體結構或電子電路具有在約1微米至約1厘米之範圍上選擇 之寬度及在約50奈米至約50微米的範圍上選擇之厚度。 The physical dimensions and compositions of the semiconductor structure or electronic device at least partially affect the overall mechanical and electronic properties of the extensible semiconductor component of the present invention. As used herein, the term "thin" means that a structure has a thickness of less than or equal to about 100 microns, and for some applications is preferably less than or equal to about 50 microns. The use of thin semiconductor structures or electronic devices such as thin semiconductor strips, small plates and strip or thin film transistors is important in certain embodiments to facilitate the formation of curved inner surfaces such as corrugated, curled or curved inner surfaces. Thereby providing a configuration that can be extended, shrunk and/or flexed without damage, mechanical failure or significant degradation of electronic properties. The use of thin semiconductor structures such as thin printable semiconductor structures and electronic devices is particularly useful for extensible semiconductors and extendable electronic devices comprising brittle semiconductor materials such as single crystal and/or polycrystalline inorganic semiconductors. In a useful embodiment, the semiconductor structure or electronic circuit has a range of from about 1 micron to about 1 centimeter. The width and thickness selected over a range of from about 50 nanometers to about 50 microns.

該支撐可撓性基板之組合物及實體尺寸亦可至少部分地影響本發明之可延伸半導體元件及可延伸電子裝置的總體機械性質。有用之可撓性基板包括(但不限於)厚度選自約0.1毫米至約100微米之範圍的可撓性基板。在一有用之實施例中，該可撓性基板包含一聚(二甲基矽氧烷)PDMS層，且具有在約0.1毫米至約10毫米的範圍上選擇之厚度。 The composition and physical dimensions of the support flexible substrate can also at least partially affect the overall mechanical properties of the extensible semiconductor component and the extendable electronic device of the present invention. Useful flexible substrates include, but are not limited to, flexible substrates having a thickness selected from the range of from about 0.1 mm to about 100 microns. In a useful embodiment, the flexible substrate comprises a poly(dimethyloxane) PDMS layer and has a thickness selected from the range of from about 0.1 mm to about 10 mm.

本發明亦包括部分處理之可延伸半導體元件或部分處理之可延伸半導體電路。舉例而言，在一實施例中，本發明包括Si帶，其上具有pn二極體裝置。以一波形構形提供之Si帶被可選擇地提供於一PDMS基板上。於此等(絕緣)二極體之間提供互連件，以使得該二極體輸出(例如，光電流)能被放大，例如經由利用蔭罩(shadow mask)之金屬蒸鍍。在一實施例中，在彈性體上製造複數個獨立的可延伸電晶體。以某些方式連線個別電晶體(例如藉由蔭罩蒸鍍)以製造其他有用之電路，例如由以特定方式連接之若干電晶體組成之電路。對於此等狀況，該等互連金屬線亦為可延伸的，因此吾人具有在彈性體上的完全可延伸電路。 The invention also includes a partially processed extensible semiconductor component or a partially processed extensible semiconductor circuit. For example, in one embodiment, the invention includes a Si strip having a pn diode device thereon. A Si strip provided in a waveform configuration is optionally provided on a PDMS substrate. Interconnects are provided between the (insulated) diodes such that the diode output (e.g., photocurrent) can be amplified, such as by metal evaporation using a shadow mask. In one embodiment, a plurality of individual extendable transistors are fabricated on the elastomer. Individual transistors are wired in some manner (e.g., by shadow mask evaporation) to make other useful circuits, such as circuits composed of a number of transistors connected in a particular manner. For these conditions, the interconnecting wires are also extendable, so that we have fully extendable circuitry on the elastomer.

在另一態樣中，本發明提供用以製造一可延伸半導體元件之方法，其包含以下步驟：(1)提供具有內表面之可轉移半導體結構；(2)提供處於一膨脹狀態之預應變彈性基板，其中該彈性基板具有一外表面；(3)將該可轉移半導體結構的內表面之至少一部分與處於膨脹狀態之預應變彈性基板之外表面結合；及(4)允許彈性基板至少部分地鬆弛至一鬆弛狀態，其中該彈性基板的鬆弛使該可轉移半導體結構之內表面彎曲，進而產生具有一曲線內表面之可延伸半導體元件。在本發明之此態樣之某些實施例中，該預應變彈性基板沿第一軸膨脹，且視情況沿一相對該第一軸正交地定位的第二軸膨脹。在一有用之實施 例中，提供至該預應變彈性基板之可轉移半導體元件係一可印刷半導體元件。 In another aspect, the present invention provides a method for fabricating an extensible semiconductor device comprising the steps of: (1) providing a transferable semiconductor structure having an inner surface; (2) providing a pre-strain in an expanded state An elastic substrate, wherein the elastic substrate has an outer surface; (3) bonding at least a portion of an inner surface of the transferable semiconductor structure to an outer surface of the pre-strained elastic substrate in an expanded state; and (4) allowing at least a portion of the elastic substrate The ground relaxes to a relaxed state in which the relaxation of the elastic substrate bends the inner surface of the transferable semiconductor structure, thereby producing an extendable semiconductor component having a curved inner surface. In some embodiments of this aspect of the invention, the pre-strained resilient substrate expands along a first axis and optionally expands along a second axis that is orthogonally positioned relative to the first axis. In a useful implementation In one example, the transferable semiconductor component provided to the pre-strained elastic substrate is a printable semiconductor component.

在另一態樣中，本發明提供一用以製造一可延伸電子電路之方法，其包含以下步驟：(1)提供一具有一內表面之可轉移電子電路；(2)提供處於一膨脹狀態之預應變彈性基板，其中該彈性基板具有一外表面；(3)將該可轉移電子電路的內表面之至少一部分與處於膨脹狀態之預應變彈性基板之外表面結合；及(4)允許該彈性基板至少部分地鬆弛至一鬆弛狀態，其中該彈性基板的鬆弛使該電子電路之內表面彎曲，進而產生該可延伸電子電路。在一有用之實施例中，提供至該預應變彈性基板之可轉移電子電路係一可印刷電子電路，諸如能經由印刷技術(諸如乾式轉移接觸印刷)轉移之電子電路。在某些實施例中，電子電路包含複數個積體裝置組件，包括(但不限於)：一或多個半導體元件(諸如可轉移、且(視情況)可印刷之半導體元件)、介電元件、電極、包括超導元件之導電元件、及摻雜半導體元件。 In another aspect, the invention provides a method for fabricating an extendable electronic circuit comprising the steps of: (1) providing a transferable electronic circuit having an inner surface; (2) providing an expanded state a pre-strained elastic substrate, wherein the elastic substrate has an outer surface; (3) combining at least a portion of an inner surface of the transferable electronic circuit with an outer surface of the pre-strained elastic substrate in an expanded state; and (4) allowing the The elastic substrate is at least partially relaxed to a relaxed state, wherein slack of the elastic substrate bends an inner surface of the electronic circuit to produce the extendable electronic circuit. In a useful embodiment, the transferable electronic circuit provided to the pre-strained flexible substrate is a printable electronic circuit, such as an electronic circuit that can be transferred via printing techniques, such as dry transfer contact printing. In some embodiments, an electronic circuit includes a plurality of integrated device components including, but not limited to, one or more semiconductor components (such as transferable and (as appropriate) printable semiconductor components), dielectric components , an electrode, a conductive element including a superconducting element, and a doped semiconductor element.

可選地，本發明之該態樣之方法可進一步包含自該支撐彈性基板將該可延伸半導體或可延伸電子電路轉移至一接收基板之步驟，該轉移之方式至少部分地保留該半導體元件或電子電路的曲線內表面及/或彎曲結構。該半導體結構或電子電路被轉移至一接收基板，該接收基板係可撓性的，諸如一聚合物接收基板，或一包含紙、金屬或半導體之接收基板。在此實施例中，所轉移之可延伸半導體或可延伸電子裝置可經由廣泛範圍之手段而與該接收基板(如一可撓性、聚合物接收基板)結合，該等手段包括(但不限於)使用黏接及/或層壓層、薄膜及/或塗層，諸如黏接層(如聚醯亞胺膠層)。或者，所轉移的可延伸半導體或可延伸電子裝置可經由所轉移的可延伸半導體或可延伸電子裝置與接收基板之間之氫鍵結、共價鍵結、偶極-偶極交互作用及凡得瓦爾力交互作用而與諸如可撓性、聚合物接收基板的接收基板結 合。 Optionally, the method of the aspect of the invention may further comprise the step of transferring the extendable semiconductor or the extendable electronic circuit from the supporting elastic substrate to a receiving substrate, the transferring manner at least partially retaining the semiconductor element or The curved inner surface and/or curved structure of the electronic circuit. The semiconductor structure or electronic circuit is transferred to a receiving substrate that is flexible, such as a polymer receiving substrate, or a receiving substrate comprising paper, metal or semiconductor. In this embodiment, the transferred extendable semiconductor or extendable electronic device can be combined with the receiving substrate (such as a flexible, polymer receiving substrate) via a wide range of means including, but not limited to, Adhesive and/or laminate layers, films and/or coatings are used, such as adhesive layers (eg, polyimide layers). Alternatively, the transferred extensible semiconductor or extensible electronic device can be hydrogen bonded, covalently bonded, dipole-dipole interaction and transferred between the transferred extensible semiconductor or extendable electronic device and the receiving substrate Valel force interaction with a receiving substrate junction such as a flexible, polymer receiving substrate Hehe.

在一實施例中，在製造具有由一彈性基板支撐之波形、翹棱、皺褶或捲曲構形之彎曲半導體結構及/或電子電路後，使用一適當黏接層或塗層將此等結構轉移至另一基板上。舉例而言，在一實施例中，在一彈性體基板上製備波形光伏打裝置，且然後(例如)使用聚醯亞胺作為膠層將其轉移至金屬箔上。在該等光伏打裝置與下層的金屬箔(其可充當集極之一，例如藉由圖案化、蝕刻以製造通孔以曝露金屬表面、金屬沈積物等等)之間建立電連接。此組態之光伏打裝置之波狀表面可被利用以增強光捕獲(或減少光反射)。舉例而言，為獲得更好之抗反射結果，可在此波狀表面上作進一步處理，諸如使表面粗糙度遠小於波狀半導體之波長。簡單說來，可將部分或全部處理之波狀/彎曲半導體/電路轉移至其他基板上(不限於PDMS)，且若必要可藉由添加進一步處理來獲得更增強的使用效能。 In one embodiment, after fabricating a curved semiconductor structure and/or electronic circuit having a wave, ridge, wrinkle or crimp configuration supported by an elastomeric substrate, the structure is formed using a suitable adhesive layer or coating. Transfer to another substrate. For example, in one embodiment, a corrugated photovoltaic device is fabricated on an elastomeric substrate and then transferred to a metal foil, for example, using polyimine as a subbing layer. Electrical connections are established between the photovoltaic devices and the underlying metal foil (which may act as one of the collectors, such as by patterning, etching to make vias to expose metal surfaces, metal deposits, etc.). The wavy surface of this configured photovoltaic device can be utilized to enhance light capture (or reduce light reflection). For example, to obtain better anti-reflection results, further processing can be performed on the wavy surface, such as to make the surface roughness much smaller than the wavelength of the wavy semiconductor. Briefly, some or all of the processed corrugated/curved semiconductor/circuit can be transferred to other substrates (not limited to PDMS), and further processing can be added to obtain more enhanced performance if necessary.

可選地，本發明之方法可進一步包含囊封、覆蓋或層壓該可延伸半導體或可延伸電子裝置之步驟。在此上下文中，囊封在分層翹棱結構之狀況下包括其中該囊封材料被提供於該等翹棱之凸起區域下以完全嵌入該翹棱結構的所有側面的幾何形狀及構形。囊封亦包括在該彎曲半導體結構或電子電路之凸起及未凸起特徵之頂部提供一囊封層，諸如聚合物層。在一實施例中，將諸如PDMS預聚合物之預聚合物澆鑄並固化於該可延伸半導體或可延伸電子裝置上。對於某些應用，囊封或覆蓋處理步驟有助於增強本發明之可延伸半導體及電子裝置之機械穩定性及穩固性。本發明包括當處於延伸、壓縮、彎曲及/或撓曲構形時展示良好機械及電子效能之囊封、覆蓋及/或層壓之可延伸半導體及電子裝置。 Alternatively, the method of the present invention may further comprise the step of encapsulating, covering or laminating the extensible semiconductor or extendable electronic device. In this context, the encapsulation, in the case of a layered rib structure, includes the geometry and configuration in which the encapsulation material is provided under the raised regions of the ridges to fully embed all sides of the rib structure. . Encapsulation also includes providing an encapsulation layer, such as a polymer layer, on top of the raised and unembossed features of the curved semiconductor structure or electronic circuit. In one embodiment, a prepolymer such as a PDMS prepolymer is cast and cured onto the extensible semiconductor or extendable electronic device. For some applications, the encapsulation or overlay processing steps help to enhance the mechanical stability and robustness of the extensible semiconductor and electronic devices of the present invention. The present invention includes expandable semiconductor and electronic devices that exhibit good mechanical and electrical performance when encapsulated, covered and/or laminated in extended, compressed, curved and/or flexed configurations.

可選地，本發明之此態樣之方法包括在諸如聚合物基板(例如，2D超薄聚合物基板)或無機基板(例如SiO2)之供體基板上組裝半導體 元件、裝置組件及/或功能性裝置之步驟。在此實施例中，然後將在該供體基板上組裝之結構轉移至預應變彈性體基板以形成可延伸材料、裝置或裝置組件。在一實施例中，電晶體、電晶體陣列或具有電晶體之電子裝置首先被組裝在供體基板上，例如經由使用可印刷半導體元件之印刷技術。接著，將整個裝置及/或裝置陣列轉移至預應變彈性基板(例如藉由接觸印刷法)以形成可延伸波形及/或翹棱系統。當在轉移至可延伸彈性體支撐物之前在一薄的、非彈性體材料(類似聚醯亞胺或苯幷環丁烯或PET等等)上製備裝置互連件及製造實際尺寸電路較為有利時此方法係有用的。在此類系統中，在組合電晶體/聚合物膜/彈性體基板系統中將獲得非週期2D波形或翹棱結構。 Optionally, the method of this aspect of the invention includes assembling semiconductor components, device components, and/or on a donor substrate such as a polymer substrate (eg, a 2D ultra-thin polymer substrate) or an inorganic substrate (eg, SiO 2 ). The steps of the functional device. In this embodiment, the structure assembled on the donor substrate is then transferred to a pre-strained elastomeric substrate to form an extensible material, device or device assembly. In an embodiment, a transistor, an array of transistors, or an electronic device having a transistor is first assembled on a donor substrate, such as via printing techniques using printable semiconductor components. Next, the entire device and/or array of devices is transferred to a pre-strained elastic substrate (eg, by contact printing) to form an extendable waveform and/or warp rib system. It is advantageous to fabricate device interconnects and fabricate actual size circuits on a thin, non-elastomeric material (like polythenimine or benzoquinone cyclobutene or PET, etc.) prior to transfer to the extensible elastomeric support. This method is useful. In such systems, aperiodic 2D waveforms or warped structures will be obtained in a combined transistor/polymer film/elastomer substrate system.

對在本方法中有用的彈性基板進行預應變之方法包括在與半導體結構及/或電子裝置接觸及結合之前及/或期間中彎曲、捲曲、撓曲、及膨脹該彈性基板(例如，藉由使用一機械平臺)。在多個方向上預應變彈性基板之一尤其有用之方法包含在與半導體結構及/或電子裝置接觸及結合之前及/或期間中藉由升高彈性基板的溫度而使該彈性基板熱膨脹。在此等實施例中，彈性基板的鬆弛是藉由在與該可轉移、且(視情況)可印刷之半導體元件或電子裝置接觸及/或結合之後降低該彈性基板之溫度來達成。在某些方法中，藉由引入約1%至約30%之應變來將該彈性基板預應變。 The method of pre-straining an elastic substrate useful in the method includes bending, crimping, flexing, and expanding the elastic substrate before and/or during contact and bonding with the semiconductor structure and/or the electronic device (eg, by Use a mechanical platform). One method that is particularly useful for one of the pre-strained elastomeric substrates in multiple directions involves thermally expanding the elastomeric substrate by increasing the temperature of the elastomeric substrate before and/or during contact with and in combination with the semiconductor structure and/or electronic device. In such embodiments, the relaxation of the elastic substrate is achieved by lowering the temperature of the flexible substrate after contact and/or bonding with the transferable and (as appropriate) printable semiconductor component or electronic device. In some methods, the elastic substrate is pre-strained by introducing a strain of from about 1% to about 30%.

在本文中，表述"彈性基板"指可延伸或變形且可返回至其原始形狀而無實質上永久變形之基板。彈性基板通常承受實質上彈性的變形。本發明中有用之例示性彈性基板包括(但不限於)彈性體及彈性體、展示彈性之聚合物及共聚物之複合材料或混合物。在某些方法中，經由一提供該彈性基板沿一或多個主軸膨脹之機構來預應變該彈性基板。舉例而言，可藉由沿第一軸膨脹該彈性基板來提供預應變。然而，本發明亦包括沿複數個軸使該彈性基板膨脹之方法，例如經由 沿相對彼此正交定位之第一及第二軸的膨脹。本方法中可用的經由提供彈性基板之膨脹的機構而預應變彈性基板之手段包括彎曲、捲曲、撓曲、整平、膨脹或以其它方式使該彈性基板變形。本發明亦包括藉由升高該彈性基板之溫度進而提供該彈性基板的熱膨脹而提供預應變之手段。 As used herein, the expression "elastic substrate" refers to a substrate that can be extended or deformed and can be returned to its original shape without substantial permanent deformation. Elastomeric substrates typically undergo substantial elastic deformation. Exemplary elastic substrates useful in the present invention include, but are not limited to, elastomers and elastomers, composites or mixtures of elastomeric polymers and copolymers. In some methods, the resilient substrate is pre-strained via a mechanism that provides expansion of the elastomeric substrate along one or more spindles. For example, the pre-strain can be provided by expanding the elastic substrate along a first axis. However, the invention also includes a method of expanding the elastic substrate along a plurality of axes, for example via Expansion of the first and second axes positioned orthogonally relative to one another. The means available in the method for pre-straining the elastic substrate via a mechanism that provides expansion of the elastic substrate includes bending, crimping, flexing, leveling, expanding, or otherwise deforming the elastic substrate. The present invention also includes means for providing pre-strain by increasing the temperature of the elastomeric substrate to provide thermal expansion of the elastomeric substrate.

本發明之方法亦能自不同於半導體材料之材料製造可延伸元件、裝置及裝置組件。本發明包括將諸如絕緣體、超導體，及半金屬之非半導體結構轉移並結合至一預應變彈性基板之方法。允許彈性基板至少部分地鬆弛會導致具有曲線內表面之可延伸非半導體結構(例如具有波形及/或翹棱輪廓形狀之非半導體結構)的形成。本發明之此態樣包括具有彎曲結構之可延伸非半導體結構，該彎曲結構諸如以捲曲構形、皺褶構形、翹棱構形及/或以波形組態提供之內表面及(視情況)外表面。 The method of the present invention can also produce extensible elements, devices and device components from materials other than semiconductor materials. The present invention includes a method of transferring and bonding a non-semiconductor structure such as an insulator, a superconductor, and a semimetal to a pre-strained elastic substrate. Allowing at least partial relaxation of the elastic substrate results in the formation of an extensible non-semiconductor structure having a curved inner surface, such as a non-semiconductor structure having a corrugated and/or chamfered profile. This aspect of the invention includes an extendable non-semiconductor structure having a curved configuration such as a crimped configuration, a pleated configuration, a raised configuration, and/or an inner surface provided in a wave configuration and (as appropriate) )The outer surface.

在本發明之可延伸半導體、電子裝置及/或裝置組件中有用之可撓性基板包括(但不限於)聚合物基板及/或塑膠基板。可延伸半導體包括包含一或多個可轉移、(視情況)可印刷之半導體結構(諸如可印刷半導體元件)之組合物，其由在製造期間預應變的一彈性基板支撐，以產生該半導體曲線內表面。或者，可延伸半導體包括包含一或多個可轉移半導體結構(諸如可印刷半導體元件)之組合物，其由不同於在製造期間預應變的彈性基板之可撓性基板支撐，以產生該半導體曲線內表面。舉例而言，本發明包括可延伸半導體，其中具有一曲線內表面之半導體結構被自該彈性基板轉移至一不同可撓性基板。 Flexible substrates useful in the extensible semiconductor, electronic device and/or device assemblies of the present invention include, but are not limited to, polymer substrates and/or plastic substrates. An extensible semiconductor includes a composition comprising one or more transferable, (as appropriate) printable semiconductor structures, such as printable semiconductor components, supported by an elastomeric substrate that is pre-strained during fabrication to produce the semiconductor curve The inner surface. Alternatively, the extendable semiconductor comprises a composition comprising one or more transferable semiconductor structures, such as a printable semiconductor component, supported by a flexible substrate different from the elastic substrate pre-strained during fabrication to produce the semiconductor curve The inner surface. For example, the invention includes an extendable semiconductor in which a semiconductor structure having a curved inner surface is transferred from the flexible substrate to a different flexible substrate.

700‧‧‧半導體元件 700‧‧‧Semiconductor components

705‧‧‧可撓性基板 705‧‧‧Flexible substrate

710‧‧‧支撐表面 710‧‧‧Support surface

715‧‧‧彎曲半導體結構 715‧‧‧Bending semiconductor structure

720‧‧‧曲線內表面 720‧‧‧ Curved inner surface

730‧‧‧變形軸 730‧‧‧ deformation axis

750‧‧‧凹入區域 750‧‧‧ recessed area

760‧‧‧起伏特徵 760‧‧‧ undulating features

776‧‧‧可印刷半導體結構 776‧‧‧ Printable semiconductor structure

777‧‧‧可撓性基板 777‧‧‧Flexible substrate

圖1提供一展示本發明之一可延伸半導體結構之原子力顯微圖。 Figure 1 provides an atomic force micrograph showing an extensible semiconductor structure of the present invention.

圖2展示一原子力顯微圖，其提供具有曲線內表面之半導體結構之展開視圖。 Figure 2 shows an atomic force micrograph showing an expanded view of a semiconductor structure having a curved inner surface.

圖3展示本發明之可延伸半導體結構之陣列的原子力顯微圖。 3 shows an atomic force micrograph of an array of extensible semiconductor structures of the present invention.

圖4展示本發明之可延伸半導體結構之光學顯微圖。 4 shows an optical micrograph of an extensible semiconductor structure of the present invention.

圖5展示本發明之具有一半導體結構之可延伸半導體結構的原子力顯微圖，該半導體結構與一具有三維起伏圖案之可撓性基板結合，該三維起伏圖案位於該基板之支撐表面上。 Figure 5 shows an atomic force micrograph of an extensible semiconductor structure having a semiconductor structure in accordance with the present invention in combination with a flexible substrate having a three-dimensional relief pattern on a support surface of the substrate.

圖6展示一說明製造本發明之可延伸半導體元件之例示性方法的流程圖。 Figure 6 shows a flow chart illustrating an exemplary method of fabricating the extensible semiconductor component of the present invention.

圖7展示具有由一可撓性橡膠基板支撐之波形曲線內表面之縱向對準的可延伸半導體結構之陣列的圖像。 Figure 7 shows an image of an array of extendable semiconductor structures having longitudinal alignment of the inner surface of a curved curve supported by a flexible rubber substrate.

圖8展示本發明之一可延伸半導體結構之截面影像，其中該可印刷半導體結構776由可撓性基板777來支撐。如圖8所示，可印刷半導體結構776具有內表面，該等內表面具有呈一週期波之輪廓形狀。 8 shows a cross-sectional image of an extensible semiconductor structure of the present invention, wherein the printable semiconductor structure 776 is supported by a flexible substrate 777. As shown in FIG. 8, the printable semiconductor structure 776 has an inner surface having a contour shape in the form of a periodic wave.

圖9A展示一說明製造可延伸薄膜電晶體之陣列的例示性方法之流程圖。圖9B展示處於鬆弛及延伸組態中之可延伸薄膜電晶體之陣列的光學顯微圖。 Figure 9A shows a flow chart illustrating an exemplary method of fabricating an array of extensible thin film transistors. Figure 9B shows an optical micrograph of an array of extensible thin film transistors in a relaxed and extended configuration.

圖10：在彈性體基板上建構可延伸單晶矽裝置之製程之示意性說明。第一步(頂部框)涉及單晶矽薄(厚度在20與320nm之間)元件或完整的積體裝置(意即電晶體、二極體等等)之製造，其藉由習知微影處理過程繼之以對絕緣物上矽(SOI)晶圓的頂部矽及SiO2層之蝕刻來完成。在此等程序之後，帶結構由下層的晶圓支撐但不與其結合(頂部框)。使一預應變彈性體基板(聚(二甲基矽氧烷)PDMS，藉由dL延伸)與該等帶之引線接觸以導致此等材料之間的結合(中部框)。剝離該PDMS，使該等帶結合於其表面上，且接著釋放該預應變使得該PDMS鬆弛回到其不受約束之狀態(無應力長度L)。該鬆弛導致在該等帶中自發性形成受到良好控制、極有週期性、可延伸之"波形"結構(底部框)。 Figure 10: Schematic illustration of a process for constructing an extendable single crystal germanium device on an elastomeric substrate. The first step (top box) involves the fabrication of a single crystal thin (between 20 and 320 nm thickness) elements or a complete integrated device (ie, a transistor, a diode, etc.) by conventional lithography The process is then completed by etching the top germanium and SiO 2 layers of the on-insulator (SOI) wafer. After these procedures, the ribbon structure is supported by the underlying wafer but not bonded to it (top frame). A pre-strained elastomeric substrate (poly(dimethyloxane) PDMS, extended by dL) is brought into contact with the leads of the ribbons to cause bonding between the materials (middle frame). The PDMS is stripped to bond the strips to its surface, and then the pre-strain is released such that the PDMS relaxes back to its unconstrained state (no stress length L). This relaxation results in the spontaneous formation of a well-controlled, highly periodic, extendable "waveform" structure (bottom frame) in the bands.

圖11：(A)在PDMS上波狀單晶矽帶(寬度=20μm；間距=20μm；厚度=100nm)之一大規模對準陣列的光學影像。(B)自(A)中展示之陣列中取得的四個波狀矽帶之有角度掃描電子顯微圖。該等波結構之波長及振幅在該陣列中極為一致。(C)作為沿PDMS上一波狀Si帶之位置的函數的表面高度(頂部框)及Si拉曼峰之波數(底部框)，分別藉由原子力及拉曼顯微法量測。該等線表示資料之正弦擬合。(D)作為矽之厚度的函數的波狀矽帶之振幅(頂部框)及波長(底部框)，皆針對PDMS中給定位準之預應變。該等線對應於計算，無任何擬合參數。 Figure 11: (A) Optical image of a massively aligned array of one of the wavy single crystal ruthenium strips (width = 20 μm; pitch = 20 μm; thickness = 100 nm) on PDMS. (B) An angled scanning electron micrograph of four corrugated ankle bands taken from the array shown in (A). The wavelengths and amplitudes of the equal wave structures are extremely uniform in the array. (C) The surface height (top frame) as a function of the position of a wavy Si band on the PDMS and the wave number (bottom frame) of the Si Raman peak were measured by atomic force and Raman microscopy, respectively. These lines represent the sinusoidal fit of the data. (D) The amplitude (top frame) and wavelength (bottom frame) of the wavy band as a function of the thickness of the crucible are all pre-strained for positioning in the PDMS. These lines correspond to calculations without any fitting parameters.

圖12：作為溫度之函數的翹棱波長。波長隨溫度增加之略微降低歸因於PDMS的熱收縮，其導致在愈高溫度下製備之樣品的波長愈短。 Figure 12: Warping wavelength as a function of temperature. The slight decrease in wavelength with temperature is attributed to the thermal shrinkage of the PDMS, which results in a shorter wavelength of the sample prepared at the higher temperature.

圖13：作為矽厚度之函數的矽應變峰值，針對約0.9%之預應變值。紅色符號對應於使用波長及振幅計算得的彎曲應變，該等波長及振幅是基於描述該翹棱過程之方程式而擷取的。黑色符號對應於類似的計算，但使用了藉由AFM量測之波長及振幅。 Figure 13: Peak strain of 矽 as a function of 矽 thickness, for a pre-strain value of about 0.9%. The red symbol corresponds to the bending strain calculated using the wavelength and amplitude, which are taken based on the equation describing the warping process. The black symbol corresponds to a similar calculation, but uses the wavelength and amplitude measured by AFM.

圖14：(A)PDMS基板上波狀單晶矽帶(寬度=20μm；厚度=100nm)之原子力顯微圖(AFM；左邊框)及起伏輪廓(右邊框；該等線係實驗資料之正弦擬合)。頂部、中部，及底部部分分別對應於當PDMS沿帶長度受到-7%(壓縮)、0%(未受力)及4.7%(延伸)的應變時之組態。(B)作為施加至PDMS基板之應變(頂部框)的函數的波狀矽帶之平均振幅(黑色)及波長變化(紅色)。為了波長量測，將不同的基板用於拉緊(圓周)及壓縮(方塊)。矽應變峰值為所施加應變(底部框)之函數。此等圖中之線表示計算，無任何自由擬合參數。 Figure 14: (A) Atomic force micrograph (AFM; left border) and undulating contour (right border; sine of the experimental data of the wavy single crystal 矽 tape (width = 20 μm; thickness = 100 nm) on the PDMS substrate Fitting). The top, middle, and bottom portions correspond to configurations when PDMS is subjected to strains of -7% (compression), 0% (unstressed), and 4.7% (extension) along the length of the strip. (B) Average amplitude (black) and wavelength change (red) of the wavy band as a function of the strain applied to the PDMS substrate (top frame). For wavelength measurement, different substrates are used for tensioning (circumference) and compression (squares). The 矽 strain peak is a function of the applied strain (bottom box). The lines in these figures represent calculations without any free-fitting parameters.

圖15：PDMS上波狀矽帶之AFM俯視影像，及在相對於該等帶之長維的一角度處估算出之切割線。 Figure 15: AFM top view image of the wavy ankle band on the PDMS, and the cut line estimated at an angle relative to the long dimension of the bands.

圖16：作為所施加應變之函數的矽帶應變。紅色符號對應於使 用波長及振幅藉由輪廓長度之數值積分而計算之應變，該等波長及振幅是使用描述該翹棱過程的方程式擷取。黑色符號對應於沿波狀Si帶在AFM表面輪廓中自表面與水平距離之比例量測得的應變。 Figure 16: Tensile strain as a function of applied strain. The red symbol corresponds to The strain is calculated by integrating the wavelength and amplitude by numerical integration of the length of the profile, which is obtained using an equation describing the warping process. The black symbol corresponds to the strain measured along the wavy Si band in the AFM surface profile in proportion to the surface to horizontal distance.

圖17：(A)處於所施加的-11%(頂部)、0%(中部)及11%(底部)應變下之PDMS基板上的可延伸單晶矽pn二極體的光學影像。鋁區域對應於薄(20nm)Al電極；粉色及綠區域對應於矽之n(硼)及p(磷)摻雜區域。(B)作為可延伸矽pn二極體之偏壓的函數的電流密度，在各種所施加應變位準下量測。標有"亮"及"暗"之曲線分別對應於曝露於環境光或遮蔽於環境光之裝置。實線展示模型化結果。(C)在所施加的-9.9%、0%及9.9%應變下量測之可延伸肖特基障壁矽MOSFET之電流-電壓特性(閘極電壓以1V步長自0V變化至-5V)。 Figure 17: (A) Optical image of a stretchable single crystal 矽 pn diode on a PDMS substrate with applied -11% (top), 0% (middle) and 11% (bottom) strain. The aluminum region corresponds to a thin (20 nm) Al electrode; the pink and green regions correspond to the n (boron) and p (phosphorus) doped regions of germanium. (B) Current density as a function of the bias of the extendable 矽 pn diode, measured at various applied strain levels. The curves labeled "Bright" and "Dark" correspond to devices that are exposed to ambient light or shaded to ambient light, respectively. The solid line shows the modeled results. (C) Current-voltage characteristics of an extendable Schottky barrier MOSFET measured at -9.9%, 0%, and 9.9% strain applied (gate voltage varied from 0V to -5V in 1V steps).

圖18：作為所施加應變之函數的矽應變峰值。藍色線基於一手風琴風箱(accordion bellows)模型，且黑色線係小應變之一近似，其亦與翹棱機構一致。 Figure 18: Peak strain of enthalpy as a function of applied strain. The blue line is based on an accordion bellows model, and the black line is one of the small strains, which is also consistent with the rib mechanism.

圖19：波狀pn二極體之電學量測值，在三個不同裝置(#1、#2及#3)之壓縮(約5%所施加應變)、延伸(約15%所施加應變)及釋放之約100個週期之前(週期之前)及之後(週期之後)在三個不同裝置中估算得出。該資料指示裝置性質無系統變化。所觀測到的變化之位準與反覆探測不改變所施加應變的單一裝置所得的變化位準相當，且可能歸因於探針觸點之輕微不同。 Figure 19: Electrical measurements of wavy pn diodes, compression (about 5% applied strain), extension (about 15% applied strain) in three different devices (#1, #2, and #3) And about 100 cycles before (before the cycle) and after (after the cycle) are estimated in three different devices. This data indicates that there is no systematic change in the nature of the device. The level of change observed is comparable to the level of change obtained by a single device that does not change the applied strain, and may be due to a slight difference in probe contacts.

圖20：處於未受力狀態(中部)及壓縮(頂部)及拉緊(底部)狀態時之波狀矽肖特基障壁MOSFET的光學影像(頂部框)。該裝置之示意性說明(底部框)。 Figure 20: Optical image (top frame) of a corrugated Schottky barrier MOSFET in an unstressed (middle) and compressed (top) and tensioned (bottom) state. A schematic illustration of the device (bottom frame).

圖21：處於不同所施加應變下時"波狀"矽肖特基障壁MOSFET中量測得之轉移曲線。 Figure 21: Transfer curve measured in a "wavy" 矽 Schottky barrier MOSFET at different applied strains.

圖22：用於在PDMS基板上產生"翹棱"及"波狀"GaAs帶之步驟之 示意性說明。左邊底部框展示用以促進與該PDMS之強結合的在該等帶之表面上的薄SiO2之沈積。此結合導致在右邊中部框中展示之波狀幾何形狀之形成。弱的凡得瓦爾力結合(及中等至高位準預應變)導致如右上部框中所展示之翹棱幾何形狀。 Figure 22: Schematic illustration of the steps used to create "warped" and "wavy" GaAs strips on a PDMS substrate. The left bottom frame shows the deposition of thin SiO 2 on the surface of the strips to promote strong bonding with the PDMS. This combination results in the formation of a wavy geometric shape shown in the middle middle frame. The weak Van der Waals force combination (and medium to high level pre-strain) results in a warp geometry as shown in the upper right frame.

圖23：以經由熱膨脹產生之約1.9%之預應變形成之在PDMS基板上的波狀GaAs帶的影像。相同樣品之光學(A)、SEM(B)、三維AFM(C)及俯視圖AFM(D)影像。該SEM影像係藉由在樣品表面與偵測方向之間將該樣品台傾斜45°角來獲取。(該等帶上的點可為該等犧牲AlAs層之殘餘物。)分別沿(D)中所示藍色及綠色線繪製之表面高度分佈(E、F)。 Figure 23: Image of a corrugated GaAs strip formed on a PDMS substrate with a pre-strain of about 1.9% generated by thermal expansion. Optical (A), SEM (B), three-dimensional AFM (C) and topographic AFM (D) images of the same sample. The SEM image was obtained by tilting the sample stage at an angle of 45° between the surface of the sample and the direction of detection. (The points on the strips may be the residues of the sacrificial AlAs layers.) The surface height distributions (E, F) plotted along the blue and green lines shown in (D), respectively.

圖24：(A)在不同所施加應變下採集的、以7.8%預應變形成、與該PDMS強結合之波狀GaAs帶之光學顯微圖。左邊及右邊的藍色條加亮顯示了該結構中之某些峰值；此等條之間距離之變化指示波長對所施加應變之相依性。(B)作為(A)中所示波狀GaAs帶之所施加應變之函數的波長變化，以黑色繪製；在嵌入PDMS之後之樣品(A)的系統之類似資料，以紅色繪製。 Figure 24: (A) Optical micrograph of a wavy GaAs ribbon formed at 7.8% pre-strain and strongly bonded to the PDMS, collected under different applied strains. The blue bars on the left and right highlight some of the peaks in the structure; the change in distance between the bars indicates the dependence of the wavelength on the applied strain. (B) Wavelength change as a function of applied strain of the wavy GaAs strip shown in (A), plotted in black; similar data for the system of sample (A) after embedding PDMS, plotted in red.

圖25：與歐姆(源極及汲極)及肖特基(閘極)觸點整合以形成完整MESFET之GaAs帶之影像。(A)使用1.9%之預應變及與該PDMS之強結合而形成之波狀帶之光學顯微圖，其展示僅在無電極的區域(灰色)中週期波之形成。以約7%之預應變及與該PDMS之弱結合形成之翹棱帶的(B)光學影像及(C)SEM影像。(D)，在(B)中所示之兩個翹棱裝置在其被延伸至平坦之後的光學影像。(E)，在(B)中所示之具有不同外部施加應變(意即自頂部至底部，5.83%之壓縮應變、無施加應變，及5.83%之延伸應變)的個別帶裝置在其被嵌入PDMS之後的一組光學影像。 Figure 25: Image of a GaAs strip integrated with ohmic (source and drain) and Schottky (gate) contacts to form a complete MESFET. (A) An optical micrograph of a wavy band formed using a pre-strain of 1.9% and a strong bond with the PDMS, which shows the formation of periodic waves only in the electrodeless region (gray). (B) Optical image and (C) SEM image of the warp strip formed by pre-strain of about 7% and weak combination with the PDMS. (D), the optical image of the two ribs shown in (B) after it is extended to flat. (E), the individual tape devices shown in (B) have different externally applied strains (ie, from top to bottom, 5.83% compressive strain, no applied strain, and 5.83% extended strain) are embedded in A set of optical images after PDMS.

圖26：(A)，在PDMS基板中建構之一PDMS***上具有不同應變 之GaAs帶MESFET的光學影像。在該等裝置被轉移至該PDMS***之表面上之前施加至該PDMS***的預應變為4.7%。(B)在該系統被施加4.7%之延伸應變之前及之後(A)中所示的裝置之I-V曲線之比較。 Figure 26: (A), one of the PDMS stamps constructed in the PDMS substrate has different strains Optical image of GaAs with MESFET. The pre-strain applied to the PDMS seal before the devices were transferred to the surface of the PDMS stamp was 4.7%. (B) Comparison of the I-V curves of the devices shown in (A) before and after the system was applied with an elongation strain of 4.7%.

圖27A-C提供展示二維可延伸性之本發明之可延伸半導體在不同放大程度的影像。 27A-C provide images of the extendable semiconductors of the present invention exhibiting two-dimensional extensibility at different levels of magnification.

圖28A-C提供展示二維可延伸性之本發明之可延伸半導體的三個不同結構構形之影像。 Figures 28A-C provide images of three different structural configurations of the extensible semiconductor of the present invention showing two-dimensional extensibility.

圖29A-D提供藉由通過熱膨脹預應變該彈性基板而製備之本發明之可延伸半導體的影像。 29A-D provide images of the extensible semiconductor of the present invention prepared by pre-straining the elastic substrate by thermal expansion.

圖30展示在變化之延伸及壓縮狀態下展示二維可延伸性之可延伸半導體的光學影像。 Figure 30 shows an optical image of an extensible semiconductor exhibiting two-dimensional extensibility in a varying extended and compressed state.

圖31A展示藉由熱膨脹來預應變彈性基板而製造之展示二維可延伸性之可延伸半導體的光學影像。 31A shows an optical image of an extensible semiconductor exhibiting two-dimensional extensibility fabricated by pre-straining an elastic substrate by thermal expansion.

圖31B及31C提供關於圖31A中展示之可延伸半導體之機械性質的實驗結果。 Figures 31B and 31C provide experimental results regarding the mechanical properties of the extensible semiconductor shown in Figure 31A.

參看該等圖式，類似參考號指示類似元件且在多個圖式中出現之相同參考號指相同元件。另外，在下文中，以下定義適用："可印刷"係關於能轉移、裝配、圖案化、組織及/或整合至基板上或其中之材料、結構、裝置組件及/或積體功能裝置。在本發明之一實施例中，可印刷材料、元件、裝置組件及裝置能經由溶液印刷或乾式轉移接觸印刷而轉移、裝配、圖案化、組織及/或整合至基板上或其中。 Referring to the drawings, like reference numerals indicate like elements and the Additionally, in the following, the following definitions apply: "printable" relates to materials, structures, device components, and/or integrated functional devices that can be transferred, assembled, patterned, organized, and/or integrated onto or into a substrate. In one embodiment of the invention, printable materials, components, device components, and devices can be transferred, assembled, patterned, organized, and/or integrated onto or into a substrate via solution printing or dry transfer contact printing.

本發明之"可印刷半導體元件"包含能(例如使用乾式轉移接觸印刷及/或溶液印刷方法)裝配及/或整合至基板表面上之半導體結構。在一實施例中，本發明之可印刷半導體元件為整體單晶(unitary single crystalline)、多晶或微晶無機半導體結構。在本文中，整體結構係具有機械相連之特徵的單體元件。本發明之半導體元件可為未摻雜或摻雜的，可具有摻雜劑之選擇的空間分佈，且可以包括P及N型摻雜劑的複數個不同摻雜劑材料來摻雜。本發明包括：至少一個截面尺寸大於或等於約1微米之微結構可印刷半導體元件、及至少一個截面尺寸小於或等於約1微米的奈米結構可印刷半導體元件。在許多應用中有用之可印刷半導體包含由對高純度塊體材料(諸如使用習知高溫處理技術產生之高純度結晶半導體晶圓)之"由上而下"處理而獲取之元件。在一實施例中，本發明之可印刷半導體元件包含複合結構，其具有一操作地連接至至少一個額外裝置組件或結構(諸如導電層、介電層、電極、額外半導體結構或此等之任何組合)之半導體。在一實施例中，本發明之可印刷半導體元件包含可延伸半導體元件及/或異質半導體元件。 The "printable semiconductor component" of the present invention comprises a semiconductor structure that can be assembled (eg, using dry transfer contact printing and/or solution printing methods) and/or integrated onto the surface of the substrate. In one embodiment, the printable semiconductor component of the present invention is a monocrystalline single unit Crystalline, polycrystalline or microcrystalline inorganic semiconductor structure. In this context, the monolithic structure is a single element that is mechanically connected. The semiconductor component of the present invention can be undoped or doped, can have a selected spatial distribution of dopants, and can be doped with a plurality of different dopant materials of P and N-type dopants. The invention includes at least one microstructured printable semiconductor component having a cross-sectional dimension greater than or equal to about 1 micron and at least one nanostructure printable semiconductor component having a cross-sectional dimension of less than or equal to about 1 micrometer. Printable semiconductors useful in many applications include elements that are obtained by "top-down" processing of high purity bulk materials, such as high purity crystalline semiconductor wafers produced using conventional high temperature processing techniques. In one embodiment, the printable semiconductor component of the present invention comprises a composite structure having an operative connection to at least one additional device component or structure (such as a conductive layer, a dielectric layer, an electrode, an additional semiconductor structure, or any of these) Combined) semiconductor. In one embodiment, the printable semiconductor component of the present invention comprises an extendable semiconductor component and/or a heterogeneous semiconductor component.

"截面尺寸"指裝置、裝置組件或材料之截面之尺寸。截面尺寸包括寬度、厚度、半徑及直徑。舉例而言，具有帶形狀之半導體元件以一長度及兩個截面尺寸：厚度及寬度，為特徵。舉例而言，具有圓柱形狀之可印刷半導體元件以一長度及截面尺寸：直徑(或者半徑)，為特徵。 "Sectional dimension" refers to the dimensions of the cross-section of the device, device component or material. Section dimensions include width, thickness, radius and diameter. For example, a semiconductor component having a strip shape is characterized by a length and two cross-sectional dimensions: thickness and width. For example, a printable semiconductor component having a cylindrical shape is characterized by a length and a cross-sectional dimension: diameter (or radius).

"由一基板支撐"指至少部分地存在於一基板表面或至少部分地存在於一或多個位於該結構與該基板表面之間的中間結構上之結構。術語"由一基板支撐"亦可指部分或全部嵌入基板之結構。 "Supported by a substrate" means a structure that is at least partially present on a substrate surface or at least partially present on one or more intermediate structures between the structure and the substrate surface. The term "supported by a substrate" may also refer to a structure that is partially or fully embedded in a substrate.

"溶液印刷"用以指諸如可印刷半導體元件之一或多個結構藉以分散入一載體介質且以一協調的方式傳送至基板表面之所選區域的過程。在一例示性溶液印刷方法中，結構被傳送至一基板表面之所選區域係藉由與經受圖案化之基板表面的形態及/或實體特性無關之方法來達成。本發明中可使用之溶液印刷方法包括(但不限於)噴墨印刷、 熱轉移印刷，及毛細作用印刷。 "Solution printing" is used to mean a process in which one or more structures, such as a printable semiconductor component, are dispersed into a carrier medium and delivered to selected areas of the substrate surface in a coordinated manner. In an exemplary solution printing method, the selected regions of the structure that are transferred to the surface of a substrate are achieved by methods that are independent of the morphology and/or physical properties of the surface of the substrate being patterned. Solution printing methods that can be used in the present invention include, but are not limited to, inkjet printing, Thermal transfer printing, and capillary printing.

"大體上縱向取向"指使得諸如可印刷半導體元件之元件群體之縱軸的方向大體上與一所選對準軸平行的取向。在此定義之上下文中，與一所選軸大體上平行指在與絕對平行方向偏差10度範圍內的取向，較佳為在與絕對平行方向偏差5度範圍內的取向。 By "substantially longitudinally oriented" is meant an orientation that causes the direction of the longitudinal axis of a population of elements, such as a printable semiconductor component, to be substantially parallel to a selected alignment axis. In the context of this definition, substantially parallel to a selected axis means an orientation that is within 10 degrees of the absolute parallel direction, preferably an orientation that is within 5 degrees of the absolute parallel direction.

"可延伸"指材料、結構、裝置或裝置組件承受應變而無破裂之能力。在一例示性實施例中，一可延伸材料、結構、裝置或裝置組件可承受大於約0.5%之應變而無破裂，對於某些應用較佳可承受大於約1%之應變而無破裂，且對於某些應用最好可承受大於約3%的應變而無破裂。 "Extensible" means the ability of a material, structure, device or device component to withstand strain without rupture. In an exemplary embodiment, an extensible material, structure, device, or device component can withstand greater than about 0.5% strain without cracking, and for some applications, can withstand greater than about 1% strain without cracking, and For some applications it is desirable to withstand strains greater than about 3% without cracking.

術語"可撓性"及"可彎曲"在本文中等同地使用，且指材料、結構、裝置或裝置組件變形為一曲線形狀而不經受會引入顯著應變的轉換之能力，該等顯著應變可諸如特徵化材料、結構、裝置或裝置組件之失效點的應變。在一例示性實施例中，可撓性材料、結構、裝置或裝置組件可變形為曲線形狀而不引入大於或等於約5%之應變，對於某些應用較佳不引入大於或等於約1%之應變，且對於某些應用最好不引入大於或等於約0.5%之應變。 The terms "flexible" and "flexible" are used equally herein and mean that the material, structure, device or device component is deformed into a curved shape without being subjected to the ability to introduce significant strain transformations, such significant strains may be Strain such as the point of failure of a characterization of a material, structure, device, or device component. In an exemplary embodiment, the flexible material, structure, device, or device component can be deformed into a curved shape without introducing a strain greater than or equal to about 5%, and for some applications preferably does not introduce greater than or equal to about 1%. The strain, and for some applications, does not introduce a strain greater than or equal to about 0.5%.

該術語"翹棱"指當薄元件、結構及/或裝置藉由在該元件、結構及/或裝置之平面外的方向上彎曲而回應於一壓縮應變時發生的實體變形。本發明包括具有一或多個表面之可延伸半導體、裝置及組件，該或該等表面具有包含一或多個翹棱之輪廓形狀。 The term "warping" refers to a physical deformation that occurs when a thin element, structure, and/or device is bent in response to a compressive strain by bending in a direction out of the plane of the element, structure, and/or device. The present invention includes an extensible semiconductor, device and assembly having one or more surfaces having a contoured shape comprising one or more ridges.

"半導體"指任何在極低溫度下係一絕緣體但在約300絕對溫度下具有一明顯導電性之材料。在本文中，對術語半導體之使用希望與此術語在微電子及電子裝置之技術領域中的使用一致。適用於本發明之半導體可包含諸如矽、鍺及金剛石之元素半導體，以及複合半導體，諸如第IV族複合半導體(諸如SiC及SiGe)、第III-V族半導體(諸如 AlSb、AlAs、Aln、AlP、BN、GaSb、GaAs、GaN、GaP、InSb、InAs、InN及InP)、第III-V族三元半導體合金(諸如AlxGa1-xAs)、第II-VI族半導體(諸如CsSe、CdS、CdTe、ZnO、ZnSe、ZnS，及ZnTe)、第I-VII族半導體CuCl、第IV-VI族半導體(諸如PbS、PbTe及SnS)、層半導體(諸如Pbl2、MoS2及GaSe)、氧化物半導體(諸如CuO及Cu2O)。術語半導體包括以一或多種選擇之材料摻雜的外質半導體及本質半導體(包括具有p型摻雜材料及n型摻雜材料的半導體)以提供適用於給定應用或裝置之有利電子性質。術語半導體包括包含半導體及/或摻雜劑之一混合物之複合材料。適用於本發明之某些應用之特殊半導體材料包括(但不限於)Si、Ge、SiC、AlP、AlAs、AlSb、GaN、GaP、GaAs、GaSb、InP、InAs、GaSb、InP、InAs、InSb、ZnO、ZnSe、ZnTe、CdS、CdSe、ZnSe、ZnTe、CdS、CdSe、CdTe、HgS、PbS、PbSe、PbTe、AlGaAs、AlInAs、AlInP、GaAsP、GaInAs、GaInP、AlGaAsSb、AlGaInP及GaInAsP。多孔矽半導體材料適用於本發明在感測器及諸如發光二極體(LED)及固態雷射之發光材料領域中之應用。半導體材料之雜質係不同於該(等)半導體材料自身或任何提供至半導體材料之摻雜劑的原子、元素、離子及/或分子。雜質係可對半導體材料之電子性質造成負面影響之存在於半導體材料中的不當物質，且包括(但不限於)氧、碳，及包括重金屬之金屬。重金屬雜質包括(但不限於)週期表上銅與鉛之間之元素族、鈣、鈉，及其所有離子、複合物及/或錯合物。 "Semiconductor" means any material that is an insulator at very low temperatures but has a significant electrical conductivity at about 300 absolute temperatures. In this context, the use of the term semiconductor is intended to be consistent with the use of this term in the art of microelectronics and electronic devices. Semiconductors suitable for use in the present invention may comprise elemental semiconductors such as germanium, antimony and diamond, as well as composite semiconductors such as Group IV composite semiconductors (such as SiC and SiGe), Group III-V semiconductors (such as AlSb, AlAs, Aln, AlP). , BN, GaSb, GaAs, GaN, GaP, InSb, InAs, InN, and InP), Group III-V ternary semiconductor alloys (such as Al x Ga 1-x As), Group II-VI semiconductors (such as CsSe, CdS, CdTe, ZnO, ZnSe, ZnS, and ZnTe), Group I-VII semiconductor CuCl, Group IV-VI semiconductors (such as PbS, PbTe, and SnS), layer semiconductors (such as Pbl 2 , MoS 2 , and GaSe), Oxide semiconductors (such as CuO and Cu 2 O). The term semiconductor includes exogenous semiconductors and intrinsic semiconductors (including semiconductors having p-type dopants and n-type dopants) doped with one or more selected materials to provide advantageous electronic properties suitable for a given application or device. The term semiconductor includes composite materials comprising a mixture of semiconductors and/or dopants. Specific semiconductor materials suitable for certain applications of the present invention include, but are not limited to, Si, Ge, SiC, AlP, AlAs, AlSb, GaN, GaP, GaAs, GaSb, InP, InAs, GaSb, InP, InAs, InSb, ZnO, ZnSe, ZnTe, CdS, CdSe, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, PbS, PbSe, PbTe, AlGaAs, AlInAs, AlInP, GaAsP, GaInAs, GaInP, AlGaAsSb, AlGaInP, and GaInAsP. The porous tantalum semiconductor material is suitable for use in the field of the present invention in the field of sensors and luminescent materials such as light emitting diodes (LEDs) and solid state lasers. The impurity of the semiconductor material is different from the semiconductor material itself or any atom, element, ion and/or molecule provided to the dopant of the semiconductor material. Impurities are undesirable materials present in semiconductor materials that can adversely affect the electronic properties of the semiconductor material, and include, but are not limited to, oxygen, carbon, and metals including heavy metals. Heavy metal impurities include, but are not limited to, the family of elements, calcium, sodium, and all of their ions, complexes, and/or complexes between copper and lead on the periodic table.

"塑性"指任何合成或自然產生之材料或材料之組合，通常當加熱時可將其模製或成型且硬化為一所要形狀。適用於本發明之裝置及方法之例示性塑膠包括(但不限於)聚合物、樹脂及纖維素衍生物。在本文中，術語塑性用以包括包含具有一或多種添加物之一或多種塑膠的複合塑性材料，該等添加物可諸如結構增強劑、填充劑、纖維、增塑 劑、穩定劑或可提供所要之化學或物理性質之添加物。 "Plastic" means any synthetic or naturally occurring material or combination of materials which are typically molded or shaped and hardened into a desired shape when heated. Exemplary plastics suitable for use in the devices and methods of the present invention include, but are not limited to, polymers, resins, and cellulose derivatives. As used herein, the term plasticity is intended to include composite plastic materials comprising one or more plastics having one or more additives, such additives, such as structural enhancers, fillers, fibers, plasticized Additives, stabilizers or additives that provide the desired chemical or physical properties.

"介電質"及"介電材料"在本文中等同地使用，且指對電流具高阻抗之物質。適用之介電材料包括(但不限於)SiO2、Ta2O5、TiO2、ZrO2、Y2O3、SiN4、STO、BST、PLZT、PMN及PZT。 "Dielectric" and "dielectric material" are used equivalently herein and refer to a substance that has a high impedance to current. Suitable dielectric materials include, but are not limited to, SiO 2 , Ta 2 O 5 , TiO 2 , ZrO 2 , Y 2 O 3 , SiN 4 , STO, BST, PLZT, PMN, and PZT.

"聚合物"指包含複數個通常稱為單體之重複化學基團之分子。聚合物通常以高分子質量為特徵。本發明中可用之聚合物可為有機聚合物或無機聚合物，且可處於非晶系、半非晶系、晶體或部分晶體狀態。聚合物可包含具有相同化學組成之單體或可包含具有不同化學組成的複數個單體(諸如共聚物)。具有鏈結的單體鏈之交聯聚合物尤其適用於本發明之某些應用。可用於本發明之方法、裝置及裝置組件之聚合物包括(但不限於)塑膠、彈性體、熱塑性彈性體、彈性塑膠、彈性塑膠、恆溫器(thermostat)、熱塑膠及丙烯酸酯。例示性聚合物包括(但不限於)縮醛聚合物、生物可降解聚合物、纖維素聚合物、含氟聚合物、耐綸、聚丙烯腈聚合物、聚醯胺-醯亞胺聚合物、聚醯亞胺、聚芳酯化合物、聚苯幷咪唑、聚丁烯、聚碳酸酯、聚酯、聚醚醯亞胺、聚乙烯、聚乙烯共聚物及經改質聚乙烯、聚酮、聚(甲基丙烯酸甲酯)、聚甲基戊烯、聚苯醚及聚苯硫醚、聚苯二甲醯胺、聚丙烯、聚胺基甲酸酯、苯乙烯樹脂、碸基樹脂、乙烯基樹脂或其任何組合。 "Polymer" means a molecule comprising a plurality of repeating chemical groups commonly referred to as monomers. Polymers are generally characterized by high molecular weight. The polymer usable in the present invention may be an organic polymer or an inorganic polymer, and may be in an amorphous, semi-amorphous, crystalline or partially crystalline state. The polymer may comprise monomers having the same chemical composition or may comprise a plurality of monomers (such as copolymers) having different chemical compositions. Crosslinked polymers having linked monomeric chains are especially useful in certain applications of the invention. Polymers useful in the methods, devices, and device components of the present invention include, but are not limited to, plastics, elastomers, thermoplastic elastomers, elastomeric plastics, elastomers, thermostats, thermoplastics, and acrylates. Exemplary polymers include, but are not limited to, acetal polymers, biodegradable polymers, cellulosic polymers, fluoropolymers, nylon, polyacrylonitrile polymers, polyamido-imine polymers, Polyimine, polyarylate, polybenzimidazole, polybutene, polycarbonate, polyester, polyetherimide, polyethylene, polyethylene copolymer and modified polyethylene, polyketone, poly (Methyl methacrylate), polymethylpentene, polyphenylene ether and polyphenylene sulfide, polyphthalamide, polypropylene, polyurethane, styrene resin, sulfhydryl resin, vinyl Resin or any combination thereof.

"彈性體"指可延伸或變形且返回至其原始形狀而無實質上永久變形的聚合材料。彈性體通常經受實質上彈性變形。適用於本發明之彈性基板至少部分包含一或多個彈性體。適用於本發明之例示性彈性體可包含聚合物、共聚物、複合材料或聚合物與共聚物之混合物。彈性體層指包含至少一個彈性體之層。彈性體層亦可包括摻雜劑及其他非彈性體材料。適用於本發明之彈性體可包括(但不限於)熱塑性彈性體、苯乙烯類材料、烯烴材料、聚烯烴、聚胺基甲酸酯熱塑性彈性體、聚醯胺、合成橡膠、PDMS、聚丁二烯、聚異丁烯、聚(苯乙烯- 丁二烯-苯乙烯)、聚胺基甲酸酯、聚氯丁二烯及聚矽氧。 "Elastomer" means a polymeric material that can be stretched or deformed and returned to its original shape without substantial permanent deformation. Elastomers are typically subjected to substantial elastic deformation. The elastic substrate suitable for use in the present invention at least partially comprises one or more elastomers. Exemplary elastomers suitable for use in the present invention may comprise a polymer, a copolymer, a composite or a mixture of a polymer and a copolymer. An elastomer layer refers to a layer comprising at least one elastomer. The elastomer layer may also include dopants and other non-elastomeric materials. Elastomers suitable for use in the present invention may include, but are not limited to, thermoplastic elastomers, styrenic materials, olefin materials, polyolefins, polyurethane thermoplastic elastomers, polyamines, synthetic rubbers, PDMS, polybutylene. Diene, polyisobutylene, poly(styrene- Butadiene-styrene), polyurethane, polychloroprene and polyfluorene.

"良好電子效能"及"高效能"在本文中等同地使用，且指裝置及裝置組件具有可提供諸如電子訊號開關及/或放大之所要功能性的諸如場效應遷移率、臨限電壓及開-關比例之電子特性。本發明之展示良好電子效能之例示性可轉移、且視情況可印刷之半導體元件可具有大於或等於100cm2 V-1 s-1的本質場效應遷移率，對於某些應用較佳具有大於或等於約300cm2 V-1 s-1的本質場效應遷移率。本發明之展示良好電子效能之例示性電晶體可具有大於或等於約100cm2 V-1 s-1的裝置場效應遷移率，對於某些應用較佳具有大於或等於約300cm2 V-1 s-1的裝置場效應遷移率，且對於某些應用最好具有大於或等於約800cm2 V-1 s-1的裝置場效應遷移率。本發明之展示良好電子效能之例示性電晶體可具有小於約5伏特的臨限電壓及/或大於約1×104之開-關比例。 "Good electronic performance" and "high performance" are used equally herein, and means that the device and device components have such desirable functions as electronic signal switching and/or amplification, such as field effect mobility, threshold voltage, and on. - Off-line electronic characteristics. Exemplary transferable, and optionally printable, semiconductor devices of the present invention that exhibit good electronic performance can have an intrinsic field effect mobility greater than or equal to 100 cm 2 V -1 s -1 , preferably greater than or for some applications It is equal to the intrinsic field effect mobility of about 300 cm 2 V -1 s -1 . Exemplary transistor exhibiting good electronic performance of the present invention can have a device field effect mobility greater than or equal to about 100 cm 2 V -1 s -1 , preferably greater than or equal to about 300 cm 2 V -1 s for some applications. The device field effect mobility of -1 , and for some applications, preferably has a device field effect mobility greater than or equal to about 800 cm 2 V -1 s -1 . Exemplary transistors show good electron efficacy of the present invention may have less than about 5 volts and the threshold voltage / opening or greater than about 1 × 10 4 - A OFF ratio.

"大面積"指大於或等於約36平方英吋之面積，諸如用於裝置製造之基板的一接收表面的面積。 "Large area" means an area greater than or equal to about 36 square feet, such as the area of a receiving surface of a substrate for device fabrication.

"裝置場效應遷移率"指使用與電子裝置對應之輸出電流資料計算得之諸如電晶體的電子裝置之場效應遷移率。 "Device field effect mobility" refers to the field effect mobility of an electronic device such as a transistor calculated using output current data corresponding to an electronic device.

"楊氏模數"係材料、裝置或層之一機械性質，其指一給定物質之應力與應變的比例。楊氏模數可由以下陳述式提供： "Young's modulus" is a mechanical property of a material, device or layer that refers to the ratio of stress to strain for a given substance. Young's modulus can be provided by the following statement:

其中E係楊氏模數，L0係平衡長度，△L係在所施加應力下之長度變化，F係所施加之力且A係施加力的面積。楊氏模數亦可通過以下方程式根據Lame常數來表示： Wherein E is the Young's modulus, L 0 is the equilibrium length, ΔL is the length change under the applied stress, and the force applied by F is the area where the force is applied by the A system. Young's modulus can also be expressed by the following equation according to the Lame constant:

其中λ及μ係Lame常數。高楊氏模數(或"高模數")及低楊氏模數 (或"低模數")係對一給定材料、層或裝置中楊氏模數之大小的相對描述。在本發明中，高楊氏模數比低楊氏模數更大，對於某些應用而言較佳約大10倍，對於其他應用而言最好約大100倍，且對於另一些應用而言最好約大1000倍。 Where λ and μ are Lame constants. High Young's modulus (or "high modulus") and low Young's modulus (or "low modulus") is a relative description of the magnitude of the Young's modulus in a given material, layer or device. In the present invention, the high Young's modulus is larger than the low Young's modulus, preferably about 10 times larger for some applications, and about 100 times larger for other applications, and for other applications. It is best to say that it is about 1000 times larger.

在下文中，闡明本發明之裝置、裝置組件及方法之大量特定細節以提供對本發明的準確性質之詳細說明。然而，對於熟習此項技術者將顯而易見的是，無此等特定細節也可實踐本發明。 In the following, numerous specific details of the device, device components and methods of the invention are set forth to provide a detailed description of the precise nature of the invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without the specific details.

本發明提供當延伸、壓縮、撓曲或者以其他方式變形時能提供良好效能之可延伸半導體及電子電路。另外，本發明之可延伸半導體及電子電路可經調適用於廣泛範圍的裝置組態以提供完全可撓性的電子及光電子裝置。 The present invention provides extendable semiconductor and electronic circuits that provide good performance when extended, compressed, flexed, or otherwise deformed. In addition, the extendable semiconductor and electronic circuits of the present invention can be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

圖1提供一展示本發明之可延伸半導體結構之原子力顯微圖。該可延伸半導體元件700包含一具有一支撐表面710之可撓性基板705(諸如聚合物及/或彈性基板)及一具有一曲線內表面720之彎曲半導體結構715。在此實施例中，彎曲半導體結構715之曲線內表面720之至少一部分與該可撓性基板705之支撐表面710結合。曲線內表面720可在沿內表面720之經選擇點處或在沿內表面720的大體上所有點處與支撐表面710結合。圖1中所說明之例示性半導體結構包含一具有一等於約100微米之寬度及一等於約100奈米之厚度之單晶矽彎曲帶。圖1中說明之可撓性基板係一具有約1毫米之厚度之PDMS基板。曲線內表面720具有一彎曲結構，其包含沿該帶之長度擴展之一大體上週期性的波形。如圖1所示，該波之振幅約為500奈米且該尖鋒間距約為20微米。圖2展示了提供具有曲線內表面720之彎曲半導體結構715之展開視圖的原子力顯微圖。圖3展示本發明之可延伸半導體結構之一陣列的原子力顯微圖。對圖3中原子力顯微圖之分析展示該等彎曲半導體結構被壓縮了約0.27%。圖4展示本發明之可延伸半導體結構之光學顯 微圖。 Figure 1 provides an atomic force micrograph showing an extensible semiconductor structure of the present invention. The extendable semiconductor component 700 includes a flexible substrate 705 (such as a polymer and/or an elastic substrate) having a support surface 710 and a curved semiconductor structure 715 having a curved inner surface 720. In this embodiment, at least a portion of the curved inner surface 720 of the curved semiconductor structure 715 is bonded to the support surface 710 of the flexible substrate 705. The curved inner surface 720 can be joined to the support surface 710 at selected points along the inner surface 720 or at substantially all points along the inner surface 720. The exemplary semiconductor structure illustrated in Figure 1 comprises a single crystal germanium ribbon having a width equal to about 100 microns and a thickness equal to about 100 nanometers. The flexible substrate illustrated in Figure 1 is a PDMS substrate having a thickness of about 1 mm. Curved inner surface 720 has a curved configuration that includes a substantially periodic waveform that extends along one of the lengths of the strip. As shown in Figure 1, the amplitude of the wave is about 500 nm and the pitch is about 20 microns. 2 shows an atomic force micrograph showing an expanded view of a curved semiconductor structure 715 having a curved inner surface 720. 3 shows an atomic force micrograph of an array of extensible semiconductor structures of the present invention. Analysis of the atomic force micrographs in Figure 3 shows that the curved semiconductor structures were compressed by about 0.27%. 4 shows the optical display of the extensible semiconductor structure of the present invention Micrograph.

曲線內表面720之輪廓形狀允許彎曲半導體結構715沿變形軸730膨脹或壓縮而不經受大量機械應變。此輪廓形狀亦可允許該半導體結構在不同於變形軸730方向的方向上彎曲、撓曲或變形而無由應變引發之顯著機械損傷或效能損失。本發明之半導體結構之曲線表面可具有提供，良好機械性質(諸如可延伸性、可撓性及/或可彎曲性)及/或良好電子效能(諸如當被撓曲、延伸或變形時展示良好場效應遷移率)的任何輪廓形狀。例示性輪廓形狀可具有以下特徵：具有複數個凸起及/或凹入區域，且具有包括正弦波、高斯波、Aries函數、方波、洛仁子波、週期波、無週期波或此等波之任何組合之多種波形。適用於本發明之波形可關於兩個或三個實體維度而變化。 The contoured shape of the curved inner surface 720 allows the curved semiconductor structure 715 to expand or compress along the deformation axis 730 without undergoing substantial mechanical strain. This contour shape may also allow the semiconductor structure to bend, flex or deform in a direction other than the direction of the deformation axis 730 without significant mechanical damage or loss of performance caused by strain. The curved surface of the semiconductor structure of the present invention can have good mechanical properties (such as extensibility, flexibility and/or bendability) and/or good electronic properties (such as good display when flexed, stretched or deformed). Any contour shape of the field effect mobility). An exemplary contour shape can have the following features: having a plurality of raised and/or recessed regions, and having a sine wave, a Gaussian wave, an Aries function, a square wave, a Loren wave, a periodic wave, a periodic wave, or the like Multiple waveforms of any combination. Waveforms suitable for use in the present invention may vary with respect to two or three physical dimensions.

圖5展示本發明之可延伸半導體結構的原子力顯微圖，該結構之半導體結構715結合至具有三維起伏圖案之可撓性基板705，該三維起伏圖案位於該基板之支撐表面710上。該三維起伏圖案包含凹入區域750及起伏特徵760。如圖5所示，彎曲半導體結構715在凹入區域750中及起伏特徵760上與支撐表面710結合。 5 shows an atomic force micrograph of an extensible semiconductor structure of the present invention bonded to a flexible substrate 705 having a three-dimensional relief pattern on a support surface 710 of the substrate. The three-dimensional relief pattern includes a recessed region 750 and an undulating feature 760. As shown in FIG. 5, the curved semiconductor structure 715 is bonded to the support surface 710 in the recessed region 750 and on the relief features 760.

圖6展示一說明製造本發明之可延伸半導體結構之一例示性方法的流程圖。在該例示性方法中，提供處於一膨脹狀態之一預應變彈性基板。預應變可藉由該項技術中習知之任何方法來達成，其包括(但不限於)輥壓及/或預彎曲該彈性基板。預應變亦可經由熱方法，例如通過由升高該彈性基板之溫度引發之熱膨脹來達成。經由熱方法之預應變之一優勢係可達成沿複數個不同軸(諸如正交的軸)之膨脹。 6 shows a flow chart illustrating an exemplary method of fabricating an extensible semiconductor structure of the present invention. In the exemplary method, a pre-strained elastic substrate in one expanded state is provided. Pre-straining can be achieved by any method known in the art including, but not limited to, rolling and/or pre-bending the elastomeric substrate. Pre-straining can also be achieved via thermal methods, such as by thermal expansion caused by raising the temperature of the elastomeric substrate. One of the advantages of pre-straining via thermal methods is that expansion along a plurality of different axes, such as orthogonal axes, can be achieved.

本發明之此方法中可用之例示性彈性基板係一具有等於約1毫米的厚度之PDMS基板。該彈性基板可藉由沿一單一軸之膨脹或藉由沿複數個軸之膨脹來預應變。如圖6所示，可印刷半導體元件之至少一部分內表面與處於一膨脹狀態之預應變彈性基板的外表面結合。結合 可藉由該半導體表面之內表面之間的共價鍵結、藉由凡得瓦爾力、藉由使用黏結劑或藉由此等方法之任何組合來達成。在該彈性基板係PDMS之例示性實施例中，該PDMS基板之支撐表面經化學改質使得其具有複數個自其表面擴展的羥基以促進與一矽半導體結構之共價鍵結。再參看圖6，在將該預應變彈性基板與半導體結構結合之後，允許該彈性基板至少部分地鬆弛至一鬆弛狀態。在此實施例中，該彈性基板之鬆弛使該半導體結構之內表面彎曲，進而產生一具有曲線內表面的半導體元件。 An exemplary elastomeric substrate useful in the method of the present invention is a PDMS substrate having a thickness equal to about 1 mm. The elastic substrate can be pre-strained by expansion along a single axis or by expansion along a plurality of axes. As shown in FIG. 6, at least a portion of the inner surface of the printable semiconductor component is bonded to the outer surface of the pre-strained elastic substrate in an expanded state. Combine This can be achieved by covalent bonding between the inner surfaces of the semiconductor surface, by van der Waals force, by the use of a binder, or by any combination of methods. In an exemplary embodiment of the elastic substrate system PDMS, the support surface of the PDMS substrate is chemically modified such that it has a plurality of hydroxyl groups extending from its surface to promote covalent bonding with a germanium semiconductor structure. Referring again to Figure 6, after the pre-strained elastic substrate is bonded to the semiconductor structure, the elastic substrate is allowed to at least partially relax to a relaxed state. In this embodiment, the relaxation of the elastic substrate bends the inner surface of the semiconductor structure to produce a semiconductor component having a curved inner surface.

如圖6中所示，該製造方法可視情況包括一第二轉移步驟及視情況之鍵結步驟，其中將具有一曲線內表面720之可轉移半導體元件715自該彈性基板轉移至另一基板，較佳一可撓性基板，諸如一聚合物基板。此第二轉移步驟可藉由使具有一曲線內表面720之半導體結構715之曝露表面與另一與該半導體結構715的曝露表面結合之基板之一接收表面接觸來達成。與該另一基板之結合可藉由能至少部分保持該半導體元件之彎曲結構的任何途徑來完成，其包括共價鍵、經由凡得瓦爾力之鍵結、偶極-偶極交互作用、倫敦(London)力之鍵結及/或氫鍵結。本發明亦包括使用提供於該可轉移半導體結構之一曝露表面與該接收表面之間的黏接層、塗層及/或薄膜。 As shown in FIG. 6, the manufacturing method may optionally include a second transfer step and optionally a bonding step, wherein the transferable semiconductor device 715 having a curved inner surface 720 is transferred from the elastic substrate to another substrate. A flexible substrate such as a polymer substrate is preferred. This second transfer step can be accomplished by contacting the exposed surface of the semiconductor structure 715 having a curved inner surface 720 with another receiving surface of the substrate bonded to the exposed surface of the semiconductor structure 715. The bonding to the other substrate can be accomplished by any means that at least partially maintains the curved structure of the semiconductor component, including covalent bonds, bonding via Van der Valli, dipole-dipole interaction, London (London) Force bond and / or hydrogen bonding. The invention also includes the use of an adhesive layer, coating and/or film provided between an exposed surface of the transferable semiconductor structure and the receiving surface.

本發明之可延伸半導體元件可有效地整合入大量功能性裝置及裝置組件，諸如電晶體、二極體、雷射、MEMS、NEMS、LEDS及OLEDS。本發明之可延伸半導體元件與習知剛性無機半導體相比具有某些功能性優勢。首先，可延伸半導體元件可為可撓性的，且因此比習知剛性無機半導體更少受由撓曲、彎曲及/或變形引起之結構損壞之影響。其次，因為彎曲半導體結構可處於一輕微機械應變狀態以提供一曲線內表面，所以本發明之可延伸半導體元件與習知無應變剛性半導體相比可展示更高之本質場效應遷移率。最後，因為可延伸半 導體元件在裝置溫度循環中能自由膨脹及收縮，所以其可能提供良好之熱性質。 The extensible semiconductor component of the present invention can be effectively integrated into a large number of functional devices and device components such as transistors, diodes, lasers, MEMS, NEMS, LEDS, and OLEDS. The extendable semiconductor component of the present invention has certain functional advantages over conventional rigid inorganic semiconductors. First, the extendable semiconductor component can be flexible and, therefore, less susceptible to structural damage caused by flexing, bending, and/or deformation than conventional rigid inorganic semiconductors. Second, because the curved semiconductor structure can be in a slight mechanical strain state to provide a curved inner surface, the extendable semiconductor component of the present invention can exhibit higher intrinsic field effect mobility than conventional strain-free rigid semiconductors. Finally, because it can be extended half The conductor element is free to expand and contract during the temperature cycle of the device, so it may provide good thermal properties.

圖7展示具有一波狀構形之縱向對準的可延伸半導體之陣列之影像。如圖7所示，該等半導體帶被以週期波構形提供且由一單一可撓性橡膠基板支撐。 Figure 7 shows an image of an array of longitudinally aligned extendable semiconductors having a wavy configuration. As shown in Figure 7, the semiconductor strips are provided in a periodic wave configuration and supported by a single flexible rubber substrate.

圖8展示本發明之可延伸半導體元件之一截面影像，其中半導體結構776由該可撓性基板777來支撐。如圖8所示，半導體結構776具有內表面，該等內表面具有一週期性波之輪廓形狀。亦如圖8所示，該週期波構形擴展穿過半導體結構776之整個截面尺寸。 8 shows a cross-sectional image of an extensible semiconductor component of the present invention in which a semiconductor structure 776 is supported by the flexible substrate 777. As shown in FIG. 8, the semiconductor structure 776 has an inner surface having a contour shape of a periodic wave. As also shown in FIG. 8, the periodic wave configuration extends through the entire cross-sectional dimension of the semiconductor structure 776.

本發明亦提供當延伸、撓曲或變形時具有良好效能之可延伸電子電路、裝置及裝置陣列。與上述可延伸半導體元件類似，本發明提供可延伸電路及電子裝置，其包含一具有一支撐表面的可撓性基板，該支撐表面與一具有一曲線內表面(諸如展示一波形結構之曲線內表面)的裝置、裝置陣列或電路接觸。在此結構排列中，該裝置、裝置陣列或電路結構之至少一部分曲線內表面與該可撓性基板之支撐表面結合。本發明之此態樣之裝置、裝置陣列或電路係一包含複數個諸如半導體、介電質、電極、摻雜半導體及導體之積體裝置組件的多組件元件。在一例示性實施例中，具有小於約10微米之淨厚度之可撓性電路、裝置及裝置陣列包含複數個積體裝置組件，其至少一部分具有週期波曲線結構。 The present invention also provides an array of extendable electronic circuits, devices, and devices that have good performance when extended, flexed, or deformed. Similar to the above extensible semiconductor component, the present invention provides an extendable circuit and an electronic device comprising a flexible substrate having a support surface having a curved inner surface (such as a curve exhibiting a wavy structure) Surface device, device array or circuit contact. In this structural arrangement, at least a portion of the curved inner surface of the device, device array or circuit structure is bonded to the support surface of the flexible substrate. A device, device array or circuit of this aspect of the invention is a multi-component component comprising a plurality of integrated device components such as semiconductors, dielectrics, electrodes, doped semiconductors, and conductors. In an exemplary embodiment, the flexible circuit, device and device array having a net thickness of less than about 10 microns comprises a plurality of integrated device components, at least a portion of which has a periodic wave curve structure.

在本發明之一有用之實施例中，提供包含複數個互連組件的獨立式電子電路或裝置。該電子電路或裝置之一內表面與一處於一膨脹狀態之預應變彈性基板接觸且至少部分結合。預應變可藉由該項技術中已知之任何方法來達成，其包括(但不限於)輥壓及/或預彎曲該彈性基板，且可藉由沿一單一軸之膨脹或藉由沿複數個軸的膨脹來預應變該彈性基板。結合可直接藉由該電子電路或裝置之至少一部分內表面 與該預應變彈性基板之間的共價鍵或凡得瓦爾力來實現，或藉由使用黏接劑或一中間結合層來達成。在使該預應變彈性基板與該電子電路或裝置結合之後，允許該彈性基板至少部分地鬆弛至一鬆弛狀態，其使該半導體結構之內表面彎曲。該電子電路或裝置之內表面之彎曲產生一曲線內表面，其在某些有用的實施例中具有一週期或無週期波構形。本發明包括多個實施例，其中包含電子裝置或電路之所有組件皆存在於一週期或無週期波組態中。 In one useful embodiment of the invention, a stand-alone electronic circuit or apparatus comprising a plurality of interconnect components is provided. The inner surface of one of the electronic circuits or devices is in contact with and at least partially bonded to a pre-strained resilient substrate in an expanded state. Pre-straining can be achieved by any method known in the art including, but not limited to, rolling and/or pre-bending the elastic substrate, and by expanding along a single axis or by plural The expansion of the shaft pre-strains the elastic substrate. Bonding may be directly by at least a portion of the inner surface of the electronic circuit or device This is achieved by covalent bonds or van der Waals forces between the pre-strained elastomeric substrate, or by the use of an adhesive or an intermediate bonding layer. After bonding the pre-strained elastic substrate to the electronic circuit or device, the elastic substrate is allowed to at least partially relax to a relaxed state that bends the inner surface of the semiconductor structure. The bending of the inner surface of the electronic circuit or device produces a curved inner surface that, in some useful embodiments, has a periodic or non-periodic configuration. The present invention includes various embodiments in which all components including electronic devices or circuits are present in a one-cycle or non-periodic configuration.

可延伸電子電路、裝置及裝置陣列之週期或無週期波組態允許其遵守延伸或彎曲組態而不在該等電路或裝置之個別組件上產生大應變。本發明之此態樣提供可延伸電子電路、裝置及裝置陣列當處於彎曲、延伸或變形狀態時之有用之電子性質。藉由本方法形成之週期波組態之週期可根據以下來變化：(i)包含該電路或裝置的積體組件之集合之淨厚度及(ii)包含積體裝置組件的材料之諸如楊氏模數及撓曲剛性之機械性質。 The periodic or non-periodic configuration of the extendable electronic circuit, device, and device array allows it to adhere to an extended or curved configuration without creating large strains on individual components of the circuits or devices. This aspect of the invention provides useful electronic properties of the extendable electronic circuit, device and array of devices when in a bent, extended or deformed state. The period of the periodic wave configuration formed by the present method may vary as follows: (i) the net thickness of the set of integrated components including the circuit or device and (ii) the material including the integrated device component such as Young's mode. The mechanical properties of the number and flexural rigidity.

圖9A展示一說明製造可延伸薄膜電晶體之陣列之例示性方法之流程圖。如圖9A所示，使用本發明之技術提供獨立式可印刷薄膜電晶體之一陣列。將薄膜電晶體之陣列經由乾式轉移接觸印刷方法以一曝露該等電晶體之內表面之方式轉移至一PDMS基板。接著將所曝露內表面與處於一膨脹狀態之室溫固化預應變PDMS層接觸。該預應變PDMS層之隨後完全固化使該等電晶體之內表面與該預應變PDMS層結合。允許該預應變PDMS層冷卻且呈現一至少部分鬆弛狀態。PDMS層之鬆弛將一週期波結構引入該陣列中之電晶體，進而使得其變為可延伸的。圖9A中之插圖提供藉由本方法製造之可延伸薄膜電晶體陣列之原子力顯微圖。該原子力顯微圖展示了在延伸或變形狀態中提供良好電子效能之週期波結構。 Figure 9A shows a flow chart illustrating an exemplary method of fabricating an array of extensible thin film transistors. As shown in Figure 9A, an array of freestanding printable film transistors is provided using the techniques of the present invention. The array of thin film transistors is transferred to a PDMS substrate via a dry transfer contact printing process in a manner that exposes the inner surface of the transistors. The exposed inner surface is then contacted with a room temperature cured pre-strained PDMS layer in an expanded state. Subsequent complete curing of the pre-strained PDMS layer combines the inner surface of the transistors with the pre-strained PDMS layer. The pre-strained PDMS layer is allowed to cool and exhibit an at least partially relaxed state. Relaxation of the PDMS layer introduces a periodic wave structure into the transistor in the array, thereby making it extendable. The inset in Figure 9A provides an atomic force micrograph of an extensible thin film transistor array fabricated by the present method. The atomic force micrograph shows a periodic wave structure that provides good electronic performance in an extended or deformed state.

圖9B提供處於鬆弛及延伸組態之可延伸薄膜電晶體陣列之光學 顯微圖。以在該陣列上產生一約20%之淨應變而不使該等薄膜電晶體破裂或損傷之方式延伸該陣列。經觀察自一鬆弛組態至一應變組態之轉換為一可逆過程。圖9B亦提供針對施加至閘極之若干電位的汲極電流對汲極電壓的圖，其展示該等可延伸薄膜電晶體在鬆弛及延伸組態皆展示良好效能。 Figure 9B provides optics of an extensible thin film transistor array in a relaxed and extended configuration Micrograph. The array is extended in such a manner that a net strain of about 20% is produced on the array without rupturing or damaging the thin film transistors. It was observed that the conversion from a slack configuration to a strain configuration was a reversible process. Figure 9B also provides a plot of the drain current versus gate voltage for a number of potentials applied to the gate, which demonstrates that the extensible thin film transistors exhibit good performance in both relaxed and extended configurations.

實例1：用於橡膠基板上的高效能電子組件之可延伸形式之單晶矽Example 1: Extendable Form Single Crystal Germanium for High Performance Electronic Components on Rubber Substrates

吾人已製造由構造為具有微尺度週期波狀幾何形狀之次微米單晶元件組成之可延伸形式的矽。當由一彈性體基板支撐時，此"波狀"矽能可逆地延伸及壓縮至大應變而不損傷矽。該等波之振幅及週期進行變化以適應此等變形，進而避免矽自身之顯著應變。與矽直接整合之介電質、摻雜劑之圖案、電極及其他元件產生完全形成的、高效能"波狀"金屬氧化物半導體場效應電晶體、pn二極體及其他裝置，其用於可延伸或壓縮至類似大之應變水準之電子電路。 We have fabricated an extensible form of tantalum consisting of submicron single crystal elements constructed to have a micro-scale periodic wavy geometry. When supported by an elastomeric substrate, this "wavy" crucible can reversibly extend and compress to large strain without damaging the crucible. The amplitudes and periods of the waves are varied to accommodate these deformations, thereby avoiding significant strain on the raft itself. Fully integrated dielectric, dopant pattern, electrode and other components to produce fully formed, high performance "wave" metal oxide semiconductor field effect transistors, pn diodes and other devices for An electronic circuit that can be extended or compressed to a similar strain level.

電子學之進步主要由為增加電路運算速度及積體密度、為減少其功率消耗及(對於顯示系統)為使大面積覆蓋成為可能所做出之努力驅使。近來之一方向尋求發展能在具有不尋常外形尺寸之非習知基板上形成高效能電路的方法及材料：紙狀顯示器及光學掃描儀之可撓性塑膠基板、焦平面陣列之球狀曲線支撐及整合之機器人感測器的保形皮膚。當以薄膜形式製備且放置在薄基板薄片上或基板層積板中之中性機械平面附近時，許多電子材料能提供良好彎曲度。在彼等狀態下，該等作用材料在彎曲期間經受之應變可保持在引發破裂所需之典型位準(約1%)以下。對於當操作時可撓曲、延伸或達到極端的彎曲水準之裝置或對於彼等可等形包覆於具有複雜、曲線形狀之支撐物的裝置，要求完全可延伸性，它是一更具挑戰性之特性。在此等系統中，在電路位準之應變可超過幾乎所有已知電子材料，尤其是彼等用於已有應用之良好發展的電子材料，之破裂極限。在某種程度上，此問題 能以使用可延伸導線來互連由剛性隔離島(isolated island)支撐之電子組件(例如電晶體)之電路來避開。可以此策略獲取有價值之結果，儘管其最適合可以相對低覆蓋面積之主動電子元件來達成的應用。吾人報告一不同方法，其中可延伸性直接以具有微米級週期、"波"狀幾何形狀之高品質單晶矽薄膜來達成。此等結構經由波振幅及波長之變化而非經由該等材料自身中之潛在破壞性應變來適應大壓縮及拉伸應變。將此等可延伸"波狀"矽元件與介電質、摻雜劑之圖案及薄金屬膜整合可導致高效能、可延伸電子裝置。 Advances in electronics have been driven primarily by efforts to increase circuit operation speed and bulk density, to reduce power consumption, and (for display systems) to make large-area coverage possible. Recently, one has sought to develop methods and materials for forming high-performance circuits on non-conventional substrates having unusual physical dimensions: flexible plastic substrates for paper displays and optical scanners, and spherical curved support for focal plane arrays. And conformal skin of the integrated robot sensor. Many electronic materials provide good bending when prepared in film form and placed on a thin substrate sheet or near a neutral mechanical plane in a substrate laminate. In these states, the strain experienced by the active materials during bending can be maintained below the typical level (about 1%) required to initiate the fracture. It is a more challenging requirement for devices that can flex, extend or reach extreme bending levels when operating, or for devices that can be isomorphically coated on supports with complex, curved shapes, requiring full extensibility Characteristics of sex. In such systems, the strain at the circuit level can exceed the cracking limit of almost all known electronic materials, especially their well-developed electronic materials for existing applications. In a way, this problem It can be avoided by using an extendable wire to interconnect circuits of electronic components (eg, transistors) supported by rigid islands. This strategy can be used to obtain valuable results, although it is best suited for applications that can be achieved with relatively low coverage active electronic components. We report a different approach in which extensibility is achieved directly with a high quality single crystal germanium film having a micron-scale, "wave"-like geometry. These structures accommodate large compression and tensile strains via changes in wave amplitude and wavelength rather than through potentially destructive strain in the materials themselves. Integrating such extendable "wavy" germanium elements with dielectrics, dopant patterns, and thin metal films can result in high performance, extendable electronics.

圖10表示在彈性體(意即橡膠)基板上波狀單晶矽帶之製造序列。第一步(頂部框)涉及用以在一絕緣物上矽(SOI)晶圓上界定一抗蝕層之光微影術，接著是用以移除頂部矽之曝露部分的蝕刻。用丙酮移除該抗蝕層且然後以濃縮氫氟酸蝕刻內埋的SiO2層使該等帶自下層矽基板釋放。該等帶之末端連接至該晶圓以防止其在蝕刻劑中被洗離。該等抗蝕線之寬度(5-50μm)及長度(約15mm)界定該等帶之尺寸。SOI晶圓上的頂部矽之厚度(20-320nm)界定該等帶厚度。在下一步驟(中間框)中，彈性地延伸一平坦彈性體基板(聚(二甲基矽氧烷)，PDMS；1-3mm厚)且然後使其與該等帶等形接觸。將該PDMS剝離會使該等帶離開該晶圓且使該等帶黏結至該PDMS表面。釋放該PDMS中之應變(意即預應變)導致會引起在該矽及該PDMS表面形成良好界定之波紋的表面變形。(圖11A及11B)該等起伏輪廓係週期在5與50μm之間且振幅在100nm及1.5μm之間(視矽之厚度及該PDMS中預應變之大小而定)的正弦曲線(頂部框，圖11C)。對於一給定系統，該等波之週期及振幅在大面積(若干cm2)上均在約5%內。該等帶之間之PDMS的平滑形態及鄰近帶之波形中不存在相關相表明了該等帶未強力地機械耦接。圖11C(底部框)展示作為沿該等波狀帶之一者之距離的函數而量測之Si尖峰之微拉曼量測結果。該等結果提供了對應力分佈之瞭解。 Fig. 10 shows a manufacturing sequence of a corrugated single crystal tantalum tape on an elastomer (i.e., rubber) substrate. The first step (top box) involves photolithography to define a resist layer on a silicon-on-insulator (SOI) wafer, followed by etching to remove the exposed portions of the top germanium. The resist is removed with acetone and then the buried SiO 2 layer is etched with concentrated hydrofluoric acid to release the strips from the underlying germanium substrate. The ends of the strips are attached to the wafer to prevent it from being washed away in the etchant. The width (5-50 μm) and length (about 15 mm) of the resist lines define the dimensions of the strips. The thickness of the top crucible (20-320 nm) on the SOI wafer defines the strip thickness. In the next step (middle frame), a flat elastomeric substrate (poly(dimethyloxane), PDMS; 1-3 mm thick) is elastically stretched and then brought into contact with the strips. Peeling the PDMS causes the strips to leave the wafer and bond the strips to the PDMS surface. Releasing the strain (i.e., pre-strain) in the PDMS results in surface deformation that causes well-defined corrugations on the surface of the crucible and the PDMS. (Figs. 11A and 11B) sinusoidal curves of the undulating contours between 5 and 50 μm and amplitudes between 100 nm and 1.5 μm (depending on the thickness of the crucible and the pre-strain in the PDMS) (top box, Figure 11C). For a given system, the period and amplitude of the waves are within about 5% over a large area (several cm 2 ). The smooth morphology of the PDMS between the bands and the absence of correlation in the waveforms of the adjacent bands indicate that the bands are not strongly mechanically coupled. Figure 11C (bottom frame) shows the micro-Raman measurement of the Si spike measured as a function of the distance along one of the undulating bands. These results provide an understanding of the stress distribution.

此靜態波狀組態之性質與在一半無限低模數支撐物上之一均勻、薄高模數層中的起始翹棱幾何形狀之非線性分析一致： The nature of this static wavy configuration is consistent with the non-linear analysis of the initial warp geometry in a uniform, thin, high modulus layer on a half-infinite low modulus support:

其中係翹棱之臨界應變，ε pre 係預應變之位 準，λ0係波長且A 0係振幅。柏松比係ν，楊氏模數係E，且該等下標指Si或PDMS之性質。矽之厚度係h。此處理涵蓋了製造成之波狀結構之許多特徵。舉例而言，圖11D展示當該預應變值固定時(約為此等資料之0.9%)，波長及振幅皆線性地視Si厚度而定。波長不取決於預應變之位準(圖12)。此外，使用Si及PDMS之機械性質之文獻值(ESi=130Gpa、EPDMS=2MPa、νSi=0.27、νPDMS=0.48)之計算產生在量測得的值的約10%(最大偏差)範圍內之振幅及波長。"帶應變"由該等帶之有效長度(由波長確定)與其實際長度(由透過AFM量測之表面距離確定)的比例來計算，且產生近似等於該PDMS中預應變之值(對於高達約3.5%之預應變)。矽自身中之應變峰值(意即最大值)(吾人稱為矽應變)係由帶厚度及在應變區中根據κh/2(K係曲率)的在該等波之極限處之曲率半徑估算得，在該等應變區中該等波存在且臨界應變(對於此處之情況，約為0.03%)與跟彎曲相關的應變峰值相比較小。對於圖11之資料，該等矽應變峰值為約0.36(±0.08)%，其比帶應變小兩倍以上。此矽應變對於給定預應變下的所有帶厚度為相同的(圖13)。所得機械優勢(其中該矽應變峰值大大小於帶應變)對於達成可延伸性至關重要。吾人注意到在蒸鍍或旋塗至PDMS上之金屬及介電質中亦已觀察到翹棱薄膜(與如本文所述之預成型、經轉移之單晶元件及裝置形成對比)。 among them The critical strain of the ridge, the level of the pre -strain of the ε pre system, the wavelength of the λ 0 system and the amplitude of the A 0 system. The cypress ratio is ν, the Young's modulus is E, and the subscripts refer to the properties of Si or PDMS. The thickness of 矽 is h. This process covers many of the features that are fabricated into wavy structures. For example, Figure 11D shows that when the pre-strain value is fixed (about 0.9% of such data), the wavelength and amplitude are linearly dependent on the thickness of the Si. The wavelength does not depend on the level of the pre-strain (Figure 12). In addition, the calculation of the literature values (E Si = 130 Gpa, E PDMS = 2 MPa, ν Si = 0.27, ν PDMS = 0.48) using the mechanical properties of Si and PDMS yields about 10% (maximum deviation) of the measured value. The amplitude and wavelength within the range. "Strain" is calculated from the ratio of the effective length of the bands (determined by the wavelength) to its actual length (determined by the surface distance measured by AFM) and produces a value approximately equal to the pre-strain in the PDMS (for up to about 3.5% pre-strain). The strain peak (ie, the maximum value) in the 矽 itself (I call it the 矽 strain) is estimated from the thickness of the belt and the radius of curvature at the limit of the wave according to κ h /2 (K-curvature) in the strain zone. It is assumed that the equipotential waves present in the strain zones and the critical strain (about 0.03% for the case herein) are small compared to the strain peaks associated with bending. For the data of Figure 11, the peak strain of the helium is about 0.36 (±0.08)%, which is more than twice the strain of the band. This strain is the same for all strip thicknesses given a pre-strain (Figure 13). The resulting mechanical advantage, where the 矽 strain peak is much less than the band strain, is critical to achieving extensibility. It has been noted that warped films have also been observed in metals and dielectrics that are either evaporated or spin coated onto PDMS (as opposed to preformed, transferred single crystal elements and devices as described herein).

在製造之後該等波狀結構對施加至彈性體基板之壓縮及拉伸應變的動態回應對可延伸電子裝置最重要。為揭示此過程之機理，當力 被施加至PDMS以在與該等帶的長維平行的方向上壓縮或延伸PDMS時，吾人藉由AFM量測波狀Si帶之幾何形狀。歸因於柏松效應，此力產生沿該等帶及與其垂直方向上之應變。該等垂直應變主要導致該等帶之間之區域中的PDMS的變形。另一方面，沿該等帶之應變是由該等波之結構的變化來適應。圖14A中之三維高度影像及表面輪廓呈現代表性的壓縮、未受力及延伸狀態(自該樣品上輕微不同之位置處收集)。在此等及其他情況下，該等帶在變形期間保持其正弦(圖14A之右邊框中的線)形狀，其中波結構的大約一半位於如由該等帶之間的區域界定之PDMS表面的未受力位置之下(圖15)。圖14B展示相對於該未受力狀態(零)之壓縮(負)及拉伸(正)施加之應變的波長及振幅。該等資料對應於自每點處大量(>50)帶收集之平均的AFM量測結果。所施加的應變由該PDMS基板之所量測的末端間尺寸變化確定。藉由AFM之直接表面量測連同由該等正弦波形估算得之圍線積分展示了所施加的應變等於此處檢查之情況之帶應變(圖16)。(在比該預應變減去該臨界應變更大之拉伸應變處持續之小振幅(<5nm)波可由在該初始翹棱過程期間Si之輕微滑動而導致。在此小(或零)振幅區中計算得之矽應變峰值及帶應變低於實際值。)有趣地是，該等結果指示了該等波狀帶對於所施加應變有兩種不同實體回應。處於緊張狀態時，該等波以一非直觀方式演變：波長不隨所施加應變而明顯變化，從而與翹棱後機理一致。相反，振幅之變化適應該應變。在此狀態中，矽應變隨著延伸該PDMS而變小；當所施加應變等於該預應變時其達到~0%。相反，在壓縮時，隨著增加所施加應變，該等波長減少且振幅增加。此機械回應與一手風琴風箱之機械回應類似，其與拉緊時之特性有本質的不同。在壓縮期間，歸因於波峰及波谷處之曲率半徑之減小，矽應變隨著所施加應變增加而增加。然而，矽應變之增加速率及大小皆遠低於帶應變，如圖14B所示。此機理使可延伸性成為可能。 The dynamic response of the wavy structures to compression and tensile strain applied to the elastomeric substrate after manufacture is of the utmost importance to the extendable electronics. To reveal the mechanism of this process, When applied to the PDMS to compress or extend the PDMS in a direction parallel to the long dimension of the strips, we measure the geometry of the corrugated Si strips by AFM. Due to the cypress effect, this force produces strain along the zones and perpendicular thereto. These vertical strains primarily result in deformation of the PDMS in the region between the bands. On the other hand, the strain along the bands is adapted by the change in the structure of the waves. The three-dimensional height image and surface profile in Figure 14A are representative of the compressed, unstressed, and extended states (collected from slightly different locations on the sample). In these and other instances, the strips maintain their sinusoidal shape (the line in the box to the right of Figure 14A) during deformation, wherein approximately half of the wave structure is located on the PDMS surface as defined by the area between the strips Below the unstressed position (Figure 15). Figure 14B shows the wavelength and amplitude of the compressive (negative) and tensile (positive) applied strain relative to the unstressed state (zero). These data correspond to the average AFM measurements collected from a large number (>50) of bands at each point. The applied strain is determined by the measured dimensional change between the ends of the PDMS substrate. The direct surface measurement by AFM along with the encirclement integral estimated from the sinusoidal waveforms shows that the applied strain is equal to the strain of the condition examined here (Fig. 16). (Small amplitude (<5 nm) waves that continue at a tensile strain greater than the pre-strain minus the critical strain can result from a slight slip of Si during the initial warping process. Here small (or zero) amplitude The calculated strain peaks and band strains in the zone are lower than the actual values.) Interestingly, these results indicate that the undulations have two different physical responses to the applied strain. When in a state of tension, the waves evolve in a non-intuitive manner: the wavelength does not change significantly with the applied strain, which is consistent with the post-warping mechanism. Instead, the change in amplitude adapts to the strain. In this state, the enthalpy strain becomes smaller as the PDMS is extended; it reaches ~0% when the applied strain is equal to the pre-strain. Conversely, as compression increases, as the applied strain increases, the wavelengths decrease and the amplitude increases. This mechanical response is similar to the mechanical response of an accordion bellows, which is essentially different from the characteristics of the tension. During compression, due to the decrease in the radius of curvature at the peaks and troughs, the enthalpy strain increases as the applied strain increases. However, the rate and magnitude of the increase in enthalpy strain are much lower than the band strain, as shown in Figure 14B. This mechanism makes extensibility possible.

與波狀幾何形狀一致之應變範圍中的完全回應可藉由給出波長λ對其在初始翹棱狀態中之值λ 0 ，及所施加應變ε applied 的相依性之方程式來定性地描述： The complete response in the strain range consistent with the wavy geometry can be qualitatively described by the equation giving the dependence of the wavelength λ on its value in the initial ridge state λ 0 and the applied strain ε applied :

舉例而言，此拉緊/壓縮不對稱可由在壓縮期間形成之該PDMS及Si之上升區域之間的輕微可逆間隔所產生。對於此情況，連同對於未呈現此不對稱性質之系統，拉緊及壓縮之波振幅A皆由對於適度應變(<10-15%)有效的單一陳述式給出： For example, this tension/compression asymmetry can result from a slight reversible separation between the PDMS and the rising region of Si formed during compression. For this case, as well as for systems that do not exhibit this asymmetrical nature, the wave amplitude A of the tension and compression is given by a single statement that is valid for moderate strain (<10-15%):

其中A 0 係對應於該初始翹棱狀態之值。如圖14A所示，此等陳述式獲得與實驗的數量一致，而無任何參數擬合。當適應該拉伸/壓縮應變之波狀起伏保持時，矽應變峰值由該彎曲條件控制且由(33)給出 Where A 0 corresponds to the value of the initial ridge state. As shown in Figure 14A, these statements were obtained consistent with the number of experiments without any parameter fit. When accommodating the undulating undulation of the tensile/compressive strain, the 矽 strain peak is controlled by the bending condition and is given by (33)

其與圖14B中由曲率量測之應變十分一致。(亦參看圖18)。此分析陳述式有助於界定該系統能承受而不使矽破裂之所施加應變之範圍。對於0.9%之預應變，若假設矽失效應變為約2%(對於壓縮或者拉伸)，則此範圍為-27% to 2.9%。控制預應變之位準允許將此應變範圍(意即接近30%)用以平衡壓縮與拉伸變形的所要程度。舉例而言，一3.5%之預應變(所檢查之最大值)產生-24% to 5.5%的範圍。吾人注意到此等計算假設甚至在極端的變形水準下所施加應變也等於帶應變。在實驗上，吾人發現歸因於在該等帶之末端以外及該等帶之間用以適應應變以使得所施加應變不被完全轉移至該等帶的PDMS之能力，此等估算結果通常被超過。 This is in good agreement with the strain measured by curvature in Figure 14B. (See also Figure 18). This analytical statement helps define the range of strains that the system can withstand without rupturing the raft. For a 0.9% pre-strain, this range is -27% to 2.9% if the 矽 failure strain is assumed to be about 2% (for compression or stretching). Controlling the level of pre-strain allows this strain range (ie, close to 30%) to balance the desired degree of compression and tensile deformation. For example, a 3.5% pre-strain (the maximum value examined) yields a range of -24% to 5.5%. We have noticed that these calculations assume that the strain applied even at extreme deformation levels is equal to the strain. Experimentally, we have found that the results are usually attributed to the ability to adapt the strain outside the ends of the bands and the bands so that the applied strain is not completely transferred to the PDMS of the bands. exceed.

吾人已藉由在製造序列(圖10，頂部框)之開始包括額外之步驟來 使用習知處理技術界定矽中摻雜劑的圖案、薄金屬觸點及介電層而建立功能性、可延伸裝置。以此方式製造之兩個及三個端子裝置、二極體及電晶體分別提供具有進階功能性之電路的基礎建構區塊。其中整合之帶裝置首先被自SOI起離至一未變形PDMS板上且然後至一預應變PDMS基板之雙重轉移過程可建立波狀裝置，其具有經曝露以用於探測的金屬觸點。圖17A及17B展示針對施加至PDMS之各種位準之應變的一可延伸pn接面二極體之光學影像及電回應。吾人發現在具有延伸或壓縮之裝置的電性質中沒有在資料之散佈範圍中的系統變化。該等曲線中之偏差主要歸因於探針觸點之品質之變化。此等pn接面二極體除作為普通整流裝置之外可用作一光偵測器(處於相反偏壓狀態)或用作光伏打裝置。光電流密度在約-1V之反向偏壓時為約35mA/cm2。在正向偏壓，短路電流密度及開路電壓分別為約17mA/cm2及0.2V，其產生0.3之填充因子。回應之形狀與模型化(圖17B中之實線)一致。裝置性質即使在約100個壓縮、延伸及釋放週期之後亦未顯著變化(圖19)。圖17C展示一可延伸、波狀矽肖特基障壁金屬氧化物半導體場效應電晶體(MOSFET)之電流-電壓特性，該MOSFET是藉由與用於pn二極體之程序類似的程序且藉由作為閘極介電質(33)之熱SiO2之整合薄層(40nm)形成。由對此波狀電晶體之電學量測而擷取之裝置參數(線形範圍遷移率約100cm2/Vs(可能限於觸點)、臨限電壓約-3V)可與使用相同處理條件在SOI晶圓上形成的裝置之裝置參數相比較。(圖20及21)。如在pn二極體中，此等波狀電晶體能可逆地延伸及壓縮至大應變位準而不損傷該等裝置或顯著改變電性質。在二極體及電晶體中，在該等裝置之末端以外的PDMS之變形導致比所施加應變更小的裝置(帶)應變。總體可延伸性由裝置可延伸性及此等類型之PDMS變形之組合效應導致。在比此處檢查之壓縮應變更大之壓縮應變下，PDMS傾向於以一使得探測變得困難的方式彎曲。在更大之拉 緊應變下，視矽厚度、帶長度及矽與PDMS之間結合的強度而定，該等帶破裂、抑或滑動且保持完整。 We have established functionality and extendability by including additional steps in the fabrication sequence (Fig. 10, top box) to define patterns, thin metal contacts and dielectric layers of dopants in germanium using conventional processing techniques. Device. Two and three terminal devices, diodes, and transistors fabricated in this manner provide a basic building block for circuits having advanced functionality, respectively. The dual band transfer process in which the integrated tape device is first separated from the SOI onto an undeformed PDMS plate and then to a pre-strained PDMS substrate can establish a wavy device having metal contacts exposed for detection. 17A and 17B show optical images and electrical responses of an extendable pn junction diode for strain applied to various levels of PDMS. We have found no systematic changes in the spread of data in the electrical properties of devices with extension or compression. The deviations in these curves are primarily due to changes in the quality of the probe contacts. These pn junction diodes can be used as a photodetector (in an opposite bias state) or as a photovoltaic device in addition to being a conventional rectifying device. The photocurrent density was about 35 mA/cm 2 at a reverse bias of about -1 V. At forward bias, the short circuit current density and open circuit voltage were about 17 mA/cm 2 and 0.2 V, respectively, which produced a fill factor of 0.3. The shape of the response is consistent with the modeling (solid line in Figure 17B). The device properties did not change significantly even after about 100 compression, extension and release cycles (Figure 19). Figure 17C shows the current-voltage characteristics of an extendable, undulating Schottky barrier MOSFET (MOSFET) that is similar to the program used for the pn diode and borrows It is formed of an integrated thin layer (40 nm) of thermal SiO 2 as a gate dielectric (33). The device parameters extracted from the electrical measurement of the corrugated transistor (linear range mobility of about 100 cm 2 /Vs (possibly limited to contacts), threshold voltage of about -3 V) can be used with the same processing conditions in the SOI crystal The device parameters of the device formed on the circle are compared. (Figures 20 and 21). As in pn diodes, such wavy transistors can reversibly extend and compress to large strain levels without damaging the devices or significantly altering electrical properties. In diodes and transistors, deformation of the PDMS beyond the ends of the devices results in straining of the device (tape) that is less than the applied change. The overall extensibility results from the combination of device extensibility and the PDMS deformation of these types. At compressive strains greater than the compressive strain examined here, PDMS tends to bend in a manner that makes detection difficult. At greater tensile strains, depending on the thickness of the crucible, the length of the strip, and the strength of the bond between the crucible and the PDMS, the strips rupture, or slip and remain intact.

此等可延伸矽MOSFET及pn二極體僅表示可形成之許多類型"波狀"電子裝置中之兩種。完整電路薄片或薄矽板亦可被結構化為單軸或雙軸可延伸波狀幾何形狀。除了波狀裝置之惟一機械特性以外，會在許多半導體中產生的應變與電子特性的耦合亦提供了設計可利用應變中之機械可調節、週期性變化以達成不同尋常之電子回應之裝置結構的機會。 These extendable MOSFETs and pn diodes represent only two of many types of "wavy" electronic devices that can be formed. The complete circuit sheet or web can also be structured into a uniaxial or biaxial extendable wavy geometry. In addition to the unique mechanical properties of the wavy device, the coupling of strain and electronic properties that can occur in many semiconductors also provides for the design of device structures that utilize mechanically adjustable, periodic variations in strain to achieve an unusual electronic response. opportunity.

材料及方法 Materials and methods

樣品製備：由Si基板(Soitec公司)上的SiO2(145nm、145nm、200nm、400nm、400nm或1μm之厚度)上的Si(20、50、100、205、290或320nm之厚度)組成之絕緣物上矽(SOI)晶圓。在一種狀況下，吾人使用Si(Shin-Etsu)上的Si(約2.5μm之厚度)及SiO2(約1.5μm之厚度)之SOI晶圓。在所有狀況下，摻雜硼(p型)或磷(n型)之頂部Si層具有在5至20Ωcm之間的電阻率。此等SOI晶圓之頂部Si以光阻劑(AZ 5214光阻劑，Karl Suss MJB-3接觸遮罩對準器)圖案化且經反應性離子蝕刻(RIE)以界定Si帶(5~50μm寬，15mm長)(PlasmaTherm RIE,SF6 40sccm,50mTorr,100W)。藉由在HF(49%)中底切蝕刻來移除該SiO2層，該蝕刻時間主要視Si帶之寬度而定。橫向蝕刻速率通常為2至3μm/min。藉由將基底與固化劑以10：1之重量比例混合且在70℃下固化>2小時或在室溫下固化>12小時來準備聚(二甲基矽氧烷)(PDMS)彈性體(Sylgard 184,Dow Corning)之板。 Sample preparation : Insulation consisting of Si (thickness of 20, 50, 100, 205, 290 or 320 nm) on SiO 2 (thickness of 145 nm, 145 nm, 200 nm, 400 nm, 400 nm or 1 μm) on a Si substrate (Soitec) On-site silicon (SOI) wafers. In one case, we used an SOI wafer of Si (thickness of about 2.5 μm) and SiO 2 (thickness of about 1.5 μm) on Si (Shin-Etsu). In all cases, the top Si layer doped with boron (p-type) or phosphorus (n-type) has a resistivity between 5 and 20 Ωcm. The top Si of these SOI wafers is patterned with a photoresist (AZ 5214 photoresist, Karl Suss MJB-3 contact mask aligner) and reactive ion etching (RIE) to define the Si band (5-50 μm) Width, 15mm long) (PlasmaTherm RIE, SF6 40sccm, 50mTorr, 100W). The SiO 2 layer was removed by undercut etching in HF (49%), which was mainly determined by the width of the Si strip. The lateral etch rate is typically 2 to 3 μm/min. Preparation of poly(dimethyloxane) (PDMS) elastomer by mixing the substrate with a curing agent in a weight ratio of 10:1 and curing at 70 ° C for > 2 hours or at room temperature for > 12 hours Sylgard 184, Dow Corning) board.

將此等PDMS平板(1至3mm之厚度)與已蝕刻SOI晶圓上之Si共形接觸以產生該等波狀結構。可使用在此接觸之前建立該PDMS之受控膨脹、繼之以在自晶圓移除後收縮的任何方法。吾人檢查三種不同技術。在第一種技術中，在接觸該SOI基板之後對PDMS之機械輥軋建 立該等預應變。儘管波狀結構可以此方式形成，但是其傾向於具有非均勻的波週期及振幅。在第二種技術中，在接觸之前將該PDMS(熱膨脹係數=3.1×10-4K-1)加熱至30℃與180℃之間的溫度且然後在自該SOI移除後將其冷卻，其以一高度可重現的方式在大面積上產生具有良好均勻性之波狀Si結構。以此方法，吾人藉由改變溫度來準確地控制PDMS中預應變位準(圖12)。第三種方法使用在與SOI接觸之前用機械台延伸且接著在移除之後實體地釋放之PDMS。與熱學方法類似，此方法允許有良好均勻性及重現性，但與該熱學方法相比更難以精細地調節預應變位準。 These PDMS plates (1 to 3 mm thickness) are conformally contacted with Si on the etched SOI wafer to create the wavy structures. Any method of establishing controlled expansion of the PDMS prior to this contact, followed by shrinkage after removal from the wafer, can be used. We check three different technologies. In the first technique, the pre-strain is established for mechanical rolling of the PDMS after contacting the SOI substrate. Although the wavy structure can be formed in this manner, it tends to have a non-uniform wave period and amplitude. In the second technique, the PDMS (thermal expansion coefficient = 3.1 × 10 -4 K -1 ) is heated to a temperature between 30 ° C and 180 ° C before contact and then cooled after being removed from the SOI, It produces a wavy Si structure with good uniformity over a large area in a highly reproducible manner. In this way, we accurately control the pre-strain level in the PDMS by changing the temperature (Figure 12). The third method uses a PDMS that is extended with a mechanical table prior to contact with the SOI and then physically released after removal. Similar to the thermal method, this method allows for good uniformity and reproducibility, but it is more difficult to finely adjust the pre-strain level than the thermal method.

對於諸如pn接面二極體及電晶體之裝置，電子束蒸鍍(Temescal BJD1800)且光微影圖案化(經由蝕刻或起離)的金屬層(Al、Cr、Au)充當觸點及閘極。將旋塗摻雜劑(SOD)(對於p型，B-75X，Honeywell，USA；對於n型，P509，Filmtronics，USA)用於摻雜矽帶。首先將該等SOD材料旋塗(4000rpm，20s)至預圖案化SOI晶圓上。藉由電漿增強化學氣相沈積(PECVD)(PlasmaTherm)製備之二氧化矽層(300nm)用作該SOD之遮罩。在950℃加熱10秒之後，使用6：1之緩衝氧化物蝕刻劑(BOE)蝕刻掉SOI晶圓上之SOD與遮罩層。對於電晶體裝置，熱生長(藉由爐中之高純度氧氣流乾式氧化至25nm與45nm之間的厚度，1100℃，10~20分鐘)之二氧化矽提供閘極介電質。在完成該SOI基板上的所有裝置處理步驟之後，藉由光阻(AZ5214或Shipley S1818)來覆蓋具有整合之裝置結構之Si帶(通常50μm寬，15mm長)以在下層SiO2之HF蝕刻期間保護該裝置層。在藉由氧電漿移除該光阻層之後，將無任何預應變之平坦PDMS(70℃，>4小時)板用於自處於平坦幾何形狀的SOI基板移除該等帶裝置。然後將部份固化的PDMS(在將基底與固化劑混合之後在室溫下>12小時)板與該完全固化PDMS板上的該等Si帶裝置接觸。完成該部份固化PDMS之固化(藉由在70℃加熱)，接 著移除此板，將該等裝置自該第一PDMS板轉移至該新PDMS基板。與冷卻至室溫相關聯之收縮會建立一預應變，使得移除及釋放建立波狀裝置，同時電極被曝露以用於探測。 For devices such as pn junction diodes and transistors, electron beam evaporation (Temescal BJD1800) and photolithographic patterning (via etching or delamination) of the metal layer (Al, Cr, Au) acts as contacts and gates pole. Spin-on dopant (SOD) (for p-type, B-75X, Honeywell, USA; for n-type, P509, Filmtronics, USA) was used for doping the anthracene. The SOD materials were first spin coated (4000 rpm, 20 s) onto a pre-patterned SOI wafer. A cerium oxide layer (300 nm) prepared by plasma enhanced chemical vapor deposition (PECVD) (Plasma Therm) was used as a mask for the SOD. After heating at 950 ° C for 10 seconds, the SOD and mask layers on the SOI wafer were etched away using a 6:1 buffered oxide etchant (BOE). For the transistor device, the thermal growth (dry oxidation of the high purity oxygen stream in the furnace to a thickness between 25 nm and 45 nm, 1100 ° C, 10-20 minutes) of the cerium oxide provides a gate dielectric. After completing all device processing steps on the SOI substrate, the Si strip (typically 50 μm wide, 15 mm long) with integrated device structure is covered by photoresist (AZ5214 or Shipley S1818) for HF etching during the underlying SiO 2 Protect the device layer. After removal of the photoresist layer by oxygen plasma, a flat PDMS (70 ° C, > 4 hour) plate without any pre-strain was used to remove the ribbon device from the SOI substrate in a flat geometry. The partially cured PDMS (>12 hours at room temperature after mixing the substrate with the curing agent) is then contacted with the Si-belt devices on the fully cured PDMS board. The curing of the partially cured PDMS is completed (by heating at 70 ° C), followed by removal of the plate, and the devices are transferred from the first PDMS plate to the new PDMS substrate. The shrinkage associated with cooling to room temperature establishes a pre-strain such that the removal and release establishes the wavy device while the electrodes are exposed for detection.

量測：將原子力顯微圖(AFM)(D1-3100，Veeco)用以精確地量測該等波性質(波長、振幅)。自所獲得之影像，量測且統計地分析沿該波狀Si之截面輪廓。使用一自製延伸台、以及AFM及半導體參數分析器(Agilent，5155C)來量測波狀Si/PDMS之機械及電回應。藉由Jobin Yvon HR 800光譜分析器使用來自He-Ne雷射之632.8nm的光執行拉曼量測。沿該波狀Si以1μm間隔量測該拉曼光譜，其中在沿該等結構之長度的每一位置處調整焦點以最大化訊號。所量測光譜藉由洛仁子函數來擬合以定位尖峰波數。歸因於尖峰波數對顯微鏡之聚焦位置之輕微依賴，拉曼結果僅提供對應力分佈的定性瞭解。 Measurement : An atomic force micrograph (AFM) (D1-3100, Veeco) was used to accurately measure the properties of the waves (wavelength, amplitude). From the obtained image, the cross-sectional profile along the wavy Si is measured and statistically analyzed. The mechanical and electrical response of the wavy Si/PDMS was measured using a self-contained extension station and an AFM and a semiconductor parameter analyzer (Agilent, 5155C). Raman measurements were performed using a Jobin Yvon HR 800 spectral analyzer using 632.8 nm light from a He-Ne laser. The Raman spectrum is measured at intervals of 1 [mu] along the wavy Si, wherein the focus is adjusted at each position along the length of the structures to maximize the signal. The measured spectra are fitted by the Loren subfunction to locate the peak wavenumber. Due to the slight dependence of the peak wavenumber on the focus position of the microscope, the Raman results only provide a qualitative understanding of the stress distribution.

圍線長度、帶應變及矽應變之計算：該等實驗結果展示，對於此處探究之材料及幾何形狀範圍，波狀Si的形狀可準確地用簡單正弦 函數(意即，y=Asin(kx)(k=2π/λ))來表示。然後按來計算 該圍線長度。 Calculation of the length of the line, the strain of the belt and the strain of the enthalpy : These experimental results show that for the material and geometry range explored here, the shape of the wavy Si can be accurately approximated by a simple sine function (ie y=Asin(kx) ) (k = 2π / λ)) to represent. then press To calculate the length of the fence.

使用來計算波狀Si之帶應變。矽應變峰值在該等波之波 峰及波谷處產生，且使用來計算，其中h為Si厚度，且R c 係 波峰或波谷處之曲率半徑，其由給出，其中n係一整數 且y"係y關於x的二階導數。使用該實際形狀之正弦函數近似，矽應變 峰值由給出。圖12展示作為用以建立該預應變之溫度之函 數的波長。如圖13展示，歸因於波振幅及波長對厚度之線形相依性(A~h，λ~h)，該應變峰值獨立於Si厚度。圖15展示了波狀結構包含相對於該等帶之間之PDMS表面的水平面的幾乎相等之向上及向下移 位。矽帶應變等於此處檢查之系統之所施加應變(圖16)。 use To calculate the strain of the wavy Si band. The peak value of the 矽 strain is generated at the peaks and troughs of the waves, and is used To calculate, where h is the thickness of Si, and R c is the radius of curvature at the peak or trough, which is determined by Given, where n is an integer and y" is the second derivative of y with respect to x. Using the sinusoidal approximation of the actual shape, the 矽 strain peak is determined by Given. Figure 12 shows the wavelength as a function of the temperature used to establish the pre-strain. As shown in Figure 13, the strain peak is independent of the Si thickness due to the wave amplitude and the linear dependence of the wavelength versus thickness ( A ~ h , λ ~ h ). Figure 15 illustrates the wavy structure comprising nearly equal upward and downward displacements relative to the horizontal plane of the PDMS surface between the bands. The enthalpy strain is equal to the strain applied by the system examined here (Figure 16).

一手風琴風箱模型：當在壓縮時矽可與PDMS分離時，系統由手風琴風箱機理而非翹棱機理支配。在該風箱狀況下，所施加之壓縮應變(εapplied)之波長為λ0(1 +εapplied)，其中λ為無應變組態中的波長，如方程式(2)所描述。因為矽帶之圍線長度在壓縮應變之前及之後近似相同，吾人可使用以下關係式來確定波振幅A。 One accordion bellows model: When 矽 can be separated from PDMS during compression, the system is dominated by the accordion bellows mechanism rather than the ribbing mechanism. In the bellows condition, the applied compressive strain (ε applied ) has a wavelength of λ 0 (1 + ε applied ), where λ is the wavelength in the unstrained configuration, as described in equation (2). Since the length of the enveloping line is approximately the same before and after the compressive strain, we can use the following relationship to determine the wave amplitude A.

此方程式對於具有漸近解。在小壓 縮應變下，此方程式簡化為方程式(3)，其亦適用於Si與PDMS之分離係不可能的情況，且該體系遵循翹棱機理。矽應變峰值由 給出。對於中度壓縮應變，此陳述式近似 與方程式(4)相同。在施加中度應變的界限內，與波振幅類似，矽應變峰值對於該風箱模型及該翹棱模型具有類似函數形式。圖18展示根據以上陳述式及根據方程式(4)計算之應變峰值。 This equation is for Asymptotic solution . At small compressive strains, this equation is reduced to equation (3), which is also applicable to the case where the separation of Si and PDMS is not possible, and the system follows the warping mechanism.矽 strain peak by Given. For moderate compressive strains, this statement is approximately the same as equation (4). Within the limits of the application of moderate strain, similar to the wave amplitude, the 矽 strain peak has a similar functional form for the bellows model and the warp model. Figure 18 shows the strain peaks calculated according to the above statement and according to equation (4).

裝置特徵化：將半導體參數分析器(Agilent，5155C)及習知探測台用於該等波狀pn接面二極體及電晶體之電學特徵化。Pn二極體之光回應在約1W/cm2之照度下量測，如藉由一光學功率計(Ophir Optronics公司，Laser Power Meter AN/2)來量測。吾人使用機械台在延伸及壓縮期間及之後來量測該等裝置。作為探究該過程之可逆性的方法，吾人在約100個壓縮(至約5%應變)、延伸(至約15%應變)及釋放週期之前及之後在環境光下量測三個不同pn二極體。圖19展示結果。圖20及21展示來自波狀電晶體之影像、示意性說明及裝置量測結果。 Device Characterization : A semiconductor parameter analyzer (Agilent, 5155C) and a conventional probe station are used for the electrical characterization of the wavy pn junction diodes and transistors. The light response of the Pn diode was measured at an illumination of about 1 W/cm 2 , as measured by an optical power meter (Ophir Optronics, Laser Power Meter AN/2). We use mechanical stations to measure these devices during and after extension and compression. As a way to explore the reversibility of this process, we measured three different pn dipoles under ambient light before and after about 100 compressions (to about 5% strain), extension (to about 15% strain), and after the release cycle. body. Figure 19 shows the results. Figures 20 and 21 show images, schematic illustrations, and device measurements from a wavy transistor.

實例2：用於彈性體基板上的高效能電子電路之翹棱及波狀GaAs帶Example 2: Warped and Wavy GaAs Tapes for High Performance Electronic Circuits on Elastomeric Substrates

製造厚度在次微米範圍內且具有良好界定的、"波狀"及/或"翹棱" 幾何形狀之單晶GaAs帶。位於一彈性體基板之表面上或嵌入一彈性體基板中之所得結構展示達到>10%之應變的可逆延伸性及壓縮性，比GaAs自身的可逆延伸及壓縮應變大十倍以上。藉由在此等結構之GaAs帶上整合歐姆及肖特基觸點，可達成高效能可延伸電子裝置(例如金屬半導體場效應電晶體)。此類電子系統可單獨使用或與類似設計之矽、介電質及/或金屬材料組合使用，以形成用於要求高頻率運作以及可延伸性、極端可撓性或與具有複雜曲線形狀之表面相符的能力之應用的電路。 Manufactured in the submicron range with well defined, "wavy" and / or "warped" A single crystal GaAs ribbon of geometric shape. The resulting structure on the surface of an elastomeric substrate or embedded in an elastomeric substrate exhibits a reversible extensibility and compressibility of >10% strain, which is more than ten times greater than the reversible extension and compressive strain of GaAs itself. By integrating ohmic and Schottky contacts on the GaAs strips of such structures, high performance extendable electronics (e.g., metal semiconductor field effect transistors) can be achieved. Such electronic systems can be used alone or in combination with similarly designed germanium, dielectric and/or metallic materials to form surfaces for requiring high frequency operation as well as extensibility, extreme flexibility, or with complex curved shapes. A circuit that matches the capabilities of the application.

在傳統微電子學中，主要根據速度、功率效率及整合層級來量測效能能力。而在其他更新的電子裝置形態中的進步是由在非習知基板(例如低成本塑膠、箔、紙)上達成整合或覆蓋大面積之能力所驅動的。舉例而言，藉由等形地包裹身體以數位地將所要組織成像之大面積成像器可達成新形式的X射線醫療診斷。可在多種表面及表面形狀上展開之輕重量、牆壁尺寸之顯示器或感測器提供了用於建築設計之新技術。已探究包括小有機分子、聚合物、非晶系矽、多晶矽、單晶矽奈米線及微結構帶之各種材料，以充當可支援此等及其他應用之類型的薄膜電子裝置的半導體通道。此等材料使具有跨越一廣泛範圍(意即自10-5至500cm2/V．s)之遷移率及在可撓性基板上呈可機械彎曲薄膜形態之電晶體成為可能。諸如大孔徑干涉合成孔徑雷達(InSAR)及射頻(RF)監視系統之要求高速運作之應用要求具有很高遷移率的半導體，諸如GaAs，或InP等等。單晶複合物半導體之脆弱性產生若干必須克服之製造挑戰以便製造具有該等半導體的高速、可撓性電晶體。吾人藉由使用自高品質塊晶圓建立之印刷GaAs線陣列來於塑膠基板上建構金屬半導體場效應電晶體(MESFET)而建立一實際方法。此等裝置即使在中等規模裝置(例如微米閘長度)中亦展示良好機械可撓性及接近2GHz之fT'。此實例展示基於GaAs帶之MESFET(與線裝置 相反)，其經設計具有特殊幾何形狀，不僅提供可彎曲性而且提供顯著超過該GaAs自身的本質屈服點(約2%)之應變水準(約10%)之機械可延伸性。所得之類型的可延伸高效能電子系統可提供極高水準的可彎曲性及與曲線表面等形整合之能力。此GaAs系統實例以四種重要方式擴展吾人所描述之"波狀"矽：(i)其展示GaAs(GaAs在實際條件下是比Si更機械脆弱之材料)之可延伸性，(ii)其引入一新"翹棱"幾何形狀，其可連同先前描述之"波狀"組態或獨立於先前描述之"波狀"組態而用於實現可延伸性，(iii)其達成一新類型可延伸裝置(意即MESFET)，及(iv)其展示了與矽相比可延伸於更大範圍中且在壓縮/拉緊中具有更大對稱性的延伸。 In traditional microelectronics, performance capabilities are measured primarily in terms of speed, power efficiency, and integration levels. Advances in other newer electronic device formats have been driven by the ability to integrate or cover large areas on non-conventional substrates such as low cost plastics, foils, and paper. For example, a new form of X-ray medical diagnosis can be achieved by a large area imager that isomorphically wraps the body to digitally image the desired tissue. Lightweight, wall-sized displays or sensors that can be deployed on a variety of surfaces and surface shapes provide new technologies for architectural design. Various materials including small organic molecules, polymers, amorphous germanium, polycrystalline germanium, single crystal germanium wires, and microstructured tapes have been explored to serve as semiconductor channels for thin film electronic devices that support these and other applications. These materials make it possible to have a mobility that spans a wide range (i.e., from 10 -5 to 500 cm 2 /V.s) and a mechanically bendable film morphology on a flexible substrate. Applications requiring high speed operation, such as large aperture interferometric synthetic aperture radar (InSAR) and radio frequency (RF) monitoring systems, require semiconductors with very high mobility, such as GaAs, or InP. The fragility of single crystal composite semiconductors creates several manufacturing challenges that must be overcome in order to fabricate high speed, flexible transistors with such semiconductors. We have established a practical method by constructing a metal semiconductor field effect transistor (MESFET) on a plastic substrate using a printed GaAs line array built from high quality bulk wafers. These devices exhibit good mechanical flexibility and f T ' near 2 GHz even in medium scale devices (e.g., micro-gate lengths). This example shows a GaAs-based MESFET (as opposed to a wire device) that is designed with a special geometry that not only provides bendability but also provides a strain level that is significantly above the inherent yield point of the GaAs itself (about 2%) (about 10 %) mechanical extensibility. The resulting type of extensible high performance electronic system provides a very high level of flexibility and the ability to integrate contours with curved surfaces. This example of a GaAs system expands the "wavy" described by us in four important ways: (i) it exhibits the extensibility of GaAs (a material that is more mechanically weaker than Si under actual conditions), and (ii) its Introducing a new "warping" geometry that can be used to achieve extensibility in conjunction with the previously described "wavy" configuration or independent of the previously described "wavy" configuration, (iii) achieving a new type An extendable device (ie MESFET), and (iv) it exhibits an extension that can extend over a larger range than 矽 and has greater symmetry in compression/tension.

圖22說明用於在一由聚(二甲基矽氧烷)(PDMS)製造之彈性體基板上製造可延伸GaAs帶之步驟。該等帶由具有多個磊晶層之高品質GaAs塊晶圓產生。該晶圓是藉由在一(100)半絕緣GaAs(Si-GaAs)晶圓上生長一200nm厚AlAs層，接著順序沈積一具有150nm厚度之Si-GaAs層及具有120nm厚度及4×1017cm-3載體濃度之Si摻雜n型GaAs層來製備。與(0 )結晶方向平行而界定之光阻線之圖案充當磊晶層(包括GaAs及AlAs)的化學蝕刻之遮罩。使用H3PO4及H2O2之含水蝕刻劑之各向異性蝕刻將此等頂部層隔離為具有由光阻界定的長度及取向，且具有相對於晶圓表面成銳角之側壁的個別條塊。在該各向異性蝕刻之後移除該光阻且接著將該晶圓浸泡於HF之乙醇溶液(乙醇與49%含水HF之間體積比為2：1)可移除該AlAs層及釋放GaAs帶(n-GaAs/Sl-GaAs)。在此步驟中，使用乙醇取代水減少了歸因於乾燥期間之毛細管力之作用而在該等易碎帶中可發生的破裂。與水相比乙醇之更低之表面張力亦最小化了在該等GaAs帶之空間布局中的由乾燥引發之無序。在下一步驟中，將具有釋放的GaAs帶之晶圓與一預延伸PDMS平板之表面接觸，使該等帶沿延伸方向對準。在此種狀況 下，凡得瓦爾力在PDMS與GaAs之間之交互作用中占主要地位。對於要求更強交互作用強度之狀況，將SiO2之一薄層沈積至GaAs上，且在接觸之前不久將PDMS曝露於紫外線引發之臭氧(意即，空氣中氧氣之產物)。臭氧在PDMS之表面上產生-Si-OH基團，其一經接觸就與SiO2表面反應以形成橋接矽氧烷-Si-O-Si-鍵。由於該等帶之側面之幾何形狀，所沈積SiO2在每一帶的邊緣處係非連續的。對於弱及強結合程序兩者而言，將該PDMS自該母晶圓剝離就使所有帶轉移至PDMS之表面。使該PDMS中預應變鬆弛會導致沿該等帶之大尺度翹棱及/或正弦波狀結構之自發形成。該等帶之幾何形狀極大地取決於施加至該***之預應變(藉由△L/L界定)、PDMS與帶之間的交互作用、及該等帶之撓曲剛性。對於此處研究之帶，小預應變(<2%)對於強及弱交互作用之狀況皆產生具有相對小的波長及振幅之高度正弦的"波"(圖22右邊框、中間框)。GaAs中此等幾何形狀與針對Si報告之幾何形狀類似。可施加更高之預應變(例如高達約15%)以建立類似類型的波，其中在該等帶與該基板之間存在強結合。在弱交互作用強度及大預應變之狀況下形成由具有相對大振幅及寬度之無週期"翹棱"組成之不同類型的幾何形狀(圖22右邊框、頂部框)。另外，吾人之研究結果展示兩種類型結構(翹棱及波)可在單一帶中共存，其撓曲剛性沿其長度變化(例如歸因於與裝置結構相關聯之厚度變化)。 Figure 22 illustrates the steps for fabricating an extensible GaAs ribbon on an elastomeric substrate made from poly(dimethyloxane) (PDMS). The strips are produced from a high quality GaAs bulk wafer having a plurality of epitaxial layers. The wafer is grown by growing a 200 nm thick AlAs layer on a (100) semi-insulating GaAs (Si-GaAs) wafer, followed by sequentially depositing a Si-GaAs layer having a thickness of 150 nm and having a thickness of 120 nm and 4×10 17 It is prepared by a Si-doped n-type GaAs layer of a cm -3 carrier concentration. And (0 The pattern of the photoresist lines defined by the parallel crystal directions serves as a mask for chemical etching of the epitaxial layers (including GaAs and AlAs). Anisotropic etching of an aqueous etchant using H 3 PO 4 and H 2 O 2 isolating the top layers into individual strips having lengths and orientations defined by photoresist and having sidewalls at acute angles relative to the wafer surface Piece. After removing the photoresist after the anisotropic etching and then immersing the wafer in an ethanol solution of HF (volume ratio of 2:1 between ethanol and 49% aqueous HF), the AlAs layer and the GaAs strip can be removed. (n-GaAs/Sl-GaAs). In this step, the use of ethanol instead of water reduces cracking that can occur in such frangible zones due to the action of capillary forces during drying. The lower surface tension of ethanol compared to water also minimizes the disorder caused by drying in the spatial layout of the GaAs ribbons. In the next step, the wafer with the released GaAs ribbon is brought into contact with the surface of a pre-stretched PDMS panel to align the ribbons in the direction of extension. Under such conditions, Van der Valli dominates the interaction between PDMS and GaAs. For conditions requiring stronger interaction strength, a thin layer of SiO 2 is deposited onto the GaAs and the PDMS is exposed to ultraviolet-induced ozone (i.e., the product of oxygen in the air) shortly before the contact. Ozone produces a -Si-OH group on the surface of the PDMS which upon contact reacts with the surface of the SiO 2 to form a bridged siloxane-Si-O-Si- linkage. Due to the geometry of the sides of the strips, the deposited SiO 2 is discontinuous at the edges of each strip. For both weak and strong bonding procedures, stripping the PDMS from the mother wafer transfers all of the tape to the surface of the PDMS. Pre-strain relaxation in the PDMS can result in spontaneous formation of large-scale ridges and/or sinusoidal structures along the zones. The geometry of the bands greatly depends on the pre-strain applied to the stamp (defined by Δ L /L), the interaction between the PDMS and the strip, and the flexural rigidity of the strips. For the bands studied here, the small pre-strain (<2%) produces a highly sinusoidal "wave" with relatively small wavelengths and amplitudes for both strong and weak interactions (Fig. 22 right border, middle frame). These geometries in GaAs are similar to the geometries reported for Si. Higher pre-strains (e.g., up to about 15%) can be applied to create similar types of waves where there is a strong bond between the strips and the substrate. Different types of geometries composed of a periodless "warping" having a relatively large amplitude and width are formed under the condition of weak interaction strength and large pre-strain (Fig. 22 right border, top frame). In addition, our findings suggest that two types of structures (warping and waves) can coexist in a single band with varying flexural stiffness along their length (eg, due to thickness variations associated with device structure).

圖23展示了藉由PDMS(約5mm厚度)與帶之間的強結合而形成之具有270nm(包括n-GaAs及Si-GaAs層)厚度及100μm(此實例中討論的所有帶皆具有100μm之寬度)寬度之波狀GaAs帶的若干顯微圖。使用在GaAs上的2-nm Ti及28-nm SiO2層，該製造遵循強結合之程序。在結合之前不久或在結合期間藉由熱膨脹(在一烘箱中加熱至90℃)而在PDMS中建立約1.9%(自PDMS之熱回應計算得)的雙軸預應變。此加熱亦加速界面矽氧烷鍵之形成。在將GaAs帶轉移之後將該PDMS冷卻至 室溫(約27℃)，從而釋放預應變。圖23之框A、B及C分別展示用光學顯微鏡、電子掃描顯微鏡(SEM)及原子力顯微鏡(AFM)自相同樣品收集之影像。該等影像展示了該等GaAs帶中週期性、波狀結構之形成。藉由自AFM影像(圖23D)估計切割線(圖23E及23F)來定量地分析該等波。與帶之縱向方向平行之圍線清楚地展示了與正弦波(圖23E之虛線)的計算擬合一致的週期性、波狀輪廓。此結果與對半無限低模數支撐物上的均勻的、薄的、高模數層中之起始翹棱幾何形狀之非線性分析達成一致。與此函數關聯之峰-峰振幅及波長分別被確定為2.56及35.0μm。自該***上鄰近兩個尖峰之間水平距離(意即該波長)與該等尖峰之間實際圍線長度(意即藉由AFM量測的表面距離)之間的比例計算之應變(吾人稱為帶應變)產生比該PDMS中預應變更小的值(意即1.3%)。此差別可歸因於PDMS之低剪力模數及與比PDMS基板之長度更短的GaAs帶之長度相關之島效應。在波峰及波谷處之GaAs帶之表面應變(吾人稱為最大GaAs應變)由帶厚度及根據kh/2(其中K為曲率)的該等波之波峰或波谷的曲率半徑求得。在此估算中，因為該PDMS可被視為模數與GaAs之模數相比較低之半無限支撐物(GaAs之楊氏模數：85.5GPa對PDMS之楊氏模數：2MPa)，所以可忽略該PDMS***中應變對GaAs的直接影響。對於圖23E之資料，最大GaAs應變為約0.62%，其比帶應變(意即1.3%)小兩倍以上。此機械優勢在GaAs帶中提供可延伸性，物理性質與波狀Si相似。 Figure 23 shows a thickness of 270 nm (including n -GaAs and Si-GaAs layers) and 100 μm formed by strong bonding between PDMS (about 5 mm thickness) and the strip (all strips discussed in this example have 100 μm) Several micrographs of wavy GaAs strips of width) width. Using a 2-nm Ti and 28-nm SiO 2 layer on GaAs, the fabrication follows a strong bonding procedure. A biaxial pre-strain of about 1.9% (calculated from the thermal response of PDMS) was established in PDMS by thermal expansion (heating to 90 ° C in an oven) shortly before or during bonding. This heating also accelerates the formation of interfacial aerobic bonds. The PDMS was cooled to room temperature (about 27 ° C) after transfer of the GaAs tape, thereby releasing the pre-strain. Frames A, B, and C of Figure 23 show images collected from the same sample by optical microscopy, electron scanning microscopy (SEM), and atomic force microscopy (AFM), respectively. These images show the formation of periodic, wavy structures in the GaAs strips. The waves are quantitatively analyzed by estimating the cut lines from the AFM image (Fig. 23D) (Figs. 23E and 23F). The perimeter line parallel to the longitudinal direction of the strip clearly shows a periodic, wavy profile consistent with the calculated fit of the sine wave (dashed line of Figure 23E). This result is consistent with a non-linear analysis of the initial warp geometry in a uniform, thin, high modulus layer on a semi-infinite low modulus support. The peak-to-peak amplitude and wavelength associated with this function were determined to be 2.56 and 35.0 μm, respectively. The strain calculated from the ratio between the horizontal distance between the two peaks (ie, the wavelength) and the actual line length between the peaks (ie, the surface distance measured by AFM) on the seal (I call it For strained strains, a value smaller than the expected change in the PDMS (ie, 1.3%) is produced. This difference can be attributed to the low shear modulus of the PDMS and the island effect associated with the length of the GaAs strip that is shorter than the length of the PDMS substrate. The surface strain of the GaAs strip at the peaks and troughs (which we call the maximum GaAs strain) is obtained from the strip thickness and the radius of curvature of the peaks or troughs of the waves according to k h /2 (where K is the curvature). In this estimation, because the PDMS can be regarded as a half-infinite support with a lower modulus than the modulus of GaAs (Young's modulus of GaAs: 85.5 GPa vs. Young's modulus of PDMS: 2 MPa), The direct effect of strain on GaAs in the PDMS stamp is ignored. For the data of Figure 23E, the maximum GaAs strain is about 0.62%, which is more than twice the band strain (ie, 1.3%). This mechanical advantage provides extensibility in GaAs tapes with physical properties similar to wavy Si.

如圖23F中所示，該等帶之波峰及波谷區域分別比原始PDMS之表面(意即無帶的區域)之輪廓水平面(綠曲線之右邊部分)更高及更低。該結果暗示作為分別由波峰及波谷中的GaAs帶施加至PDMS之向上及向下力之結果，GaAs下的PDMS採取一波狀輪廓。靠近該等波之波峰的PDMS之準確幾何形狀難以直接估計。吾人懷疑除了向上變形外亦存在由柏松效應引起之橫向頸縮。可藉由將應變施加至PDMS來 延伸及壓縮(所謂的所施加應變分別對延伸表示為正而對壓縮表示為負)該PDMS印製器上的波狀帶。圖23A及23B之插圖展示當施加一相對小延伸應變(意即約1.5%)時變形為其原始扁平幾何形狀之帶的影像。進一步的延伸將更多張力應變轉移至該扁平GaAs帶，從而當此過量應變達到GaAs之失效應變時導致帶之破損。施加至基板之壓縮應變減少該等波狀帶之波長且增加該等波狀帶之振幅。當波峰(及波谷)處之彎曲應變超過該失效應變時就產生壓縮失效。此隨著應變之波長變化與先前矽中的觀察結果一致且與由理想模型推導出的波長不變性之預測不同。 As shown in Fig. 23F, the peaks and trough regions of the bands are higher and lower than the contour level (the right portion of the green curve) of the surface (i.e., the unbanded region) of the original PDMS, respectively. This result implies that the PDMS under GaAs takes a wavy profile as a result of the upward and downward forces applied to the PDMS by the GaAs strips in the peaks and troughs, respectively. The exact geometry of the PDMS near the peaks of the waves is difficult to estimate directly. I suspect that in addition to upward deformation, there is also a lateral necking caused by the cypress effect. Can be applied to PDMS by applying strain The extension and compression (so-called applied strain is expressed as positive for extension and negative for compression) is the wavy band on the PDMS printer. The insets of Figures 23A and 23B show images of a strip deformed to its original flat geometry when a relatively small extension strain (i.e., about 1.5%) is applied. A further extension transfers more tension strain to the flat GaAs strip, causing damage to the strip when this excess strain reaches the strain strain of GaAs. The compressive strain applied to the substrate reduces the wavelength of the undulating bands and increases the amplitude of the undulating bands. Compression failure occurs when the bending strain at the peak (and trough) exceeds the failure strain. This variation with the wavelength of the strain is consistent with the observations in the previous 且 and is different from the prediction of the wavelength invariance derived from the ideal model.

可藉由經由使用一機械台(與熱膨脹相反)而增加施加至PDMS的預應變來改良波狀GaAs帶之可延伸性。舉例而言，將具有SiO2層之GaAs帶轉移至一具有7.8%預應變之PDMS***的表面上可產生GaAs中無任何可觀測破裂之波狀帶(圖24A)。此種狀況下，波峰處的彎曲應變估算為約1.2%，其比GaAs之失效應變(意即約2%)更低。與該低預應變狀況類似，當延伸及壓縮該系統時該等波狀帶類似於一手風琴般運作：波長及振幅變化以適應所施加應變。如圖24A所示，該等波長隨著拉伸應變而增加，直至該等帶變為扁平，且隨著壓縮應變減小，直至該等帶破裂。此等變形為完全可逆的，且不包含PDMS上的GaAs之任何可量測的滑動。與在具有弱結合及低得多的預應變之Si帶中所觀測到之略微不對稱性質相比，波長在壓縮及拉伸中隨著所施加應變而線性地變化(見圖24B中黑色線及符號)。 The extensibility of the corrugated GaAs tape can be improved by increasing the pre-strain applied to the PDMS by using a mechanical stage (as opposed to thermal expansion). For example, transferring a GaAs band with a SiO 2 layer onto a surface having a 7.8% pre-strained PDMS stamp produces a wavy band without any observable rupture in GaAs (Fig. 24A). In this case, the bending strain at the peak is estimated to be about 1.2%, which is lower than the failure strain of GaAs (that is, about 2%). Similar to this low pre-strain condition, the undulating bands operate like an accordion when extending and compressing the system: wavelength and amplitude changes to accommodate the applied strain. As shown in Figure 24A, the wavelengths increase with tensile strain until the bands become flat and as the compressive strain decreases until the bands break. These deformations are fully reversible and do not include any measurable slip of GaAs on the PDMS. Compared to the slightly asymmetrical nature observed in Si bands with weak bonding and much lower pre-strain, the wavelength varies linearly with compression applied in compression and stretching (see black line in Figure 24B). And symbols).

在實際應用中，以一保持該等GaAs帶及裝置之可延伸性之方式將其囊封可為有用的。作為一種可能性之簡單展示，吾人在諸如圖24A中所示者的樣品上澆鑄且固化PDMS預聚合物以將該等帶嵌入PDMS。經嵌入系統展示與未嵌入之系統類似之機械性質，意即延伸該系統時增加波長而壓縮該系統時減少波長(圖24B中紅色線及符 號)。歸因於固化第二PDMS層之收縮產生中等量的額外應變(約1%)。此應變導致該等波狀帶之波長中的略微減少，進而略微擴展了可延伸性之範圍。圖24B展示該差別。總的來說，以約7.8%之預應變產生之系統可延伸或壓縮至高達約10%的應變而不在GaAs中引致任何可觀測之破損。 In practical applications, it may be useful to encapsulate the GaAs tapes and devices in a manner that preserves their extensibility. As a simple demonstration of one possibility, we cast and cure the PDMS prepolymer on a sample such as that shown in Figure 24A to embed the ribbons into the PDMS. The embedded system exhibits mechanical properties similar to those of an unembedded system, meaning that the wavelength is increased when the system is extended and the wavelength is reduced when the system is compressed (the red line and the symbol in Figure 24B) number). A moderate amount of additional strain (about 1%) is due to shrinkage of the cured second PDMS layer. This strain causes a slight decrease in the wavelength of the wavy bands, which in turn slightly extends the range of extensibility. Figure 24B shows this difference. In general, a system produced with a pre-strain of about 7.8% can be stretched or compressed to a strain of up to about 10% without causing any observable breakage in GaAs.

PDMS基板上的波狀GaAs帶可用以製造高效能電子裝置，諸如MESFET，該等電子裝置之電極是經由在轉移至PDMS之前在晶圓上的金屬化及加工而形成。此等金屬層以一空間相依之方式改變該等帶之撓曲剛性。圖25A展示在轉移至一具有約1.9%之預應變之PDMS基板之後與歐姆條(源極及汲極)及肖特基觸點(閘極)整合的GaAs帶。該等歐姆觸點由包括AuGe(70nm)/Ni(10nm)/Au(70nm)之金屬堆疊組成，該等金屬堆疊係經由微影界定之遮罩以及在一具有流動的N2之石英管中在高溫(意即450℃持續1min)下將晶圓之順序退火而形成於初始晶圓上。此等歐姆區段具有500μm之長度。兩個相鄰歐姆觸點之間之距離為500μm(意即通道長度)。具有240μm之長度(意即閘極長度)之肖特基觸點係藉由根據光微影設計之遮罩經由電子束蒸鍍直接沈積75-nm Cr層及75-nm Au層來產生。該等電極具有等於該等GaAs帶之寬度，意即100μm；其相對大尺寸便利了探測。可顯著減小電極及半導體通道之尺寸以達成增強之裝置效能。如圖25A中所示，此等可延伸GaAs MESFET僅在無電極之區域中展示短程週期波。在較厚區域中不存在波是由主要歸因於與該等金屬相關聯之額外厚度的該等區域的增強的撓曲剛性所引起的。可藉由使用大於約3%之預應變而在更厚區域中起始週期波。然而，在此等狀況下，歸因於關鍵瑕疵及/或在該等金屬電極之邊緣附近的高應變峰值，該等帶傾向於在該等金屬電極的邊緣處破裂。此失效模式限制了可延伸性。 The corrugated GaAs ribbon on the PDMS substrate can be used to fabricate high performance electronic devices, such as MESFETs, whose electrodes are formed via metallization and processing on the wafer prior to transfer to PDMS. These metal layers change the flexural rigidity of the strips in a spatially dependent manner. Figure 25A shows a GaAs ribbon integrated with ohmic strips (source and drain) and Schottky contacts (gate) after transfer to a PDMS substrate having a pre-strain of about 1.9%. The ohmic contacts are composed of a metal stack comprising AuGe (70 nm) / Ni (10 nm) / Au (70 nm), which are via a lithographically defined mask and in a quartz tube with flowing N 2 The wafer is sequentially annealed at a high temperature (ie, 450 ° C for 1 min) to form an initial wafer. These ohmic sections have a length of 500 μm. The distance between two adjacent ohmic contacts is 500 μm (meaning channel length). A Schottky contact having a length of 240 μm (that is, a gate length) is produced by directly depositing a 75-nm Cr layer and a 75-nm Au layer by electron beam evaporation according to a mask designed by photolithography. The electrodes have a width equal to the width of the GaAs strips, meaning 100 μm; their relatively large size facilitates detection. The size of the electrodes and semiconductor channels can be significantly reduced to achieve enhanced device performance. As shown in Figure 25A, these extendable GaAs MESFETs exhibit short-range periodic waves only in areas without electrodes. The absence of waves in thicker regions is caused by the enhanced flexural rigidity of the regions that are primarily attributed to the extra thickness associated with the metals. The periodic wave can be initiated in a thicker region by using a pre-strain greater than about 3%. However, under such conditions, the bands tend to rupture at the edges of the metal electrodes due to critical enthalpy and/or high strain peaks near the edges of the metal electrodes. This failure mode limits extensibility.

為克服此侷限性，吾人藉由消除矽氧烷鍵結來減小MESFET與 PDMS之間之交互作用的強度。對於此等實例，歸因於該等帶自PDMS表面之實體脫離，>3%之預應變就產生具有相對大寬度及振幅之大的、無週期翹棱。圖25B呈現此類型系統(如以約7%之預應變製備)，其中該等大的翹棱形成於該等裝置的較薄之區域中。如該等垂直線所指示，該脫離似乎略微擴展至具有歐姆條之較厚區域。沿帶之對比度變化係歸因於反射及與通過該曲線GaAs區段之光相關的折射。該SEM影像(圖25C)清楚地展示弧形翹棱及扁平、未受力PDMS之形成。此等翹棱顯示尾部延伸至具有歐姆觸點之側邊的非對稱輪廓(如由紅色曲線指示)。此不對稱可歸因於個別電晶體之歐姆條及肖特基觸點之不等長度(500μm對240μm)。藉由約6%與約7%之間之所施加延伸應變，此類翹棱MESFET可延伸至其原始扁平狀態(圖25D)。然而，由於弱結合，壓縮圖25B中所示之系統導致帶自PDMS表面之連續脫離而形成更大的翹棱。根據先前描述之程序將此等裝置嵌入PDMS中消除了此類非受控之性質。圖25B展示此系統，其中液態PDMS前驅物填充該等翹棱之下之間隙。完全包圍之PDMS限定了該等帶且防止其滑動及脫離。嵌入裝置能可逆地延伸及壓縮至高達約6%之應變而不損壞該等帶。值得注意的是，當將嵌入系統壓縮-5.83%(圖25E之頂部框)時，在具有金屬電極之區域中形成週期性的小的波狀以及在翹棱區域中形成新的波紋。此等新的小波狀之形成(與該等大翹棱組合)增強了可壓縮性。延伸該系統迫使該等翹棱區域以一使得此等翹棱可變平之方式來壓縮及延伸該PDMS，進而伸長了該等帶的伸出長度(圖25E之底部框)。此等結果表明具有大翹棱(幾何形狀與波狀截然不同)之嵌入裝置代表了一可與波狀方法組合使用或獨立於該波狀方法使用的用以達成可延伸性及可壓縮性之有希望的方法。 To overcome this limitation, we have reduced MESFETs by eliminating the siloxane coupling. The strength of the interaction between PDMS. For these examples, due to the detachment of the strips from the PDMS surface, a pre-strain of > 3% produces a large, non-periodic ridge with a relatively large width and amplitude. Figure 25B presents a system of this type (e.g., prepared with a pre-strain of about 7%) wherein the large ridges are formed in the thinner regions of the devices. As indicated by the vertical lines, the detachment appears to extend slightly to a thicker region with ohmic strips. The contrast variation along the band is due to reflection and refraction associated with light passing through the GaAs segment of the curve. The SEM image (Fig. 25C) clearly shows the formation of curved ridges and flat, unstressed PDMS. These ribs indicate that the tail extends to an asymmetrical profile with the sides of the ohmic contacts (as indicated by the red curve). This asymmetry can be attributed to the unequal lengths of the ohmic strips and Schottky contacts of the individual transistors (500 μm versus 240 μm). Such a warped MESFET can be extended to its original flat state by an applied extended strain of between about 6% and about 7% (Fig. 25D). However, due to the weak bond, compressing the system shown in Figure 25B results in a continuous detachment of the tape from the PDMS surface to create a larger ridge. Embedding such devices into PDMS according to the previously described procedures eliminates such uncontrolled nature. Figure 25B shows the system in which a liquid PDMS precursor fills the gap below the ribs. The fully enclosed PDMS defines the bands and prevents them from slipping and escaping. The embedding device can reversibly extend and compress to strains up to about 6% without damaging the bands. It is worth noting that when the embedded system is compressed by -5.83% (the top frame of Fig. 25E), a periodic small wave shape is formed in the region having the metal electrode and a new corrugation is formed in the warp region. The formation of these new wavelets (in combination with these large ridges) enhances compressibility. Extending the system forces the slanted regions to compress and extend the PDMS in such a manner that the ridges are flattened, thereby elongating the extended length of the strips (bottom frame of Figure 25E). These results indicate that an embedded device with large ridges (distinct geometry and wavy) represents a combination of wavy methods or independent of the wavy method for achieving extensibility and compressibility. Promising approach.

翹棱裝置之效能可藉由直接探測自源極至汲極之電流來評估。 圖26A展示在一晶圓上製造，使用一扁平PDMS***揀取且轉移印刷至一具有4.7%之預應變之PDMS基板上的GaAs帶裝置。在此組態中，金屬電極曝露至空氣以用於電探測。在將預延伸之PDMS鬆弛至3.4%之應變之後，週期性的小波狀形成於MESFET之薄區域中(圖26A：自頂部第二個框)。當將該預延伸PDMS***完全鬆弛時，在純GaAs之每一區段中的小波狀合併為個別的大翹棱(圖26A：自頂部第三個框)。藉由施加4.7%的延伸應變，該等翹棱裝置可延伸至其扁平狀態(圖26A：底部框)。具有0.0%(圖26A：自頂部第三個框)及4.7%(圖26A：底部框)之所施加應變之相同裝置的IV曲線分別以紅色及黑色繪製於圖26B中。該等結果指示PDMS基板上翹棱MESFET之自源極至汲極之電流可以施加至閘極之電壓來良好地調節，且所施加延伸應變對裝置效能僅產生微小影響。 The performance of the warp device can be evaluated by directly detecting the current from the source to the drain. Figure 26A shows a GaAs tape device fabricated on a wafer, picked up using a flat PDMS stamp and transferred to a PDMS substrate with 4.7% pre-strain. In this configuration, the metal electrode is exposed to air for electrical detection. After relaxing the pre-stretched PDMS to a strain of 3.4%, a periodic wavelet is formed in the thin region of the MESFET (Fig. 26A: second box from the top). When the pre-stretched PDMS stamp is completely relaxed, the wavelets in each section of pure GaAs merge into individual large ridges (Fig. 26A: third box from the top). By applying an elongation strain of 4.7%, the warping devices can be extended to their flattened state (Fig. 26A: bottom frame). The IV curves of the same device with the applied strain of 0.0% (Fig. 26A: third frame from the top) and 4.7% (Fig. 26A: bottom frame) are plotted in red and black, respectively, in Fig. 26B. These results indicate that the current from the source to the drain of the warped MESFET on the PDMS substrate can be well regulated by the voltage applied to the gate, and the applied extension strain has only a minor effect on device performance.

概括而言，此實例揭示了一用以在PDMS彈性體基板上形成"翹棱"及"波狀"GaAs帶及形成嵌入PDMS彈性體基板中之"翹棱"及"波狀"GaAs帶之方法。此等帶之幾何組態視製造中所使用之預應變位準、PDMS與帶之間交互作用強度、及所使用材料的厚度及類型而定。歸因於翹棱及波狀帶之幾何形狀的以一能適應所施加應變而不將彼等應變轉移至材料自身的方式來進行調節之能力，GaAs多層堆疊及完全形成之MESFET裝置之翹棱及波狀帶展示了較高水準的可壓縮性/可延伸性。在一類似GaAs之本質脆弱之材料中成功實現高水準的機械可延伸性(且作為結果，諸如極端可彎曲性的其他具有吸引力之機械特性)提供了可適用於寬廣範圍的其他材料類型的類似策略。 In summary, this example discloses a "warping" and "wavy" GaAs tape for forming "warping" and "wavy" GaAs tapes on a PDMS elastomer substrate and forming a PDMS elastomer substrate. method. The geometric configuration of these bands depends on the pre-strain level used in the manufacturing, the strength of the interaction between the PDMS and the tape, and the thickness and type of material used. The ability to adjust the geometry of the ribbed and wavy strips in a manner that accommodates the applied strain without transferring the strain to the material itself, the GaAs multilayer stack and the fully formed MESFET device And the wavy band exhibits a higher level of compressibility/extensibility. Successfully achieving high levels of mechanical extensibility in a material that is inherently weak in GaAs (and, as a result, other attractive mechanical properties such as extreme bendability) provides a wide range of other material types that can be applied to a wide range of materials. A similar strategy.

熱誘發之預應變係歸因於PDMS***之熱膨脹，其具有α L =3.1×10-4μm/μm/℃的本體線性熱膨脹係數。另一方面，GaAs之熱膨脹係數僅為5.73×10-6μm/μm/℃。因此，對於在90℃製備且冷卻至27℃之樣品，PDMS上的預應變(相對GaAs帶)根據△α L ×△T=(3.1×10-4- 5.73×10-6)×(90-27)=1.9%來測定。 The thermally induced pre-strain system is attributed to the thermal expansion of the PDMS stamp, which has a bulk linear thermal expansion coefficient of α L = 3.1 × 10 -4 μm / μm / ° C. On the other hand, the thermal expansion coefficient of GaAs is only 5.73 × 10 -6 μm / μm / °C. Therefore, for samples prepared at 90 ° C and cooled to 27 ° C, the pre-strain on the PDMS (relative GaAs band) is based on Δα L × Δ T = (3.1 × 10 -4 - 5.73 × 10 -6 ) × (90- 27) = 1.9% to determine.

方法：自IQE公司(伯利恆，PA)購買具有用戶設計之磊晶層之GaAs晶圓。微影製程使用AZ光阻劑(即AZ 5214及AZ nLOF 2020分別用於正及負成像)。在以冰水浴冷卻之蝕刻劑(4mL H3PO4(85重量%)、52mL H2O2(30重量%)，及48mL去離子水)中各向異性地蝕刻具有光阻遮罩圖案之GaAs晶圓。用乙醇的稀HF溶液(體積比1：2)(Fisher® Chemicals)將AlAs層溶解。將在母體晶圓上具有釋放的帶之樣品在一通風櫥中乾燥。將經乾燥之樣品置於電子束蒸鍍器(Temescal FC-1800)之腔室中，且鍍覆2-nm Ti及28-nm SiO2之順序的層。在AlAs層之移除之前藉由電子束蒸鍍而沈積用於MESFET裝置之金屬。藉由將低模數PDMS之混合物(A：B=1：10，Sylgard 184，Dow Corning)倒至以(三癸氟基-1,1,2,2-四氫辛基)-1-三氯矽烷之單層預改質的一片矽晶圓上，接著在65℃下烘焙4小時來製備具有約5mm厚度之PDMS印製器。為了產生強結合，將該等***曝露至UV光5分鐘。在該轉移過程中，經由熱膨脹(在烘箱中)及/或機械力來延伸該等***。然後將具有釋放的帶之晶圓層壓至經延伸之PDMS***的表面上，且使其在高溫(視所需預應變而定)保持接觸5分鐘。將母體晶圓自該等***剝離且將所有帶轉移至***。經由冷卻至室溫及/或移除該等機械力而將施加至***之預應變釋放，從而導致沿該等帶之波狀輪廓的形成。在該等機械評估中，使用一特殊設計之台來延伸以及壓縮具有"波狀"及"翹棱"GaAs帶之PDMS***。 Method: A GaAs wafer with a user-designed epitaxial layer was purchased from IQE Corporation (Bethleton, PA). The lithography process uses AZ photoresist (ie AZ 5214 and AZ nLOF 2020 for positive and negative imaging, respectively). The photoresist pattern was anisotropically etched in an etchant (4 mL H 3 PO 4 (85% by weight), 52 mL H 2 O 2 (30% by weight), and 48 mL of deionized water) cooled in an ice water bath. GaAs wafers. The AlAs layer was dissolved in a dilute HF solution of ethanol (volume ratio 1:2) (Fisher® Chemicals). A sample of the tape having the release on the parent wafer was dried in a fume hood. The dried sample was placed in a chamber of an electron beam evaporator (Temescal FC-1800) and a layer of 2-nm Ti and 28-nm SiO 2 was plated. The metal for the MESFET device is deposited by electron beam evaporation prior to removal of the AlAs layer. By pouring a mixture of low modulus PDMS (A: B = 1:10, Sylgard 184, Dow Corning) to (tris-fluorenyl-1,1,2,2-tetrahydrooctyl)-1-three A single layer pre-modified ruthenium chloride wafer was then baked at 65 ° C for 4 hours to prepare a PDMS printer having a thickness of about 5 mm. To create a strong bond, the seals were exposed to UV light for 5 minutes. During the transfer, the stamps are extended via thermal expansion (in the oven) and/or mechanical force. The wafer with the released tape was then laminated to the surface of the extended PDMS stamp and allowed to remain in contact for 5 minutes at high temperatures (depending on the desired pre-strain). The parent wafer is stripped from the stamps and all strips are transferred to the stamp. The pre-strain applied to the stamp is released by cooling to room temperature and/or removing such mechanical forces, resulting in the formation of undulating contours along the strip. In these mechanical evaluations, a specially designed stage is used to extend and compress the PDMS stamp with "wavy" and "warped" GaAs strips.

實例3：二維可延伸半導體Example 3: Two-dimensional extensible semiconductor

本發明提供能在多個方向(包括彼此正交定向之方向)上延伸、壓縮及/或撓曲的可延伸半導體及可延伸電子裝置。本發明之此態樣之可延伸半導體及可延伸電子裝置當在多個方向上延伸及/或壓縮時展示良好的機械及電子性質及/或裝置效能。 The present invention provides extendable semiconductors and extendable electronic devices that are capable of extending, compressing, and/or flexing in a plurality of directions, including directions oriented orthogonally to one another. The extendable semiconductor and extendable electronic device of this aspect of the invention exhibit good mechanical and electronic properties and/or device performance when extended and/or compressed in multiple directions.

圖27A-C提供本發明之展示二維可延伸性之可延伸矽半導體在不同放大程度的影像。圖27A-B中展示之可延伸半導體係藉由透過熱膨脹而預應變一彈性基板來製備。 27A-C provide images of the present invention showing two-dimensional extensibility of extensible germanium semiconductors at different levels of magnification. The extensible semiconductor shown in Figures 27A-B is prepared by pre-straining an elastic substrate through thermal expansion.

圖28A-C提供本發明之展示二維可延伸性之可延伸半導體的三個不同結構構形之影像。如圖所示，圖28A中的半導體結構展示一邊緣線波狀構形，圖28B中的半導體結構展示一人字形波狀構形，且圖28C中的半導體結構展示一隨機波狀構形。 28A-C provide images of three different structural configurations of the present invention showing a two-dimensional extensible extensible semiconductor. As shown, the semiconductor structure of Figure 28A exhibits an edge line wavy configuration, the semiconductor structure of Figure 28B exhibits a herringbone wavy configuration, and the semiconductor structure of Figure 28C exhibits a random wavy configuration.

圖29A-D提供透過熱膨脹而預應變一彈性基板來製造之本發明之可延伸半導體的影像。 29A-D provide an image of an extensible semiconductor of the present invention fabricated by pre-straining an elastic substrate by thermal expansion.

圖30展示透過熱膨脹而預應變一彈性基板來製備之展示二維可延伸性之可延伸半導體的光學影像。圖30展示對應於多種延伸及壓縮條件之影像。 Figure 30 shows an optical image of an extensible semiconductor exhibiting two-dimensional extensibility prepared by pre-straining an elastic substrate by thermal expansion. Figure 30 shows an image corresponding to a variety of extension and compression conditions.

圖31A展示透過熱膨脹而預應變一彈性基板來製造之展示二維可延伸性之可延伸半導體的一光學影像。圖31B及31C提供關於圖31A中展示之可延伸半導體之機械性質的實驗結果。 31A shows an optical image of an extensible semiconductor exhibiting two-dimensional extensibility fabricated by pre-straining an elastic substrate by thermal expansion. Figures 31B and 31C provide experimental results regarding the mechanical properties of the extensible semiconductor shown in Figure 31A.

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關於以引用方式的併入及變化之聲明Statement on the incorporation and change by reference

以下參考係關於可在本發明之方法中用以經由接觸印刷及/或溶液印刷技術來轉移、裝配及互連可印刷半導體元件之自裝配技術，且其全文以引用的方式併入本文：(1) "Guided molecular self-assembly: a review of recent efforts", Jiyun C Huie Smart Mater. Struct. (2003) 12, 264-271; (2) "Large-Scale Hierarchical Organization of Nanowire Arrays for Integrated Nanosystems", Whang, D.; Jin, S.; Wu, Y.; Lieber, C. M. Nano Lett. (2003) 3(9), 1255-1259; (3) "Directed Assembly of One-Dimensional Nanostructures into Functional Networks", Yu Huang, Xiangfeng Duan, Qingqiao Wei, and Charles M. Lieber, Science (2001) 291, 630-633；及(4)"Electric-field assisted assembly and alignment of metallic nanowires", Peter A. Smith等人，Appl. Phys. Lett. (2000) 77(9), 1399-1401。 The following references relate to self-assembly techniques that can be used in the methods of the present invention to transfer, assemble, and interconnect printable semiconductor components via contact printing and/or solution printing techniques, and are incorporated herein by reference in their entirety: 1) "Guided molecular self-assembly: a review of recent efforts", Jiyun C Huie Smart Mater. Struct. (2003) 12, 264-271; (2) "Large-Scale Hierarchical Organization of Nanowire Arrays for Integrated Nanosystems", Whang, D.; Jin, S.; Wu, Y.; Lieber, CM Nano Lett. (2003) 3(9), 1255-1259; (3) "Directed Assembly of One-Dimensional Nanostructures into Functional Networks", Yu Huang, Xiangfeng Duan, Qingqiao Wei, and Charles M. Lieber, Science (2001) 291, 630-633; and (4) "Electric-field assisted assembly and alignment of metallic nanowires", Peter A. Smith et al., Appl. Phys. Lett. (2000) 77(9), 1399-1401.

貫穿本申請案之所有參考，例如包括已頒予或准予之專利或其等效物之專利文獻；專利申請案公開案；未公開專利申請案；及非專利文獻或其他資訊來源材料，以全文引用的方式併入本文，該引用的程度就如同以引用的方式個別併入該等文獻直至每一文獻至少部分與本申請案之揭示內容不一致之範圍(例如，部分不一致的文獻的除了該部分不一致部分外皆被以引用之方式併入本文)。 All references throughout this application, such as patent documents including patents granted or granted, or equivalents thereof; patent application publications; unpublished patent applications; and non-patent literature or other information source materials, full text The manner in which they are incorporated is incorporated by reference to the extent of the extent of the extent of the disclosure of the disclosure of the disclosure of each of the of Inconsistent parts are incorporated herein by reference.

本文之任何附錄以引用之方式併入本文作為本說明書及/或圖式之部分。 Any of the appendices herein are hereby incorporated by reference herein in its entirety in its entirety in its entirety herein.

在本文中使用術語"包含(comprise)"、"包含了(comprises)"、"所包含(comprised)"、"正包含(comprising)"處，應將這些表達理解為規定所說明特徵、整數、步驟，或組件之存在，但不排除一或多個其他特徵、整數、步驟、組件，或其群組之存在或添加。在術語"正包含 (comprising)"或"包含(了)(comprise(s))"或"所包含(comprised)"視情況可由語法上類似之術語，例如"由...組成"或"實質上由...組成"來替代時，亦希望涵蓋本發明之單獨實施例，從而描述不一定同延的另外的實施例。 Where the terms "comprise", "comprises", "comprised", "comprising" are used herein, the expression should be understood to mean the stated features, integers, The presence of steps, or components, does not exclude the presence or addition of one or more other features, integers, steps, components, or groups thereof. In the term "includes (comprising) "or" (comprising) (comprise(s))" or "comprised" may be grammatically similar, such as "consisting of" or "substantially by..." In the alternative, it is also intended to cover the individual embodiments of the invention, so as to describe additional embodiments that are not necessarily the same.

已參考各種特定及較佳實施例及技術描述本發明。然而，應瞭解到可進行各種變化及修改而同時保持在本發明之精神及範疇內。對於一般熟習此項技術者顯而易見的是，不同於本文中特定描述者之組合物、方法、裝置、裝置元件、材料、程序及技術可應用於如本文廣泛揭示之本發明之實踐而無須訴諸於不適當的實驗。本文所描述之組合物、方法、裝置、裝置元件、材料、程序及技術之所有此項技術中已知之功能等效物皆希望包含於本發明中。無論何時揭示一範圍，皆希望包含所有子範圍及個別值，就像其被獨立提出一樣。本發明並非由所揭示之實施例(包括在圖式中展示或在本說明書中例示者)來限制，該等實施例以實例或說明之方式給出(不具限制性)。本發明之範疇應僅由申請專利範圍來限制。 The invention has been described with reference to various specific and preferred embodiments and techniques. However, it will be appreciated that various changes and modifications can be made while remaining within the spirit and scope of the invention. It will be apparent to those skilled in the art that compositions, methods, devices, device components, materials, procedures, and techniques other than those specifically described herein may be applied to the practice of the invention as broadly disclosed herein without resorting to In inappropriate experimentation. All of the functional equivalents of the compositions, methods, devices, device components, materials, procedures, and techniques described herein are intended to be included in the present invention. Whenever a range is revealed, it is desirable to include all sub-ranges and individual values as if they were presented independently. The present invention is not limited by the disclosed embodiments (including those shown in the drawings or exemplified in the specification), which are given by way of illustration or description. The scope of the invention should be limited only by the scope of the patent application.

Claims (1)

一種可延伸半導體元件，其包含：一具有一支撐表面之可撓性基板；一具有一內表面之半導體結構，其中該內表面之多個離散點係結合至該可撓性基板的該支撐表面，且結合之該等離散點藉由沒有直接黏合至該可撓性基板之該半導體結構的一翹曲(buckled)區域而彼此分開，其中該半導體結構的該翹曲區域沒有與該可撓性基板的該支撐表面實體接觸；及一嵌入該半導體結構的該翹曲區域之囊封層。 An extendable semiconductor component comprising: a flexible substrate having a support surface; a semiconductor structure having an inner surface, wherein a plurality of discrete points of the inner surface are bonded to the support surface of the flexible substrate And the discrete points combined are separated from each other by a buckled region of the semiconductor structure that is not directly bonded to the flexible substrate, wherein the warped region of the semiconductor structure is not flexible The support surface of the substrate is in physical contact; and an encapsulation layer embedded in the warped region of the semiconductor structure.
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