TW201708798A - Packaging method, cover structure of temperature sensing element and method for fabricating the same - Google Patents
Packaging method, cover structure of temperature sensing element and method for fabricating the same Download PDFInfo
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Abstract
Description
下列敘述是有關於一種封裝方法，特別是有關於溫測元件之封裝方法以及整體形成(monolithic)的蓋體結構。The following description relates to a packaging method, particularly to a packaging method for a temperature sensing element and a monolithic cover structure.
目前，紅外線(IR)視頻攝影機已經被應用於記錄及貯存連續之熱影像，在紅外線(IR)視頻攝影機中包含一溫測晶片，其包含溫度感測元件陣列(array)，每一溫度感測元件陣列可根據其接收到的紅外線輻射能量而對應地改變其電阻值，因此每一溫度感測元件陣列的電阻值改變可對應熱能量的強弱，每一溫度感測元件陣列便可產生一熱影像。At present, infrared (IR) video cameras have been used to record and store continuous thermal images. In an infrared (IR) video camera, a temperature measurement wafer is included, which includes an array of temperature sensing elements, each temperature sensing. The array of components can correspondingly change the resistance value according to the infrared radiant energy received by the component, so that the resistance value change of each temperature sensing component array can correspond to the thermal energy intensity, and each temperature sensing component array can generate a heat. image.
溫測晶片係設置在一基座上，然後以蓋體與基座封裝，而且為了避免封裝空間中產生熱對流而影響溫度感測元件陣列所感測的熱能量，封裝空間係維持在真空狀態，而溫度感測元件陣列的靈敏度係與封裝空間之真空程度有關。The temperature measuring chip is disposed on a pedestal and then encapsulated by the cover and the pedestal, and the package space is maintained in a vacuum state in order to avoid thermal convection in the package space and affect the thermal energy sensed by the temperature sensing element array. The sensitivity of the array of temperature sensing elements is related to the degree of vacuum in the package space.
對於抽真空的過程，封裝腔室體積越小越有利於抽真空的速度。但是在習知技藝中，溫測晶片需要放置在基座中，所以基座必須有一定的空間，所以封裝腔室體積不易縮小。For the vacuuming process, the smaller the volume of the packaging chamber, the better the speed of vacuuming. However, in the prior art, the temperature measurement wafer needs to be placed in the pedestal, so the pedestal must have a certain space, so the package chamber volume is not easily reduced.
有鑑於上述問題，本發明之目的係提供一種溫測元件之封裝方法，以有效提高溫測元件的封裝速率。In view of the above problems, an object of the present invention is to provide a method of packaging a temperature measuring component to effectively increase the packaging rate of the temperature sensing component.
有鑑於上述問題，本發明之另一目的係提供一種溫測元件之封裝方法，以有效降低封裝體積提高溫測元件的真空度。In view of the above problems, another object of the present invention is to provide a method for packaging a temperature measuring element to effectively reduce the package volume and increase the degree of vacuum of the temperature measuring element.
基於上述目的，本發明係提供一種溫測元件之封裝方法，包含下列步驟。首先，提供蓋板，其第一表面上具有複數個封裝結構圖案，每一封裝結構圖案可包含複數個島狀體以及環狀平台(bonding ring)。在蓋板中形成複數個蝕刻保護區域。在每一封裝結構圖案上形成熱吸收層結構以及熱電阻層。蝕刻熱吸收層結構以產生複數個開槽，其係暴露熱電阻層；在熱吸收層結構以及島狀體上形成一第一金屬層，第一金屬層係透過開槽電性接觸熱電阻層。在環狀平台上形成一第二金屬層。在封裝結構圖案上形成複數個穿槽以曝露蓋板。透過穿槽對蓋板進行蝕刻，以在熱吸收層結構下方形成槽穴，並由蝕刻保護區域係形成支撐柱。提供基板，並在基板上形成晶片、複數個電性接觸點，以及至少一焊接區。最後，在真空中將蓋板之第一表面朝向晶片，覆蓋基板，將複數個島狀體上的複數個第一金屬層與複數個電性接觸點相焊接，以及將環狀平台上的第二金屬層與至少一焊接區相焊接。Based on the above object, the present invention provides a method of packaging a temperature measuring element, comprising the following steps. First, a cover plate is provided having a plurality of package structure patterns on a first surface thereof, and each package structure pattern may include a plurality of island bodies and a bonding ring. A plurality of etch protection regions are formed in the cover. A heat absorbing layer structure and a thermal resistance layer are formed on each package structure pattern. Etching the heat absorbing layer structure to generate a plurality of trenches exposing the thermal resistance layer; forming a first metal layer on the heat absorbing layer structure and the island body, the first metal layer passing through the slotted electrical contact thermal resistance layer . A second metal layer is formed on the annular platform. A plurality of slots are formed in the package structure pattern to expose the cover. The cover is etched through the slot to form a recess below the heat absorbing layer structure and the support pillar is formed by etching the protective region. A substrate is provided and a wafer, a plurality of electrical contacts, and at least one land are formed on the substrate. Finally, the first surface of the cover plate faces the wafer in a vacuum, covers the substrate, and the plurality of first metal layers on the plurality of islands are welded to the plurality of electrical contact points, and the first on the annular platform The two metal layers are soldered to at least one of the pads.
較佳地，熱吸收層結構包含熱吸收層以及一保護層，在熱電阻層係形成於熱吸收層上，而保護層係形成於熱電阻層上，而封裝方法更包含蝕刻保護層以產生複數個開槽。Preferably, the heat absorbing layer structure comprises a heat absorbing layer and a protective layer, wherein the thermal resistance layer is formed on the heat absorbing layer, and the protective layer is formed on the thermal resistance layer, and the packaging method further comprises etching the protective layer to generate Multiple slots.
較佳地，熱吸收層結構包含一第一熱吸收層以及一第二熱吸收層，熱電阻層係形成於第一熱吸收層以及第二熱吸收層之間，而封裝方法更包含蝕刻第二熱吸收層以產生複數個開槽。Preferably, the heat absorbing layer structure comprises a first heat absorbing layer and a second heat absorbing layer, the thermal resistance layer is formed between the first heat absorbing layer and the second heat absorbing layer, and the packaging method further comprises etching The two heat absorbing layers are used to create a plurality of slots.
基於上述目的，本發明再提供一種溫測元件之封裝方法，包含下列步驟。提供蓋板，蓋板具有凹槽，凹槽內有複數個支撐柱結構。在凹槽中填入犧牲材料並進行蝕刻，以形成複數個封裝結構圖案，每一封裝結構圖案可包含複數個島狀體以及環狀平台。在封裝結構圖案上形成熱吸收層結構以及熱電阻層。蝕刻熱吸收層結構以產生複數個開槽以暴露熱電阻層。在熱吸收層結構以及島狀體上形成一第一金屬層，金屬層係透過開槽電性接觸熱電阻層。在環狀平台上形成一第二金屬層。在封裝結構圖案上形成複數個穿槽以曝露犧牲材料。透過複數個穿槽對犧牲材料進行蝕刻，以在熱吸收層結構下方形成槽穴以及保留複數個支撐柱結構。提供基板，並在基板上設置晶片、複數個電性接觸點，以及至少一焊接區。最後，在真空中將蓋板上具有複數個封裝結構圖案之一表面朝向晶片，覆蓋基板，且將複數個島狀體上的第一金屬層與電性接觸點相焊接，以及將環狀平台第二金屬層與至少一焊接區相焊接。Based on the above object, the present invention further provides a method for packaging a temperature measuring element, comprising the following steps. A cover plate is provided, the cover plate has a groove, and the groove has a plurality of support column structures. The sacrificial material is filled in the recess and etched to form a plurality of package structure patterns, and each package structure pattern may include a plurality of islands and an annular platform. A heat absorbing layer structure and a thermal resistance layer are formed on the package structure pattern. The heat absorbing layer structure is etched to create a plurality of trenches to expose the thermal resistance layer. A first metal layer is formed on the heat absorbing layer structure and the island body, and the metal layer is electrically contacted with the thermal resistance layer through the slot. A second metal layer is formed on the annular platform. A plurality of slots are formed in the package structure pattern to expose the sacrificial material. The sacrificial material is etched through a plurality of slots to form a cavity below the heat absorbing layer structure and to retain a plurality of support pillar structures. A substrate is provided, and a wafer, a plurality of electrical contacts, and at least one land are disposed on the substrate. Finally, a surface of the plurality of package structure patterns on the cover plate faces the wafer in a vacuum, covers the substrate, and solders the first metal layer on the plurality of islands to the electrical contact points, and the annular platform The second metal layer is welded to the at least one weld zone.
較佳地，熱吸收層結構包含熱吸收層以及一保護層，在熱電阻層係形成於熱吸收層上，而保護層係形成於熱電阻層上，而封裝方法更包含蝕刻保護層以產生複數個開槽。Preferably, the heat absorbing layer structure comprises a heat absorbing layer and a protective layer, wherein the thermal resistance layer is formed on the heat absorbing layer, and the protective layer is formed on the thermal resistance layer, and the packaging method further comprises etching the protective layer to generate Multiple slots.
較佳地，熱吸收層結構包含一第一熱吸收層以及一第二熱吸收層，熱電阻層係形成於第一熱吸收層以及第二熱吸收層之間，而封裝方法更包含蝕刻第二熱吸收層以產生複數個開槽。Preferably, the heat absorbing layer structure comprises a first heat absorbing layer and a second heat absorbing layer, the thermal resistance layer is formed between the first heat absorbing layer and the second heat absorbing layer, and the packaging method further comprises etching The two heat absorbing layers are used to create a plurality of slots.
基於上述目的，本發明再提供一種用於晶片封裝之蓋體結構的製造方法，其包含下列步驟提供蓋板，其第一表面上具有複數個封裝結構圖案，每一封裝結構圖案可包含複數個島狀體以及環狀平台。在蓋板中形成複數個蝕刻保護區域。在封裝結構圖案上形成一輔助層結構以及一反應作用層。蝕刻輔助層結構以產生複數個開槽，以暴露反應作用層。在輔助層結構以及島狀體上形成一第一金屬層，第一金屬層係透過複數個開槽電性接觸反應作用層。在環狀平台上形成一第二金屬層。在封裝結構圖案上形成複數個穿槽，以曝露蓋板。最後，透過複數個穿槽，對蓋板進行蝕刻，以在輔助層結構下方形成槽穴，而複數個蝕刻保護區域係形成複數個支撐柱，藉此以形成蓋體結構。Based on the above object, the present invention further provides a method for fabricating a cover structure for a chip package, comprising the steps of providing a cover plate having a plurality of package structure patterns on a first surface thereof, each package structure pattern may include a plurality of Island and ring platform. A plurality of etch protection regions are formed in the cover. An auxiliary layer structure and a reaction layer are formed on the package structure pattern. The auxiliary layer structure is etched to create a plurality of trenches to expose the reactive layer. A first metal layer is formed on the auxiliary layer structure and the island body, and the first metal layer is passed through a plurality of slotted electrical contact reaction layers. A second metal layer is formed on the annular platform. A plurality of slots are formed in the package structure pattern to expose the cover. Finally, the cover is etched through a plurality of slots to form a recess below the auxiliary layer structure, and the plurality of etch protection regions form a plurality of support pillars to form a cover structure.
基於上述目的，本發明再提供一種用於晶片封裝之蓋體結構的製造方法，其包含下列步驟提供蓋板，蓋板具有凹槽，凹槽內有複數個支撐柱結構。在凹槽中填入犧牲材料並進行蝕刻，以形成複數個封裝結構圖案，每一封裝結構圖案可包含複數個島狀體以及環狀平台。在封裝結構圖案上形成一輔助層結構以及一反應作用層。蝕刻輔助層結構以產生複數個開槽，以暴露反應作用層。在輔助層結構以及島狀體上形成一第一金屬層，第一金屬層係透過複數個開槽電性接觸反應作用層。在環狀平台上形成一第二金屬層。在封裝結構圖案上形成複數個穿槽，以曝露犧牲材料。最後，透過複數個穿槽對犧牲材料進行蝕刻，以在輔助層結構下方形成槽穴以及保留複數個支撐柱結構，藉此以形成蓋體結構。In view of the above, the present invention further provides a method of fabricating a cover structure for a wafer package, comprising the steps of providing a cover having a recess having a plurality of support post structures therein. The sacrificial material is filled in the recess and etched to form a plurality of package structure patterns, and each package structure pattern may include a plurality of islands and an annular platform. An auxiliary layer structure and a reaction layer are formed on the package structure pattern. The auxiliary layer structure is etched to create a plurality of trenches to expose the reactive layer. A first metal layer is formed on the auxiliary layer structure and the island body, and the first metal layer is passed through a plurality of slotted electrical contact reaction layers. A second metal layer is formed on the annular platform. A plurality of slots are formed in the package structure pattern to expose the sacrificial material. Finally, the sacrificial material is etched through a plurality of slots to form a cavity below the auxiliary layer structure and to retain a plurality of support pillar structures, thereby forming a lid structure.
較佳地，輔助層結構包含熱吸收層以及一保護層，反應作用層可為熱電阻層，在熱電阻層係形成於熱吸收層以及保護層之間，而複數個開槽係穿透保護層。Preferably, the auxiliary layer structure comprises a heat absorbing layer and a protective layer, the reactive layer may be a thermal resistance layer, the thermal resistance layer is formed between the heat absorbing layer and the protective layer, and the plurality of slotting systems are penetrated and protected. Floor.
較佳地，輔助層結構包含一第一熱吸收層以及一第二熱吸收層，反應作用層可為熱電阻層，熱電阻層係形成於第一熱吸收層以及第二熱吸收層之間，而複數個開槽係穿透第二熱吸收層。Preferably, the auxiliary layer structure comprises a first heat absorbing layer and a second heat absorbing layer, and the reactive layer may be a thermal resistance layer formed between the first heat absorbing layer and the second heat absorbing layer And a plurality of slotting systems penetrate the second heat absorbing layer.
基於上述目的，本發明再提供.一種用於封裝的蓋體結構，其包含蓋板、輔助層結構、反應作用層、第一金屬層以及第二金屬層。蓋板具凹槽，而凹槽中具有至少一支撐柱以及環狀平台。輔助層結構之第一表面可連接至少一支撐柱，使反應作用層結構懸浮設置於凹槽上，輔助層結構之相對於第一表面的一第二表面上具有複數個島狀體以及一凹陷區，在凹陷區中有複數個開槽。反應作用層係設置於輔助層結構中並由複數個開槽所暴露。第一金屬層係形成於輔助層結構上並透過複數個開槽電性接觸反應作用層。第二金屬層係形成於環狀平台上。In view of the above, the present invention further provides a cover structure for a package comprising a cover sheet, an auxiliary layer structure, a reaction layer, a first metal layer, and a second metal layer. The cover plate has a groove, and the groove has at least one support column and an annular platform. The first surface of the auxiliary layer structure may be connected to at least one support column, and the reaction layer structure is suspended and disposed on the groove, and the auxiliary layer structure has a plurality of island bodies and a depression on a second surface of the first surface Zone, there are a plurality of slots in the recessed zone. The reactive layer is disposed in the auxiliary layer structure and exposed by a plurality of slots. The first metal layer is formed on the auxiliary layer structure and penetrates the plurality of slotted electrical contact reaction layers. The second metal layer is formed on the annular platform.
較佳地，輔助層結構包含熱吸收層以及一保護層，反應作用層可為熱電阻層，在熱電阻層係形成於熱吸收層以及保護層之間，而複數個開槽係穿透保護層。Preferably, the auxiliary layer structure comprises a heat absorbing layer and a protective layer, the reactive layer may be a thermal resistance layer, the thermal resistance layer is formed between the heat absorbing layer and the protective layer, and the plurality of slotting systems are penetrated and protected. Floor.
較佳地，輔助層結構包含一第一熱吸收層以及一第二熱吸收層，反應作用層可為熱電阻層，熱電阻層係形成於第一熱吸收層以及第二熱吸收層之間，而複數個開槽係穿透第二熱吸收層。Preferably, the auxiliary layer structure comprises a first heat absorbing layer and a second heat absorbing layer, and the reactive layer may be a thermal resistance layer formed between the first heat absorbing layer and the second heat absorbing layer And a plurality of slotting systems penetrate the second heat absorbing layer.
於此使用，詞彙“與/或”包含一或多個相關條列項目之任何或所有組合。當“至少其一”之敘述前綴於一元件清單前時，係修飾整個清單元件而非修飾清單中之個別元件。As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. When the phrase "at least one of" is preceded by a list of elements, the entire list of elements is modified instead of the individual elements in the list.
參閱第1圖以及第2A至2I圖，其分別為根據本發明之用於晶片封裝之蓋體結構的製造方法之第一實施例之流程圖以及各個步驟之示意圖。圖中，製造方法包含下列步驟。步驟S10提供一蓋板10，其第一表面16上具有複數個封裝結構圖案11，每一封裝結構圖案11可包含複數個島狀體12以及一環狀平台(bonding ring) 13，如第2A圖所示。Referring to Fig. 1 and Figs. 2A to 2I, which are respectively a flow chart and a schematic view of each step of the first embodiment of the method for manufacturing a cover structure for a wafer package according to the present invention. In the figure, the manufacturing method includes the following steps. Step S10 provides a cover 10 having a plurality of package structure patterns 11 on the first surface 16, each package structure pattern 11 may include a plurality of islands 12 and a bonding ring 13, such as 2A. The figure shows.
在步驟S11，在蓋板10中形成複數個蝕刻保護區域15以定義島狀體支撐柱以及環狀平台焊接區，如第2B圖所示。實施上，可在特定位置植入滲雜(doping)可抑制蝕刻速率的材料，藉此形成蝕刻保護區域15。In step S11, a plurality of etch protection regions 15 are formed in the cap plate 10 to define the island support columns and the annular land lands, as shown in FIG. 2B. In practice, a material that can inhibit the etch rate can be implanted at a specific location, thereby forming an etch protection region 15.
在步驟S12，在封裝結構圖案11上形成一熱吸收層結構20(請見第2圖)以及一反應作用層。實施上，反應作用層係設置於熱吸收層結構20之間。而反應作用層可包含光電轉換層、焦電材料層或是熱電阻層。在此實施例中係以熱電阻層30作為反應作用層之舉例來進行說明。In step S12, a heat absorbing layer structure 20 (see Fig. 2) and a reaction layer are formed on the package structure pattern 11. In practice, the reactive layer is disposed between the heat absorbing layer structures 20. The reaction layer may comprise a photoelectric conversion layer, a pyroelectric material layer or a thermal resistance layer. In this embodiment, the example in which the thermal resistance layer 30 is used as the reaction layer is explained.
熱吸收層結構20可用多種態樣來實現，第一種態樣如第2B圖至第2F圖所示，先在蓋板10上形成第一熱吸收層22，接著在第一熱吸收層22上形成熱電阻層30，接著對熱電阻層30進行蝕刻，只保留在島狀體12之間定義為像素區域中的熱電阻層30。接著，在第一熱吸收層22以及熱電阻層30上形成第二熱吸收層23，第二熱吸收層23係覆蓋熱電阻層30，藉此以完成熱吸收層結構20。The heat absorbing layer structure 20 can be implemented in a variety of aspects. The first aspect, as shown in Figures 2B through 2F, first forms a first heat absorbing layer 22 on the cover 10, followed by a first heat absorbing layer 22. The thermal resistance layer 30 is formed thereon, and then the thermal resistance layer 30 is etched, leaving only the thermal resistance layer 30 defined as a pixel region between the islands 12. Next, a second heat absorbing layer 23 is formed on the first heat absorbing layer 22 and the thermistor layer 30, and the second heat absorbing layer 23 covers the thermistor layer 30, thereby completing the heat absorbing layer structure 20.
在其他態樣中，亦可用有保護效果的保護層來取代第二熱吸收層23，以緩衝應力。此外，保護層亦可同時具有吸收熱的功能。在其他態樣中，第一熱吸收層22、第二熱吸收層23或是保護層可具有單層結構或是多層結構，可依需要而搭配設計。In other aspects, the second heat absorbing layer 23 may be replaced with a protective layer to protect the stress. In addition, the protective layer can also have the function of absorbing heat. In other aspects, the first heat absorbing layer 22, the second heat absorbing layer 23 or the protective layer may have a single layer structure or a multilayer structure, and may be designed as needed.
實施上，熱吸收層可使用氮化矽(SixNy)來形成，保護層可使用二氧化矽(SiO2) 來形成，熱電阻層可使用氧化釩( VOx)或非晶(a-Si)。In practice, the heat absorbing layer can be formed using tantalum nitride (SixNy), the protective layer can be formed using cerium oxide (SiO2), and the thermal resistance layer can be made of vanadium oxide (VOx) or amorphous (a-Si).
在步驟S13，蝕刻熱吸收層結構20以產生複數個開槽21，每一開槽21係暴露熱電阻層30，如第2G圖所示。接著，在步驟S14，在熱吸收層結構20以及島狀體12上形成一第一金屬層40，以及在環狀平台13上形成一第二金屬層41。第一金屬層40係透過複數個開槽21電性接觸熱電阻層30，如第2H圖所示。實施上，第一金屬層40與第二金屬層41可為相同金屬或是相異的金屬；此外，第一金屬層40或第二金屬層41可為單層結構或是多層結構。較佳者，第一金屬層40及第二金屬層42上可進一步形成保護層42，保護層42只露出第一金屬層40及第二金屬層42，作為後續與晶片電性連接與環狀焊接之部份。In step S13, the heat absorbing layer structure 20 is etched to produce a plurality of slots 21, each of which exposes the thermal resistance layer 30 as shown in FIG. 2G. Next, in step S14, a first metal layer 40 is formed on the heat absorbing layer structure 20 and the island 12, and a second metal layer 41 is formed on the annular platform 13. The first metal layer 40 is electrically connected to the thermal resistance layer 30 through a plurality of slots 21, as shown in FIG. 2H. In practice, the first metal layer 40 and the second metal layer 41 may be the same metal or different metals; in addition, the first metal layer 40 or the second metal layer 41 may be a single layer structure or a multilayer structure. Preferably, the first metal layer 40 and the second metal layer 42 may further form a protective layer 42. The protective layer 42 exposes only the first metal layer 40 and the second metal layer 42 as electrical connections and loops to the wafer. The part of the weld.
此外，環狀平台13上亦可有第一金屬層40，但第一金屬層40在第二金屬層41下方。實施上，第一金屬層40以及第二金屬層41上再增加形成其他保護層，以避免金屬氧化。In addition, the annular metal plate 40 may also have a first metal layer 40, but the first metal layer 40 is below the second metal layer 41. In practice, the first metal layer 40 and the second metal layer 41 are further formed with other protective layers to avoid metal oxidation.
在步驟S15，在封裝結構圖案11上形成複數個穿槽50，複數個穿槽50係曝露蓋板10。如第2I圖所示，穿槽50係穿過熱吸收層結構20以及熱電阻層30。In step S15, a plurality of slots 50 are formed in the package structure pattern 11, and the plurality of slots 50 expose the cover 10. As shown in FIG. 2I, the through grooves 50 pass through the heat absorbing layer structure 20 and the thermal resistance layer 30.
在步驟S16中透過複數個穿槽50對蓋板10進行蝕刻，以在熱吸收層結構20下方形成一槽穴51，而複數個蝕刻保護區域15係形成複數個支撐柱52，如第2J圖所示，所完成的蓋體結構係為一懸浮結構。In step S16, the cover 10 is etched through a plurality of slots 50 to form a slot 51 under the heat absorbing layer structure 20, and the plurality of etch protection regions 15 form a plurality of support columns 52, as shown in FIG. As shown, the completed cover structure is a suspended structure.
請參閱第3圖以及第4A至4B圖，其係根據本發明之溫測元件之封裝方法之第一實施例之部分流程圖。此流程係接續於步驟S10至步驟S17所製造出的蓋體結構。Please refer to FIG. 3 and FIGS. 4A-4B, which are partial flow charts of the first embodiment of the packaging method of the temperature measuring element according to the present invention. This flow is continued from the cover structure manufactured in steps S10 to S17.
在步驟S31，提供一基板60，且基板60包含複數個晶片61、複數個電性接觸點62，以及複數個焊接區63，如第4A圖所示。實施上，基板60之晶片61可為訊號讀取線路設計晶片(Read act integrate circuit)，晶片61上可設有一金屬反射層，較佳者，可為薄的金屬反射層。In step S31, a substrate 60 is provided, and the substrate 60 includes a plurality of wafers 61, a plurality of electrical contact points 62, and a plurality of pads 63, as shown in FIG. 4A. In practice, the wafer 61 of the substrate 60 can be a read act integrated circuit. The wafer 61 can be provided with a metal reflective layer. Preferably, it can be a thin metal reflective layer.
在步驟S32，在真空中將蓋體結構之第一表面16朝向晶片61以覆蓋基板60，且複數個島狀體12係對應電性接觸點62，環狀平台13係對應至少一焊接區63。接著，並將島狀體12上的第一金屬層40與電性接觸點62相焊接，將環狀平台13上的第二金屬層41與至少一焊接區63相焊接，如第4B圖所示，以形成一晶片封裝結構。實施上，熱電阻層30到晶片61之上表面的反射層的間隔長度為所偵測紅外線之1/4波長。In step S32, the first surface 16 of the cover structure is directed toward the wafer 61 in a vacuum to cover the substrate 60, and the plurality of islands 12 correspond to the electrical contact points 62, and the annular platform 13 corresponds to at least one of the pads 63. . Next, the first metal layer 40 on the island 12 is soldered to the electrical contact 62, and the second metal layer 41 on the annular platform 13 is soldered to at least one of the pads 63, as shown in FIG. 4B. Shown to form a wafer package structure. In practice, the length of the reflective layer of the thermal resistance layer 30 to the upper surface of the wafer 61 is 1/4 wavelength of the detected infrared light.
此外，在習知技藝中，晶片和懸浮結構係一起形成，之後再切割而放到陶瓷槽座內，所以吸氣劑(getter)只能放在蓋體或陶瓷槽座。但是在本發明之封裝方法中，吸氣劑可形成在晶片61的表面，或是蓋體結構的內側面，進而增加可能的設置空間。Further, in the prior art, the wafer and the suspension structure are formed together, and then cut and placed in the ceramic holder, so that the getter can only be placed on the cover or the ceramic holder. However, in the encapsulation method of the present invention, the getter may be formed on the surface of the wafer 61 or on the inner side of the cover structure, thereby increasing the possible installation space.
如此，熱電阻層30、金屬層40在蓋板10上為整體沉積形成，未經過焊接/黏接。Thus, the thermal resistance layer 30 and the metal layer 40 are integrally deposited on the cover 10 without being soldered/bonded.
相對於傳統的封裝方法，本發明之封裝方法係將蓋體與懸浮結構一起做成晶圓級蓋體，再直接將晶圓級的封裝蓋體，焊接於設有晶片的基板上，所以不需要載體便可進行封裝，能有效縮小封裝面積以及體積，因此需要抽真空的體積比較小，可以大幅提高抽真空的效率以及封裝真空度。Compared with the conventional packaging method, the packaging method of the present invention forms the wafer-level cover body together with the suspension structure, and directly solders the wafer-level package cover body to the substrate on which the wafer is disposed, so The carrier can be packaged, and the package area and volume can be effectively reduced. Therefore, the volume required for vacuuming is relatively small, and the vacuuming efficiency and the package vacuum can be greatly improved.
此外，在習知技藝中，晶片與懸浮結構係一同在基板上形成，但是在本發明之封裝方法，晶片與懸浮結構分開形成，因此可以各自進行製程優化，同時也可以減少彼此所使用的材料條件之間的影響。例如，在習知技藝中，先形成晶片然後再形成懸浮結構，為了避免晶片在懸浮結構之製程中因為高溫而損壞，因此懸浮結構之製程溫度受限於晶片的可承受溫度，所以能選擇的製程方法就受到限制。而在本發明中，晶片與懸浮結構分開形成，可避免彼此的影響，所以可選擇更多種懸浮結構的製程方法，進一步提高懸浮結構的良率。In addition, in the prior art, the wafer is formed on the substrate together with the suspension structure, but in the packaging method of the present invention, the wafer is formed separately from the suspension structure, so that process optimization can be performed separately, and materials used for each other can also be reduced. The effect between conditions. For example, in the prior art, a wafer is first formed and then a suspended structure is formed. In order to avoid damage of the wafer due to high temperature in the process of the suspension structure, the process temperature of the suspension structure is limited by the temperature at which the wafer can withstand, so that it can be selected. The process method is limited. In the present invention, the wafer is formed separately from the suspended structure, and the influence of each other can be avoided, so that a plurality of processes for the suspension structure can be selected to further improve the yield of the suspended structure.
晶片與懸浮結構分開形成的另一優點在於可避免晶片與懸浮結構的良率彼此影響。在習知技藝中，晶片與懸浮結構中其中一個壞了則整個都不能用；若是分開製造，甚至可以搭配基座晶片及蓋板基板的配對良率以提高晶片封裝的整體良率。Another advantage of the wafer being formed separately from the suspended structure is that the yield of the wafer and the suspended structure can be prevented from affecting each other. In the prior art, one of the wafer and the suspension structure is broken and the whole cannot be used; if it is manufactured separately, the matching yield of the base wafer and the cover substrate can be matched to improve the overall yield of the chip package.
舉例來說，當晶片與懸浮結構同在基板上形成時，由於懸浮結構之製程溫度受限於晶片的可承受溫度，所以能選的製程有限，加上晶片與懸浮結構中其中一個壞了則整個都不能用，所以假設晶片的良率為90%，而懸浮結構僅能採用良率60%的製程，則整體可能的良率為54% (即90%*60%)；但是，如果是分開形成，則懸浮結構可選擇良率80%的製程，再搭配晶片的良率為90%，所以整體的良率有機會可以提高到72%，若分別選擇良率更高的製程，整體良率則可望達到80%以上。For example, when the wafer and the suspension structure are formed on the substrate, since the process temperature of the suspension structure is limited by the temperature at which the wafer can withstand, the available process is limited, and one of the wafer and the suspension structure is broken. The whole can't be used, so if the wafer yield is 90%, and the suspension structure can only use the 60% yield process, the overall possible yield is 54% (ie 90%*60%); Separately formed, the suspension structure can select a process with a yield of 80%, and the yield of the matched wafer is 90%, so the overall yield can be increased to 72%. If the process with higher yield is selected, the overall good is good. The rate is expected to reach more than 80%.
請參閱第5圖以及第6A圖至第6J圖，其分別繪示本發明之用於晶片封裝之蓋體結構的製造方法之第二實施例之流程圖，以及部分示意圖。Referring to FIG. 5 and FIG. 6A to FIG. 6J, a flow chart and a partial schematic view of a second embodiment of a method for manufacturing a cover structure for a chip package of the present invention are respectively shown.
第二實施例與第一實施例的主要差異在於，第二實施例中步驟S80係提供一蓋板70，其具有一凹槽77，凹槽77內有複數個支撐柱結構72，如第6A圖所示。接著在步驟S81，在凹槽77中填入一犧牲材料19並進行蝕刻，以形成複數個封裝結構圖案71，每一封裝結構圖案71可包含複數個島狀體712以及一環狀平台713，如第6B圖所示。The main difference between the second embodiment and the first embodiment is that step S80 in the second embodiment provides a cover plate 70 having a recess 77 having a plurality of support post structures 72, such as section 6A. The figure shows. Then, in step S81, a sacrificial material 19 is filled in the recess 77 and etched to form a plurality of package structure patterns 71. Each package structure pattern 71 may include a plurality of islands 712 and an annular platform 713. As shown in Figure 6B.
接著，步驟S82至步驟S84與第一實施例之步驟S12至步驟S14相似，故在此不再贅述。而第6C圖至第6H圖的說明亦請參考第一實施例的說明。Then, the steps S82 to S84 are similar to the steps S12 to S14 of the first embodiment, and thus are not described herein again. For the description of FIGS. 6C to 6H, please refer to the description of the first embodiment.
在步驟S85，在封裝結構圖案71上形成複數個穿槽50，複數個穿槽50係曝露犧牲材料19。接著在步驟S86，透過複數個穿槽50對犧牲材料19進行蝕刻，將犧牲材料19蝕刻移除，而在熱吸收層結構20下方形成一槽穴51以及保留複數個支撐柱結構，藉此將熱吸收層結構20懸浮支撐於蓋板70上，以形成一蓋體結構。In step S85, a plurality of through grooves 50 are formed in the package structure pattern 71, and the plurality of through grooves 50 expose the sacrificial material 19. Next, in step S86, the sacrificial material 19 is etched through the plurality of slots 50 to etch away the sacrificial material 19, and a cavity 51 is formed under the heat absorbing layer structure 20 and a plurality of support pillar structures are retained, thereby The heat absorbing layer structure 20 is suspended and supported on the cover 70 to form a cover structure.
至於第二實施例之蓋體結構覆蓋於晶片上的後續封裝流程皆與第一實施例相同，故在此不再贅述。The subsequent packaging process of the cover structure of the second embodiment covering the wafer is the same as that of the first embodiment, and therefore will not be described herein.
請參閱第7圖，其為本發明之蓋體結構之第一實施例之俯視圖。圖中係顯示蓋體結構上可一次形成複數個懸浮結構131，而每一個懸浮結構131都由環狀平台13所環繞，並對應於晶片61每一個像素的位置，而各懸浮結構131之間無封裝牆。而第2A圖到第2I圖，以及第6A圖到6J圖係為沿著第7圖中剖面線AA’所取得。Please refer to Fig. 7, which is a plan view of the first embodiment of the cover structure of the present invention. The figure shows that a plurality of suspension structures 131 can be formed at a time on the cover structure, and each suspension structure 131 is surrounded by the annular platform 13 and corresponds to the position of each pixel of the wafer 61, and between the suspension structures 131. No encapsulation wall. The 2A to 2I, and the 6A to 6J drawings are taken along the section line AA' in Fig. 7.
請參閱第8圖係為本發明之蓋體結構之其他實施例之俯視圖。圖中，本發明之蓋體結構上亦形成有複數個懸浮結構131，且各懸浮結構131係設計為針對感測晶片61的每一個像素都有相對應的懸浮結構131，且不同像素之間共用環狀平台13。 如此，可提昇像素的解析度，並簡化製作個別環狀平台13所需的製程。Please refer to Fig. 8 for a plan view of another embodiment of the cover structure of the present invention. In the figure, the cover structure of the present invention is also formed with a plurality of suspension structures 131, and each suspension structure 131 is designed to have a corresponding suspension structure 131 for each pixel of the sensing wafer 61, and between different pixels. The annular platform 13 is shared. In this way, the resolution of the pixels can be improved, and the process required to fabricate the individual ring platforms 13 can be simplified.
第9圖例本發明之蓋體結構之其他實施例之俯視圖。圖中，本發明之蓋體結構上有複數個懸浮結構131，各懸浮結構131係設計為針對感測晶片61的每一組像素都有相對應的懸浮結構以及環狀平台13，而每一組封裝結構可為複數個像素之陣列所組成。如此，在各像素陣列中，即使有幾個像素的密封空間之真空度下降，也不會影響其他像素，即使真空度下降的像素對紅外線的感測值有誤差，仍可用其周圍像素的感測值來補償估算，使得溫測晶片整體的感測圖像數據可呈現不受影響。此處，各組像素陣列中各包含四個像素，且各組像素共用封裝牆，但不以此為限，像素陣列中像素的數量可根據使用者需求來設計。Figure 9 is a plan view of another embodiment of the cover structure of the present invention. In the figure, the cover structure of the present invention has a plurality of suspension structures 131, and each suspension structure 131 is designed to have a corresponding suspension structure and an annular platform 13 for each group of pixels of the sensing wafer 61, and each The group package structure can be composed of an array of a plurality of pixels. In this way, in each pixel array, even if the vacuum of the sealed space of several pixels is lowered, the other pixels are not affected, and even if the pixel whose degree of vacuum is lowered has an error in the sensed value of the infrared ray, the sense of surrounding pixels can be used. The measurements are used to compensate for the estimate so that the sensed image data of the entire temperature measurement wafer can be rendered unaffected. Here, each group of pixel arrays includes four pixels, and each group of pixels shares a package wall, but not limited thereto, the number of pixels in the pixel array can be designed according to user requirements.
在較佳實施例之詳細說明中所提出之具體實施例僅用以方便說明本發明之技術內容，而非將本發明狹義地限制於上述實施例，在不超出本發明之精神及以下申請專利範圍之情況，所做之種種變化實施，皆屬於本發明之範圍。The specific embodiments of the present invention are intended to be illustrative only and not to limit the invention to the above embodiments, without departing from the spirit of the invention and the following claims. The scope of the invention and the various changes made are within the scope of the invention.
10、70‧‧‧蓋板
11‧‧‧封裝結構圖案
12、712‧‧‧島狀體
13、713‧‧‧環狀平台
131‧‧‧懸浮結構
15‧‧‧蝕刻保護區域
16‧‧‧第一表面
17‧‧‧凹槽
19‧‧‧犧牲材料
20‧‧‧熱吸收層結構
21‧‧‧開槽
22、23‧‧‧熱吸收層
30‧‧‧熱電阻層
40‧‧‧第一金屬層
41‧‧‧第二金屬層
42‧‧‧保護層
50‧‧‧穿槽
51‧‧‧槽穴
52、72‧‧‧支撐柱
60‧‧‧基板
61‧‧‧晶片
62‧‧‧電性接觸點
63‧‧‧焊接區
AA’ ‧‧‧剖面線
S10~S16‧‧‧步驟流程10, 70‧‧‧ cover
11‧‧‧Package structure pattern
12, 712‧‧‧ islands
13, 713‧‧‧ ring platform
131‧‧‧suspension structure
15‧‧‧ Etched protected area
16‧‧‧ first surface
17‧‧‧ Groove
19‧‧‧Sacrificial materials
20‧‧‧ Heat absorbing layer structure
21‧‧‧ slotting
22, 23‧‧‧ heat absorbing layer
30‧‧‧Thermal resistance layer
40‧‧‧First metal layer
41‧‧‧Second metal layer
42‧‧‧Protective layer
50‧‧‧through slot
51‧‧‧Slots
52, 72‧‧‧ support column
60‧‧‧Substrate
61‧‧‧ wafer
62‧‧‧Electrical contact points
63‧‧‧Weld area
AA' ‧‧‧ hatching
S10~S16‧‧‧Step procedure
本發明之上述及其他特徵及優勢將藉由參照附圖詳細說明其例 示性實施例而變得更顯而易知，其中： 第1圖係為根據本發明之用於晶片封裝之蓋體結構的製造方法之第一實施 例之流程圖。 第2A圖至第2I圖係為根據本發明之用於晶片封裝之蓋體結構的製造方法之 第一實施例之各個步驟之示意圖。 第3圖係為根據本發明之溫測元件之封裝方法之第一實施例之部分流程圖。 第4A圖至第4B圖係為本發明之溫測元件之封裝方法之第一實施例之部分 示意圖。 第5圖係為根據本發明之用於晶片封裝之蓋體結構的製造方法之第二實施 例之流程圖。 第6A圖至第6J圖係為本發明之溫測元件之封裝方法之第二實施例之部分示 意圖。 第7圖係為本發明之蓋體結構之第一實施例之俯視圖。 第8圖係為本發明之蓋體結構之其他實施例之俯視圖。 第9圖係為本發明之蓋體結構之其他實施例之俯視圖。The above and other features and advantages of the present invention will become more apparent from the detailed description of the exemplary embodiments illustrated in the accompanying drawings in which: FIG. 1 is a cover structure for a wafer package according to the present invention. A flow chart of a first embodiment of the manufacturing method. 2A to 2I are schematic views showing respective steps of the first embodiment of the method of manufacturing a cover structure for a wafer package according to the present invention. Figure 3 is a partial flow chart of a first embodiment of a method of packaging a temperature sensing element in accordance with the present invention. 4A to 4B are views showing a part of the first embodiment of the packaging method of the temperature measuring element of the present invention. Fig. 5 is a flow chart showing a second embodiment of a method of manufacturing a lid structure for a wafer package according to the present invention. 6A to 6J are partial views showing a second embodiment of the packaging method of the temperature measuring element of the present invention. Figure 7 is a plan view showing a first embodiment of the cover structure of the present invention. Figure 8 is a plan view of another embodiment of the cover structure of the present invention. Figure 9 is a plan view of another embodiment of the cover structure of the present invention.
S10~S17‧‧‧步驟流程 S10~S17‧‧‧Step process
Claims (13)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104127576A TWI561799B (en) | 2015-08-24 | 2015-08-24 | Packaging method, cover structure of temperature sensing element and method for fabricating the same |
| CN201510582194.5A CN106486385A (en) | 2015-08-24 | 2015-09-14 | Packaging method of temperature measurement assembly, cover body structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104127576A TWI561799B (en) | 2015-08-24 | 2015-08-24 | Packaging method, cover structure of temperature sensing element and method for fabricating the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TWI561799B TWI561799B (en) | 2016-12-11 |
| TW201708798A true TW201708798A (en) | 2017-03-01 |
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| TW104127576A TWI561799B (en) | 2015-08-24 | 2015-08-24 | Packaging method, cover structure of temperature sensing element and method for fabricating the same |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN106486385A (en) |
| TW (1) | TWI561799B (en) |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3435925B2 (en) * | 1995-08-25 | 2003-08-11 | ソニー株式会社 | Semiconductor device |
| TW408495B (en) * | 1998-12-09 | 2000-10-11 | Shie Jeng Shiung | Vacuum package method of the infrared microsense device |
| US6890834B2 (en) * | 2001-06-11 | 2005-05-10 | Matsushita Electric Industrial Co., Ltd. | Electronic device and method for manufacturing the same |
| US7180064B2 (en) * | 2003-07-24 | 2007-02-20 | Delphi Technologies, Inc. | Infrared sensor package |
| JP5097275B2 (en) * | 2008-10-28 | 2012-12-12 | パナソニック株式会社 | Imaging unit |
| CN101691200B (en) * | 2009-09-29 | 2012-07-18 | 中国科学院上海微***与信息技术研究所 | Low temperature vacuum encapsulation structure of non-refrigeration infrared detector and manufacturing method thereof |
| CN203967072U (en) * | 2014-07-16 | 2014-11-26 | 佳霖科技股份有限公司 | For temperature, survey the wafer level packaging structure of assembly |
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2015
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| CN106486385A (en) | 2017-03-08 |
| TWI561799B (en) | 2016-12-11 |
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