TW201637244A - 發光二極體封裝結構及其製作方法 - Google Patents

發光二極體封裝結構及其製作方法 Download PDF

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TW201637244A
TW201637244A TW105108593A TW105108593A TW201637244A TW 201637244 A TW201637244 A TW 201637244A TW 105108593 A TW105108593 A TW 105108593A TW 105108593 A TW105108593 A TW 105108593A TW 201637244 A TW201637244 A TW 201637244A
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emitting diode
light emitting
electrode
package structure
conductive pad
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TW105108593A
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TWI692122B (zh
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洪欽華
林育鋒
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新世紀光電股份有限公司
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Abstract

本發明為一種發光二極體封裝結構及其製作方法。發光二極體封裝結構包括承載基座、靜電保護元件及發光二極體。承載基座具有第一導接墊及第二導接墊。靜電保護元件係設置於承載基座上，具有第一電極及第二電極，且第一、第二電極分別電性連接於第一、第二導接墊。發光二極體設置於靜電保護元件上方，具有第三電極及第四電極，第三、第四電極分別電性連接於第一、第二導接墊。

Description

發光二極體封裝結構及其製作方法
本發明係關於一種發光二極體封裝結構及其製作方法，特別是一種具有靜電保護元件的發光二極體封裝結構及其製作方法。
發光二極體具有諸如壽命長、體積小、高抗震性、低熱產生及低功率消耗等優點，因此隨著科技的發展，發光二極體已被廣泛應用於家用及各種設備中的指示器或光源。雖然發光二極體具有上述眾多優點，但卻常因異常電壓或靜電放電(electrostatic discharge，ESD)而損壞。
在先前技術中，為了避免發光二極體因異常電壓或靜電放電而損壞，而將發光二極體與靜電防護元件，例如是稽納二極體(Zener diode)同時設置在同一承載基座上，且發光二極體與稽納二極體是透過電極反向相連接，來避免發光二極體受到異常電壓或靜電放電的破壞。然而，由於發光二極體與靜電防護元件設置在同一承載基座的相同平面上，靜電防護元件會阻擋及吸收發光二極體所發出的光，會導致整體發光二極體的發光效率降低並造成封裝結構面積過大，在應用上就受到許多限制。
因此，有必要發明一種發光二極體封裝結構及其製作方法，以解決先前技術的缺失。
本發明實施例在提供一種發光二極體封裝結構及其製作方法，以改善上述習知問題。
本發明一實施例有關於一種發光二極體封裝結構。發光二極體封裝結構包括承載基座、靜電保護元件及發光二極體。承載基座具有第一導接墊及第二導接墊。靜電保護元件係設置於承載基座上，具有第一電極及第二電極，且第一、第二電極分別電性連接於第一、第二導接墊。發光二極體設置於靜電保護元件上方，具有第三電極及第四電極，第三、第四電極分別電性連接於第一、第二導接墊。
本發明另一實施例有關於一種發光二極體封裝結構之製作方法。製作方法包括以下步驟：提供承載基座，其中承載基座具有第一導接墊及第二導接墊；設置靜電保護元件於承載基座上，其中靜電保護元件具有第一電極及第二電極；使第一電極及第二電極分別電性連接於第一導接墊及第二導接墊；設置發光二極體於靜電保護元件之上方，其中發光二極體具有第三電極及第四電極；以及使第三電極及第四電極分別電性連接於第一導接墊及第二導接墊。
請參考圖1A及圖1B。圖1A係本發明一實施例之發光二極體封裝結構10a之俯視圖，而圖1B係圖1A之發光二極體封裝結構10a沿方向1B-1B’之剖視圖。
發光二極體封裝結構10a包括承載基座20、靜電保護元件30及發光二極體40。
承載基座20用以承載靜電保護元件30及發光二極體40。承載基座20包括第一導接墊20a、第二導接墊20b及絕緣體60。第一導接墊20a與第二導接墊20b透過絕緣體60電性隔離。舉例來說，第一導接墊20a與第二導接墊20b之間具有一間隔P1。絕緣體60包括間隔部61及邊緣部62，其中間隔部61填入間隔P1的至少一部分，以隔離第一導接墊20a與第二導接墊20b。此外，邊緣部62包覆第一導接墊20a的側面及第二導接墊20b的側面，可防止第一導接墊20a的側面及第二導接墊20b的側面露出，進而避免第一導接墊20a與第二導接墊20b透過側面電性短路。
在一實施例中，第一導接墊20a及第二導接墊20b的材料可以是金屬，如銅、鋁或其合金，但本發明實施例並不限於此。在一實施例中，絕緣體60的材料可以為矽氧樹脂(Silicone)、環氧樹脂(Epoxy)或聚鄰苯二甲醯胺樹脂(PPA)等，但本發明實施例並不限於此。
靜電保護元件30係設置於承載基座20上，靜電保護元件30可為一種用以防止異常電壓或靜電放電的電子元件，例如稽納二極體，但本發明實施例並不限於此。靜電保護元件30具有第一電極31及第二電極32，第一電極31係電性連接至第一導接墊20a，而第二電極32電性連接至第二導接墊20b。雖然圖未繪示，然第一電極31與第一導接墊20a之間可包含有焊錫，而第二電極32與第二導接墊20b之間可包含有焊錫，焊錫可焊合電極與導接墊。
承載基座20具有凹槽21，凹槽21從第一導接墊20a之第一上表面20a1及第二導接墊20b之第二上表面20b1往下延伸，但不貫穿第一導接墊20a及第二導接墊20b。凹槽21可採用例如是半蝕刻技術或機械加工技術形成，但本發明實施例並不限於此方式。
靜電保護元件30係設置於凹槽21內，因此不會干涉到上方的發光二極體40，且亦可充分利用承載基座20沿厚度方向的空間。
靜電保護元件30的至少一電極可位於發光二極體40的第三電極41與第四電極42之間。例如，如圖1B所示，本實施例之靜電保護元件30的第一電極31及第二電極32位於第三電極41與第四電極42之間。
此外，承載基座20具有一側壁，靜電保護元件30可位於側壁內。例如，如第1A圖所示，靜電保護元件30受到凹槽21的內側壁21w圍繞。如圖1B所示，凹槽21具有相對之內側壁21w1與21w2，靜電保護元件30位於相對二內側壁21w1與21w2內或之間。
發光二極體40可發出一光線。發光二極體40配置於承載基座20上。舉例來說，發光二極體40具有第三電極41及第四電極42，第三電極41電性連接至第一導接墊20a，而第四電極42電性連接至第二導接墊20b。如此一來，靜電保護元件30的第一電極31與發光二極體40的第三電極41共接點，而靜電保護元件30的第二電極32與發光二極體40的第四電極42共接點，因此靜電保護元件30與發光二極體40並聯；如此一來，靜電保護元件30可避免發光二極體40受到異常電壓或靜電放電的破壞。
此外，發光二極體40與承載基座20採用共晶接合方式等方式進行接合，但本發明實施例不限於此。雖然圖未繪示，然第三電極41與第一導接墊20a之間可包含有焊錫，而第四電極42與第二導接墊20b之間可包含有焊錫，焊錫可焊合電極與導接墊。
如圖1B所示，發光二極體40可直接設置於靜電保護元件30之正上方。藉由發光二極體40與靜電保護元件30沿垂直方位配置，可避免靜電保護元件30占用承載基座20的水平面積，進而使發光二極體封裝結構10a的表面積縮小。
發光二極體40之表面積係大於凹槽21之表面積。舉例來說，如圖1B所示，發光二極體40的體積大於凹槽21的容積，因此發光二極體40的表面積大於凹槽21之表面積。
如圖1B所示，發光二極體40具有第一寬度W1，而靜電保護元件30具有第二寬度W2，其中第一寬度W1大於第二寬度W2，使發光二極體40可覆蓋整個靜電保護元件30。在一實施例中，第一寬度W1可以是第二寬度W2的三倍，然亦可為三倍以下或以上。此外，承載基座20具有第一厚度H1，靜電保護元件30具有第二厚度H2，而凹槽21具有深度H3。在一實施例中，第一厚度H1例如是介於0.38毫米與0.5毫米之間，第二厚度度H2例如是0.1毫米，而深度H3可滿足下式(1)及(2)，其中式(2)中的A例如是介於0.05毫米與0.1毫米之間的數值。
H3＜0.5´H1…………………(1)
H3=H2+A……………………(2)
由於第一厚度H1、第二厚度H2及深度H3的設計，使當發光二極體40設置於該靜電保護元件30上方時，從發光二極體封裝結構10a的外觀幾乎看不到靜電保護元件30，且/或凹槽21之深度也不會影響到承載基座20原來的作用。
如圖1B所示，發光二極體40例如是覆晶式(Flip-Chip)發光二極體，但本發明實施例不限於此。發光二極體40更包括基板43、第一型半導體層44、第二型半導體層45、發光層46及第二反射層47。第一型半導體層44形成於基板43上，發光層46例如是多層量子井結構(Multiple Quantum Well，MQW)，其形成於第一型半導體層44與第二型半導體層45之間。第一型半導體層44例如是P型與N型半導體之一者，而第二型半導體層45例如是P型與N型半導體之另一者。
在本實施例中，第二反射層47形成布拉格反射層DBR(Distributed Bragg reflector)結構。第二反射層47可形成於發光二極體40的底層，例如是形成於第二型半導體層45的下方。如此，可將射向第二反射層47的光線反射至從基板43出光，亦可避免光線往承載基座20的方向漏光。
如圖1B所示，靜電保護元件30的頂部也可以形成具有第一反射層30a，以提高光反射效果。此外，第二反射層47及/或第一反射層30a可採用蒸鍍方式形成。在一實施例中，第二反射層47及/或第一反射層30a的材料例如是金屬。在另一實施例中，發光二極體40可省略第二反射層47與第一反射層30a之至少一者。
如圖1B所示，第二反射層47具有二開孔(未標示)，其分別露出第一型半導體層44與第二型半導體層45。第三電極41及第四電極42可透過二開孔分別電性連接於第一型半導體層44與第二型半導體層45。
如圖1B所示，凹槽21內可不包含任何膠體；或者，凹槽21內除了靜電保護元件30外，可不包含任何實體元件，然本發明實施例不以此為限。
圖2為本發明另一實施例之發光二極體封裝結構10a’之剖視圖。發光二極體封裝結構10a’包括承載基座20、靜電保護元件30、發光二極體40及高反射膠體50。與前述發光二極體封裝結構10a不同的是，本實施例之發光二極體封裝結構10a’更包括高反射膠體50。
高反射膠體50可填入凹槽21的至少一部分，以固定靜電保護元件30與承載基座20的相對位置。高反射膠體50的材質可為環氧樹脂或矽樹脂，其反射率可超過90%，但本發明實施例並不限於此。如圖2所示，高反射膠體50可包覆靜電保護元件30的整個頂面及整個側面，然在另一實施例中，高反射膠體50可包覆靜電保護元件30的頂面的一部分及/或側面的一部分。在本實施例中，高反射膠體50不接觸發光二極體40的底面，然在另一實施例中，高反射膠體50可接觸發光二極體40的底部，如接觸電極及/或第二反射層47。
如圖2所示，由於高反射膠體50的設計，靜電保護元件30可省略第一反射層30a，然亦可包含有第一反射層30a。
圖3為本發明另一實施例之發光二極體封裝結構10b之剖視圖。發光二極體封裝結構10b包括承載基座20、靜電保護元件30、發光二極體40及高反射膠體50。
與上述發光二極體封裝結構10a’不同的是，本實施例之發光二極體封裝結構10b的高反射膠體50更包覆發光二極體40的四周，如側面40s；如此一來，當發光二極體40之側面40s發出的光線到達高反射膠體50時，可被反射至從發光二極體40的上表面出光，藉此，可使發光二極體40的發光更集中，而不會往四周散射出去。
圖4為本發明另一實施例之發光二極體封裝結構10c之剖視圖。發光二極體封裝結構10c包括承載基座20、靜電保護元件30、發光二極體40’、高反射膠體50及數條焊線55及55’。
與上述發光二極體40不同的是，本實施例之發光二極體40’的結構例如是橫向芯片(Lateral Chip)結構發光二極體。
舉例來說，發光二極體40’包括基板43、第一型半導體層44、第二型半導體層45、發光層46、第二反射層47、第三反射層48及絕緣層49。第一型半導體層44形成於基板43上，發光層46形成於第一型半導體層44與第二型半導體層45之間。第二反射層47可形成於發光層46下方，以將到達第二反射層47的光線反射至從發光二極體40’上表面出光，亦可避免光線往承載基座20的方向漏光。絕緣層49形成於第三反射層48上，例如是形成於第三反射層48的下方，以隔離第三反射層48與承載基座20，避免第三反射層48與承載基座20電性短路。
此外，第二反射層47及/或第三反射層48可採用蒸鍍方式形成。在一實施例中，第三反射層48及/或第二反射層47的材料例如是金屬。在另一實施例中，發光二極體40’可省略第二反射層47與第三反射層48之至少一者。
第二反射層47及第三反射層48可形成全方向反射層ODR結構(Omni-Directional reflector)結構。在另一實施例中，若省略第三反射層48，則第二反射層47可形成DBR(Distributed Bragg reflector)結構。
如圖4所示，一焊線55可連接第一導接墊20a與第二型半導體層45，而另一焊線55’可連接第二導接墊20b與第一型半導體層44，使承載基座20與發光二極體40’透過焊線55及55’電性連接。
在另一實施例中，圖4之發光二極體封裝結構10c的高反射膠體50可更包覆焊線55及55’及發光二極體40’的側面40s，但可不包覆發光二極體40’的出光上表面。在其它實施例中，發光二極體封裝結構10c可省略高反射膠體50。
圖5為本發明另一實施例之發光二極體封裝結構10d之剖視圖。發光二極體封裝結構10d包括承載基座20’、靜電保護元件30、發光二極體40及高反射膠體50。
與前述實施例不同的是，本發明實施例之承載基座20’為陶瓷基板。承載基座20’包括堆疊之數片陶瓷片24、第一導接墊20a’、第二導接墊20b’、第一導通孔22a、第二導通孔22b、第三導接墊20c’及第四導接墊20d’及凹槽21。
凹槽21從承載基座20’的上表面20u (如最上層之陶瓷片24的頂面)往承載基座20’的下表面20e的方向延伸，但不貫穿堆疊之數片陶瓷片24的厚度。第一導接墊20a’及第二導接墊20b’從上表面20u延伸至凹槽21內，第一導接墊20a’與第二導接墊20b’彼此隔離。第三導接墊20c’及第四導接墊20d’形成於承載基座20’的下表面20e，第三導接墊20c’與第四導接墊20d’彼此隔離。第一導通孔22a及第二導通孔22b貫穿堆疊之陶瓷片24，其中第一導通孔22a連接第一導接墊20a’與第三導接墊20c’，而第二導通孔22b連接第二導接墊20b’與第四導接墊20d’。
靜電保護元件30設於凹槽21內。靜電保護元件30包括第一電極31及第二電極32，其中第一電極31電性連接第一導接墊20a’，而第二電極32連接第二導接墊20b’。雖然圖未繪示，然第一電極31與第一導接墊20a’之間可包含有焊錫，而第二電極32與第二導接墊20b’之間可包含有焊錫，焊錫可焊合電極與導接墊。
發光二極體40可設置於承載基座20’的上表面20u上。發光二極體40的第三電極41電性連接於第一導接墊20a’，而第四電極42電性連接於第二導接墊20b’。雖然圖未繪示，然第三電極41與第一導接墊20a’之間包含有焊錫，而第四電極42與第二導接墊20b’之間包含有焊錫，焊錫可焊合電極與導接墊。
由於靜電保護元件30的第一電極31與發光二極體40的第三電極41共接點，而靜電保護元件30的第二電極32與發光二極體40的第四電極42共接點，因此靜電保護元件30與發光二極體40並聯；如此一來，靜電保護元件30可避免發光二極體40受到異常電壓或靜電放電的破壞。
在一實施例中，第一導接墊20a’、第二導接墊20b’、第三導接墊20c’與第四導接墊20d’中至少一者可採用例如是電鍍方式在同一製程中形成，然本發明實施例不限於此。在一實施例中，第一導通孔22a及第二導通孔22b可採用例如是鑽孔及電鍍方式形成。以材料而言，第一導接墊20a’、第二導接墊20b’、第三導接墊20c’及第四導接墊20d’可以是銀或其合金，而第一導通孔22a及第二導通孔22b可以是銅或其合金。
在另一實施例中，發光二極體封裝結構10d可省略高反射膠體50；或者，發光二極體封裝結構10d的高反射膠體50可僅包覆靜電保護元件30的至少一部分，但不包覆發光二極體40。
圖6A至6F為圖1B之發光二極體封裝結構10a及圖3之發光二極體封裝結構10b的製造過程圖。
首先，提供一承載基座20。以下說明承載基座20的製作方法。
如圖6A所示，提供第一導接墊20a及第二導接墊20b。第一導接墊20a與第二導接墊20b相距一間隔P1，使第一導接墊20a與第二導接墊20b透過間隔P1彼此電性隔離。第一導接墊20a具有第一子凹槽211，而第二導接墊20b具有第二子凹槽212，第一子凹槽211與第二子凹槽212形成凹槽21。第一子凹槽211、第二子凹槽212與間隔P1可於同一製程中形成，然亦可於不同製程中分別形成。此外，第一子凹槽211、第二子凹槽212及/或間隔P1可採用例如是半蝕刻技術或機械加工技術形成。
如圖6B所示，可採用例如是封裝技術或點膠技術，形成絕緣體60，以形成承載基座20，其中絕緣體60可填入間隔P1的至少一部分，且包覆第一導接墊20a的側面及第二導接墊20b的側面。
如圖6C所示，可採用例如是表面接合技術(SMT)或是共晶接合技術，設置靜電保護元件30於凹槽21內。靜電保護元件30包括第一電極31及第二電極32，其分別電性連接於第一導接墊20a及第二導接墊20b。
如圖6D所示，提供發光二極體40。發光二極體40至少包括第三電極41及第四電極42。
如圖6E所示，可採用例如是表面接合技術或是共晶接合技術，設置發光二極體40於承載基座20上，以形成圖1B所示之發光二極體封裝結構10a，其中發光二極體40的第三電極41及第四電極42分別電性連接於第一導接墊20a及第二導接墊20b。
如圖6E所示，靜電保護元件30的第一電極31與發光二極體40的第三電極41共接點，而靜電保護元件30的第二電極32與發光二極體40的第四電極42共接點，因此靜電保護元件30與發光二極體40並聯；如此一來，靜電保護元件30可避免發光二極體40受到異常電壓或靜電放電的破壞。
如圖6F所示，可採用例如是封裝技術或點膠技術，形成高反射膠體50，以形成圖3所示之發光二極體封裝結構10b，其中高反射膠體50填滿凹槽21且覆蓋發光二極體40的側面40s。
在另一實施例中，圖6F之高反射膠體50可僅覆蓋靜電保護元件30的至少一部分，但不覆蓋發光二極體40的側面40s，如此可形成例如是圖2所示之發光二極體封裝結構10a’。
圖4之發光二極體封裝結構10c的製造過程類似發光二極體封裝結構10a，差異在於發光二極體封裝結構10c的製造過程增加一焊線55的打線步驟。
圖7A至7C為圖1B、圖2、圖3及圖4之承載基座20的另一種製造過程圖。
如圖7A所示，提供第一導接墊20a及第二導接墊20b，其中第一導接墊20a與第二導接墊20b之間相距一間隔P1，使第一導接墊20a與第二導接墊20b透過間隔P1彼此電性隔離。相較於圖6A的導接墊，本步驟所提供的第一導接墊20a尚未形成第一子凹槽211且第二導接墊20b尚未形成第二子凹槽212。
如圖7B所示，可採用例如是封裝技術或點膠技術，形成絕緣體60，其中絕緣體60可填入間隔P1的至少一部分，且包覆第一導接墊20a的側面及第二導接墊20b的側面。
如圖7C所示，可採用例如是半蝕刻技術或機械加工技術，移除圖7B之第一導接墊20a、第二導接墊20b及絕緣體60的一部分，以形成凹槽21，進而。形成承載基座20。
圖8A至8F為圖5之發光二極體封裝結構10d的製造過程圖。
如圖8A所示，堆疊數片陶瓷片24形成一堆疊陶瓷基板。數片陶瓷片24形成凹槽21，凹槽21從堆疊陶瓷基板的上表面20u往下表面20e方向延伸，但不貫穿堆疊陶瓷基板。例如，數片陶瓷片24的一些陶瓷片24’各具有開孔24a，此些陶瓷片24’堆疊後形成凹槽21。
如圖8B所示，可採用例如是鑽孔技術，形成第一導通孔22a及第二導通孔22b貫穿堆疊陶瓷基板。
如圖8C所示，可採用例如是電鍍技術或微影蝕刻，形成第一導接墊20a’、第二導接墊20b’、第三導接墊20c’及第四導接墊20d’，以形成承載基座20’，其中第一導接墊20a’及第二導接墊20b’從堆疊陶瓷基板的上表面20u延伸至凹槽21內，而第三導接墊20c’及第四導接墊20d’形成於堆疊陶瓷基板的下表面20e，且第一導通孔22a連接第一導接墊20a’與第三導接墊20c’，而第二導通孔22b連接第二導接墊20b’與第四導接墊20d’。
如圖8D所示，可採用例如是表面接合技術或是共晶接合技術，設置靜電保護元件30於承載基座20’的凹槽21內。靜電保護元件30包括第一電極31及第二電極32，其分別電性連接於第一導接墊20a’及第二導接墊20b’。
如圖8E所示，提供發光二極體40。發光二極體40至少包括第三電極41及第四電極42。
然後，可採用例如是表面接合技術或是共晶接合技術，設置發光二極體40於承載基座20’上。發光二極體40的第三電極41及第四電極42分別電性連接於第一導接墊20a’及第二導接墊20b’。如此一來，靜電保護元件30的第一電極31與發光二極體40的第三電極41共接點，而靜電保護元件30的第二電極32與發光二極體40的第四電極42共接點，因此靜電保護元件30與發光二極體40並聯；如此一來，靜電保護元件30可避免發光二極體40受到異常電壓或靜電放電的破壞。
如圖8F所示，可採用例如是封裝技術或點膠技術，形成高反射膠體50，以形成圖5所示之發光二極體封裝結構10d，其中高反射膠體50可填入凹槽21且包覆發光二極體40的側面40s。
在另一實施例中，高反射膠體50可僅包覆靜電保護元件30的至少一部分，但不包覆發光二極體40之側面40s。在其它實施例中，可省略如圖8F所示之高反射膠體50的形成步驟。
綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之靜電保護範圍當視後附之申請專利範圍所界定者為準。
需注意的是，上述僅為實施例，而非限制於實施例。譬如 此不脫離本發明基本架構者，皆應為本專利所主張之權利範圍，而應以專利申請範圍為準。
10a、10a’、10b、10c、10d‧‧‧發光二極體封裝結構
20、20’‧‧‧承載基座
20a、20a’‧‧‧第一導接墊
20b’、20b’‧‧‧第二導接墊
20c’‧‧‧第三導接墊
20d’‧‧‧第四導接墊
20a1‧‧‧第一上表面
20b1‧‧‧第二上表面
20e‧‧‧下表面
20u‧‧‧上表面
21‧‧‧凹槽
21w、21w1、21w2‧‧‧內側壁
211‧‧‧第一子凹槽
212‧‧‧第二子凹槽
22a‧‧‧第一導通孔
22b‧‧‧第二導通孔
24‧‧‧陶瓷片
24a‧‧‧開孔
30‧‧‧靜電保護元件
30a‧‧‧第一反射層
31‧‧‧第一電極
32‧‧‧第二電極
40、40’‧‧‧發光二極體
40s‧‧‧側面
41‧‧‧第三電極
42‧‧‧第四電極
43‧‧‧基板
44‧‧‧第一型半導體層
45‧‧‧第二型半導體層
46‧‧‧發光層
47‧‧‧第二反射層
48‧‧‧第三反射層
49‧‧‧絕緣層
50‧‧‧高反射膠體
55、55’‧‧‧焊線
60‧‧‧絕緣體
61‧‧‧間隔部
62‧‧‧邊緣部
H1‧‧‧第一厚度
H2‧‧‧第二厚度
H3‧‧‧深度
P1‧‧‧間隔
W1‧‧‧第一寬度
W2‧‧‧第二寬度
圖1A係本發明一實施例之發光二極體封裝結構之俯視圖。 圖1B係圖1A之發光二極體封裝結構沿方向1B-1B’之剖視圖。 圖2為本發明另一實施例之發光二極體封裝結構之剖視圖。 圖3為本發明另一實施例之發光二極體封裝結構之剖視圖。 圖4為本發明另一實施例之發光二極體封裝結構之剖視圖。 圖5為本發明另一實施例之發光二極體封裝結構之剖視圖。 圖6A至6F為圖1B之發光二極體封裝結構及圖3之發光二極體封裝結構的製造過程圖。 圖7A至7C為圖1B、圖2、圖3及圖4之承載基座的另一種製造過程圖。 圖8A至8F為圖5之發光二極體封裝結構的製造過程圖。
10a‧‧‧發光二極體封裝結構
20‧‧‧承載基座
20a‧‧‧第一導接墊
20a1‧‧‧第一上表面
20b‧‧‧第二導接墊
20b1‧‧‧第二上表面
21‧‧‧凹槽
21w1、21w2‧‧‧內側壁
30‧‧‧靜電保護元件
30a‧‧‧第一反射層
31‧‧‧第一電極
32‧‧‧第二電極
40‧‧‧發光二極體
41‧‧‧第三電極
42‧‧‧第四電極
43‧‧‧基板
44‧‧‧第一型半導體層
45‧‧‧第二型半導體層
46‧‧‧發光層
47‧‧‧第二反射層
60‧‧‧絕緣體
61‧‧‧間隔部
62‧‧‧邊緣部
H1‧‧‧第一厚度
H2‧‧‧第二厚度
H3‧‧‧深度
P1‧‧‧間隔
W1‧‧‧第一寬度
W2‧‧‧第二寬度

Claims (20)

  1. 一種發光二極體封裝結構，包括： 一承載基座，具有一第一導接墊及一第二導接墊； 一靜電保護元件，設置於該承載基座上，具有一第一電極及一第二電極，且該第一、第二電極分別電性連接於該第一、第二導接墊；以及 一發光二極體，設置於該靜電保護元件上方，具有一第三電極及一第四電極，該第三、第四電極分別電性連接於該第一、第二導接墊。
  2. 申請專利範圍第1項所述之發光二極體封裝結構，其中該承載基座具有一凹槽，該靜電保護元件係設置於該凹槽內。
  3. 如申請專利範圍第2項所述之發光二極體封裝結構，其中該發光二極體之表面積係大於該凹槽之表面積。
  4. 如申請專利範圍第2項所述之發光二極體封裝結構，其中該凹槽之深度係小於該承載基座之厚度之一半。
  5. 如申請專利範圍第2項所述之發光二極體封裝結構，更包括一高反射膠體，係填充於該凹槽內，以固定該靜電保護元件。
  6. 如申請專利範圍第5項所述之發光二極體封裝結構，其中該高反射膠體係進一步填充於該發光二極體之四周。
  7. 如申請專利範圍第1項所述之發光二極體封裝結構，其中該靜電保護元件係為一稽納二極體。
  8. 如申請專利範圍第7項所述之發光二極體封裝結構，其中該靜電保護元件之頂部設有一第一反射層。
  9. 如申請專利範圍第1項所述之發光二極體封裝結構，其中該發光二極體係的底部設有一第二反射層。
  10. 如申請專利範圍第1項所述之發光二極體封裝結構，其中該承載基座具有相對二側壁，該靜電保護元件位於該相對二側壁內。
  11. 如申請專利範圍第1項所述之發光二極體封裝結構，其中該靜電保護元件之該第一電極與該第二電極至少一者位於該發光二極體之該第三電極與該第四電極側壁之間。
  12. 一種製作發光二極體封裝結構之方法，包括以下步驟： 提供一承載基座，其中該承載基座具有一第一導接墊及一第二導接墊； 設置一靜電保護元件於該承載基座上，其中該靜電保護元件具有一第一電極及一第二電極； 使該第一電極及該第二電極分別電性連接於該第一導接墊及該第二導接墊； 設置一發光二極體於該靜電保護元件之上方，其中該發光二極體具有一第三電極及一第四電極；以及 使該第三電極及該第四電極分別電性連接於該第一導接墊及該第二導接墊。
  13. 如申請專利範圍第12項所述之製作發光二極體封裝結構之方法，更包括以下步驟： 設置該靜電保護元件於該承載基座之一凹槽中。
  14. 如申請專利範圍第13項所述之製作發光二極體封裝結構之方法，更包括以下步驟： 填充一高反射膠體於該凹槽內以固定該靜電保護元件。
  15. 如申請專利範圍第14項所述之製作發光二極體封裝結構之方法，更包括以下步驟： 填充該高反射膠體於該發光二極體之四周。
  16. 如申請專利範圍第13項所述之製作發光二極體封裝結構之方法，其中提供該承載基座之方法包括以下步驟： 設置一絕緣體於該第一導接墊及該第二導接墊之間；以及 藉由一半蝕刻技術於該第一導接墊及該第二導接墊之間形成該凹槽。
  17. 如申請專利範圍第13項所述之製作發光二極體封裝結構之方法，其中提供該承載基座之方法包括以下步驟： 提供該第一導接墊，該第一導接墊具有一第一子凹槽； 提供該第二導接墊，該第二導接墊具有一第二子凹槽，該第一子凹槽與該第二子凹槽形成該凹槽；以及 設置一絕緣體於該第一導接墊及該第二導接墊之間。
  18. 如申請專利範圍第13項所述之製作發光二極體封裝結構之方法，其中提供該承載基座之方法包括以下步驟： 藉由一堆疊技術形成一陶瓷基板，該陶瓷基板具有一凹槽； 形成一第一導通孔及一第二導通孔貫穿該陶瓷基板； 形成該第一導接墊及該第二導接墊於該陶瓷基板的上表面，其中該第一導接墊及該第二導接墊分別電性連接該第一導通孔及該第二導通孔；以及 形成一第三導接墊及一第四導接墊於該陶瓷基板的下表面，其中第三導接墊及一第四導接墊分別電性連接該第一導通孔及該第二導通孔。
  19. 如申請專利範圍第12項所述之製作發光二極體封裝結構之方法，更包括將一第二反射層設置於該發光二極體之一底部之步驟。
  20. 如申請專利範圍第12項所述之製作發光二極體封裝結構之方法，更包括將一第一反射層設置於該靜電保護元件之一頂部之步驟。
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