TW201637143A - Interposer, semiconductor device, and method for manufacture thereof - Google Patents
Interposer, semiconductor device, and method for manufacture thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/32—Holders for supporting the complete device in operation, i.e. detachable fixtures
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Abstract
Description
本發明係有關中介層、半導體裝置及其等之製造方法之技術。 The present invention relates to techniques for an interposer, a semiconductor device, and the like.
在晶圓製程所製造的各種記憶體、CMOS、CPU等之半導體元件係具有電性連接用端子。其連接用端子的間隔與應和半導體元件進行電性連接的印刷配線板側之連接部的間隔在其標度(scale)上有從數倍到數十倍左右的差異。因此，在欲將半導體元件和印刷基板電性連接的情況，使用稱為中介層之間隔變換用的仲介用基板(半導體元件封裝用基板)。一般是進行在中介層的一面封裝半導體元件，而在另一面或基板的周邊連接印刷配線板。 The semiconductor elements such as various memories, CMOS, and CPU manufactured by the wafer process have terminals for electrical connection. The interval between the terminals for connection and the connection portion on the side of the printed wiring board to be electrically connected to the semiconductor element has a difference of several times to several tens of times on the scale. Therefore, in the case where the semiconductor element and the printed circuit board are to be electrically connected, an intermediate dielectric substrate (a substrate for semiconductor element packaging) called a spacer layer is used. Generally, a semiconductor element is packaged on one side of the interposer, and a printed wiring board is connected on the other side or the periphery of the substrate.
用以將半導體元件封裝於印刷配線板之中介層，以往就一直採用利用了有機材料的基板迄今。然而，近年因以智慧手機為代表之電子機器的急速發展，使得將半導體元件縱向積層、將不同類型的半導體元件排列於同一基板上並封裝之3次元或2.5次元封裝技術成為越來越不可欠缺。透過前述之技術開發，認為可實現電子機器更高速化、大容量化、低耗電力化。另一方面， 隨著半導體元件高密度化，中介層亦被要求製作微細的配線。然而，就以往的有機基板而言，會有因樹脂的吸濕或溫度所致之伸縮大，難以形成和標度相匹配的微細配線之課題。 In order to encapsulate a semiconductor element in an interposer of a printed wiring board, a substrate using an organic material has been conventionally used. However, in recent years, due to the rapid development of electronic devices represented by smart phones, it has become increasingly indispensable to vertically stack semiconductor components, arrange different types of semiconductor components on the same substrate, and package 3-dimensional or 2.5-dimensional packaging technology. . Through the development of the aforementioned technology, it is considered that the electronic device can be made higher in speed, larger in capacity, and lower in power consumption. on the other hand, As semiconductor devices are densified, interposers are also required to produce fine wiring. However, in the conventional organic substrate, the expansion and contraction of the resin due to moisture absorption or temperature is large, and it is difficult to form a fine wiring that matches the scale.
於是，近年在基板使用矽或玻璃的中介層之開發上受到了眾多的目光。由此等材料所成的基板因為不易受吸濕或伸縮的影響，故有利於形成微細配線。又可形成在內部開設微細的貫通孔供導電性物質填充之稱為TSV(Through-Silicon Via；矽通孔)或TGV(Through-Glass Via；玻璃通孔)的貫通電極。此貫通電極係將基板之表背面的配線用最短距離連接，實現信號傳送速度之高速化等優異的電氣特性。而且由於是內部形成配線的構造，故可說是在裝置的小型化或高密度化亦有效的封裝方法。又藉由採用貫通電極，成為可多銷並列連接，故變得無需使LSI自體高速化而可實現低耗電力化。如此一來，在基板使用矽或玻璃的中介層具有多個優點。 As a result, in recent years, the development of an interposer using ruthenium or glass on a substrate has attracted a lot of attention. Since the substrate formed by such materials is less susceptible to moisture absorption or expansion and contraction, it is advantageous to form fine wiring. Further, a through electrode called TSV (Through-Silicon Via) or TGV (Through-Glass Via) may be formed in which a fine through hole is formed in the inside and filled with a conductive material. This through electrode connects the wiring on the front and back sides of the substrate with the shortest distance, and achieves excellent electrical characteristics such as an increase in signal transmission speed. Further, since it is a structure in which wiring is formed inside, it can be said that it is an effective packaging method for miniaturization or high density of the device. Further, since the through electrodes are used, the multi-pins can be connected in parallel, so that it is possible to achieve low power consumption without increasing the speed of the LSI itself. As such, the use of an interposer of germanium or glass on the substrate has several advantages.
兩者經比較後，矽中介層(Si-IP)的微細加工性更優於玻璃中介層(G-IP)，且配線、TSV形成程序也已被建立。另一方面，具有所謂因只能處理圓形的矽晶圓而無法使用晶圓周邊部，或因無法以大型尺寸一齊生產而成本變高之缺點。G-IP係能進行利用大型面板的一齊處理，且亦能考量利用卷對卷(roll to roll)方式的生產方法，故可大幅降低成本。而且和藉由放電或雷射加工等而形成貫通孔之TGV不同，TSV因藉由氣體蝕刻持續挖孔而加工時間變長、含有晶圓薄化步驟等亦成為高成本 的要因。 After the comparison between the two, the fine processing property of the germanium interposer (Si-IP) is better than that of the glass interposer (G-IP), and wiring and TSV formation procedures have also been established. On the other hand, there is a drawback that the wafer peripheral portion cannot be used because only a circular germanium wafer can be processed, or the cost cannot be increased by large-scale production. The G-IP system can perform the processing using a large panel, and can also consider the production method using the roll to roll method, so that the cost can be greatly reduced. Further, unlike the TGV in which the through holes are formed by discharge or laser processing, the TSV has a long processing time due to the continuous boring by gas etching, and the wafer thinning step also becomes a high cost. The cause.
再者，就電氣特性而言，因為G-IP係基板自體不同於Si-IP，因為是絕緣體，所以不擔心即使在高速電路中亦產生寄生元件的情況，電氣特性更為優異。畢竟基板一使用玻璃時則形成絕緣膜的步驟本身就不需要，故而絕緣可靠性高且生產節拍亦短。 Further, in terms of electrical characteristics, since the G-IP substrate is different from Si-IP, since it is an insulator, there is no fear that parasitic elements are generated even in a high-speed circuit, and electrical characteristics are further improved. After that, when the substrate is used as a glass, the step of forming the insulating film itself is not required, so that the insulation reliability is high and the production tact is short.
[專利文獻1]日本特開2006-60119號公報 [Patent Document 1] Japanese Patent Laid-Open Publication No. 2006-60119
[專利文獻2]日本特開2012-15209號公報 [Patent Document 2] Japanese Patent Laid-Open Publication No. 2012-15209
如以上那樣，雖當使用玻璃基板時就能以低成本製作中介層，但在課題方面，可舉出形成微細配線或TGV之程序尚未被建立、且配線材料主流的銅與玻璃之密接性不佳等。 As described above, the interposer can be produced at a low cost when a glass substrate is used. However, in terms of problems, the procedure for forming fine wiring or TGV has not been established, and the adhesion between copper and glass in the mainstream of the wiring material is not Good.
一般，在對玻璃基板形成金屬電極方面，為提升玻璃與金屬電極之密接，在玻璃表面形成無機密接層，從其上形成電極。(參照上述專利文獻1)。在對玻璃密接性良好的物質方面，可舉出鈦、鉻等，但鉻、鈦難以用濕式處理程序來形成，在如上述專利文獻1所示的乾式處理程序中，就中介層的貫通孔之直徑10μm~200μm而言，開口狹窄，無法在貫通孔內部形成密接層。又，鉻、鈦的導電性比銅還低，在高頻的傳送方面，因為集 膚效應而使電流集中在鉻層或鈦層，引起傳送損失。此現象在外周是被鈦、鉻所覆蓋的TGV特別顯著，會損及玻璃的優異電氣特性。 In general, in order to form a metal electrode on a glass substrate, in order to improve adhesion between the glass and the metal electrode, an inorganic adhesion layer is formed on the surface of the glass, and an electrode is formed thereon. (Refer to the above Patent Document 1). Titanium, chromium, etc. are mentioned in the case of the material which is excellent in the adhesiveness of the glass. However, it is difficult to form a chromium and titanium by a wet processing procedure. In the dry processing procedure as described in the above-mentioned patent document 1, the interposer is penetrated. When the diameter of the hole is 10 μm to 200 μm, the opening is narrow, and an adhesion layer cannot be formed inside the through hole. Moreover, the conductivity of chromium and titanium is lower than that of copper, and in terms of high-frequency transmission, The skin effect causes the current to concentrate on the chrome layer or the titanium layer, causing transmission loss. This phenomenon is particularly remarkable in the periphery of the TGV covered with titanium and chromium, which may impair the excellent electrical characteristics of the glass.
如上述專利文獻2般為提升貫通孔與貫通電極之密接性，雖有試著使用樹脂，但因為貫通孔的直徑狹窄，所以會因為在塗工等之濕式處理程序所形成的樹脂導致貫通孔被完全填充而有無法形成貫通電極之問題。 In the case of the above-mentioned Patent Document 2, the adhesion between the through hole and the through electrode is improved. Although the resin is tried to be used, the diameter of the through hole is narrow, and the resin is formed by the resin formed by the wet processing procedure such as coating. The hole is completely filled and there is a problem that the through electrode cannot be formed.
本發明之目的在於防止因為中介層使用玻璃基板等所導致諸特性之惡化，具體言之，提供貫通孔內部的基板與導電層之密接性高的中介層、半導體裝置及其等之製造方法；及在貫通孔內部之高頻傳送損失少且具有高電氣特性與形成微細配線之中介層、半導體裝置及其等之製造方法。 An object of the present invention is to prevent deterioration of characteristics due to the use of a glass substrate or the like in an interposer, and more particularly to provide an interposer having a high adhesion between a substrate and a conductive layer in a through-hole, a semiconductor device, and the like; And a method for manufacturing a dielectric layer having a high frequency transmission loss inside the through hole and having high electrical characteristics and forming fine wiring, a semiconductor device, and the like.
用以解決上述課題之本發明的一態樣為，一種中介層，包含：具有貫通孔的基板；隔著種層而配置在基板上之1層以上的配線層；密接層，形成於貫通孔的壁面且由氧化物所成的絕緣體、樹脂所構成的絕緣體、鈦、鉻中任一者所構成；及貫通電極，可將形成在密接層上的前述基板之兩面側導通。 An aspect of the present invention for solving the above problems is that an interposer includes: a substrate having a through hole; a wiring layer of one or more layers disposed on the substrate via a seed layer; and an adhesion layer formed in the through hole The wall surface is composed of an insulator made of an oxide, an insulator made of a resin, titanium or chromium, and a through electrode that can be electrically connected to both sides of the substrate formed on the adhesion layer.
又，本發明其他態樣，係為在上述的中介層固定有半導體晶片之半導體裝置。 Further, another aspect of the present invention is a semiconductor device in which a semiconductor wafer is fixed to the above interposer.
又，本發明其他態樣為，一種中介層之製造方法，包含：將基板固定於表面經氧化物所成的絕緣體、樹脂所成的絕緣體、鈦、鉻中任一者所修飾的支持基 板之步驟；貫通孔形成步驟，在基板形成貫通孔；密接層形成步驟，在貫通孔側壁形成由氧化物所成的絕緣體、樹脂所成的絕緣體、鈦、鉻中任一者所構成之密接層；貫通電極形成步驟，在貫通孔填充導電性材料以形成可將基板的兩面側導通之貫通電極；及導電層除去步驟，將基板的表面上之導電層的一部份選擇性除去。 Further, another aspect of the present invention provides a method for producing an interposer, comprising: fixing a substrate to an insulator formed by an oxide formed on a surface, an insulator formed of a resin, or a support modified by either titanium or chromium; Step of forming a through hole; forming a through hole in the substrate; forming an adhesion layer, forming an insulator formed of an oxide, an insulator made of a resin, or an alloy made of titanium or chromium on the side wall of the through hole a through electrode forming step of filling a conductive material in the through hole to form a through electrode that can conduct both sides of the substrate; and a conductive layer removing step to selectively remove a portion of the conductive layer on the surface of the substrate.
又，本發明其他態樣為，係一種半導體裝置之製造方法，包含在以上述的中介層之製造方法所製造的中介層固定半導體晶片之步驟。 Moreover, another aspect of the present invention provides a method of manufacturing a semiconductor device, comprising the step of fixing a semiconductor wafer in an interposer manufactured by the above-described interposer manufacturing method.
對基板的貫通孔內，將玻璃和密接性佳且難以濕式處理程序形成的金屬層形成為密接層所構成的貫通電極、與隔著會依銅配線層用的蝕刻而溶解的密接層而形成在玻璃基板上之表背面的配線層進行電性連接。據此，可提高貫通電極的密接性。因此，依據本發明，提供一中介層，其可兼顧電性連接的高可靠性與形成微細配線。 In the through hole of the substrate, the glass and the metal layer which is excellent in adhesion and difficult to be subjected to the wet processing procedure are formed as a through electrode composed of the adhesion layer and an adhesion layer which is dissolved by etching for the copper wiring layer. The wiring layers formed on the front and back surfaces of the glass substrate are electrically connected. Thereby, the adhesion of the through electrode can be improved. Therefore, according to the present invention, an interposer is provided which can achieve both high reliability of electrical connection and formation of fine wiring.
又，可提供在貫通孔內部之高頻傳送損失少且具有高電氣特性與形成微細配線之中介層。 Further, it is possible to provide an interposer having low electric-frequency transmission loss inside the through-hole and having high electrical characteristics and forming fine wiring.
100、101、102、103‧‧‧中介層 100, 101, 102, 103‧‧‧ intermediary
200、201、202、203‧‧‧中介層 Intermediary level 200, 201, 202, 203‧‧
300、301、302、303‧‧‧半導體裝置 300, 301, 302, 303‧‧‧ semiconductor devices
10‧‧‧帶有支持體的玻璃基板 10‧‧‧Glass substrate with support
11‧‧‧玻璃基板 11‧‧‧ glass substrate
12‧‧‧帶有金屬的支持體(支持基板) 12‧‧‧Metal support (support substrate)
13‧‧‧貫通孔 13‧‧‧through holes
14‧‧‧種層 14‧‧‧ layers
15‧‧‧阻劑 15‧‧‧Resist
16‧‧‧密接層 16‧‧ ‧ close layer
20‧‧‧貫通電極 20‧‧‧through electrode
21‧‧‧鍍敷層 21‧‧‧ plating layer
22‧‧‧埋入樹脂 22‧‧‧ buried resin
23‧‧‧配線層 23‧‧‧Wiring layer
25‧‧‧導通孔 25‧‧‧vias
30‧‧‧絕緣樹脂層 30‧‧‧Insulating resin layer
40‧‧‧銲料 40‧‧‧ solder
41‧‧‧連接墊 41‧‧‧Connecting mat
42‧‧‧連接盤 42‧‧‧Connector
50‧‧‧半導體晶片 50‧‧‧Semiconductor wafer
圖1係顯示第1實施形態的中介層的構造之概略剖面圖。 Fig. 1 is a schematic cross-sectional view showing the structure of an interposer according to a first embodiment.
圖2係顯示第1實施形態的中介層的變形例的構造之概略剖面圖。 Fig. 2 is a schematic cross-sectional view showing a structure of a modification of the interposer of the first embodiment.
圖3係顯示在第1實施形態的中介層封裝半導體晶片而成之半導體裝置的構造之概略剖面圖。 3 is a schematic cross-sectional view showing the structure of a semiconductor device in which a semiconductor wafer is packaged in an interposer according to the first embodiment.
圖4係顯示第1實施形態的中介層的形成方法之流程圖。 Fig. 4 is a flow chart showing a method of forming an interposer according to the first embodiment.
圖5係顯示第1實施形態的中介層的形成方法的步驟之概略剖面圖。 Fig. 5 is a schematic cross-sectional view showing the steps of a method of forming an interposer according to the first embodiment.
圖6係顯示第2實施形態的中介層的構造之概略剖面圖。 Fig. 6 is a schematic cross-sectional view showing the structure of an interposer according to a second embodiment.
圖7係顯示第2實施形態的中介層的形成方法之流程圖。 Fig. 7 is a flow chart showing a method of forming an interposer according to the second embodiment.
圖8係顯示第2實施形態的中介層的形成方法的步驟之概略剖面圖。 Fig. 8 is a schematic cross-sectional view showing the steps of a method of forming an interposer according to a second embodiment.
圖9係顯示第2實施形態的中介層封裝半導體晶片而成之半導體裝置的構造之概略剖面圖。 Fig. 9 is a schematic cross-sectional view showing the structure of a semiconductor device in which a semiconductor wafer is interposed in an interposer according to a second embodiment.
圖10係顯示第2實施形態的中介層的變形例的構造之概略剖面圖。 Fig. 10 is a schematic cross-sectional view showing a structure of a modification of the interposer of the second embodiment.
圖11係顯示第3實施形態的中介層的構造之概略剖面圖。 Fig. 11 is a schematic cross-sectional view showing the structure of an interposer according to a third embodiment.
圖12係顯示第3實施形態的中介層的變形例的構造之概略剖面圖。 Fig. 12 is a schematic cross-sectional view showing a structure of a modification of the interposer of the third embodiment.
圖13係顯示在第3實施形態的中介層封裝半導體晶片而成之封裝半導體裝置的構造之概略剖面圖。 Fig. 13 is a schematic cross-sectional view showing the structure of a packaged semiconductor device in which a semiconductor wafer is packaged in an interposer according to a third embodiment.
圖14係顯示第3實施形態的中介層的形成方法之流程圖。 Fig. 14 is a flow chart showing a method of forming an interposer according to the third embodiment.
圖15係顯示第3實施形態的中介層的形成方法的步 驟之概略剖面圖。 Fig. 15 is a view showing a step of forming an interposer according to a third embodiment; A schematic cross-sectional view of the step.
圖16係顯示第4實施形態的中介層的構造之概略剖面圖。 Fig. 16 is a schematic cross-sectional view showing the structure of an interposer according to a fourth embodiment.
圖17係顯示第4實施形態的中介層的形成方法之流程圖。 Fig. 17 is a flow chart showing a method of forming an interposer according to the fourth embodiment.
圖18係顯示第4實施形態的中介層的形成方法的步驟之概略剖面圖。 Fig. 18 is a schematic cross-sectional view showing the steps of a method of forming an interposer according to a fourth embodiment.
圖19係顯示第4實施形態的中介層的變形例的構造之概略剖面圖。 Fig. 19 is a schematic cross-sectional view showing a structure of a modification of the interposer of the fourth embodiment.
圖20係顯示在第4實施形態的中介層封裝半導體晶片而成之半導體裝置的構造之概略剖面圖。 Fig. 20 is a schematic cross-sectional view showing the structure of a semiconductor device in which a semiconductor wafer is packaged in an interposer according to a fourth embodiment.
其次，針對本發明的實施形態參照圖面作說明。 Next, an embodiment of the present invention will be described with reference to the drawings.
本實施形態的中介層包含：具有貫通孔的基板；隔著能被配線層用蝕刻液蝕刻之種層(seed layer)而配置在基板上之1層以上的配線層；形成於貫通孔的壁面且由氧化物、樹脂等所成之絕緣體、或由鈦、鉻等之金屬所構成之密接層；可將形成於密接層上之基板的兩面側導通之貫通電極；及形成在貫通電極的端面之連接盤。 The interposer of the present embodiment includes a substrate having a through hole, and a wiring layer of one or more layers disposed on the substrate via a seed layer which can be etched by the etching solution for the wiring layer, and is formed on the wall surface of the through hole. And an insulator formed of an oxide or a resin, or an adhesion layer made of a metal such as titanium or chromium; a through electrode that can be electrically connected to both sides of the substrate formed on the adhesion layer; and an end surface formed on the through electrode The connection plate.
又，本實施形態的中介層之製造方法包含：將基板固定於表面經氧化物、樹脂等所成之絕緣體、或由鈦、鉻等之金屬所修飾的支持基板之步驟；貫通孔形成步驟，在基板形成貫通孔；密接層形成步驟，在貫通孔側壁形成氧化物、樹脂等所成的絕緣體，或由鈦、鉻 等之金屬所構成的密接層；貫通電極形成步驟，在貫通孔填充導電性材料以形成可將基板的兩面側導通之貫通電極；及導電層除去步驟，將基板的表面上之導電層的一部份選擇性除去。又，除了此中介層之製造方法之外，亦可包含固定半導體晶片的步驟。 Further, the method for producing an interposer according to the present embodiment includes a step of fixing a substrate to an insulator formed of an oxide or a resin, or a support substrate modified with a metal such as titanium or chromium, and a through hole forming step. a through hole is formed in the substrate; an adhesion layer forming step is performed to form an insulator such as an oxide or a resin on the sidewall of the through hole, or titanium or chromium An adhesive layer formed of a metal; a through electrode forming step of filling a conductive material in the through hole to form a through electrode capable of conducting both sides of the substrate; and a conductive layer removing step of forming a conductive layer on the surface of the substrate Partially removed. Further, in addition to the manufacturing method of the interposer, a step of fixing the semiconductor wafer may be included.
在以下的說明中，以使用玻璃作為基板的情況為例作說明。基板不受限於玻璃基板，亦可為矽製等。 In the following description, a case where glass is used as a substrate will be described as an example. The substrate is not limited to the glass substrate, and may be tantalum or the like.
(第1實施形態) (First embodiment)
圖1係顯示第1實施形態的中介層100的構造之概略剖面圖。如圖1所示，第1實施形態的中介層100係具備：具有貫通孔13的玻璃基板11；形成在玻璃基板11表面的種層14；形成在種層14上的配線層23；形成在貫通孔13的密接層16；及形成在密接層16上的貫通電極20。 Fig. 1 is a schematic cross-sectional view showing the structure of an interposer 100 according to the first embodiment. As shown in FIG. 1, the interposer 100 of the first embodiment includes a glass substrate 11 having a through hole 13 , a seed layer 14 formed on the surface of the glass substrate 11 , and a wiring layer 23 formed on the seed layer 14 . The adhesion layer 16 of the through hole 13 and the through electrode 20 formed on the adhesion layer 16 .
配線層23係透過貫通電極20而被電性連接。 The wiring layer 23 is electrically connected to the through electrode 20 .
形成配線層23與貫通電極20之導電性材料，係設為由銅、銀、金、鎳、鉑、鈀、釕、錫、錫銀、錫銀銅、錫銅、錫鉍、錫鉛、鋁中至少1者，或此等的化合物中至少1者，或此等的金屬粉與樹脂材料之混合物中至少1者所構成即可。關於貫通電極20亦是相同。 The conductive material forming the wiring layer 23 and the through electrode 20 is made of copper, silver, gold, nickel, platinum, palladium, rhodium, tin, tin silver, tin silver copper, tin copper, tin antimony, tin lead, aluminum. At least one of these, or at least one of these compounds, or at least one of these metal powders and a mixture of resin materials may be used. The through electrodes 20 are also the same.
後述的絕緣樹脂層30及埋入樹脂22係由環氧/苯酚、聚醯亞胺、環烯、PBO中任一者，或此等的複合材料所成，且設成線膨脹係數是30ppm/K以上40ppm/K以下即可。 The insulating resin layer 30 and the embedded resin 22 to be described later are formed of any one of epoxy/phenol, polyimine, cycloolefin, and PBO, or a composite material thereof, and have a linear expansion coefficient of 30 ppm/ K can be 40 ppm/K or less.
貫通孔13係設為最大徑是15μm以上100μm以下且深度是50μm以上700μm以下者即可。 The through hole 13 may have a maximum diameter of 15 μm or more and 100 μm or less and a depth of 50 μm or more and 700 μm or less.
後述之帶有金屬的支持體12的基材係由環氧/苯酚、聚醯亞胺、環烯、PBO中任一者，或此等的複合材料所構成，且設成線膨脹係數是30ppm/K以上40ppm/K以下即可。 The base material of the metal-supported body 12 described later is composed of any one of epoxy/phenol, polyimine, cycloolefin, and PBO, or a composite material thereof, and has a linear expansion coefficient of 30 ppm. /K or more above 40ppm/K.
帶有金屬的支持體12之金屬係由鈦、鎳、鉻中至少1者所成者構成。 The metal of the metal-containing support 12 is made of at least one of titanium, nickel, and chromium.
圖2係顯示中介層100的變形例的中介層200之概略剖面圖。如圖2所示，亦可配置成將絕緣樹脂層30和配線層23交互積層於玻璃基板11上，將各配線層23透過形成於積層在各配線層23上的絕緣樹脂層30之導通孔25而和鄰接之別的配線層23電性連接。 2 is a schematic cross-sectional view showing the interposer 200 of a modification of the interposer 100. As shown in FIG. 2, the insulating resin layer 30 and the wiring layer 23 may be alternately laminated on the glass substrate 11, and the wiring layers 23 may be transmitted through the via holes formed in the insulating resin layer 30 laminated on the respective wiring layers 23. 25 is electrically connected to the adjacent wiring layer 23.
圖3係顯示在中介層100封裝半導體晶片而成之半導體裝置300的構造之概略剖面圖。如圖3所示，在上述的中介層100上，例如透過連接墊41固定(封裝)半導體晶片50而構成半導體裝置300。 3 is a schematic cross-sectional view showing the structure of a semiconductor device 300 in which a semiconductor wafer is packaged in an interposer 100. As shown in FIG. 3, on the interposer 100 described above, the semiconductor wafer 50 is fixed (encapsulated) via the connection pad 41, for example, to constitute the semiconductor device 300.
在本實施形態之中介層100的形成為，例如圖4所示，按照支持體固定、形成貫通孔、形成密接層、形成種層、形成貫通電極、配線層之各步驟的順序進行。 The interposer 100 of the present embodiment is formed in the order of the steps of fixing the support, forming the through hole, forming the adhesion layer, forming the seed layer, and forming the through electrode and the wiring layer, as shown in FIG. 4, for example.
其次，參照圖4及圖5，說明中介層的形成方法。圖4係顯示中介層100的形成方法之流程圖。圖5係顯示中介層100的形成方法的步驟之概略剖面圖。 Next, a method of forming an interposer will be described with reference to FIGS. 4 and 5. 4 is a flow chart showing a method of forming the interposer 100. FIG. 5 is a schematic cross-sectional view showing the steps of a method of forming the interposer 100.
以下針對各形成的步驟作說明。 The steps of each formation will be described below.
(帶有金屬的支持體與玻璃基板固定的步驟) (Step of fixing the metal support to the glass substrate)
首先，在如圖5的(a)所示之表面以金屬修飾的帶有金屬的支持體12(支持基板)上將玻璃基板11利用 膠帶等作固定。玻璃基板11的厚度為，例如，50μm以上700μm以下。帶有金屬的支持體12的基材係由環氧/苯酚、聚醯亞胺、環烯、PBO中任一者，或此等的複合材料，或玻璃，或陶瓷等所構成，且設成線膨脹係數是1ppm/K以上40ppm/K以下即可。 First, the glass substrate 11 is utilized on a metal-supported metal-supported body 12 (support substrate) having a surface as shown in FIG. 5(a). Tape and the like are fixed. The thickness of the glass substrate 11 is, for example, 50 μm or more and 700 μm or less. The substrate of the metal-supported body 12 is composed of any one of epoxy/phenol, polyimine, cycloolefin, and PBO, or a composite material thereof, or glass, ceramics, or the like, and is formed. The coefficient of linear expansion may be 1 ppm/K or more and 40 ppm/K or less.
帶有金屬的支持體12之金屬部分(金屬層)係以由鈦、鎳、鉻中至少1者所成者構成。 The metal portion (metal layer) of the metal-containing support 12 is made of at least one of titanium, nickel, and chromium.
玻璃基板11朝帶有金屬的支持體12之固定係能利用膠帶、樹脂進行接著或利用水、溶劑進行吸附來進行。 The fixing of the glass substrate 11 to the metal-provided support 12 can be carried out by using an adhesive tape or a resin, followed by adsorption with water or a solvent.
(貫通孔形成的步驟) (Step of forming through holes)
其次，如圖5的(b)所示，對玻璃基板11形成貫通孔13。貫通孔13的徑，例如為15μm以上100μm以下，深度是50μm以上700μm以下。貫通孔13的形成係使用準分子雷射、或UV-YAG雷射、CO2雷射等來開口。 Next, as shown in FIG. 5(b), a through hole 13 is formed in the glass substrate 11. The diameter of the through hole 13 is, for example, 15 μm or more and 100 μm or less, and the depth is 50 μm or more and 700 μm or less. The formation of the through holes 13 is performed using a pseudo-molecular laser, a UV-YAG laser, a CO 2 laser or the like.
(密接層形成的步驟) (Step of forming an adhesion layer)
其次，經由貫通孔13利用雷射加工帶有金屬的支持體12。金屬係藉由雷射的能量而昇華，如圖5的(c)所示，在貫通孔13內(側壁)形成密接層16。密接層16的厚度係設成20nm以上500nm以下即可。 Next, the metal-provided support 12 is processed by laser through the through holes 13. The metal is sublimated by the energy of the laser, and as shown in FIG. 5(c), the adhesion layer 16 is formed in the through hole 13 (side wall). The thickness of the adhesion layer 16 may be 20 nm or more and 500 nm or less.
藉由此步驟，可將難以濕式處理程序形成的鈦、鍍敷的環境負荷高的鉻等之密接層16形成在難以乾式處理程序形成的貫通孔13內部。 By this step, it is possible to form the adhesion layer 16 such as titanium which is difficult to be formed by a wet treatment process or chromium having a high environmental load, which is formed in the through hole 13 which is formed by a dry process.
(種層形成的步驟) (Steps of seed layer formation)
其次，如圖5的(d)所示，從帶有金屬的支持 體12將玻璃基板11分離，在玻璃基板11表面形成是導電層的種層14。種層14的形成方法係可選擇濺鍍、無電解鍍敷等適合之方法。其次，如圖5的(e)所示，在種層14上以光蝕刻(photolithography)形成阻劑15。 Second, as shown in (d) of Figure 5, from the support with metal The body 12 separates the glass substrate 11 and forms a seed layer 14 which is a conductive layer on the surface of the glass substrate 11. The method of forming the seed layer 14 is a suitable method such as sputtering or electroless plating. Next, as shown in (e) of FIG. 5, a resist 15 is formed on the seed layer 14 by photolithography.
(貫通電極、配線層形成的步驟) (Step of forming through-electrode and wiring layer)
其次，如圖5的(f)所示，在貫通孔13內和阻劑15的開口部填充導電性材料以形成貫通電極20、配線層23。此時，亦可在貫通電極20的端面形成連接盤。 Next, as shown in FIG. 5(f), a conductive material is filled in the through hole 13 and the opening of the resist 15 to form the through electrode 20 and the wiring layer 23. At this time, a land may be formed on the end surface of the through electrode 20.
導電性材料係由銅、銀、金、鎳、鉑、鈀、釕、錫、錫銀、錫銀銅、錫銅、錫鉍、錫鉛、鋁中至少1者，或此等的化合物中至少1者，或此等的金屬粉與樹脂材料之混合物中至少1者所成。 The conductive material is at least one of copper, silver, gold, nickel, platinum, palladium, rhodium, tin, tin silver, tin silver copper, tin copper, tin antimony, tin lead, aluminum, or at least one of these compounds One, or at least one of the mixture of the metal powder and the resin material.
其次，如圖5的(g)所示，在除去玻璃基板11上的阻劑15之後，藉由蝕刻除去種層14的一部份。 Next, as shown in (g) of FIG. 5, after the resist 15 on the glass substrate 11 is removed, a part of the seed layer 14 is removed by etching.
經以上的步驟，製造圖1的中介層100。 Through the above steps, the interposer 100 of FIG. 1 is fabricated.
透過用乾式處理程序來形成貫通電極20內的密接層16，可形成比用濕式處理程序所形成者還具有高密接力之密接層16。結果，可獲得導電部分沒有剝離之可靠性高的中介層。 By forming the adhesion layer 16 in the through electrode 20 by a dry process, it is possible to form the adhesion layer 16 having a higher adhesion than those formed by the wet process. As a result, an intermediate layer having high reliability in which the conductive portion is not peeled off can be obtained.
此處，如圖2所示，亦可在所製作的中介層100上形成絕緣樹脂層30，設置複數層配線層23，使絕緣樹脂層30和配線層23交互積層。在玻璃基板11的表背面，所積層之絕緣樹脂層30與配線層23之數量亦可不同。此時，各配線層23係透過形成於積層在各配線層23上的絕緣層之導通孔25而和鄰接之其他的配線層23電性連接。 Here, as shown in FIG. 2, the insulating resin layer 30 may be formed on the interposer 100 to be formed, and the plurality of wiring layers 23 may be provided to alternately laminate the insulating resin layer 30 and the wiring layer 23. The number of the insulating resin layers 30 and the wiring layers 23 to be laminated may be different on the front and back surfaces of the glass substrate 11. At this time, each of the wiring layers 23 is electrically connected to the adjacent wiring layer 23 through the via holes 25 formed in the insulating layers laminated on the respective wiring layers 23.
又，在中介層100封裝半導體晶片50可作成如圖3所示的半導體裝置200。 Further, the semiconductor wafer 50 is packaged in the interposer 100 to form the semiconductor device 200 as shown in FIG.
(第2實施形態) (Second embodiment)
其次，針對第2實施形態，參照圖面作說明。 Next, the second embodiment will be described with reference to the drawings.
圖6係顯示第2實施形態的中介層101的構造之概略剖面圖。 Fig. 6 is a schematic cross-sectional view showing the structure of the interposer 101 of the second embodiment.
第2實施形態的中介層101之基本構造和第1實施形態的中介層相同。 The basic structure of the interposer 101 of the second embodiment is the same as that of the interposer of the first embodiment.
此處，第1實施形態中，說明了步驟的起始材料使用玻璃基板11，於形成貫通孔13後在貫通孔13內部形成密接層16，填充導電材料以形成貫通電極20的例子。相對地，本實施形態係為以鍍敷和樹脂等之複數種類進行貫通孔13內的填充之情況的例子。 In the first embodiment, the glass substrate 11 is used as the starting material for the step, and the adhesion layer 16 is formed inside the through hole 13 after the through hole 13 is formed, and the conductive material is filled to form the through electrode 20. In contrast, this embodiment is an example in which the filling in the through hole 13 is performed in a plurality of types such as plating and resin.
在本實施形態中之中介層101的形成為，例如圖7所示，按照支持體固定、形成貫通孔、形成密接層、形成種層、形成鍍敷層、填充埋入樹脂、研磨、形成種層、形成鍍敷層、形成配線層、貫通電極之各步驟的順序進行。 In the present embodiment, the interposer 101 is formed, for example, as shown in FIG. 7, in which a support is fixed, a through hole is formed, an adhesion layer is formed, a seed layer is formed, a plating layer is formed, a buried resin is filled, and polishing is performed to form a seed. The steps of forming a layer, forming a plating layer, forming a wiring layer, and penetrating the electrode are performed in this order.
其次，參照圖7及圖8，說明中介層101的形成方法。圖7係顯示中介層101的形成方法之流程圖。圖8係顯示中介層101的形成方法的步驟之概略剖面圖。 Next, a method of forming the interposer 101 will be described with reference to FIGS. 7 and 8. FIG. 7 is a flow chart showing a method of forming the interposer 101. Fig. 8 is a schematic cross-sectional view showing the steps of a method of forming the interposer 101.
以下針對各形成的步驟作說明。 The steps of each formation will be described below.
(帶有金屬的支持體與玻璃基板固定的步驟) (Step of fixing the metal support to the glass substrate)
首先，在如圖8的(a)所示之表面以金屬修飾的帶有金屬的支持體12上將玻璃基板11利用膠帶等作固 定。玻璃基板11朝帶有金屬的支持體12之固定係能利用膠帶、樹脂進行接著或利用水、溶劑進行吸附來進行。 First, the glass substrate 11 is fixed by a tape or the like on the metal-supported support 12 having a metal surface as shown in FIG. 8(a). set. The fixing of the glass substrate 11 to the metal-provided support 12 can be carried out by using an adhesive tape or a resin, followed by adsorption with water or a solvent.
(貫通孔形成的步驟) (Step of forming through holes)
其次，如圖8的(b)所示，對玻璃基板11形成貫通孔13。貫通孔13的徑，例如為15μm以上100μm以下，深度是50μm以上700μm以下。貫通孔13的形成係使用準分子雷射，或UV-YAG雷射、CO2雷射等進行開口。 Next, as shown in FIG. 8(b), a through hole 13 is formed in the glass substrate 11. The diameter of the through hole 13 is, for example, 15 μm or more and 100 μm or less, and the depth is 50 μm or more and 700 μm or less. The through hole 13 is formed by using an excimer laser, or a UV-YAG laser, a CO 2 laser, or the like.
(密接層形成的步驟) (Step of forming an adhesion layer)
其次經由貫通孔13利用雷射加工帶有金屬的支持體12。金屬係藉由雷射的能量而昇華，如圖8的(c)所示，在貫通孔13內(側壁)形成密接層16。密接層16的厚度係設成20nm以上500nm以下即可。 Next, the metal-provided support 12 is processed by laser through the through hole 13. The metal is sublimated by the energy of the laser, and as shown in FIG. 8(c), the adhesion layer 16 is formed in the through hole 13 (side wall). The thickness of the adhesion layer 16 may be 20 nm or more and 500 nm or less.
(種層形成的步驟) (Steps of seed layer formation)
其次，如圖8的(d)所示，從帶有金屬的支持體12將玻璃基板11分離，在玻璃基板11表面形成種層14。種層14的形成方法係可選擇濺鍍、無電解鍍敷等適合之方法。 Next, as shown in FIG. 8(d), the glass substrate 11 is separated from the metal-containing support 12, and the seed layer 14 is formed on the surface of the glass substrate 11. The method of forming the seed layer 14 is a suitable method such as sputtering or electroless plating.
(鍍敷層形成的步驟) (Step of forming a plating layer)
其次，如圖8的(e)所示在貫通孔13內及種層14上形成鍍敷層21。鍍敷層21的厚度係以不堵塞貫通孔13那樣的條件進行。 Next, as shown in FIG. 8(e), a plating layer 21 is formed in the through hole 13 and on the seed layer 14. The thickness of the plating layer 21 is performed under the condition that the through holes 13 are not blocked.
(埋入樹脂填充的步驟) (Step of embedding resin filling)
其次，如圖8的(f)所示，將埋入樹脂22填充於貫通孔13內。在填充方面，可使用利用網版印刷法或分配器(dispenser)之填充等。透過填充埋入樹脂22，貫 通孔13內的空隙消失，可防止貫通孔13內部的鍍敷層21之剝離。 Next, as shown in FIG. 8(f), the embedded resin 22 is filled in the through hole 13. In terms of filling, filling by a screen printing method or a dispenser, or the like can be used. Through the filling of the embedded resin 22, The voids in the through holes 13 disappear, and peeling of the plating layer 21 inside the through holes 13 can be prevented.
(研磨的步驟) (step of grinding)
其次，如圖8的(g)所示，將玻璃基板11表面的種層14與盛滿於貫通孔13上的埋入樹脂22利用研磨除去。藉此步驟使玻璃基板11表面平滑，可提升在配線層23之形成或封裝時的可靠性。 Next, as shown in (g) of FIG. 8, the seed layer 14 on the surface of the glass substrate 11 and the embedded resin 22 which is filled in the through hole 13 are removed by polishing. By this step, the surface of the glass substrate 11 is smoothed, and the reliability at the time of formation or packaging of the wiring layer 23 can be improved.
研磨方法係可考慮拋光研磨等之物理研磨、CMP等之化學研磨，選擇適合於埋入樹脂的材料之方法。 The polishing method is a method of selecting a material suitable for embedding a resin by physical polishing such as polishing or polishing, chemical polishing such as CMP, or the like.
(種層形成的步驟) (Steps of seed layer formation)
其次，如圖8的(h)所示，在玻璃基板11表面形成種層14。種層14的形成方法係可選擇濺鍍、無電解鍍敷等適合之方法。 Next, as shown in (h) of FIG. 8, a seed layer 14 is formed on the surface of the glass substrate 11. The method of forming the seed layer 14 is a suitable method such as sputtering or electroless plating.
(鍍敷層形成的步驟) (Step of forming a plating layer)
其次，如圖8的(i)及(j)所示，在形成阻劑15後，進行鍍敷層21的形成。 Next, as shown in (i) and (j) of FIG. 8, after the resist 15 is formed, the plating layer 21 is formed.
(配線層，貫通電極形成的步驟) (wiring layer, step of forming through electrodes)
其次，在除去阻劑15後，藉由蝕刻除去種層14的一部份，如圖8的(k)那樣，形成貫通電極20，配線層23。此時，亦可在貫通電極20的端面形成連接盤。 Next, after the resist 15 is removed, a part of the seed layer 14 is removed by etching, and as shown in FIG. 8(k), the through electrode 20 and the wiring layer 23 are formed. At this time, a land may be formed on the end surface of the through electrode 20.
藉由以上的步驟，製造圖6所示的中介層101。 Through the above steps, the interposer 101 shown in Fig. 6 is manufactured.
基於和第1實施形態相同的理由，可獲得耐熱性高，可靠性高的中介層101。 For the same reason as in the first embodiment, the interposer 101 having high heat resistance and high reliability can be obtained.
又，在本實施形態中因為在貫通電極20的填充方法上使用埋入樹脂22，所以即使是貫通孔13的開口徑大的 情況，亦可形成貫通電極20。 Further, in the present embodiment, since the embedded resin 22 is used in the filling method of the through electrode 20, even the opening diameter of the through hole 13 is large. In other cases, the through electrode 20 can also be formed.
此外，關於在上述各實施形態獲得之中介層，可適宜地選擇適合於要形成之配線的尺寸之工法。例如，在微細的配線層23的形成上使用增層(build-up)工法，使用在配線尺寸非微細的配線層23上積層習知的預浸材(Pre-preg)和銅箔之工法，亦可製造中介層。 Further, regarding the interposer obtained in each of the above embodiments, a method suitable for the size of the wiring to be formed can be appropriately selected. For example, a build-up method is used for forming the fine wiring layer 23, and a conventional prepreg (pre-preg) and copper foil are laminated on the wiring layer 23 having a non-fine wiring size. An interposer can be made.
圖9係顯示在中介層101封裝半導體晶片而成之半導體裝置301的構造之概略剖面圖。如圖9所示，在上述的中介層101隔著例如連接墊41將半導體晶片50封裝而構成半導體裝置301。 FIG. 9 is a schematic cross-sectional view showing the structure of a semiconductor device 301 in which a semiconductor wafer is packaged in an interposer 101. As shown in FIG. 9, the semiconductor wafer 50 is packaged by the above-described interposer 101 via, for example, a connection pad 41, thereby constituting the semiconductor device 301.
此處，上述實施形態中，雖以在形成密接層16之後，從帶有金屬的支持體12將玻璃基板11剝離而形成種層14之步驟作說明，但亦可將玻璃基板11固定於帶有金屬的支持體12的狀態下在密接層16上進行鍍敷。 Here, in the above-described embodiment, the step of forming the seed layer 14 by peeling off the glass substrate 11 from the metal-containing support 12 after forming the adhesion layer 16 is described. However, the glass substrate 11 may be fixed to the tape. Plating is performed on the adhesion layer 16 in a state in which the metal support 12 is provided.
圖10顯示中介層101的變形例的中介層201之概略剖面圖。上述實施形態中的配線層僅1層，但藉由將配線層23與絕緣樹脂層30交互地積層且透過導通孔25連接，亦可製造形成有如圖10所示之複數個配線層之中介層201。 FIG. 10 is a schematic cross-sectional view showing the interposer 201 of a modification of the interposer 101. In the above-described embodiment, the wiring layer is only one layer. However, by interposing the wiring layer 23 and the insulating resin layer 30 alternately and connecting through the via holes 25, an interposer in which a plurality of wiring layers as shown in FIG. 10 are formed can be manufactured. 201.
(第3實施形態) (Third embodiment)
圖11係顯示第3實施形態的中介層102的構造之概略剖面圖。如圖11所示，第3實施形態的中介層102係具備：具有貫通孔13的玻璃基板11；形成在貫通孔13內面的密接層16；形成在玻璃基板11的表面及密接層16上的種層14、形成在種層14上的配線層23；及將貫通孔13貫通 的貫通電極20。 Fig. 11 is a schematic cross-sectional view showing the structure of the interposer 102 of the third embodiment. As shown in FIG. 11 , the interposer 102 of the third embodiment includes a glass substrate 11 having a through hole 13 , an adhesion layer 16 formed on the inner surface of the through hole 13 , and a surface of the glass substrate 11 and the adhesion layer 16 . Seed layer 14, a wiring layer 23 formed on the seed layer 14, and a through hole 13 Through electrode 20.
圖12係顯示第3實施形態的變形例的中介層202之概略剖面圖。如圖12所示，中介層202中，絕緣樹脂層30和配線層23交互積層於玻璃基板11上，各配線層23是經由導通孔25被電性連接。 Fig. 12 is a schematic cross-sectional view showing an interposer 202 according to a modification of the third embodiment. As shown in FIG. 12, in the interposer 202, the insulating resin layer 30 and the wiring layer 23 are alternately laminated on the glass substrate 11, and the wiring layers 23 are electrically connected via the via holes 25.
圖13係顯示在第3實施形態的中介層102封裝半導體晶片而成之半導體裝置302的構造之概略剖面圖。如圖13所示，在上述的中介層102的連接盤42，例如透過銲料40固定(封裝)半導體晶片50的連接墊41而構成半導體裝置302。 Fig. 13 is a schematic cross-sectional view showing the structure of a semiconductor device 302 in which a semiconductor wafer is packaged in the interposer 102 of the third embodiment. As shown in FIG. 13, the connection pad 42 of the interposer 102 described above is fixed (packaged) with the connection pads 41 of the semiconductor wafer 50 by solder 40, for example, to constitute the semiconductor device 302.
其次，參照圖14及圖15，說明中介層的形成方法。圖14係顯示本實施形態的中介層102的形成方法之流程圖。本實施形態的中介層102的形成為，例如圖14所示，按照支持體固定、形成貫通孔、貫通孔內密接層、形成種層、形成貫通電極、形成配線層之各步驟的順序進行。 Next, a method of forming an interposer will be described with reference to Figs. 14 and 15 . Fig. 14 is a flow chart showing a method of forming the interposer 102 of the present embodiment. The interposer 102 of the present embodiment is formed in the order of the steps of fixing the support, forming the through hole, the through hole in the adhesion layer, forming the seed layer, forming the through electrode, and forming the wiring layer, as shown in FIG.
圖15係顯示中介層102的形成方法的步驟之概略剖面圖。 Fig. 15 is a schematic cross-sectional view showing the steps of a method of forming the interposer 102.
(玻璃基板朝支持體固定的步驟) (Step of fixing the glass substrate to the support)
首先，如圖15的(a)所示，在表面經絕緣體17修飾後的支持體12(支持基板)上將玻璃基板11利用膠帶等作固定。玻璃基板11的厚度，例如為50μm以上、700μm以下。支持體12的基材係由環氧/苯酚、聚醯亞胺、環烯、PBO(poly(p-phenylenebenzobisoxazole)；聚對苯苯并雙噁唑)中任一者，或此等的複合材料，或玻璃，或陶瓷等 所成，使用線膨脹係數是1ppm/K以上40ppm/K以下者即可。支持體12的絕緣體部分，係由SiO2等的氧化物絕緣體或PVC(聚氯乙烯)、環氧樹脂等的樹脂絕緣體中至少1者所成且與利用鍍敷產生的導電金屬之密接性良好的物質所構成。 First, as shown in FIG. 15(a), the glass substrate 11 is fixed by a tape or the like on the support 12 (support substrate) whose surface is modified by the insulator 17. The thickness of the glass substrate 11 is, for example, 50 μm or more and 700 μm or less. The substrate of the support 12 is any one of epoxy/phenol, polyimine, cycloolefin, PBO (poly(p-phenylenebenzobisoxazole); polyparaphenylene bisoxazole), or a composite material thereof. Or a glass, ceramic, or the like, and a linear expansion coefficient of 1 ppm/K or more and 40 ppm/K or less may be used. The insulator portion of the support 12 is made of at least one of an oxide insulator such as SiO 2 or a resin insulator such as PVC (polyvinyl chloride) or epoxy resin, and has good adhesion to a conductive metal produced by plating. Made up of substances.
玻璃基板11朝支持體12之固定係能利用膠帶、樹脂進行接著或利用水、溶劑進行吸附來進行。 The fixing of the glass substrate 11 to the support 12 can be carried out by using an adhesive tape or a resin, followed by adsorption with water or a solvent.
(貫通孔形成的步驟) (Step of forming through holes)
其次，如圖15的(b)所示，對玻璃基板11形成貫通孔13。貫通孔13的徑，例如為15μm以上100μm以下，深度是50μm以上700μm以下。貫通孔13係使用準分子雷射、或UV-YAG雷射、CO2雷射等來形成。 Next, as shown in FIG. 15(b), the through hole 13 is formed in the glass substrate 11. The diameter of the through hole 13 is, for example, 15 μm or more and 100 μm or less, and the depth is 50 μm or more and 700 μm or less. The through hole 13 is formed using an excimer laser, a UV-YAG laser, a CO 2 laser, or the like.
(貫通孔內密接層形成的步驟) (Step of forming an adhesion layer in the through hole)
其次，通過貫通孔13向支持體12的絕緣體17照射雷射。絕緣體17係藉由所照射之雷射的能量而昇華並和貫通孔13的內壁密接，如圖15的(c)所示，在貫通孔13內(側壁)形成密接層16。密接層16的厚度作成是20nm以上500nm以下即可。又，密接層16的電阻係數大於1×1016Ω‧m。 Next, the insulator 17 of the support 12 is irradiated with a laser through the through hole 13. The insulator 17 is sublimated by the energy of the irradiated laser light and is in close contact with the inner wall of the through hole 13, and as shown in FIG. 15(c), the adhesion layer 16 is formed in the through hole 13 (side wall). The thickness of the adhesion layer 16 may be 20 nm or more and 500 nm or less. Further, the resistivity of the adhesion layer 16 is greater than 1 × 10 16 Ω ‧ m.
藉由此步驟，可將難以濕式處理程序形成的氧化物或將因填充而導致堵塞貫通孔的樹脂等作為材料使用的密接層16，形成於貫通孔13內部。 By this step, the adhesion layer 16 which is difficult to be used in the wet processing process or the resin which is used as a material by blocking the through-holes due to filling can be formed inside the through hole 13.
(種層形成的步驟) (Steps of seed layer formation)
其次，如圖15的(d)所示，從支持體12將玻璃基板11分離，在玻璃基板11表面及貫通孔13內的密接層16上形 成是導電層的種層14。種層14的形成方法係選擇濺鍍、無電解鍍敷等適合的方法。其次，如圖15的(e)所示，在形成於玻璃基板11表面的種層14上以光蝕刻形成阻劑15。 Next, as shown in FIG. 15(d), the glass substrate 11 is separated from the support 12, and is formed on the surface of the glass substrate 11 and the adhesion layer 16 in the through hole 13. The seed layer 14 is a conductive layer. The method of forming the seed layer 14 is a suitable method such as sputtering or electroless plating. Next, as shown in (e) of FIG. 15, the resist 15 is formed by photolithography on the seed layer 14 formed on the surface of the glass substrate 11.
(貫通電極形成、配線層形成的步驟) (Step of forming through-electrode and forming wiring layer)
其次，如圖15的(f)所示，在貫通孔13內與阻劑15的開口部填充導電性材料而形成貫通電極20和配線層23。此時，亦可在貫通電極20的端面形成連接盤。 Next, as shown in FIG. 15(f), a conductive material is filled in the through hole 13 and the opening of the resist 15 to form the through electrode 20 and the wiring layer 23. At this time, a land may be formed on the end surface of the through electrode 20.
導電性材料，係由銅、銀、金、鎳、鉑、鈀、釕、錫、錫銀、錫銀銅、錫銅、錫鉍、錫鉛、鋁中至少1者，或此等的化合物中至少1者，或此等的導電性材料的粉末與樹脂材料之混合物中至少1者所構成。 The conductive material is made of at least one of copper, silver, gold, nickel, platinum, palladium, rhodium, tin, tin silver, tin silver copper, tin copper, tin antimony, tin lead, aluminum, or the like. At least one of them, or at least one of a mixture of the powder of the conductive material and the resin material.
其次，如圖15的(g)所示，在除去玻璃基板11上的阻劑15之後，藉由蝕刻除去種層14的一部份。 Next, as shown in (g) of FIG. 15, after the resist 15 on the glass substrate 11 is removed, a part of the seed layer 14 is removed by etching.
經以上的步驟，製造圖11的中介層102。 Through the above steps, the interposer 102 of FIG. 11 is fabricated.
此處，如圖12所示，亦可在所製作的中介層102上形成絕緣樹脂層30，設置複數層配線層23，使絕緣樹脂層30和配線層23交互積層。 Here, as shown in FIG. 12, the insulating resin layer 30 may be formed on the interposer 102 to be formed, and the plurality of wiring layers 23 may be provided to alternately laminate the insulating resin layer 30 and the wiring layer 23.
絕緣樹脂層30係由環氧/苯酚、聚醯亞胺、環烯、PBO中任一者，或此等的複合材料所成，且設成線膨脹係數是30ppm/K以上40ppm/K以下即可。在玻璃基板11的表背面，被積層之絕緣樹脂層30與配線層23之數亦可不同。圖12中，各配線層23係透過形成於積層在各配線層23上的絕緣層之導通孔25而和鄰接之別的配線層23電性連接。 The insulating resin layer 30 is made of any one of epoxy/phenol, polyimine, cycloolefin, and PBO, or a composite material thereof, and has a linear expansion coefficient of 30 ppm/K or more and 40 ppm/K or less. can. The number of the insulating resin layer 30 and the wiring layer 23 to be laminated may be different from the front and back surfaces of the glass substrate 11. In FIG. 12, each of the wiring layers 23 is electrically connected to the adjacent wiring layer 23 through the via holes 25 formed in the insulating layers laminated on the respective wiring layers 23.
又，在中介層102的連接盤42上隔著銲料40封裝半導體晶片50可作成如圖13所示的半導體裝置302。 Further, the semiconductor wafer 50 is packaged on the land 42 of the interposer 102 via the solder 40 to form the semiconductor device 302 as shown in FIG.
依據本實施形態的中介層及其製造方法，對玻璃基板11的貫通孔13內，將玻璃和密接性佳且難以濕式處理程序形成的氧化物絕緣體或絕緣樹脂形成為密接層16且建構於密接層16上的貫通電極20，與隔著種層14形成於玻璃基板11上的表背面的配線層進行電性連接。藉此，可獲得具有對於高速傳送低損失且密接性高的貫通電極20之中介層。又，透過用乾式處理程序來形成貫通電極20內的密接層16，可形成密接力高且貫通電極20周邊部僅以導電性高的導電材料構成之貫通電極20。結果，可獲得高速傳送優異且可靠性高的中介層。 According to the interposer of the present embodiment and the method for producing the same, an oxide insulator or an insulating resin which is excellent in adhesion between the glass and the through-hole 13 of the glass substrate 11 and which is difficult to be wet-processed is formed as the adhesion layer 16 and is constructed. The through electrode 20 on the adhesion layer 16 is electrically connected to the wiring layer formed on the front and back surfaces of the glass substrate 11 via the seed layer 14 . Thereby, an interposer having the through electrode 20 having low loss for high-speed transmission and high adhesion can be obtained. Further, by forming the adhesion layer 16 in the through electrode 20 by a dry process, it is possible to form the through electrode 20 having a high adhesion and a conductive material having a high conductivity only in the peripheral portion of the through electrode 20. As a result, an interposer excellent in high-speed transfer and high in reliability can be obtained.
(第4實施形態) (Fourth embodiment)
其次，針對第4實施形態，參照圖16~圖20作說明。圖16係顯示第4實施形態的中介層103的構造之概略剖面圖。 Next, a fourth embodiment will be described with reference to Figs. 16 to 20 . Fig. 16 is a schematic cross-sectional view showing the structure of the interposer 103 of the fourth embodiment.
此處，第3實施形態中，說明了步驟的起始材料使用玻璃基板11，於形成貫通孔13後在貫通孔13內部形成密接層16，填充導電材料以形成貫通電極20的例子。第4實施形態的中介層103之基本構造和第3實施形態的中介層相同，但本實施形態在貫通孔13內之填充是利用鍍敷和樹脂等之複數種類來進行的這點上與第3實施形態不同。 In the third embodiment, the glass substrate 11 is used as the starting material for the step, and the adhesion layer 16 is formed inside the through hole 13 after the through hole 13 is formed, and the conductive material is filled to form the through electrode 20. The basic structure of the interposer 103 of the fourth embodiment is the same as that of the interposer of the third embodiment. However, in the present embodiment, the filling in the through hole 13 is performed by a plurality of types such as plating and resin. 3 implementations are different.
具體言之，如圖16所示，第4實施形態的中介層103係具備：具有貫通孔13的玻璃基板11；形成於貫通孔13內面的密接層16；形成於玻璃基板11的表面及密接層16上的種層14；形成於玻璃基板11表面的種層14上的配線層23；形成於種層14上的鍍敷層21；及填充於鍍敷 層21內部的空間之埋入樹脂22。亦即，貫通電極20係以鍍敷層21為主體所構成。 Specifically, as shown in FIG. 16 , the interposer 103 of the fourth embodiment includes a glass substrate 11 having a through hole 13 , an adhesion layer 16 formed on the inner surface of the through hole 13 , and a surface formed on the glass substrate 11 and a seed layer 14 on the adhesion layer 16; a wiring layer 23 formed on the seed layer 14 on the surface of the glass substrate 11; a plating layer 21 formed on the seed layer 14; and filling in the plating The resin 22 is buried in the space inside the layer 21. That is, the through electrode 20 is mainly composed of the plating layer 21.
其次，參照圖17及圖18，說明中介層的形成方法。圖17係顯示本實施形態的中介層103的形成方法之流程圖。本實施形態的中介層103的形成為，例如圖17所示，按照支持體固定、形成貫通孔、貫通孔內密接層、形成種層、形成鍍敷層、填充埋入樹脂、表面研磨、形成種層、形成鍍敷層、形成配線層、貫通電極之各步驟的順序進行。 Next, a method of forming an interposer will be described with reference to FIGS. 17 and 18. Fig. 17 is a flow chart showing a method of forming the interposer 103 of the present embodiment. The interposer 103 of the present embodiment is formed, for example, as shown in FIG. 17, and is formed by a support, a through hole, a through-hole adhesion layer, a seed layer, a plating layer, a buried resin, and surface polishing. The steps of the seed layer, the formation of the plating layer, the formation of the wiring layer, and the through electrode are performed in this order.
圖18係顯示中介層103的形成方法的步驟之概略剖面圖。 Fig. 18 is a schematic cross-sectional view showing the steps of a method of forming the interposer 103.
(玻璃基板朝支持體固定的步驟) (Step of fixing the glass substrate to the support)
首先，如圖18的(a)所示，在表面經絕緣體17修飾後的支持體12上將玻璃基板11利用膠帶等作固定。玻璃基板11及支持體12係可使用和第3實施形態的玻璃基板11及帶有絕緣體的支持體12相同者。玻璃基板11朝支持體12之固定係能利用膠帶、樹脂進行接著或利用水、溶劑進行吸附來進行。 First, as shown in FIG. 18(a), the glass substrate 11 is fixed by a tape or the like on the support 12 whose surface is modified by the insulator 17. The glass substrate 11 and the support 12 can be the same as the glass substrate 11 of the third embodiment and the support 12 with an insulator. The fixing of the glass substrate 11 to the support 12 can be carried out by using an adhesive tape or a resin, followed by adsorption with water or a solvent.
(貫通孔形成的步驟) (Step of forming through holes)
其次，如圖18的(b)所示，對玻璃基板11形成貫通孔13。貫通孔13的徑，例如為15μm以上100μm以下，深度是50μm以上700μm以下。貫通孔13係使用準分子雷射、或UV-YAG雷射、CO2雷射等來形成。 Next, as shown in FIG. 18(b), the through hole 13 is formed in the glass substrate 11. The diameter of the through hole 13 is, for example, 15 μm or more and 100 μm or less, and the depth is 50 μm or more and 700 μm or less. The through hole 13 is formed using an excimer laser, a UV-YAG laser, a CO 2 laser, or the like.
(貫通孔密接層形成的步驟) (Step of forming through-hole adhesion layer)
其次，通過貫通孔13向支持體12的絕緣體17照射雷 射。絕緣體係藉由所照射之雷射的能量而昇華並在貫通孔13內密接，如圖18的(c)所示，在貫通孔13內(側壁)形成密接層16。密接層16的厚度作成是20nm以上500nm以下即可。又，密接層16的電阻係數大於1×1016Ω‧m。 Next, the insulator 17 of the support 12 is irradiated with a laser through the through hole 13. The insulating system is sublimated by the energy of the irradiated laser light and is in close contact with each other in the through hole 13, and as shown in FIG. 18(c), the adhesion layer 16 is formed in the through hole 13 (side wall). The thickness of the adhesion layer 16 may be 20 nm or more and 500 nm or less. Further, the resistivity of the adhesion layer 16 is greater than 1 × 10 16 Ω ‧ m.
(種層形成的步驟) (Steps of seed layer formation)
其次，如圖18的(d)所示，從支持體12將玻璃基板11分離，在玻璃基板11表面及貫通孔13內的密接層16上形成種層14。種層14的形成方法係選擇濺鍍、無電解鍍敷等適合的方法。 Next, as shown in FIG. 18(d), the glass substrate 11 is separated from the support 12, and the seed layer 14 is formed on the surface of the glass substrate 11 and the adhesion layer 16 in the through hole 13. The method of forming the seed layer 14 is a suitable method such as sputtering or electroless plating.
(鍍敷層形成的步驟) (Step of forming a plating layer)
其次，如圖18的(e)所示在貫通孔13內的種層14上形成鍍敷層21。鍍敷層21係形成為不會堵塞貫通孔13的厚度。 Next, as shown in FIG. 18(e), a plating layer 21 is formed on the seed layer 14 in the through hole 13. The plating layer 21 is formed so as not to block the thickness of the through hole 13.
(埋入樹脂填充的步驟) (Step of embedding resin filling)
其次，如圖18的(f)所示，將埋入樹脂22填充於貫通孔13內。在填充方面，可使用利用網版印刷法或分配器之填充等。埋入樹脂22係由環氧/苯酚、聚醯亞胺、環烯、PBO中任一者，或此等的複合材料所成，且設成線膨脹係數是30ppm/K以上40ppm/K以下即可。因為填充埋入樹脂22，使貫通孔13內的空隙消失，可防止貫通孔13內部的鍍敷層21之剝離。又，即使在高頻傳送之情況，會發生集膚效應係在與貫通電極20的密接層16之界面附近，形成在貫通孔13中心側之埋入樹脂22不會有妨礙高頻傳送之情況。 Next, as shown in FIG. 18(f), the embedded resin 22 is filled in the through hole 13. In terms of filling, a filling using a screen printing method or a dispenser or the like can be used. The embedded resin 22 is made of any one of epoxy/phenol, polyimine, cycloolefin, and PBO, or a composite material thereof, and has a linear expansion coefficient of 30 ppm/K or more and 40 ppm/K or less. can. Since the embedded resin 22 is filled and the voids in the through holes 13 are eliminated, peeling of the plating layer 21 inside the through holes 13 can be prevented. Further, even in the case of high-frequency transmission, the skin effect occurs in the vicinity of the interface with the adhesion layer 16 of the through electrode 20, and the embedded resin 22 formed on the center side of the through hole 13 does not hinder the high-frequency transmission. .
(研磨的步驟) (step of grinding)
其次，如圖18的(g)所示，將玻璃基板11表面的種層14與盛滿於貫通孔13上的埋入樹脂22利用研磨除去。透過此步驟使玻璃基板11表面平滑，可提升在配線層23之形成或封裝時的可靠性。研磨方法係採用拋光研磨等之物理的研磨、CMP(Chemical Mechanical Planarization；化學機械平坦化)等之化學研磨，選適合於埋入樹脂的材料之方法。 Next, as shown in FIG. 18(g), the seed layer 14 on the surface of the glass substrate 11 and the embedded resin 22 which is filled in the through hole 13 are removed by polishing. By this step, the surface of the glass substrate 11 is smoothed, and the reliability at the time of formation or packaging of the wiring layer 23 can be improved. The polishing method is a method in which a material suitable for embedding a resin is selected by chemical polishing such as polishing or polishing, chemical polishing such as CMP (Chemical Mechanical Planarization).
(種層形成的步驟) (Steps of seed layer formation)
其次，如圖18的(h)所示，在玻璃基板11表面形成種層14。種層14的形成方法係可選擇濺鍍、無電解鍍敷等適合之方法。 Next, as shown in (h) of FIG. 18, a seed layer 14 is formed on the surface of the glass substrate 11. The method of forming the seed layer 14 is a suitable method such as sputtering or electroless plating.
(鍍敷層形成的步驟) (Step of forming a plating layer)
其次，如圖18的(i)及(j)所示，在種層14上形成阻劑15後，進行鍍敷層21的形成。 Next, as shown in (i) and (j) of FIG. 18, after the resist 15 is formed on the seed layer 14, the plating layer 21 is formed.
(配線層、貫通電極形成的步驟) (Step of forming wiring layer and through electrode)
其次，於除去阻劑15後，藉由蝕刻除去種層14的一部份，如圖18的(k)那樣，形成貫通電極20和配線層23。配線層23的一部份係透過貫通電極20而被電性連接。此時，亦可在貫通電極20的端面形成連接盤。形成貫通電極20與配線層23之導電性材料，係銅、銀、金、鎳、鉑、鈀、釕、錫、錫銀、錫銀銅、錫銅、錫鉍、錫鉛、鋁中至少1者，或此等的化合物中至少1者，或此等的導電性材料的粉末與樹脂材料之混合物中至少1者所構成。 Next, after the resist 15 is removed, a part of the seed layer 14 is removed by etching, and the through electrode 20 and the wiring layer 23 are formed as shown in (k) of FIG. A part of the wiring layer 23 is electrically connected through the through electrode 20. At this time, a land may be formed on the end surface of the through electrode 20. The conductive material forming the through electrode 20 and the wiring layer 23 is at least 1 of copper, silver, gold, nickel, platinum, palladium, rhodium, tin, tin silver, tin silver copper, tin copper, tin antimony, tin lead, and aluminum. At least one of these compounds, or at least one of a mixture of a powder of such a conductive material and a resin material.
藉由以上的步驟，製造如圖16所示的中介層103。 Through the above steps, the interposer 103 as shown in FIG. 16 is fabricated.
依據本實施形態的中介層及其製造方法，基於和第3實施形態相同的理由，可獲得高速傳送優異且可靠性高的中介層103。又，本實施形態中因為在貫通電極20的填充方法上使用埋入樹脂22，所以即使是貫通孔13的開口徑大的情況，亦可形成貫通電極20。 According to the interposer of the present embodiment and the method of manufacturing the same, the interposer 103 having excellent high-speed transmission and high reliability can be obtained for the same reason as in the third embodiment. Further, in the present embodiment, since the embedded resin 22 is used in the filling method of the through electrode 20, the through electrode 20 can be formed even when the opening diameter of the through hole 13 is large.
圖19係中介層103的變形例的中介層203之概略剖面圖。上述實施形態中的配線層僅1層，但是藉由將配線層23和絕緣樹脂層30交互積層且透過導通孔25連接，亦可製造形成有如圖19所示的複數個配線層之中介層203。此外，絕緣樹脂層30係由環氧/苯酚、聚醯亞胺、環烯、PBO中任一者，或此等的複合材料所成，且設成線膨脹係數是30ppm/K以上40ppm/K以下即可。 19 is a schematic cross-sectional view of the interposer 203 of a modification of the interposer 103. In the above-described embodiment, the wiring layer is only one layer. However, by interposing the wiring layer 23 and the insulating resin layer 30 alternately and connecting through the via holes 25, the interposer 203 in which a plurality of wiring layers as shown in FIG. 19 are formed can be manufactured. . Further, the insulating resin layer 30 is formed of any one of epoxy/phenol, polyimine, cycloolefin, and PBO, or a composite material thereof, and has a linear expansion coefficient of 30 ppm/K or more and 40 ppm/K. The following can be.
圖20係顯示在中介層103封裝半導體晶片而成之半導體裝置303的構造之概略剖面圖。如圖20所示，在上述的中介層103的連接盤42，例如透過銲料40固定(封裝)半導體晶片50的連接墊41而構成半導體裝置303。 20 is a schematic cross-sectional view showing the structure of a semiconductor device 303 in which a semiconductor wafer is packaged in an interposer 103. As shown in FIG. 20, the connection pad 42 of the interposer 103 described above is fixed (packaged) with the connection pads 41 of the semiconductor wafer 50 by solder 40, for example, to constitute the semiconductor device 303.
此外，上述的各實施形態中，係在形成密接層16之後，從支持體12將玻璃基板11剝離而形成種層14，但亦可作成在將玻璃基板11固定於支持體12的狀態下在密接層16上進行鍍敷。 Further, in each of the above-described embodiments, after the adhesion layer 16 is formed, the glass substrate 11 is peeled off from the support 12 to form the seed layer 14, but the glass substrate 11 may be fixed to the support 12 in a state where the glass substrate 11 is fixed to the support 12 Plating is performed on the adhesion layer 16.
此外，關於在上述各實施形態獲得之中介層，可適宜地選擇適合於要形成之配線的尺寸之工法。例如，在微細的配線層23的形成上使用增層工法，使用在配線尺寸非微細的配線層23上積層習知的預浸材和銅箔之工法，亦可製造中介層。 Further, regarding the interposer obtained in each of the above embodiments, a method suitable for the size of the wiring to be formed can be appropriately selected. For example, a layering method is used for forming the fine wiring layer 23, and an intermediate layer can be produced by a method of laminating a conventional prepreg and a copper foil on the wiring layer 23 having a non-fine wiring size.
(實施例1) (Example 1)
以下，說明本發明的實施例1。實施例1係對應上述的第1實施形態的製造方法(圖5)。 Hereinafter, the first embodiment of the present invention will be described. The first embodiment corresponds to the manufacturing method (Fig. 5) of the first embodiment described above.
首先，在低膨脹玻璃基板(厚度300μm，CTE：3.5ppm/K)上將帶有銅的支持體利用膠帶作固定。(參照圖5的(a))。其次，利用UV-YAG雷射形成開口徑70μm的貫通孔(參照圖5的(b))後，再進行雷射加工，將銅的密接層形成於貫通孔內(參照圖5的(c))。 First, a support with copper was fixed with a tape on a low-expansion glass substrate (thickness: 300 μm, CTE: 3.5 ppm/K). (Refer to (a) of Fig. 5). Next, a through hole having an opening diameter of 70 μm is formed by a UV-YAG laser (see FIG. 5( b )), and then laser processing is performed to form a copper adhesion layer in the through hole (see (c) of FIG. 5 . ).
其次，在玻璃基板表面進行Ti/Cu濺鍍，形成種層(參照圖5的(d))。 Next, Ti/Cu sputtering was performed on the surface of the glass substrate to form a seed layer (see (d) of Fig. 5).
其次，在所獲得之玻璃基板的兩面上層疊日立化成股份有限公司製乾膜阻劑RY-3525(厚度25μm)之後，利用光蝕刻形成開口部(參照圖5的(e))，藉由電解銅鍍敷對貫通電極和配線層進行鍍敷(參照圖5的(f))。 Next, a dry film resist RY-3525 (thickness: 25 μm) manufactured by Hitachi Chemical Co., Ltd. was laminated on both surfaces of the obtained glass substrate, and then an opening was formed by photolithography (see (e) of FIG. 5) by electrolysis. Copper plating is performed to plate the through electrode and the wiring layer (see (f) of FIG. 5 ).
其次，除去阻劑，藉由蝕刻除去種層的一部份(參照圖5的(g))，獲得使用了具有貫通電極和配線層之玻璃基板的中介層(參照圖5的(g))。 Next, the resist is removed, and a part of the seed layer is removed by etching (see (g) of FIG. 5) to obtain an interposer using a glass substrate having a through electrode and a wiring layer (refer to (g) of FIG. 5). .
(實施例2) (Example 2)
以下，說明本發明的實施例2。實施例2係對應上述的第3實施形態的製造方法(圖15)。 Hereinafter, a second embodiment of the present invention will be described. The second embodiment corresponds to the manufacturing method (Fig. 15) of the third embodiment described above.
首先，在低膨脹玻璃基板(厚度300μm、CTE：3.5ppm/K)上將形成有SiN(矽化氮)的支持體利用膠帶作固定(參照圖15的(a))。其次，利用UV-YAG雷射形成開口徑70μm的貫通孔(參照圖15的(b))後，再進行雷射加工 ，將SiN的密接層形成於貫通孔內(參照圖15的(c))。 First, a support on which a SiN (deuterium telluride) was formed was fixed on a low-expansion glass substrate (thickness: 300 μm, CTE: 3.5 ppm/K) by a tape (see (a) of FIG. 15). Next, a through hole having an opening diameter of 70 μm is formed by a UV-YAG laser (see (b) of FIG. 15), and then laser processing is performed. The adhesion layer of SiN is formed in the through hole (see (c) of FIG. 15).
其次，在從支持體將玻璃基板分離，於玻璃基板表面進行Ti/Cu濺鍍後，進行無電解鍍敷，在玻璃基板表面與貫通孔壁面形成種層(參照圖15的(d))。 Next, after separating the glass substrate from the support and performing Ti/Cu sputtering on the surface of the glass substrate, electroless plating is performed to form a seed layer on the surface of the glass substrate and the through-hole wall surface (see (d) of FIG. 15).
其次，在所獲得之玻璃基板的兩面上層疊日立化成股份有限公司製乾膜阻劑RY-3525(厚度25μm)之後，利用光蝕刻形成開口部(參照圖15的(e))，藉由電解銅鍍敷對貫通電極和配線層進行鍍敷(參照圖15的(f))。 Next, a dry film resist RY-3525 (thickness: 25 μm) manufactured by Hitachi Chemical Co., Ltd. was laminated on both surfaces of the obtained glass substrate, and then an opening was formed by photolithography (see (e) of Fig. 15) by electrolysis. The through electrode and the wiring layer are plated by copper plating (see (f) of FIG. 15).
其次，除去阻劑，藉由蝕刻除去種層的一部份(參照圖15的(g))，獲得使用了具有貫通電極和配線層之玻璃基板的中介層(參照圖15的(g))。 Next, the resist is removed, and a part of the seed layer is removed by etching (see (g) of FIG. 15) to obtain an interposer using a glass substrate having a through electrode and a wiring layer (refer to (g) of FIG. 15). .
本發明的中介層、半導體裝置及其等之製造方法係可利用於經由連接孔設有層間連接構造之半導體裝置或其一部份。 The interposer, the semiconductor device, and the like of the present invention can be utilized in a semiconductor device or a portion thereof having an interlayer connection structure via a connection hole.
Claims (9)
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| JP2015005993A JP2016134392A (en) | 2015-01-15 | 2015-01-15 | Interposer, semiconductor device, manufacturing methods of interposer and semiconductor device |
| JP2015116723A JP2017005081A (en) | 2015-06-09 | 2015-06-09 | Interposer, semiconductor device, and method of manufacturing them |
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| CN110730574A (en) * | 2018-07-17 | 2020-01-24 | 株式会社日立电力解决方案 | Double-sided circuit non-oxide ceramic substrate and method for producing same |
| TWI782100B (en) * | 2017-09-29 | 2022-11-01 | 日商大日本印刷股份有限公司 | Through-electrode substrate and semiconductor device using through-electrode substrate |
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| US11152294B2 (en) * | 2018-04-09 | 2021-10-19 | Corning Incorporated | Hermetic metallized via with improved reliability |
| JP2022521578A (en) | 2019-02-21 | 2022-04-11 | コーニング インコーポレイテッド | Glass or glass-ceramic articles with copper metallized through holes and their manufacturing methods |
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| JP2010087230A (en) * | 2008-09-30 | 2010-04-15 | Sanyo Electric Co Ltd | Element mounting substrate, semiconductor module, portable device, and method of manufacturing element mounting substrate |
| JP5904556B2 (en) * | 2010-03-03 | 2016-04-13 | ジョージア テック リサーチ コーポレイション | Through-package via (TPV) structure on inorganic interposer and manufacturing method thereof |
| JP5547566B2 (en) * | 2010-06-29 | 2014-07-16 | 株式会社アドバンテスト | Method for manufacturing through wiring board |
| JP5597853B2 (en) * | 2010-09-28 | 2014-10-01 | 国立大学法人 千葉大学 | Through-hole electrode forming method and electronic component |
| JP6201663B2 (en) * | 2013-11-13 | 2017-09-27 | 大日本印刷株式会社 | Penetration electrode substrate manufacturing method, penetration electrode substrate, and semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI782100B (en) * | 2017-09-29 | 2022-11-01 | 日商大日本印刷股份有限公司 | Through-electrode substrate and semiconductor device using through-electrode substrate |
| CN110730574A (en) * | 2018-07-17 | 2020-01-24 | 株式会社日立电力解决方案 | Double-sided circuit non-oxide ceramic substrate and method for producing same |
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