TW201637140A - Wiring substrate laminate and method for manufacturing semiconductor device using same - Google Patents
Wiring substrate laminate and method for manufacturing semiconductor device using same Download PDFInfo
- Publication number
- TW201637140A TW201637140A TW105101324A TW105101324A TW201637140A TW 201637140 A TW201637140 A TW 201637140A TW 105101324 A TW105101324 A TW 105101324A TW 105101324 A TW105101324 A TW 105101324A TW 201637140 A TW201637140 A TW 201637140A
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- wiring
- support
- copper foil
- semiconductor wafer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
本發明係關於一種配線基板積層體及使用其之半導體裝置的製造方法。 The present invention relates to a wiring substrate laminate and a method of manufacturing a semiconductor device using the same.
近幾年，使用半導體晶片及外部連接構件的半導體裝置被使用於電子機器及汽車等各式各樣的領域。下述專利文獻1中記載了一種於半導體晶片上直接形成具有再配線層及外部連接端子的外部連接構件之半導體裝置的製造方法。在此製造方法方面，係於半導體晶片區域內形成具有再配線層及外部連接端子的外部連接構件。利用該製造方法所設置的半導體裝置被稱為Fan-in型的WLP(Wafer Level Package：晶圓級封裝體)。 In recent years, semiconductor devices using semiconductor wafers and external connection members have been used in various fields such as electronic equipment and automobiles. Patent Document 1 listed below discloses a method of manufacturing a semiconductor device in which an external connection member having a rewiring layer and an external connection terminal is directly formed on a semiconductor wafer. In this manufacturing method, an external connection member having a rewiring layer and an external connection terminal is formed in a semiconductor wafer region. The semiconductor device provided by this manufacturing method is called a Fan-in type WLP (Wafer Level Package).
此外，下述專利文獻2中記載了一種形成覆蓋固定於支持基板上的半導體晶片周圍的絕緣層，於該半導體晶片上及該絕緣層上形成具有再配線層及外部連接端子的外部連接構件之半導體裝置的製造方法。在此製造方法方面，係於比半導體晶片外緣更外側的周邊區域上也形成具有再配線層及外部連接端子的外部連接構件。利用該製造方法所設置的半導體裝置被稱為Fan-out型的WLP。 Further, in Patent Document 2 described below, an insulating layer covering a periphery of a semiconductor wafer fixed on a support substrate is formed, and an external connection member having a rewiring layer and an external connection terminal is formed on the semiconductor wafer and the insulating layer. A method of manufacturing a semiconductor device. In this manufacturing method, an external connection member having a rewiring layer and an external connection terminal is also formed on a peripheral region outside the outer edge of the semiconductor wafer. The semiconductor device provided by this manufacturing method is called a Fan-out type WLP.
[專利文獻1]日本特開平11-111896號公報 [Patent Document 1] Japanese Patent Laid-Open No. Hei 11-111896
[專利文獻2]日本特開2011-187473號公報 [Patent Document 2] Japanese Patent Laid-Open Publication No. 2011-187473
[專利文獻3]日本特開2014-7315號公報 [Patent Document 3] Japanese Patent Laid-Open Publication No. 2014-7315
在上述專利文獻1所記載之製造方法方面，由於外部連接構件形成於半導體晶片區域內，所以外部連接端子的數量及位置受到限制。此外，在專利文獻1、2所記載之製造方法方面，由於在所單片化的半導體晶片上直接形成外部連接構件，所以半導體裝置的製造效率降低。 In the manufacturing method described in Patent Document 1, since the external connection member is formed in the semiconductor wafer region, the number and position of the external connection terminals are limited. Further, in the manufacturing methods described in Patent Documents 1 and 2, since the external connection member is directly formed on the singulated semiconductor wafer, the manufacturing efficiency of the semiconductor device is lowered.
本發明之目的在於提供一種使配線基板薄型化與半導體裝置製造效率化成為可能的配線基板積層體及使用其之半導體裝置的製造方法。 An object of the present invention is to provide a wiring board laminate which can reduce the thickness of a wiring board and the efficiency of manufacturing a semiconductor device, and a method of manufacturing a semiconductor device using the same.
關於本發明之配線基板積層體係用於製造內建半導體晶片的半導體裝置的配線基板積層體，具備：支持體；銅箔層，其可剝離地層積於支持體的至少一方的面上；及配線基板，其層積於銅箔層上。該配線基板包含：外部連接端子，其設於銅箔層上；一層或多層的配線層，其設於外部連接端子的上層；絕緣層，其設於外部連接端子與配線層的層間和多層配線層的層間；通 路孔，其用於電性連接外部連接端子與配線層的層間和多層配線層的層間；絕緣膜，其設於最上層的配線層上；及晶片連接端子，其藉由去除絕緣膜的一部分使最上層的配線層的一部分露出而形成，成為和半導體晶片的連接處。 The wiring board laminate of the present invention is a wiring board laminate for manufacturing a semiconductor device in which a semiconductor wafer is built, and includes: a support; a copper foil layer which is detachably laminated on at least one surface of the support; and wiring A substrate laminated on the copper foil layer. The wiring board includes: an external connection terminal provided on the copper foil layer; one or more wiring layers provided on an upper layer of the external connection terminal; and an insulating layer provided between the external connection terminal and the wiring layer and the multilayer wiring Interlayer a via hole for electrically connecting an interlayer of the external connection terminal and the wiring layer and a layer of the multilayer wiring layer; an insulating film provided on the uppermost wiring layer; and a wafer connection terminal by removing a part of the insulating film A part of the uppermost wiring layer is exposed and formed to form a connection with the semiconductor wafer.
此外，關於本發明之半導體裝置的製造方法係使用上述配線基板積層體之半導體裝置的製造方法，具備以下步驟：藉由將半導體晶片電性連接於形成於支持基板上的至少一方的面上的配線基板上的晶片連接端子，安裝半導體晶片之步驟；形成密封所安裝的半導體晶片的密封樹脂之步驟；藉由使銅箔層從支持體剝離，使密封樹脂、半導體晶片、配線基板及銅箔層一體地從支持體分離之步驟；藉由蝕刻去除形成於配線基板表面上的銅箔層，使外部連接端子露出之步驟；在露出的外部連接端子上形成銲料層之步驟；及藉由切斷密封樹脂及配線基板，使半導體裝置單片化之步驟。 Further, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device using the wiring board laminate, comprising the step of electrically connecting a semiconductor wafer to at least one surface formed on a support substrate. a step of mounting a semiconductor wafer on a wafer connection terminal on a wiring substrate; a step of forming a sealing resin for sealing the mounted semiconductor wafer; and a sealing resin, a semiconductor wafer, a wiring substrate, and a copper foil by peeling the copper foil layer from the support a step of integrally separating the layers from the support; a step of removing the copper foil layer formed on the surface of the wiring substrate by etching to expose the external connection terminals; a step of forming a solder layer on the exposed external connection terminals; and by cutting The step of breaking the sealing resin and the wiring substrate to singulate the semiconductor device.
藉由本發明，可提供一種使配線基板薄型化與半導體裝置製造效率化成為可能的配線基板積層體及使用其之半導體裝置的製造方法。 According to the present invention, it is possible to provide a wiring board laminate which can reduce the thickness of the wiring substrate and the semiconductor device manufacturing efficiency, and a method of manufacturing a semiconductor device using the same.
1‧‧‧半導體裝置 1‧‧‧Semiconductor device
10‧‧‧配線基板 10‧‧‧Wiring substrate
11‧‧‧半導體晶片 11‧‧‧Semiconductor wafer
12‧‧‧支持體 12‧‧‧Support
13‧‧‧底層充填材料 13‧‧‧Underfill material
14‧‧‧密封樹脂 14‧‧‧ Sealing resin
15‧‧‧外部連接端子 15‧‧‧External connection terminal
16‧‧‧凸起電極 16‧‧‧ bump electrode
17‧‧‧焊料層 17‧‧‧ solder layer
18‧‧‧焊球 18‧‧‧ solder balls
19‧‧‧切割帶 19‧‧‧Cutting Tape
20‧‧‧銅箔層 20‧‧‧ copper foil layer
21‧‧‧絕緣樹脂層 21‧‧‧Insulating resin layer
22‧‧‧配線層 22‧‧‧Wiring layer
23‧‧‧絕緣膜 23‧‧‧Insulation film
24‧‧‧和半導體晶片的連接端子 24‧‧‧Connecting terminal with semiconductor wafer
25‧‧‧通路孔 25‧‧‧ access hole
第1圖為說明使用關於實施形態之配線基板積層體所製造的半導體裝置的圖。 Fig. 1 is a view for explaining a semiconductor device manufactured using the wiring board laminate of the embodiment.
第2圖為說明關於實施形態之配線基板積層體的圖。 Fig. 2 is a view for explaining a wiring board laminate of the embodiment.
第3圖為說明放大第2圖(a)中的A部分之配線基板積層體的製造方法之一例的圖。 Fig. 3 is a view for explaining an example of a method of manufacturing the wiring board laminate of the portion A in Fig. 2(a).
第4圖為說明放大第2圖(a)中的A部分之配線基板積層體的製造方法之一例的圖。 Fig. 4 is a view for explaining an example of a method of manufacturing the wiring board laminate of the portion A in Fig. 2(a).
第5圖為說明半導體裝置的製造方法之一例的圖。 Fig. 5 is a view for explaining an example of a method of manufacturing a semiconductor device.
第6圖為說明半導體裝置的製造方法之變形例的圖。 Fig. 6 is a view for explaining a modification of the method of manufacturing the semiconductor device.
第7圖為說明半導體裝置的製造方法之變形例的圖。 Fig. 7 is a view for explaining a modification of the method of manufacturing the semiconductor device.
第8圖為說明接著從支持體剝離配線基板之後的半導體裝置的製造方法之一例的圖。 Fig. 8 is a view for explaining an example of a method of manufacturing a semiconductor device after the wiring substrate is subsequently peeled off from the support.
以下，參照附圖，就本發明的較佳實施形態詳細地進行說明。再者，在以下的說明中，對於相同要素或具有相同功能的要素，使用相同符號，省略重複的說明。 Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, the same elements or elements having the same functions are denoted by the same reference numerals, and the description thereof will not be repeated.
第1圖為說明使用關於本發明實施形態之配線基板所製造的半導體裝置的圖。如第1圖所示，半導體裝置1具備配線基板10、半導體晶片11、底層充填材料13、密封樹脂14、複數個外部連接端子15及複數個焊球18。再者，關於配線基板10的詳情，後述之。 Fig. 1 is a view for explaining a semiconductor device manufactured using a wiring board according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor device 1 includes a wiring board 10, a semiconductor wafer 11, a base filling material 13, a sealing resin 14, a plurality of external connection terminals 15, and a plurality of solder balls 18. In addition, the details of the wiring board 10 will be described later.
半導體晶片11為例如具有形成於半導體基板表面上的電晶體或二極體等的積體電路(IC或LSI)，具有大略長方體形狀。用於半導體晶片11的半導體基板使用例如矽基板(Si基板)、氮化鎵基板(GaN基板)或碳化矽基板(SiC基板)等以無機物為主要成分的基板。在本實施形態中，使用矽基板作為半導體基板。使用矽基板所形成 的半導體晶片11的線膨脹係數(CTE：Coefficient of Thermal Expansion)為約2~4ppm/℃(例如3ppm/℃)。本實施形態中的線膨脹係數設定為例如對應於20℃~260℃的溫度範圍內的溫度的上升而變化的長度。 The semiconductor wafer 11 is, for example, an integrated circuit (IC or LSI) having a transistor or a diode formed on the surface of the semiconductor substrate, and has a substantially rectangular parallelepiped shape. The semiconductor substrate used for the semiconductor wafer 11 is, for example, a substrate mainly composed of an inorganic material such as a tantalum substrate (Si substrate), a gallium nitride substrate (GaN substrate), or a tantalum carbide substrate (SiC substrate). In the present embodiment, a tantalum substrate is used as the semiconductor substrate. Formed using a germanium substrate The coefficient of thermal expansion (CTE: Coefficient of Thermal Expansion) of the semiconductor wafer 11 is about 2 to 4 ppm/° C. (for example, 3 ppm/° C.). The linear expansion coefficient in the present embodiment is set to, for example, a length that changes in accordance with an increase in temperature in a temperature range of 20 ° C to 260 ° C.
在半導體晶片11的和配線基板對向之面的表面上設有凸起電極16(也稱為凸塊)。半導體晶片11經由此凸起電極16而和形成於配線基板10主面上的連接端子電性連接。凸起電極16係由例如Au、Ag、Cu、Al等金屬或此等金屬的合金、對Cu施以鍍Au等的金屬複合體、或Sn、Sn-Pb、Sn-Ag、Sn-Cu、Sn-Ag-Cu、Sn-Bi或Au系等焊料所形成。凸起電極16可以配置於半導體晶片11的整個區域內，也可以配置於半導體晶片11的周邊區域上。就互相連接半導體晶片11與配線基板10的方式而言，可舉出例如引線接合方式或倒裝晶片方式。在本實施形態中，從安裝面積縮小化及作業效率化的觀點，利用倒裝晶片方式互相連接半導體晶片11與配線基板10。 A bump electrode 16 (also referred to as a bump) is provided on a surface of the semiconductor wafer 11 opposite to the wiring substrate. The semiconductor wafer 11 is electrically connected to a connection terminal formed on the main surface of the wiring substrate 10 via the bump electrode 16. The bump electrode 16 is made of, for example, a metal such as Au, Ag, Cu, or Al or an alloy of such a metal, a metal composite plated with Au or the like, or Sn, Sn-Pb, Sn-Ag, Sn-Cu, or the like. A solder such as Sn-Ag-Cu, Sn-Bi or Au is formed. The bump electrode 16 may be disposed in the entire region of the semiconductor wafer 11, or may be disposed on the peripheral region of the semiconductor wafer 11. The form in which the semiconductor wafer 11 and the wiring substrate 10 are connected to each other is, for example, a wire bonding method or a flip chip method. In the present embodiment, the semiconductor wafer 11 and the wiring substrate 10 are connected to each other by flip chip bonding from the viewpoints of reduction in mounting area and work efficiency.
底層充填材料13為將半導體晶片11固定及密封於配線基板10上所使用的接著劑。就底層充填材料13而言，可使用例如環氧樹脂、聚胺酯樹脂、矽氧樹脂、聚酯樹脂、環氧丙烷樹脂及馬來醯亞胺樹脂中的一種或混合此等樹脂兩種以上的樹脂中加進二氧化矽、氧化鈦、氧化鋁、氧化鎂或氧化鋅等作為充填物的材料。底層充填材料13可以是液狀，也可以是膜狀。 The underfill material 13 is an adhesive used to fix and seal the semiconductor wafer 11 on the wiring substrate 10. As the underlying filling material 13, one of, for example, an epoxy resin, a polyurethane resin, a silicone resin, a polyester resin, a propylene oxide resin, and a maleic imide resin, or a resin in which two or more of these resins are mixed may be used. A material such as cerium oxide, titanium oxide, aluminum oxide, magnesium oxide or zinc oxide is added as a filler. The underfill material 13 may be in the form of a liquid or a film.
密封樹脂14為覆蓋半導體晶片11進行密封及保護所使用的密封樹脂。就密封樹脂14而言，可使用例 如環氧樹脂、聚胺酯樹脂、矽氧樹脂、聚酯樹脂、環氧丙烷樹脂及馬來醯亞胺樹脂中的一種或混合此等樹脂兩種以上的樹脂中加進二氧化矽、氧化鈦、氧化鋁、氧化鎂或氧化鋅等作為充填物的材料。 The sealing resin 14 is a sealing resin used to cover and protect the semiconductor wafer 11. For the sealing resin 14, a usable example For example, one of epoxy resin, polyurethane resin, oxime resin, polyester resin, propylene oxide resin and maleic imide resin, or a mixture of two or more resins of these resins, adding cerium oxide, titanium oxide, A material such as alumina, magnesia or zinc oxide as a filler.
外部連接端子15設於配線基板10的背面(和裝載有半導體晶片11的主面相反側之面)上。外部連接端子15經由設於配線基板10內的配線層而和半導體晶片11電性連接。利用例如Sn、Sn-Pb、Sn-Ag、Sn-Cu、Sn-Ag-Cu或Sn-Bi等焊料形成於外部連接端子15上。外部連接端子15由焊料所形成的情況，在形成外部連接端子15之前，或者配線基板10的外部連接端子15表面露出時，可以施以例如鍍Ni、鍍Au、鍍Pd或鍍Sn，可以施以預焊處理，也可以施以OSP(Organic Solderability Preservative；有機可焊性保存)等有機覆膜處理。 The external connection terminal 15 is provided on the back surface of the wiring substrate 10 (the surface on the opposite side to the main surface on which the semiconductor wafer 11 is mounted). The external connection terminal 15 is electrically connected to the semiconductor wafer 11 via a wiring layer provided in the wiring substrate 10. Solder such as Sn, Sn-Pb, Sn-Ag, Sn-Cu, Sn-Ag-Cu, or Sn-Bi is formed on the external connection terminal 15. When the external connection terminal 15 is formed of solder, before the external connection terminal 15 is formed, or when the surface of the external connection terminal 15 of the wiring substrate 10 is exposed, for example, Ni plating, Au plating, Pd plating, or Sn plating may be applied. An organic film treatment such as OSP (Organic Solderability Preservative) may be applied by pre-welding treatment.
第2圖(a)為顯示關於實施形態之配線基板積層體一例的概略圖。關於本實施形態的配線基板10係經由可從支持體12剝離的銅箔20而形成於支持體12兩面的各面上。銅箔20的剝離面為和支持體12的對向面，當從支持體12剝離配線基板10之際，和配線基板10共同剝離銅箔層20。形成於支持體12兩面的可剝離的銅箔20上的配線基板10為表裡都是相同構造的基板。 Fig. 2(a) is a schematic view showing an example of a wiring board laminate of the embodiment. The wiring board 10 of the present embodiment is formed on each of both surfaces of the support 12 via the copper foil 20 which can be peeled off from the support 12 . The peeling surface of the copper foil 20 is the opposing surface of the support body 12, and when the wiring board 10 is peeled from the support body 12, the copper foil layer 20 is peeled together with the wiring board 10. The wiring substrate 10 formed on the peelable copper foil 20 on both sides of the support 12 is a substrate having the same structure in the front and back.
第2圖(b)為第2圖(a)中的A部分的放大圖，為說明本實施形態的配線基板積層體詳細構造的圖。如第2圖(b)所示，關於本發明的配線基板10形成於支持體12上所形成的銅箔層20上。配線基板10具有絕緣樹脂層21、 絕緣膜23、外部連接端子15、配線層22、和半導體晶片的連接端子24、焊料層17及電性連接多層配線層間的通路孔25。配線基板10的厚度為從第2圖的銅箔層20上到絕緣膜23上面的厚度。本發明的配線基板10的厚度，最好是0.001mm以上，不到0.001mm時，難以確保配線層22間的電路絕緣性。大於1mm時，就沒有形成於支持體12上可使配線基板10薄型化此一優點。因此，配線基板10的厚度最好是0.001mm以上1mm以下。 Fig. 2(b) is an enlarged view of a portion A in Fig. 2(a), and is a view for explaining a detailed structure of the wiring board laminate of the embodiment. As shown in FIG. 2(b), the wiring board 10 of the present invention is formed on the copper foil layer 20 formed on the support 12. The wiring substrate 10 has an insulating resin layer 21, The insulating film 23, the external connection terminal 15, the wiring layer 22, and the connection terminal 24 of the semiconductor wafer, the solder layer 17, and the via hole 25 electrically connected to the multilayer wiring layer. The thickness of the wiring substrate 10 is the thickness from the copper foil layer 20 of FIG. 2 to the upper surface of the insulating film 23. The thickness of the wiring board 10 of the present invention is preferably 0.001 mm or more, and when it is less than 0.001 mm, it is difficult to ensure circuit insulation between the wiring layers 22. When it is larger than 1 mm, there is no advantage that the wiring board 10 can be made thinner on the support body 12. Therefore, the thickness of the wiring board 10 is preferably 0.001 mm or more and 1 mm or less.
第2圖(a)及(b)記載的支持體12的20℃到260℃的平均熱膨脹係數為-1ppm/℃以上15ppm/℃以下。支持體12的熱膨脹係數設定為不到-1ppm/℃時，沒有可用作支持體12的材料的選項消失的現實性。支持體12的熱膨脹係數大於15ppm/℃時，與和半導體晶片的熱膨脹係數的差異變大，難以良率佳地安裝、製造半導體裝置。支持體12的熱膨脹係數更好為2ppm/℃以上10ppm/℃以下。藉由本發明的配線基板10，利用使支持體12的熱膨脹係數接近矽，可抑制位置偏移所造成的良率降低。 The support 12 of the second embodiment (a) and (b) has an average thermal expansion coefficient of from 20 ° C to 260 ° C of from -1 ppm / ° C to 15 ppm / ° C. When the thermal expansion coefficient of the support 12 is set to less than -1 ppm/° C., there is no practicality that the option of the material that can be used as the support 12 disappears. When the thermal expansion coefficient of the support 12 is more than 15 ppm/° C., the difference from the thermal expansion coefficient of the semiconductor wafer becomes large, and it is difficult to mount and manufacture the semiconductor device with good yield. The thermal expansion coefficient of the support 12 is more preferably 2 ppm/° C. or more and 10 ppm/° C. or less. According to the wiring board 10 of the present invention, by lowering the thermal expansion coefficient of the support 12 to 矽, it is possible to suppress a decrease in yield due to the positional deviation.
支持體12為玻璃基板、玻璃纖維強化樹脂基板或敷銅積層板在實際上可廉價取得，所以比較理想。例如，就玻璃基板而言，可使用例如石英玻璃、硼矽酸玻璃、無鹼玻璃、鈉玻璃或藍寶石玻璃等。玻璃纖維強化樹脂基板的樹脂一般可舉出環氧樹脂、雙馬來醯亞胺三嗪樹脂，並不受本發明限定。也可以是敷銅積層板，若是20℃到260℃之間的平均線熱膨脹係數為-1ppm/℃ 以上15ppm/℃以下即可。支持體12的厚度並不受特別限定，若是0.2mm以上3mm以下，則容易進行製程上的處理，所以比較理想。支持體12的厚度更好為0.4mm以上2mm以下。 It is preferable that the support 12 is a glass substrate, a glass fiber reinforced resin substrate, or a copper-clad laminate, which can be obtained at a low cost in practice. For example, as the glass substrate, for example, quartz glass, borosilicate glass, alkali-free glass, soda glass, sapphire glass, or the like can be used. The resin of the glass fiber reinforced resin substrate is generally exemplified by an epoxy resin or a bismaleimide triazine resin, and is not limited by the present invention. It can also be a copper-clad laminate, if the average linear thermal expansion coefficient between 20 ° C and 260 ° C is -1 ppm / ° C Above 15ppm/°C can be used. The thickness of the support 12 is not particularly limited, and if it is 0.2 mm or more and 3 mm or less, it is easy to carry out the processing on the process, which is preferable. The thickness of the support 12 is preferably 0.4 mm or more and 2 mm or less.
可從支持體12剝離的銅箔層20可由例如可在層間剝離地層積有兩層的銅箔的可剝離銅箔構成。層積形成於支持體12上的方法，可以在支持體兩面上配置半固化片，再在其上重疊配置可剝離銅箔，利用眞空加壓在支持體12上層積貼合可剝離銅箔。或者，也可以在支持體12上經由接著材料而貼合可剝離銅箔。接著劑可以由例如環氧樹脂、聚胺酯樹脂、矽氧樹脂、聚酯樹脂、環氧丙烷樹脂及馬來醯亞胺樹脂、丙烯酸樹脂中選擇。也可以使用此等樹脂的一種或混合此等樹脂兩種以上的樹脂作為接著劑。接著劑的厚度為例如20μm~100μm左右。關於接著劑的種類、厚度、塗布方法、貼合方法，並不受特別限定，可以採用眾所周知的方法。形成配線基板10之側的銅箔的厚度最好為5μm以上20μm以下。形成配線基板10之側的銅箔的厚度不到5μm時，有產生針孔或因蝕刻處理而在製程中從支持體剝離的可能性。另一方面，形成配線基板10之側的銅箔的厚度大於20μm時，其後難以蝕刻去除銅箔層20。 The copper foil layer 20 which can be peeled off from the support 12 can be composed of, for example, a peelable copper foil in which two layers of copper foil can be laminated between layers. In the method of laminating on the support 12, a prepreg can be disposed on both surfaces of the support, and a peelable copper foil can be placed on top of the support, and the peelable copper foil can be laminated on the support 12 by hollow pressing. Alternatively, the peelable copper foil may be bonded to the support 12 via a bonding material. The subsequent agent may be selected from, for example, an epoxy resin, a polyurethane resin, a silicone resin, a polyester resin, a propylene oxide resin, a maleimide resin, or an acrylic resin. It is also possible to use one of these resins or a resin in which two or more of these resins are mixed as an adhesive. The thickness of the subsequent agent is, for example, about 20 μm to 100 μm. The type, thickness, coating method, and bonding method of the adhesive are not particularly limited, and a well-known method can be employed. The thickness of the copper foil on the side on which the wiring substrate 10 is formed is preferably 5 μm or more and 20 μm or less. When the thickness of the copper foil on the side where the wiring substrate 10 is formed is less than 5 μm, pinholes may occur or may be peeled off from the support during the process by the etching treatment. On the other hand, when the thickness of the copper foil on the side on which the wiring substrate 10 is formed is more than 20 μm, it is difficult to etch and remove the copper foil layer 20 thereafter.
或者，可從支持體12剝離的銅箔層20也可以在支持體12上形成選自鎳、鈷、鈦、錫、鋅的金屬或其化合物層作為剝離層後，藉由層積銅而形成。支持體12上的剝離層可以利用由例如濺鍍法、蒸鍍法、CVD法、 無電解鍍敷法所選的方法形成作為上述金屬的皮膜。若支持體12為敷銅積層板，則利用電鍍法也可以形成上述金屬層。也可以將上述金屬層形成複數種多層。再者，上述金屬的化合物層的形成方法，也可以利用加熱氧化形成氧化膜層。再者，也可以藉由進行鉻酸處理而形成鉻酸鹽皮膜。形成上述剝離層後形成銅箔層20，可以得到可從支持體剝離的銅箔層20。銅箔層20可由例如濺鍍法、蒸鍍法、CVD法、無電解鍍敷法、電鍍法形成。更好是利用電鍍法形成，為簡便，比較理想。設於剝離層上的銅箔層20的厚度最好為5μm以上20μm以下。設於剝離層上的銅箔層20的厚度不到5μm時，有產生針孔或因蝕刻處理而在製程中從支持體剝離的可能性。設於剝離層上的銅箔層20的厚度大於20μm時，其後難以蝕刻去除銅箔層。 Alternatively, the copper foil layer 20 which can be peeled off from the support 12 may be formed by forming a metal selected from nickel, cobalt, titanium, tin, zinc or a compound layer thereof as a release layer on the support 12, and then laminating copper. . The release layer on the support 12 can be utilized, for example, by sputtering, evaporation, CVD, The method selected by the electroless plating method forms a film as the above metal. If the support 12 is a copper-clad laminate, the above-mentioned metal layer can also be formed by electroplating. It is also possible to form the above metal layer into a plurality of layers. Further, in the method of forming the compound layer of the above metal, an oxide film layer may be formed by heating and oxidation. Further, a chromate film may be formed by performing chromic acid treatment. After the above-mentioned release layer is formed, the copper foil layer 20 is formed, and the copper foil layer 20 which can be peeled from the support can be obtained. The copper foil layer 20 can be formed, for example, by a sputtering method, a vapor deposition method, a CVD method, an electroless plating method, or a plating method. It is better to form by electroplating, which is ideal for simplicity. The thickness of the copper foil layer 20 provided on the peeling layer is preferably 5 μm or more and 20 μm or less. When the thickness of the copper foil layer 20 provided on the peeling layer is less than 5 μm, pinholes may occur or may be peeled off from the support during the process due to the etching treatment. When the thickness of the copper foil layer 20 provided on the peeling layer is more than 20 μm, it is difficult to etch and remove the copper foil layer thereafter.
在銅箔層20上形成有外部連接端子15。面臨銅箔層20的外部連接端子15在後續的步驟中和銅箔層20共同從支持體12被剝離，再藉由蝕刻去除銅箔層20，露出於配線基板10的背面上。再者，由於在後續的步驟中形成焊接凸塊，所以在外部連接端子15的表面上最好預先形成由Ni、Au、Pd、Sn構成的金屬皮膜。因此，最好在外部連接端子形成處的表面上利用上述金屬進行表面處理後，形成外部連接端子15。外部連接端子15是銅，為簡便，比較理想。此情況，外部連接端子15的銅層的厚度為例如1μm以上20μm以下。 An external connection terminal 15 is formed on the copper foil layer 20. The external connection terminal 15 facing the copper foil layer 20 is peeled off from the support 12 together with the copper foil layer 20 in the subsequent step, and the copper foil layer 20 is removed by etching to be exposed on the back surface of the wiring substrate 10. Further, since the solder bumps are formed in the subsequent steps, it is preferable to form a metal film made of Ni, Au, Pd, and Sn on the surface of the external connection terminal 15 in advance. Therefore, it is preferable to form the external connection terminal 15 after surface treatment with the above metal on the surface on which the external connection terminal is formed. The external connection terminal 15 is copper, which is preferable for convenience. In this case, the thickness of the copper layer of the external connection terminal 15 is, for example, 1 μm or more and 20 μm or less.
絕緣樹脂層21為設於銅箔層20上及配線層22 間的絕緣樹脂層。絕緣樹脂層21係由環氧樹脂、聚醯亞胺樹脂、雙馬來醯亞胺三嗪樹脂、氰酸鹽樹脂、聚苯醚、液晶聚合物或矽氧樹脂等樹脂材料、或者含有此等樹脂材料的組合樹脂、半固化片、或者聚醯亞胺樹脂、此等之複合材料所形成。此外，絕緣樹脂層21中也可以含有二氧化矽、氧化鋁、碳酸鋇等無機充填物或有機充填物。或者，絕緣樹脂層21也可以是玻璃纖維強化材料。絕緣樹脂層21的厚度為例如0.5μm以上40μm以下。 The insulating resin layer 21 is provided on the copper foil layer 20 and the wiring layer 22 An insulating resin layer between. The insulating resin layer 21 is made of a resin material such as an epoxy resin, a polyimide resin, a bismaleimide triazine resin, a cyanate resin, a polyphenylene ether, a liquid crystal polymer or a silicone resin, or the like. A composite resin of a resin material, a prepreg, or a polyimide resin, or a composite material of these. Further, the insulating resin layer 21 may contain an inorganic filler such as cerium oxide, aluminum oxide or cerium carbonate or an organic filler. Alternatively, the insulating resin layer 21 may be a glass fiber reinforced material. The thickness of the insulating resin layer 21 is, for example, 0.5 μm or more and 40 μm or less.
通路孔(通孔)25電性連接外部連接端子15與配線層22，並且電性連接配線層22彼此。通路孔直徑並不受特別限定，最好為5μm以上100μm以下。通路孔直徑不到5μm時，會擔心通孔連接可靠性降低。另一方面，通路孔直徑大於100μm時，會不利於細微的電路形成。通孔由導電體形成即可，但更好是和配線相同的金屬，為簡便，較佳。更好是通孔以銅形成。通孔內部為充填構造，所謂的充填通孔構造，可通孔堆疊，有利於細微電路形成，所以比較理想，但也可以是未將導電體金屬充填到通孔內部的保形(conformal)通孔。如以上，可以是具有經由通路孔25而形成多層配線層22的多層配線的配線基板，也可以是單層電路。 The via hole (via) 25 electrically connects the external connection terminal 15 and the wiring layer 22, and electrically connects the wiring layers 22 to each other. The diameter of the via hole is not particularly limited, but is preferably 5 μm or more and 100 μm or less. When the diameter of the via hole is less than 5 μm, there is a concern that the reliability of the via connection is lowered. On the other hand, when the via hole diameter is larger than 100 μm, it is disadvantageous for the formation of a fine circuit. The through hole may be formed of a conductor, but is preferably a metal having the same wiring as that of the wiring, which is simple and preferable. More preferably, the through holes are formed of copper. The inside of the through hole is a filling structure, the so-called filling through hole structure, and the through hole stacking is advantageous for the formation of a fine circuit, so it is preferable, but it may also be a conformal pass in which the conductive metal is not filled into the inside of the through hole. hole. As described above, the wiring board having the multilayer wiring in which the multilayer wiring layer 22 is formed via the via hole 25 may be used, or may be a single layer circuit.
在配線基板10的最表層上形成阻焊劑或由絕緣樹脂層構成的絕緣膜23，成為只露出形成有和半導體晶片的連接端子24部分的構造。連接端子24設置成容易和半導體晶片11的凸起電極16電性連接。在連接端子24上，利用例如共晶焊料或無鉛焊料(Sn-Ag、Sn-Cu、 Sn-Ag-Cu或Sn-Bi等)形成焊料層17。連接端子24也可以是在由各種金屬構成的導電層上設有共晶焊料或無鉛焊料的端子。此外，也可以對開口部施以Ni、Au、Pd、Sn等電鍍處理或施以OSP等有機覆膜處理，形成連接端子24。此外，連接端子24也可以藉由對配線層22進行鍍金而形成。此情況，連接端子24的導電性提高，並可抑制連接端子24的腐蝕。半導體晶片11的凸起電極16為金球形凸塊(例如Au、含Au的合金、或對表面施以鍍Au的金屬複合體的金凸塊、或由Au系的焊料所形成的凸塊)時，該凸起電極16與施以鍍金的連接端子的接合性提高。 A solder resist or an insulating film 23 made of an insulating resin layer is formed on the outermost layer of the wiring substrate 10, and only a portion in which the connection terminal 24 of the semiconductor wafer is formed is exposed. The connection terminal 24 is disposed to be electrically connected to the bump electrode 16 of the semiconductor wafer 11. On the connection terminal 24, for example, eutectic solder or lead-free solder (Sn-Ag, Sn-Cu, The solder layer 17 is formed by Sn-Ag-Cu or Sn-Bi or the like. The connection terminal 24 may be a terminal provided with a eutectic solder or a lead-free solder on a conductive layer made of various metals. Further, the opening portion may be subjected to a plating treatment such as Ni, Au, Pd, or Sn or an organic coating treatment such as OSP to form the connection terminal 24. Further, the connection terminal 24 may be formed by gold plating the wiring layer 22. In this case, the conductivity of the connection terminal 24 is improved, and corrosion of the connection terminal 24 can be suppressed. The bump electrode 16 of the semiconductor wafer 11 is a gold spherical bump (for example, Au, an alloy containing Au, or a gold bump of a metal composite plated with Au on the surface, or a bump formed of an Au-based solder) At the same time, the adhesion between the bump electrode 16 and the gold-plated connection terminal is improved.
其次，一面參照第3圖及第4圖，一面說明關於本實施形態之配線基板積層體的製造方法。第3圖及第4圖為說明關於本實施形態之配線基板積層體的製造方法一例的圖，為放大圖示第2圖(a)的A部分的圖。再者，雖然第3圖及第4圖為部分圖示關於本實施形態之配線基板的圖，但本發明之配線基板及半導體裝置並不受第3圖及第4圖所限定。 Next, a method of manufacturing the wiring board laminate according to the present embodiment will be described with reference to FIGS. 3 and 4. 3 and 4 are views for explaining an example of a method of manufacturing the wiring board laminate of the embodiment, and are enlarged views of a portion A of Fig. 2(a). In addition, in the drawings, the wiring board and the semiconductor device of the present invention are not limited to the third and fourth drawings.
首先，如第3圖(a)所示，在支持體12的表面上形成可剝離的銅箔層20。就銅箔層20的形成方法而言，可舉出將先前所述的可剝離銅箔經由半固化片而貼在支持體12上的方法、或以接著劑貼在支持體12上的方法。接著劑的塗布方法可採用例如印刷法、真空加壓法、真空層壓法、輥層壓法、旋塗法、模塗法、幕塗法、輥塗法、眾所周知的方法。 First, as shown in Fig. 3(a), a peelable copper foil layer 20 is formed on the surface of the support 12. The method for forming the copper foil layer 20 may be a method of attaching the peelable copper foil described above to the support 12 via a prepreg or a method of attaching the adhesive to the support 12 with an adhesive. The coating method of the subsequent agent can be, for example, a printing method, a vacuum press method, a vacuum lamination method, a roll lamination method, a spin coating method, a die coating method, a curtain coating method, a roll coating method, or a well-known method.
此外，也可以在支持體12上預先形成選自鎳 、鈷、鈦、錫、鋅的金屬或其化合物的層作為剝離層後，藉由層積銅而形成銅箔層20。就在基板上形成由上述金屬構成的剝離層的方法而言，可利用選自例如濺鍍法、蒸鍍法、CVD法、無電解鍍敷法所選的方法。若支持體為敷銅積層板，則利用電解鍍敷法也可以形成上述的金屬層。上述的金屬層也可以以複數種的金屬層形成為多層。再者，上述金屬的化合物層的形成方法，也可以利用加熱氧化形成氧化膜層。再者，也可以藉由進行鉻酸處理而形成鉻酸鹽皮膜。形成上述剝離層後層積銅，可得到可從支持體剝離的銅箔層20。銅箔層20的形成可由濺鍍法、蒸鍍法、CVD法、無電解鍍敷法、電解鍍敷法形成。更好是利用電解鍍敷法形成，為簡便，比較理想。 In addition, it is also possible to pre-form a support selected from nickel on the support 12. After the layer of the metal of cobalt, titanium, tin, or zinc or a compound thereof is used as a release layer, the copper foil layer 20 is formed by laminating copper. In the method of forming the release layer made of the above metal on the substrate, a method selected from, for example, a sputtering method, a vapor deposition method, a CVD method, or an electroless plating method can be used. If the support is a copper-clad laminate, the above-described metal layer can also be formed by electrolytic plating. The above metal layer may be formed in a plurality of layers by a plurality of metal layers. Further, in the method of forming the compound layer of the above metal, an oxide film layer may be formed by heating and oxidation. Further, a chromate film may be formed by performing chromic acid treatment. After the formation of the above-mentioned release layer, copper is laminated to obtain a copper foil layer 20 which can be peeled off from the support. The formation of the copper foil layer 20 can be formed by a sputtering method, a vapor deposition method, a CVD method, an electroless plating method, or an electrolytic plating method. It is better to form by electrolytic plating, which is ideal for simplicity.
其次，如第3圖(b)所示，在支持體上形成可剝離的銅箔層20後，將外部連接端子15形成於銅箔層20上。外部連接端子15的形成方法，利用眾所周知的半加工法形成，為簡便，比較理想。說明其中一例，例如在銅箔層20上形成阻劑層。阻劑可以是正型或負型的液體阻劑，也可以是乾膜阻劑，乾膜阻劑為簡便又廉價，比較理想。形成阻劑層後，使用描繪有對應於所希望的外部連接端子的圖案的光罩進行曝光，形成阻劑圖案。也可以對銅箔層露出的部分的外部連接端子15預先進行鍍Ni、鍍Au、鍍Pd或鍍Sn作為表面處理。形成方法最好為無電解鍍敷或電解鍍敷。表面處理後進行電鍍銅，可形成外部連接端子15。藉由剝離不要的阻劑圖案，得到形 成有第3圖(b)記載的外部連接端子15的基板。 Next, as shown in FIG. 3(b), after the peelable copper foil layer 20 is formed on the support, the external connection terminal 15 is formed on the copper foil layer 20. The method of forming the external connection terminal 15 is formed by a well-known semi-machining method, and is preferably simple. One example is described, for example, a resist layer is formed on the copper foil layer 20. The resist may be a positive or negative liquid resist or a dry film resist. The dry film resist is simple and inexpensive, and is ideal. After the resist layer is formed, exposure is performed using a photomask which is drawn with a pattern corresponding to a desired external connection terminal to form a resist pattern. The external connection terminal 15 of the exposed portion of the copper foil layer may be previously subjected to Ni plating, Au plating, Pd plating, or Sn plating as a surface treatment. The formation method is preferably electroless plating or electrolytic plating. After the surface treatment, copper plating is performed to form the external connection terminal 15. Get shape by stripping the unwanted resist pattern The substrate of the external connection terminal 15 described in FIG. 3(b) is formed.
其次，如第3圖(c)記載，在外部連接端子15上形成絕緣樹脂層21。絕緣樹脂層21為環氧樹脂、聚醯亞胺樹脂、雙馬來醯亞胺三嗪樹脂、氰酸鹽樹脂、聚苯醚、液晶聚合物或矽氧樹脂等樹脂材料、或者含有此等樹脂材料的組合樹脂、半固化片、或者聚醯亞胺樹脂。或者，絕緣樹脂層21也可以含有此等複合材料。此外，絕緣樹脂層21也可以含有二氧化矽、氧化鋁、碳酸鋇等無機充填物或有機充填物。或者，絕緣樹脂層21也可以是玻璃纖維強化材料。絕緣樹脂層21的厚度為例如0.5μm以上40μm以下。絕緣樹脂層21以例如印刷法、真空加壓法、真空層壓法、輥層壓法、旋塗法、模塗法、幕塗法、輥塗法或光蝕刻法等眾所周知的方法形成。通路孔25係藉由例如對絕緣樹脂層21進行雷射加工或光蝕刻，去除絕緣樹脂層21的一部分而形成。 Next, as described in FIG. 3(c), the insulating resin layer 21 is formed on the external connection terminal 15. The insulating resin layer 21 is a resin material such as an epoxy resin, a polyimide resin, a bismaleimide triazine resin, a cyanate resin, a polyphenylene ether, a liquid crystal polymer or a silicone resin, or contains such a resin. A combination of materials, prepregs, or polyimide resins. Alternatively, the insulating resin layer 21 may also contain such composite materials. Further, the insulating resin layer 21 may contain an inorganic filler such as cerium oxide, aluminum oxide or cerium carbonate or an organic filler. Alternatively, the insulating resin layer 21 may be a glass fiber reinforced material. The thickness of the insulating resin layer 21 is, for example, 0.5 μm or more and 40 μm or less. The insulating resin layer 21 is formed by a well-known method such as a printing method, a vacuum press method, a vacuum lamination method, a roll lamination method, a spin coating method, a die coating method, a curtain coating method, a roll coating method, or a photolithography method. The via hole 25 is formed by, for example, performing laser processing or photolithography on the insulating resin layer 21 to remove a part of the insulating resin layer 21.
其次，如第3圖(d)所示，在絕緣樹脂層21上形成配線層22。電路形成於絕緣樹脂上最好利用減去法及半加法形成。更好是由於半加法有利於形成細微電路，所以更理想。茲說明半加法的電路形成，在形成有通路孔25的絕緣樹脂層21上形成薄的金屬層(種子層)。此時，也可以在形成種子層之前，藉由將樹脂表面進行過錳酸處理、或者UV去污、氬電漿或氧電漿處理，進行粗化或清理，藉此以進行將種子層與樹脂層的密合性提高。種子層可列舉如鎳、鈦、銅、銀、錫、金等，銅為簡便，比較理想。種子層的形成方法，可舉出濺鍍法、CVD 法、蒸鍍法、離子鍍法、無電解鍍敷法，濺鍍法或無電解鍍敷法為簡便且較可行。在絕緣樹脂層21上及通路孔25的表面上形成種子層後，在種子層上形成阻劑圖案。阻劑可以是液體的正型阻劑或負型阻劑，也可以是乾膜阻劑，乾膜阻劑為簡便又廉價，比較理想。藉由對形成於種子層上的阻劑層使用描繪有所希望的配線圖案的光罩進行曝光顯影處理，得到電路部分露出的阻劑圖案。接著，藉由以種子層為供電層而進行電解鍍銅處理，形成配線層22。形成配線層後剝離處理不要的阻劑層，藉由蝕刻去除不要部分的種子層，得到配線層22。如此一來，得到形成有配線層22的配線基板。 Next, as shown in FIG. 3(d), the wiring layer 22 is formed on the insulating resin layer 21. The circuit is formed on the insulating resin and is preferably formed by subtractive and semi-additive methods. More preferably, it is more desirable because the half addition is advantageous for forming a fine circuit. The circuit formation of the half addition is explained, and a thin metal layer (seed layer) is formed on the insulating resin layer 21 on which the via holes 25 are formed. At this time, before the seed layer is formed, the resin layer may be subjected to permanganic treatment, or UV decontamination, argon plasma or oxygen plasma treatment to be roughened or cleaned, thereby performing seed layer formation. The adhesion of the resin layer is improved. The seed layer may, for example, be nickel, titanium, copper, silver, tin, gold or the like, and copper is convenient and preferable. The formation method of the seed layer may be a sputtering method or a CVD method. The method, the vapor deposition method, the ion plating method, the electroless plating method, the sputtering method or the electroless plating method are simple and feasible. After the seed layer is formed on the insulating resin layer 21 and on the surface of the via hole 25, a resist pattern is formed on the seed layer. The resist can be a liquid positive resist or a negative resist, or a dry film resist. The dry film resist is simple and inexpensive, and is ideal. The resist pattern which is exposed to the circuit portion is obtained by performing exposure and development processing on the resist layer formed on the seed layer using a mask which depicts a desired wiring pattern. Next, the wiring layer 22 is formed by performing electrolytic copper plating treatment using the seed layer as a power supply layer. After forming the wiring layer, the resist layer which is not subjected to the peeling treatment is removed, and the seed layer of the unnecessary portion is removed by etching to obtain the wiring layer 22. In this way, the wiring substrate on which the wiring layer 22 is formed is obtained.
形成多層配線層時，藉由反覆第3圖(c)及第3圖(d)的步驟，可得到第4圖(e)所示的多層配線基板。配線的層數不受本發明限定。 When the multilayer wiring layer is formed, the multilayer wiring board shown in Fig. 4(e) can be obtained by repeating the steps of Figs. 3(c) and 3(d). The number of layers of wiring is not limited by the present invention.
接著，如第4圖(f)所示，在多層配線層的最外層上形成和半導體晶片的連接端子。和半導體晶片的連接端子24可以在最外層的配線層22上形成絕緣膜23後，藉由設置開口部而設置連接端子24，也可以形成和絕緣樹脂層21相同的材料後，藉由設置開口而形成連接端子24，連接端子24的製造方法不受特別限定，可採用眾所周知的方法。更好是最好設置阻焊層作為絕緣膜23。絕緣膜23以例如印刷法、真空加壓法、真空層壓法、輥層壓法、旋塗法、模塗法、幕塗法、輥塗法或光蝕刻法等眾所周知的方法形成。開口部係藉由進行雷射的照射或光蝕刻，去除絕緣膜23的一部分而形成。在連接端子 24的表面上也可以進行鍍Ni、鍍Au、鍍Pd或鍍Sn作為表面處理。連接端子24也可以進一步藉由將共晶焊料或無鉛焊料供應給開口部而設置。藉由以上，形成含有支持體12、可剝離的銅箔層20、絕緣樹脂層21、外部連接端子15、配線層22、和半導體晶片的連接端子24的配線基板10。 Next, as shown in Fig. 4 (f), a connection terminal to the semiconductor wafer is formed on the outermost layer of the multilayer wiring layer. The connection terminal 24 of the semiconductor wafer may be formed with the insulating film 23 on the outermost wiring layer 22, and the connection terminal 24 may be provided by providing the opening portion. Alternatively, the same material as the insulating resin layer 21 may be formed, and the opening may be provided. The method of manufacturing the connection terminal 24 and the connection terminal 24 is not particularly limited, and a well-known method can be employed. More preferably, it is preferable to provide a solder resist layer as the insulating film 23. The insulating film 23 is formed by a well-known method such as a printing method, a vacuum press method, a vacuum lamination method, a roll lamination method, a spin coating method, a die coating method, a curtain coating method, a roll coating method, or a photolithography method. The opening portion is formed by removing a part of the insulating film 23 by laser irradiation or photo etching. At the connection terminal Ni plating, Au plating, Pd plating, or Sn plating may also be performed on the surface of 24 as a surface treatment. The connection terminal 24 can also be further provided by supplying eutectic solder or lead-free solder to the opening. As described above, the wiring substrate 10 including the support 12, the peelable copper foil layer 20, the insulating resin layer 21, the external connection terminals 15, the wiring layer 22, and the connection terminals 24 of the semiconductor wafer is formed.
再者，配線基板10可以只形成於支持體12的一方面上，也可以形成於的兩面上。在支持體12的兩面上形成配線基板10時，可以支持體12的各單面進行第3圖及第4圖所示的各步驟，也可以在支持體12的兩面上同時進行。 Further, the wiring substrate 10 may be formed only on one side of the support 12 or on both sides. When the wiring board 10 is formed on both surfaces of the support 12, the respective steps shown in FIGS. 3 and 4 may be performed on each of the single faces of the support 12, or may be simultaneously performed on both surfaces of the support 12.
其次，一面參照第5圖，一面說明使用關於本實施形態之配線基板積層體製造半導體裝置的方法。第5圖為說明半導體裝置的製造方法一例的圖。 Next, a method of manufacturing a semiconductor device using the wiring board laminate of the present embodiment will be described with reference to Fig. 5. Fig. 5 is a view for explaining an example of a method of manufacturing a semiconductor device.
首先，如第5圖(a)所示，準備在支持體12上層積有可剝離的銅箔層20與配線基板10的配線基板積層體。可剝離的銅箔層20及配線基板10形成於支持體12的兩面上。配線基板10和第1圖、第2圖、第4圖(f)所示者相同。 First, as shown in Fig. 5(a), a wiring substrate laminate in which the peelable copper foil layer 20 and the wiring substrate 10 are laminated on the support 12 is prepared. The peelable copper foil layer 20 and the wiring substrate 10 are formed on both surfaces of the support 12 . The wiring board 10 is the same as that shown in FIG. 1, FIG. 2, and FIG. 4(f).
其次，如第5圖(b)所示，在配線基板10上裝載複數個半導體晶片11。具體而言，在配線基板10上以倒裝晶片方式裝載半導體晶片11。將半導體晶片11裝載於配線基板10上時，互相連接半導體晶片11的凸起電極16與配線基板10的連接端子24(參照第2圖、第4圖)。此外，藉由在半導體晶片11及配線基板10之間預先設置底 層充填材料13，固定及密封半導體晶片11及配線基板10。底層充填材料13可以在將半導體晶片11裝載於配線基板10上後，供應於半導體晶片11及配線基板10之間。此外，可以使底層充填材料13預先附著於半導體晶片11或配線基板10上，和將半導體晶片裝載於配線基板上同時使底層充填材料13的密封完成。藉由例如對底層充填材料13施以加熱或照射光的硬化處理，進行底層充填材料13的固定及密封半導體晶片11及配線基板10。底層充填材料13亦可為非必要設置。 Next, as shown in FIG. 5(b), a plurality of semiconductor wafers 11 are mounted on the wiring substrate 10. Specifically, the semiconductor wafer 11 is flip-chip mounted on the wiring substrate 10. When the semiconductor wafer 11 is mounted on the wiring substrate 10, the bump electrodes 16 of the semiconductor wafer 11 and the connection terminals 24 of the wiring substrate 10 are connected to each other (see FIGS. 2 and 4). Further, a bottom is provided in advance between the semiconductor wafer 11 and the wiring substrate 10 The layer filling material 13 fixes and seals the semiconductor wafer 11 and the wiring substrate 10. The underfill material 13 can be supplied between the semiconductor wafer 11 and the wiring substrate 10 after the semiconductor wafer 11 is mounted on the wiring substrate 10. Further, the underfill material 13 may be previously attached to the semiconductor wafer 11 or the wiring substrate 10, and the semiconductor wafer may be mounted on the wiring substrate while the sealing of the underfill material 13 is completed. The underfill material 13 is fixed and sealed to the semiconductor wafer 11 and the wiring substrate 10 by, for example, a hardening treatment for heating or irradiating the underlying filling material 13. The underfill material 13 may also be an optional arrangement.
其次，如第5圖(c)所示，在配線基板10的主面上形成密封樹脂14。此時，利用密封樹脂14埋設半導體晶片11。密封樹脂14以例如轉注成型法或灌注法等眾所周知的方法形成。 Next, as shown in FIG. 5(c), the sealing resin 14 is formed on the main surface of the wiring board 10. At this time, the semiconductor wafer 11 is buried by the sealing resin 14. The sealing resin 14 is formed by a well-known method such as a transfer molding method or a potting method.
其次，如第5圖(d)所示，從支持體12剝離形成於支持體12兩面的裝載有半導體晶片11且形成有密封樹脂14的半導體裝置。從配線基板10剝離支持體12的方法可以手動，也可以使用機械進行。再者，可以兩面同時剝離，也可以單面一個個剝離。 Next, as shown in FIG. 5(d), the semiconductor device in which the semiconductor wafer 11 is formed on both surfaces of the support 12 and the sealing resin 14 is formed is peeled off from the support 12. The method of peeling off the support 12 from the wiring substrate 10 may be performed manually or by using a machine. Furthermore, it is possible to peel off both sides at the same time, or to peel off one by one.
第6圖及第7圖為第5圖所示的半導體裝置的製造方法的變形例，為說明對設於支持體12兩面的配線基板10一面一面地裝載半導體晶片11之例的圖。 6 and 7 are views showing a modification of the method of manufacturing the semiconductor device shown in FIG. 5, and an example in which the semiconductor wafer 11 is mounted on one surface of the wiring substrate 10 provided on both surfaces of the support 12 is described.
首先，如第6圖(a)所示，準備在支持體12上層積有可剝離的銅箔層20與配線基板10的基板。可剝離的銅箔層20及配線基板10形成於支持體12的兩面上。配線基板10和第1圖、第2圖、第4圖(f)所示者相同。 First, as shown in Fig. 6(a), a substrate on which the peelable copper foil layer 20 and the wiring substrate 10 are laminated on the support 12 is prepared. The peelable copper foil layer 20 and the wiring substrate 10 are formed on both surfaces of the support 12 . The wiring board 10 is the same as that shown in FIG. 1, FIG. 2, and FIG. 4(f).
其次，如第6圖(b)所示，在支持體12一方面的配線基板上裝載半導體晶片11。半導體晶片11的裝載方法可以採用以第5圖(b)說明者。 Next, as shown in FIG. 6(b), the semiconductor wafer 11 is mounted on the wiring substrate on the one hand side of the support 12. The method of loading the semiconductor wafer 11 can be as described in FIG. 5(b).
其次，如第6圖(c)所示，在裝載有半導體晶片11的配線基板10上形成密封樹脂14，埋設半導體晶片11。密封樹脂的形成方法可以採用以第5圖(c)說明者。 Next, as shown in FIG. 6(c), a sealing resin 14 is formed on the wiring substrate 10 on which the semiconductor wafer 11 is mounted, and the semiconductor wafer 11 is buried. The method of forming the sealing resin can be as described in Fig. 5(c).
其次，如第7圖(d)所示，從支持體只剝離裝載有半導體晶片11並形成有密封樹脂14的配線基板10。支持體12的剝離方法可以採用以第5圖(d)說明者。 Next, as shown in FIG. 7(d), only the wiring substrate 10 on which the semiconductor wafer 11 is mounted and the sealing resin 14 is formed is peeled off from the support. The peeling method of the support 12 can be as described in Fig. 5(d).
其後，如第7圖(e)~(g)所示，在另一方的配線基板10上裝載半導體晶片11，形成密封樹脂14後，從支持體12剝離配線基板10。再者，第7圖(e)~(g)的步驟和第6圖(b)~第7圖(d)同樣地進行。 Then, as shown in FIGS. 7(e) to 7(g), the semiconductor wafer 11 is placed on the other wiring substrate 10, and after the sealing resin 14 is formed, the wiring substrate 10 is peeled off from the support 12. Further, the steps of (e) to (g) of Fig. 7 are performed in the same manner as in Figs. 6(b) to 7(d).
第8圖為說明關於本實施形態之半導體裝置的製造方法一例的圖，為顯示接著在第5圖(d)、第7圖(d)及第7圖(g)從支持體12剝離配線基板10後的步驟的圖。 FIG. 8 is a view for explaining an example of a method of manufacturing the semiconductor device of the embodiment, and showing that the wiring substrate is peeled off from the support 12 in the fifth (d), seventh (d), and seventh (g) portions. Figure of the steps after 10th.
如第8圖(a)所示，在從支持體12剝離配線基板10的狀態，以覆蓋設於配線基板10背面的外部連接端子15的方式形成有銅箔層20。 As shown in FIG. 8( a ), the copper foil layer 20 is formed so as to cover the external connection terminals 15 provided on the back surface of the wiring substrate 10 in a state in which the wiring substrate 10 is peeled off from the support 12 .
其次，如第8圖(b)所示，去除銅箔層20，使外部連接端子15露出。銅箔層20的去除可使用銅的蝕刻液進行。銅的蝕刻液可選自硫酸與過氧化氫的混合水溶液、過硫酸鹽類(鈉、鉀、銨鹽)的水溶液、氯化鐵液、氯化銅液、氯化銅與氨混合蝕刻液、氨-過氧化氫混合水溶液、硝酸。由於蝕刻量的控制容易，所以最好使用硫 酸與過氧化氫的混合水溶液、過硫酸鹽水溶液。在剝離後的銅箔層20上有異種金屬或有機物的附著等時，可以預先進行去除此等附著的處理之後再進行銅箔層20的蝕刻處理。 Next, as shown in Fig. 8(b), the copper foil layer 20 is removed to expose the external connection terminals 15. The removal of the copper foil layer 20 can be carried out using an etching solution of copper. The etching solution of copper may be selected from a mixed aqueous solution of sulfuric acid and hydrogen peroxide, an aqueous solution of persulfate (sodium, potassium, ammonium salt), a ferric chloride liquid, a copper chloride liquid, a mixed etching solution of copper chloride and ammonia, Ammonia-hydrogen peroxide mixed aqueous solution, nitric acid. Since the control of the amount of etching is easy, it is preferable to use sulfur. A mixed aqueous solution of an acid and hydrogen peroxide, and an aqueous solution of persulfate. When the dissimilar metal or the organic substance adheres to the copper foil layer 20 after peeling, the process of removing these adhesion may be performed previously, and the etching process of the copper foil layer 20 may be performed.
其次，如第8圖(c)所示，在外部連接端子15上裝載焊球18。焊球的形成方法可以是焊膏的網版印刷法、球裝載工法任一眾所周知的方法。 Next, as shown in Fig. 8(c), the solder balls 18 are mounted on the external connection terminals 15. The method of forming the solder balls may be any of the well-known methods of the screen printing method of the solder paste and the ball loading method.
其次，如第8圖(d)所示，在密封樹脂14上貼附切割帶19後，切斷位於各半導體晶片11間的區域的配線基板10及密封樹脂14，進行單片化。配線基板10及密封樹脂14的切斷可使用例如切割鋸或雷射等進行。 Then, as shown in FIG. 8(d), after the dicing tape 19 is attached to the sealing resin 14, the wiring board 10 and the sealing resin 14 in the region between the semiconductor wafers 11 are cut and singulated. The cutting of the wiring board 10 and the sealing resin 14 can be performed using, for example, a dicing saw or a laser.
藉由經過以上的步驟，如第8圖(e)所示，可製造使用配線基板積層體所形成的半導體裝置1。 By the above steps, as shown in Fig. 8(e), the semiconductor device 1 formed using the wiring substrate laminate can be manufactured.
以上說明的關於本實施形態之配線基板10起作用作為將半導體晶片11連接於外部裝置用的外部連接構件。由於可各別地製造半導體晶片11與成為外部連接構件的配線基板10，所以沒有外部連接端子的數量或配置的限制，並可改善半導體裝置1的製造效率。此外，配線基板10形成於支持體12上所形成的可剝離去除的銅箔層20上。因此，在接合半導體晶片11與配線基板10後，可容易剝離支持體12，使用該配線基板10所製造的半導體裝置1的薄型化成為可能。再者，藉由使用具有支持體12的配線基板10製造半導體裝置1，即使是配線基板10為幾十μm左右的極薄型基板，也可以容易進行處理。因此，不僅可改善基板製造時的良率，而且可改善半導體 晶片11安裝組合時的良率。 The wiring board 10 of the present embodiment described above functions as an external connection member for connecting the semiconductor wafer 11 to an external device. Since the semiconductor wafer 11 and the wiring substrate 10 serving as the external connection member can be separately manufactured, there is no limitation in the number or arrangement of the external connection terminals, and the manufacturing efficiency of the semiconductor device 1 can be improved. Further, the wiring substrate 10 is formed on the peelable copper foil layer 20 formed on the support 12. Therefore, after the semiconductor wafer 11 and the wiring substrate 10 are bonded, the support 12 can be easily peeled off, and the thickness of the semiconductor device 1 manufactured using the wiring substrate 10 can be reduced. In addition, by manufacturing the semiconductor device 1 using the wiring substrate 10 having the support 12, even if the wiring substrate 10 is an extremely thin substrate of several tens of μm or so, the processing can be easily performed. Therefore, not only can the yield of the substrate be improved, but also the semiconductor can be improved. The yield of the wafer 11 when the combination is mounted.
此外，也可以在支持體12的表背兩面上製作相同構造的配線基板10，並且可以抑制絕緣樹脂層21的硬化收縮、或起因於配線層22的面積比率、層積於支持體12上的異種材料的熱膨脹係數差的翹曲產生。因此，可以抑制起因於配線基板10翹曲的良率降低。 In addition, the wiring board 10 having the same structure can be formed on both the front and back sides of the support 12, and the curing shrinkage of the insulating resin layer 21 or the area ratio of the wiring layer 22 can be suppressed and laminated on the support 12. The warpage of the difference in thermal expansion coefficient of the dissimilar material is generated. Therefore, it is possible to suppress a decrease in yield due to warpage of the wiring substrate 10.
此外，支持體12的線膨脹係數為-1ppm/℃以上15ppm/℃以下。由於半導體晶片11係由矽基板等以無機物為主要成分的基板所製造，所以半導體晶片11的線膨脹係數與支持體12的線膨脹係數成為互相接近的值。因此，可抑制在配線基板10上裝載半導體晶片11時產生的位置偏移。因此，可抑制半導體晶片11不能裝載於配線基板10上的情事及接合半導體晶片11與配線基板10的部分破壞的情事。 Further, the linear expansion coefficient of the support 12 is -1 ppm / ° C or more and 15 ppm / ° C or less. Since the semiconductor wafer 11 is manufactured from a substrate containing an inorganic material as a main component such as a tantalum substrate, the linear expansion coefficient of the semiconductor wafer 11 and the linear expansion coefficient of the support 12 are close to each other. Therefore, positional displacement occurring when the semiconductor wafer 11 is mounted on the wiring substrate 10 can be suppressed. Therefore, it is possible to suppress the fact that the semiconductor wafer 11 cannot be mounted on the wiring substrate 10 and the partial destruction of the semiconductor wafer 11 and the wiring substrate 10.
此外，支持體12可以是玻璃基板、玻璃纖維強化樹脂基板或敷銅積層板，可使支持體12廉價又提高強度，並且支持體12容易大型化。 Further, the support 12 may be a glass substrate, a glass fiber reinforced resin substrate, or a copper-clad laminate, which makes it possible to inexpensively increase the strength of the support 12, and to easily increase the size of the support 12.
此外，配線基板10的厚度為0.001mm以上1mm以下。此情況，可確保配線基板10的配線圖案的絕緣性，並可享有因本發明的配線基板薄型化而使半導體裝置薄型化的優點。 Further, the thickness of the wiring substrate 10 is 0.001 mm or more and 1 mm or less. In this case, the insulation of the wiring pattern of the wiring substrate 10 can be ensured, and the advantage of reducing the thickness of the wiring device of the present invention and making the semiconductor device thin can be enjoyed.
此外，使用關於本實施形態之配線基板10所製造的半導體裝置1具備配線基板10、及在表面上經由焊料層17而連接於配線基板10的配線層22的半導體晶片11。在此半導體裝置1方面，由於可各別地製造半導體晶片 11與外部連接構件的配線基板10，所以可改善半導體裝置1的製造效率。此外，藉由將配線基板10在支持體12上形成後從支持體12剝離，可使配線基板10薄型化，此結果，半導體裝置1的薄型化成為可能。 In addition, the semiconductor device 1 manufactured by the wiring board 10 of the present embodiment includes the wiring board 10 and the semiconductor wafer 11 which is connected to the wiring layer 22 of the wiring board 10 via the solder layer 17 on the surface. In this semiconductor device 1, since semiconductor wafers can be separately manufactured Since the wiring board 10 is connected to the external member, the manufacturing efficiency of the semiconductor device 1 can be improved. In addition, the wiring board 10 is formed on the support 12 and then peeled off from the support 12, whereby the wiring board 10 can be made thinner, and as a result, the thickness of the semiconductor device 1 can be reduced.
本發明之配線基板、半導體裝置及半導體裝置的製造方法並不限於上述的實施形態，可以是其他各式各樣的變形。也可以例如適當組合上述實施形態及變形例。此外，層積於配線基板10的半導體晶片11也可以裝載複數片於單片化的配線基板10的區域上。此外，在配線基板10上也可以裝載半導體晶片11以外的構件(例如電容器等被動元件)。 The wiring board, the semiconductor device, and the method of manufacturing the semiconductor device of the present invention are not limited to the above-described embodiments, and various other modifications are possible. The above embodiments and modifications may be combined as appropriate, for example. Further, the semiconductor wafer 11 laminated on the wiring substrate 10 may be mounted on a plurality of regions of the singulated wiring substrate 10. Further, a member other than the semiconductor wafer 11 (for example, a passive element such as a capacitor) may be mounted on the wiring substrate 10.
此外，配線基板10的配線層22不限於半加法，可用例如減去法或全加法等眾所周知的方法形成。此處所謂減去法，係在Cu層等導體層上形成具有所希望的圖案的阻劑，蝕刻不要的導體層後，剝離阻劑而得到配線圖案的方法。此外，全加法係使樹脂層上吸附無電解鍍敷觸媒，將所希望的圖案的阻劑形成於樹脂層上，在保留此阻劑作為絕緣膜的狀態下使觸媒活化，利用無電解鍍敷法使阻劑開口部內析出Cu等導體後，去除阻劑而得到所希望的配線圖案的方法。 Further, the wiring layer 22 of the wiring substrate 10 is not limited to the half addition, and can be formed by a well-known method such as subtraction or full addition. Here, the subtraction method is a method of forming a resist pattern having a desired pattern on a conductor layer such as a Cu layer, etching a unnecessary conductor layer, and then removing the resist to obtain a wiring pattern. Further, the total addition method causes an electroless plating catalyst to be adsorbed on the resin layer, a resist of a desired pattern is formed on the resin layer, and the catalyst is activated while leaving the resist as an insulating film, and electroless is utilized. In the plating method, a conductor such as Cu is deposited in the opening of the resist, and then the resist is removed to obtain a desired wiring pattern.
茲將本發明利用以下的實施例進一步詳細地進行說明。 The invention will be further illustrated in detail by the following examples.
(配線基板) (wiring substrate)
配線基板10按照第3圖及第4圖所示的步驟製作。 The wiring board 10 is produced in accordance with the procedures shown in FIGS. 3 and 4.
首先，如第3圖(a)所示，在支持體12的兩面上配置15μm厚的半固化片及可剝離銅箔後進行真空加壓，在支持體12的兩面上形成可剝離的銅箔層20。作為銅箔層20，使用形成配線基板10之側的銅箔厚為5μm、和支持體12經由半固化片而連接之側的銅箔厚為18μm的銅箔層。作為支持體12，使用下述的支持體： First, as shown in Fig. 3(a), a prepreg and a peelable copper foil having a thickness of 15 μm are placed on both surfaces of the support 12, and then vacuum-pressed, and a peelable copper foil layer 20 is formed on both surfaces of the support 12. . As the copper foil layer 20, a copper foil having a copper foil having a thickness of 5 μm on the side on which the wiring substrate 10 was formed and a copper foil having a thickness of 18 μm on the side where the support 12 was connected via the prepreg was used. As the support 12, the following support is used:
．實施例1：玻璃(OA-10G(日本電氣玻璃股份有限公司製))、1.1mm厚、線膨脹係數4ppm/℃ . Example 1: Glass (OA-10G (manufactured by Nippon Electric Glass Co., Ltd.)), 1.1 mm thick, linear expansion coefficient 4 ppm/°C
．實施例2：玻璃纖維強化環氧樹脂、1.0mm厚、線膨脹係數7ppm/℃ . Example 2: Glass fiber reinforced epoxy resin, 1.0 mm thick, linear expansion coefficient 7 ppm / ° C
．實施例3：敷銅兩面板、1.0mm厚、線膨脹係數8ppm/℃ . Example 3: Two copper-clad panels, 1.0 mm thick, linear expansion coefficient 8 ppm/°C
其次，如第3圖(b)所示，在可剝離的銅箔層20上形成外部連接端子15。外部連接端子15的形成方法使用半加法進行。具體而言，在形成於支持體12上兩面的可剝離的銅箔層20上，將厚度25μm的乾膜阻劑利用層壓法形成於兩面。其次，使用描繪有對應於外部連接端子的圖案的光罩一面進行表背對準一面進行曝光處理，以1%碳酸鈉水溶液進行噴霧顯影處理。接著，將可剝離的銅箔層作為供電層，形成電解鍍Ni1μm、電解鍍金0.05μm、電解鍍Ni3μm、電解鍍銅15μm，形成外部連接端子15。外部連接端子形成後，將乾膜阻劑以60℃、3%的氫氧化鈉溶液進行噴霧剝離處理，得到形成有外部連接端子15的基板。 Next, as shown in Fig. 3(b), the external connection terminal 15 is formed on the peelable copper foil layer 20. The method of forming the external connection terminal 15 is performed using a half addition method. Specifically, on the peelable copper foil layer 20 formed on both surfaces of the support 12, a dry film resist having a thickness of 25 μm was formed on both surfaces by a lamination method. Next, exposure treatment was performed while performing back-to-back alignment using a mask on which a pattern corresponding to the external connection terminal was drawn, and spray development treatment was performed with a 1% sodium carbonate aqueous solution. Next, the peelable copper foil layer was used as a power supply layer, and electrolytic plating Ni1 μm, electrolytic gold plating 0.05 μm, electrolytic plating Ni 3 μm, and electrolytic copper plating 15 μm were formed to form the external connection terminal 15. After the external connection terminals were formed, the dry film resist was spray-released at 60 ° C and a 3% sodium hydroxide solution to obtain a substrate on which the external connection terminals 15 were formed.
其次，如第3圖(c)所示，形成絕緣樹脂層21 及通路孔25。具體而言，將外部連接端子15及可剝離的銅箔層20上的銅層進行粗化處理，進行和形成於上層的絕緣樹脂層21的密合提高處理後，真空層壓形成ABF-GX-T31(Ajinomoto Fine-Techno Co.,Inc.製)。層壓後，將樹脂固化之後，藉由照射二氧化碳雷射，設置通路孔25。雷射加工後，浸漬於鹼性過錳酸溶液中，將通路孔中的污跡及樹脂表面進行粗化處理。 Next, as shown in Fig. 3(c), the insulating resin layer 21 is formed. And via hole 25. Specifically, the external connection terminal 15 and the copper layer on the peelable copper foil layer 20 are subjected to a roughening treatment, and after the adhesion improving treatment with the insulating resin layer 21 formed on the upper layer is performed, vacuum lamination is performed to form ABF-GX. -T31 (manufactured by Ajinomoto Fine-Techno Co., Inc.). After lamination, after curing the resin, the via hole 25 is provided by irradiating a carbon dioxide laser. After laser processing, it is immersed in an alkaline permanganic acid solution to roughen the stains in the via holes and the surface of the resin.
其次，如第3圖(d)所示，形成配線層22。具體而言，進行無電鍍銅處理，在形成有通路孔25的絕緣樹脂層21表面上以0.7μm厚度形成無電解鍍敷層。接著，將厚度25μm的乾膜阻劑層壓於無電解鍍敷層上，使用描繪有配線電路的光罩進行對準曝光，形成阻劑圖案。接著，將無電解鍍敷層作為供電層，進行電解鍍敷處理。再藉由將乾膜阻劑進行噴霧剝離處理去除，藉由將不要的無電解鍍銅層以硫酸-過氧化氫水溶液蝕刻去除，得到在支持體12上形成有配線層22的基板。 Next, as shown in Fig. 3(d), the wiring layer 22 is formed. Specifically, an electroless copper plating treatment was performed to form an electroless plating layer on the surface of the insulating resin layer 21 on which the via holes 25 were formed with a thickness of 0.7 μm. Next, a dry film resist having a thickness of 25 μm was laminated on the electroless plating layer, and alignment exposure was performed using a photomask on which a wiring circuit was drawn to form a resist pattern. Next, the electroless plating layer is used as a power supply layer, and electrolytic plating treatment is performed. Further, the dry film resist is removed by a spray stripping treatment, and the unnecessary electroless copper plating layer is removed by etching with a sulfuric acid-hydrogen peroxide aqueous solution to obtain a substrate on which the wiring layer 22 is formed on the support 12.
再經過和第3圖(c)及(d)相同的步驟，如第4圖(e)所示，將絕緣樹脂層21及配線層22形成另外一層。 Further, as in the fourth step (c) and (d), as shown in Fig. 4(e), the insulating resin layer 21 and the wiring layer 22 are formed in another layer.
其次，如第4圖(f)所示，在形成有多層配線層的配線基板10上以20μm厚度形成絕緣膜23。將對應於半導體晶片的連接端子的部分使用描繪有阻焊劑圖案的光罩進行曝光，開口形成和半導體晶片的連接端子24。接著，藉由浸漬於鹼性過錳酸溶液中，將連接端子24表面進行清理後，進行鍍Ni-Pd-Au。接著，藉由以球裝載工法形成焊料層17，得到關於實施例1~3的配線基板10。 Next, as shown in FIG. 4(f), the insulating film 23 is formed on the wiring substrate 10 on which the multilayer wiring layer is formed with a thickness of 20 μm. A portion corresponding to the connection terminal of the semiconductor wafer is exposed using a photomask on which a solder resist pattern is drawn, and the opening is formed with a connection terminal 24 of the semiconductor wafer. Next, the surface of the connection terminal 24 is cleaned by immersing in an alkaline permanganic acid solution, and then Ni-Pd-Au is plated. Next, the wiring layer 10 of Examples 1 to 3 was obtained by forming the solder layer 17 by a ball loading method.
(半導體裝置) (semiconductor device)
半導體裝置1按照第5圖及第8圖所示的步驟製作。 The semiconductor device 1 is fabricated in accordance with the steps shown in Figs. 5 and 8.
首先，如第5圖(a)及(b)所示，在關於實施例1~3的配線基板10上裝載半導體晶片11。關於半導體晶片11，使用具有在Cu柱的前端形成有Sn-3.5Ag焊料層的凸起電極16的晶片。此外，半導體晶片11的線膨脹係數為約3ppm/℃。預先供應底層充填材料13給配線基板10。進行半導體晶片11的凸起電極16與配線基板10的連接端子24的對位後，使半導體晶片11壓接於配線基板10，進行加熱。 First, as shown in Fig. 5 (a) and (b), the semiconductor wafer 11 is mounted on the wiring substrate 10 of the first to third embodiments. Regarding the semiconductor wafer 11, a wafer having the bump electrode 16 in which the Sn-3.5Ag solder layer is formed at the front end of the Cu pillar is used. Further, the linear expansion coefficient of the semiconductor wafer 11 is about 3 ppm/°C. The underlying filling material 13 is supplied to the wiring substrate 10 in advance. After the bump electrode 16 of the semiconductor wafer 11 is aligned with the connection terminal 24 of the wiring substrate 10, the semiconductor wafer 11 is pressure-bonded to the wiring substrate 10 to be heated.
其次，如第5圖(c)所示，將包含半導體晶片11的配線基板10的上面利用轉注成型法，使用密封樹脂14進行密封。 Next, as shown in FIG. 5(c), the upper surface of the wiring substrate 10 including the semiconductor wafer 11 is sealed by a transfer molding method using a sealing resin 14.
其次，如第5圖(d)所示，從支持體剝離、分離具有經由銅箔層20而形成於支持體12上的配線基板10的半導體裝置。 Next, as shown in FIG. 5(d), the semiconductor device having the wiring substrate 10 formed on the support 12 via the copper foil layer 20 is peeled off and separated from the support.
其次，如第8圖(a)及(b)所示，藉由將銅箔層20以硫酸-過氧化氫水溶液進行噴霧蝕刻處理，溶解去除銅箔層20與外部連接端子15的鎳皮膜。在此狀態，外部連接端子15表面在為鍍Ni-Au所表面處理的狀態。 Next, as shown in Fig. 8 (a) and (b), the copper foil layer 20 is spray-etched with a sulfuric acid-hydrogen peroxide aqueous solution to dissolve and remove the nickel film of the copper foil layer 20 and the external connection terminal 15. In this state, the surface of the external connection terminal 15 is in a state of being surface-treated with Ni-Au plating.
其次，如第8圖(c)所示，在外部連接端子15上裝載Sn-3Ag-0.5Cu焊料，形成焊球18。 Next, as shown in Fig. 8(c), Sn-3Ag-0.5Cu solder is placed on the external connection terminal 15 to form solder balls 18.
其次，如第8圖(d)所示，在此構造體上貼附切割帶19，藉由切割，得到第8圖(e)(第1圖)所示的半導體裝置1。 Next, as shown in Fig. 8(d), the dicing tape 19 is attached to the structure, and the semiconductor device 1 shown in Fig. 8(e) (Fig. 1) is obtained by dicing.
(X光透視裝置的觀察) (Observation of X-ray equipment)
將如上述所製成的實施例1~3的半導體裝置1以X光透視裝置(Uni-Hite System Corporation製、XVA-160α)進行觀察。觀察半導體裝置1的結果，在半導體晶片11的凸起電極16與配線基板10的連接端子24之間產生了離設計值約2μm的位置偏移。此處，作為半導體裝置1的配線基板10的支持體12，使用線膨脹係數為25ppm/℃的玻璃纖維強化環氧樹脂基板及線膨脹係數為20ppm/℃的敷銅兩面板時，在半導體晶片11的凸起電極與配線基板10的連接端子24之間，通常會產生離設計值約15μm的位置偏移。由此種支持體12的材質而產生的位置偏移的不同被認為是因為支持體12的線膨脹係數大於約15ppm/℃，和半導體晶片11的線膨脹係數(約2~4ppm/℃)大不相同。對此，在實施例1~3的配線基板10方面，藉由以支持體的線膨脹係數為4~8ppm/℃，可確認在半導體晶片11與配線基板10之間產生的位置偏移變小了。 The semiconductor device 1 of Examples 1 to 3 produced as described above was observed by an X-ray fluoroscopy device (manufactured by Uni-Hite System Corporation, XVA-160α). As a result of observing the semiconductor device 1, a positional deviation of about 2 μm from the design value was generated between the bump electrode 16 of the semiconductor wafer 11 and the connection terminal 24 of the wiring substrate 10. Here, as the support 12 of the wiring substrate 10 of the semiconductor device 1, when a glass fiber reinforced epoxy resin substrate having a linear expansion coefficient of 25 ppm/° C. and a copper-clad two-layer panel having a linear expansion coefficient of 20 ppm/° C. are used, the semiconductor wafer is used. Between the bump electrode of 11 and the connection terminal 24 of the wiring substrate 10, a positional deviation of about 15 μm from the design value is usually generated. The difference in positional displacement caused by the material of the support 12 is considered to be because the linear expansion coefficient of the support 12 is greater than about 15 ppm/° C., and the linear expansion coefficient (about 2 to 4 ppm/° C.) of the semiconductor wafer 11 is large. Not the same. On the other hand, in the wiring board 10 of the first to third embodiments, the linear expansion coefficient of the support is 4 to 8 ppm/° C., and it is confirmed that the positional shift between the semiconductor wafer 11 and the wiring substrate 10 is small. It is.
藉由本發明之配線基板、半導體裝置及製造該半導體裝置的方法，可提供半導體裝置製造效率的改善及該半導體裝置的薄型化、或改善半導體裝置的薄型化及製造效率。 According to the wiring board, the semiconductor device, and the method of manufacturing the semiconductor device of the present invention, it is possible to improve the manufacturing efficiency of the semiconductor device, to reduce the thickness of the semiconductor device, and to improve the thickness and the manufacturing efficiency of the semiconductor device.
10‧‧‧配線基板 10‧‧‧Wiring substrate
12‧‧‧支持體 12‧‧‧Support
15‧‧‧外部連接端子 15‧‧‧External connection terminal
17‧‧‧焊料層 17‧‧‧ solder layer
20‧‧‧銅箔層 20‧‧‧ copper foil layer
21‧‧‧絕緣樹脂層 21‧‧‧Insulating resin layer
22‧‧‧配線層 22‧‧‧Wiring layer
23‧‧‧絕緣膜 23‧‧‧Insulation film
24‧‧‧和半導體晶片的連接端子 24‧‧‧Connecting terminal with semiconductor wafer
25‧‧‧通路孔 25‧‧‧ access hole
Claims (8)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015008097A JP2016134497A (en) | 2015-01-19 | 2015-01-19 | Wiring board laminate and semiconductor device manufacturing method using the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW201637140A true TW201637140A (en) | 2016-10-16 |
Family
ID=56416550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW105101324A TW201637140A (en) | 2015-01-19 | 2016-01-18 | Wiring substrate laminate and method for manufacturing semiconductor device using same |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2016134497A (en) |
| TW (1) | TW201637140A (en) |
| WO (1) | WO2016116980A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109346432A (en) * | 2018-11-16 | 2019-02-15 | 深圳市和美精艺科技有限公司 | A kind of packaging method and its structure of superthin PCB substrate |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101952864B1 (en) | 2016-09-30 | 2019-02-27 | 삼성전기주식회사 | Fan-out semiconductor package |
| JP6880661B2 (en) * | 2016-11-04 | 2021-06-02 | 昭和電工マテリアルズ株式会社 | A temporary fixing material for a semiconductor and a method for manufacturing a semiconductor device using the temporary fixing material. |
| JP7083600B2 (en) * | 2017-05-25 | 2022-06-13 | 凸版印刷株式会社 | Glass circuit board with built-in capacitor and its manufacturing method |
| JP6816046B2 (en) * | 2018-02-06 | 2021-01-20 | アオイ電子株式会社 | Manufacturing method of semiconductor devices |
| US20230420270A1 (en) * | 2020-11-11 | 2023-12-28 | Mitsui Mining & Smelting Co., Ltd. | Method for producing wiring board |
| JPWO2023286711A1 (en) * | 2021-07-13 | 2023-01-19 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5526746B2 (en) * | 2009-12-04 | 2014-06-18 | 凸版印刷株式会社 | Multilayer substrate manufacturing method and supporting substrate |
| JP5042297B2 (en) * | 2009-12-10 | 2012-10-03 | 日東電工株式会社 | Manufacturing method of semiconductor device |
| JP5972137B2 (en) * | 2012-10-05 | 2016-08-17 | 新光電気工業株式会社 | Wiring board manufacturing method |
| US20150366077A1 (en) * | 2013-01-30 | 2015-12-17 | Kyocera Corporation | Method for producing mounted structure |
-
2015
- 2015-01-19 JP JP2015008097A patent/JP2016134497A/en active Pending
- 2015-12-04 WO PCT/JP2015/006048 patent/WO2016116980A1/en active Application Filing
-
2016
- 2016-01-18 TW TW105101324A patent/TW201637140A/en unknown
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109346432A (en) * | 2018-11-16 | 2019-02-15 | 深圳市和美精艺科技有限公司 | A kind of packaging method and its structure of superthin PCB substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2016116980A1 (en) | 2016-07-28 |
| JP2016134497A (en) | 2016-07-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW201637140A (en) | Wiring substrate laminate and method for manufacturing semiconductor device using same | |
| US9735099B2 (en) | Wiring substrate, semiconductor device and method for manufacturing semiconductor device | |
| JP5540276B2 (en) | Electronic component built-in substrate and manufacturing method thereof | |
| JPWO2017150284A1 (en) | Copper foil with carrier, coreless support with wiring layer, and method for producing printed wiring board | |
| US20160035661A1 (en) | Support member, wiring substrate, method for manufacturing wiring substrate, and method for manufacturing semiconductor package | |
| US20120138337A1 (en) | Printed circuit board and method of manufacturing the same | |
| JP6455197B2 (en) | Wiring substrate, semiconductor device, and manufacturing method of semiconductor device | |
| JP2008311592A (en) | Method of manufacturing electronic device | |
| JP2009158912A (en) | Package substrate and method of manufacturing the same | |
| JP2017050464A (en) | Wiring board laminate, manufacturing method therefor, and manufacturing method for semiconductor device | |
| JP2003218273A (en) | Semiconductor chip-mounting circuit board and its manufacturing method, and semiconductor module | |
| JP4601158B2 (en) | Multilayer printed wiring board and manufacturing method thereof | |
| JP4376891B2 (en) | Semiconductor module | |
| JP2003234432A (en) | Semiconductor chip mounting circuit board and multilayered circuit board | |
| JP5861400B2 (en) | Semiconductor mounting materials | |
| KR101197514B1 (en) | Circuit board, semiconductor package and method for fabricating the same | |
| JP2002083926A (en) | Circuit board for semiconductor chip mounting and its manufacturing method as well as multilayered circuit board | |
| JP2018204066A (en) | Electrode formation method, and electrode structure of semiconductor element | |
| JP4376890B2 (en) | Circuit board for mounting semiconductor chips | |
| JP2003234431A (en) | Semiconductor chip mounting circuit board, its manufacturing method and multilayered circuit board | |
| JP2017168639A (en) | Wiring board and manufacturing method of semiconductor device using the same | |
| KR101422524B1 (en) | PCB having fine pitch connection and method of manufacturing the same | |
| KR101416042B1 (en) | PCB and method of manufacturing the same | |
| JP6776686B2 (en) | Wiring board, wiring board, manufacturing method of semiconductor device | |
| JP6447075B2 (en) | Wiring substrate, semiconductor device, and manufacturing method of semiconductor device |