TW201538415A - 半導體封裝，半導體裝置及其形成方法 - Google Patents

半導體封裝，半導體裝置及其形成方法 Download PDF

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TW201538415A
TW201538415A TW103146013A TW103146013A TW201538415A TW 201538415 A TW201538415 A TW 201538415A TW 103146013 A TW103146013 A TW 103146013A TW 103146013 A TW103146013 A TW 103146013A TW 201538415 A TW201538415 A TW 201538415A
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wafer
package
semiconductor package
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TWI618671B (zh
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余振華
劉重希
黃致凡
蔡再宗
林威宏
鄭明達
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台灣積體電路製造股份有限公司
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Abstract

根據一例示的實施例，是提供一半導體封裝。此半導體封裝是包含：至少一個晶片；以及至少一個構件，其相鄰於上述至少一晶片；其中上述至少一個晶片與上述至少一個構件是被模封於一相同的模封體。

Description

半導體封裝，半導體裝置及其形成方法
本發明總體而言是關於半導體，特別是關於半導體封裝及其形成方法。
被動元件及晶片是散佈在印刷電路板上，並藉由此印刷電路板的走線而電性連接。這樣的連接會導致大面積及厚度相關的成本支出。因此，有需求來減少這樣的成本支出。
第1圖是一剖面圖，顯示根據一例示的實施例之一例示的半導體封裝。
第2圖是一剖面圖，顯示根據一例示的實施例之一例示的半導體封裝。
第3圖是一剖面圖，顯示根據一例示的實施例之一例示的半導體封裝。
第4圖是一剖面圖，顯示根據一例示的實施例之一例示的半導體封裝。
第5圖是一剖面圖，顯示根據一例示的實施例之一例示的半導體封裝。
第6圖是一剖面圖，顯示根據一例示的實施例之一例示的 半導體封裝。
第7圖是一剖面圖，顯示根據一例示的實施例之一例示的半導體裝置。
第8圖是另一剖面圖，顯示根據一例示的實施例之一例示的半導體裝置。
第9圖是另一剖面圖，顯示根據一例示的實施例之一例示的半導體裝置。
第10圖是一方塊圖，顯示在顯微鏡視野中的模封劑的一部分，此部分是與根據一例示的實施例之一例示的半導體封裝的重分布層接觸的部分。
第11圖是一剖面圖，顯示根據一例示的實施例之一例示的半導體裝置。
第12圖是一流程圖，用以形成根據一例示的實施例之一半導體裝置。
第13圖是一流程圖，用以形成根據一例示的實施例之一半導體裝置。
請參考繪示於所附圖式之例示的實施例的細節。關於相同或類似的部件，在整份圖式中會儘量使用相同的編號。
本揭露是敘述一半導體封裝，其藉由使用一嶄新的罩幕層結構與一直接曝露模封製程(direct exposed molding process)，將構件與晶片組合在相同的模封體中。上述罩幕層結構指的是一罩幕層，此罩幕層是置於上述構件與上述晶片之 間。上述直接曝露模封製程指的是藉由此製程，不使用一研磨製程而在模封後使上述構件與上述晶片(或晶粒)直接曝露。
上述直接曝露模封製程亦可稱為一轉注模封製程(transfer molding process)或一壓擠模封製程(compression molding process)。轉注模封或壓擠模封，是在模封開始前測量模封材料的量並加以注入的製程。將上述模封材料預熱並裝填到已知為罐(pot)的反應室。然後使用一柱塞(plunger)迫使上述材料從上述罐通過已知為澆口(sprue)與流道系統(runner system)的通道，進入膜穴中。模具在注入上述材料時維持閉鎖，並打開以使構件與上述澆口與流道系統分離。將膜壁加熱至高於上述模封材料的熔點的溫度，可使上述材料較快地流到整個膜穴。
上述晶片可為選自矽半導體或iii-v族半導體矽半導體或iii-v半導體所組成的族群的晶片，且上述晶片可包含一微機電系統(microelectromechanical system；MEMS)。上述構件是置於上述半導體封裝的一展開(fan-out)區域。
藉由使用上述直接曝露模封製程，可將上述構件與上述晶片整合於同一層並同時模封。請注意上述構件可以是被動元件，例如電阻器、電感器、或電容器。此外具有類似掏度的構件與晶片可以藉由一重分布層而互連，減少上述構件與晶片的額外連接導致的良率損失的問題。
第1圖是一剖面圖，顯示根據一例示的實施例之一例示的半導體封裝100。如第1圖所示，一暫時性的連接層104是塗於一載體102的上方。載體102可由金屬或玻璃形成。
第2圖是一剖面圖，顯示根據一例示的實施例之一例示的半導體封裝100。如第2圖所示，可將一貼附膜202提供於暫時性的連接層104的上方。貼附膜202可由例如環氧樹脂或聚合物形成。將晶片204a、204b與構件206a、206b提供於貼附膜202的上方。晶片204a、204b分別具有輸入/輸出205a、205b。在晶片204a、204b與構件206a、206b之間提供罩幕層208a、208b、208c。構件206a、206b可以是被動元件，例如電阻器、電感器、或電容器。構件206a、206b的寬度可以是例如100-500微米。晶片204a、204b與構件206a、206b之間的距離可以是例如50-300微米。
第3圖是一剖面圖，顯示根據一例示的實施例之一例示的半導體封裝100。如第3圖所示，藉由使用直接曝露模封製程，將模封劑302a、302b、302c提供於罩幕層208a、208b、208c的凹部(或是閘口)中，以形成模封體304。模封劑302d、302e則提供於不同的封裝之間。因此，將晶片204a、204b與構件206a、206b模封於相同的模封體304中。罩幕層208a、208b、208c可由例如聚合物形成。晶片204a、204b與構件206a、206b之間的罩幕層208a、208b、208c可以使模封劑具有較均衡的流動，並亦強化填充凹部的能力。
在本實施例中，半導體封裝100可包含晶片204a、204b、構件206a、206b及模封劑302a-302e。構件206a、206b是相鄰於晶片204a、204b。模封劑302a-302e是置於晶片204a、204b與構件206a、206b之間。晶片204a、204b、構件206a、206b與模封劑302a-302e可形成模封體304。
第4圖是一剖面圖，顯示根據一例示的實施例之一例示的半導體封裝100。如第4圖所示，在模封體304的上方提供一重分布層(redistribution layer；RDL)402，並使重分布層402連接於晶片204a、204b與構件206a、206b。
第5圖是一剖面圖，顯示根據一例示的實施例之一例示的半導體封裝100。如第5圖所示，在重分布層(RDL)402的上方提供複數個金屬凸塊502，並使金屬凸塊502藉由重分布層(RDL)402而連接於晶片204a、204b與構件206a、206b。
第6圖是一剖面圖，顯示根據一例示的實施例之一例示的半導體封裝100。如第6圖所示，藉由對暫時性的連接層104施加一雷射光束或加熱器，將半導體封裝100從載體102(示於第5圖)脫離。
第7圖是一剖面圖，顯示根據一例示的實施例之一例示的半導體裝置700。如第7圖所示，將半導體封裝100提供於一印刷電路板704的上方，並連接於印刷電路板704。將半導體封裝100焊接於印刷電路板704之後，將例如環氧樹脂的一底填充物702注入半導體封裝100的下方，而有效地將半導體封裝600黏著於印刷電路板704。如此，提供一半導體裝置700。
第8圖是另一剖面圖，顯示根據一例示的實施例之一例示的半導體裝置800。接續第6圖，如第8圖所示，將半導體封裝100提供於一印刷電路板804的上方，並連接於印刷電路板804。將半導體封裝100焊接於印刷電路板804之後，將例如環氧樹脂的一底填充物802注入半導體封裝100的下方，而有效地將半導體封裝600黏著於印刷電路板804。此外，將一微影可 製造檢查層(lithography manufacturability check layer)806置於重分布層402與印刷電路板804之間。將一蓋體(或是一背側保護膜)808置於半導體封裝100的上方。
第9圖是另一剖面圖，顯示根據一例示的實施例之一例示的半導體裝置900。接續第6圖，如第8圖所示，藉由使用一堆疊封裝結構(package-on-package structure)904，將一記憶體902提供於半導體封裝100的上方並連接於半導體封裝100。第9圖中的其餘元件則類似於第8圖，在此處不再重複敘述。
第10圖是一方塊圖，顯示在顯微鏡視野中的模封劑的一部分，此部分是與根據一例示的實施例之一例示的半導體封裝的重分布層接觸的部分。如第4與10圖所示，提供一例示圖式顯示模封劑302d的一顯微鏡照像。在本實施例中，模封劑302d可包含環氧樹脂1004與玻璃球填充物1002a、1002b、1002c，其中有可觀數量的玻璃球填充物具有完整的形狀，因為執行直接曝露模封製程而未作一額外的研磨製程。否則，若對模封劑302d施以一研磨製程，在模封劑302d與重分布層402之間的接面404附近的玻璃球填充物1002a、1002b、1002c會顯示一切斷形狀或一劈裂形狀。可簡單注意到，任何半導體裝置，其具有的半導體封裝如前所述顯示玻璃球填充物具有一完整形狀而非一切斷形狀或一劈裂形狀者，是落入本揭露的範圍中。
第11圖是一剖面圖，顯示根據一例示的實施例之一例示的半導體裝置。如第11圖所示，提供一半導體裝置 1100。半導體裝置1100包含一半導體封裝1110、一印刷電路板1102與一底填充層1104。
半導體封裝1110具有晶片1104a、1104b與一構件1106a。構件1106a是鄰接於晶片1104a、1104b。晶片1104a、1104b與構件1106a是被模封於一相同的模封體1109中。構件1106a可以是被動元件，例如電阻器、電感器、或電容器。
在本實施例中，半導體封裝1110可包含晶片1104a、1104b、構件1106a及模封劑1118a-1118d。構件1106a是鄰接於模封劑1118a-1118d。模封劑1118a-1118d是置於晶片1104a、1104b與構件1106a之間。晶片1104a、1104b、構件1106a與模封劑1118a-1118d形成模封體1109。
在本例示的實施例中，晶片1104a、1104b分別包含輸入/輸出1105a、1105b。在晶片1104a、1104b與構件1106a之間，提供罩幕層1108a、1108b。藉由使用直接曝露模封製程，將模封劑1118a、1118b、1118c提供於罩幕層1108a、1108b的凹部(或是閘口)中，以形成模封體1109。模封劑1118c、1118d則提供於不同的封裝之間。在本例示的實施例中，可將晶片1104a、1104b與構件1106a藉由使用直接曝露模封製程而模封於模封體1109中。
在本例示的實施例中，半導體封裝1110更包含一貼附膜1112。貼附膜1112可由例如環氧樹脂或聚合物形成。構件1106a的寬度可以是例如100-500微米。晶片1104a、1104b與構件1106a之間的距離可以是例如50-300微米。
在本例示的實施例中，半導體封裝1110可更包含 一重分布層(RDL)1114，並使重分布層1114連接於晶片1104a、1104b與構件1106a。
在本例示的實施例中，半導體封裝1110可更包含複數個金屬凸塊1106，並使金屬凸塊1106藉由重分布層1114而連接於晶片1104a、1104b與構件1106a。
在本例示的實施例中，是將半導體封裝1110提供於一印刷電路板1102的上方，並連接於印刷電路板1102。將半導體封裝1100焊接於印刷電路板1102之後，將例如環氧樹脂的一底填充物1104注入半導體封裝1100的下方，而有效地將半導體封裝1110黏著於印刷電路板1102。此外，將一微影可製造檢查層1120置於重分布層1114與印刷電路板1102之間。
在本例示的實施例中，晶片1104a、1104b可以是至少矽半導體或iii-v族半導體之一。在本例示的實施例中，晶片1104a、1104b可包含一微機電系統(MEMS)。在本例示的實施例中，晶片1104a、1104b可以是應用處理器(application processor)。
在本例示的實施例中，模封劑1118a-1118d可包含環氧樹脂與球填充物，上述球填充物具有完整的形狀，而非一劈裂形狀。在本例示的實施例中，構件1106a可置於上述半導體封裝的一展開(fan-out)區域。在本例示的實施例中，半導體裝置1100可更具有一記憶體，此記憶體是藉由一封裝體堆疊製程置於半導體封裝1110的上方並連接於半導體封裝1110。在本例示的實施例中，半導體裝置1100可更具有一蓋體，此蓋體是置於半導體封裝1110的上方。
第12圖是一流程圖，用以形成根據一例示的實施例之一半導體裝置。如第12圖所示，提供一方法1200。方法1200包含下列操作：將至少一個晶片與至少一個構件模封於一相同的模封體中(1202)。
第13圖是一流程圖，用以形成根據一例示的實施例之一半導體裝置。如第13圖所示，提供一方法1300。方法1300包含下列操作：在一載體上提供一暫時性的連接層(1302)；在上述暫時性的連接層的上方提供上晶片與上述構件(1304)；在上述晶片與上述構件之間提供一罩幕層(1306)；將至少一個晶片與至少一個構件模封於一相同的模封體中(1202)；藉由使用一直接曝露模封製程將一模封劑提供於上述罩幕層的一凹部中，以形成上述模封體(1308)；在上述晶片與上述構件的上方提供一重分布層，上述重分布層連接於上述晶片與上述構件(1310)；提供複數個金屬凸塊，上述金屬凸塊藉由上述重分布層而連接於上述晶片與上述構件(1312)；將上述半導體封裝從上述載體分離(1314)；以及將上述半導體封裝提供於一印刷電路板的上方且連接於上述印刷電路板(1316)。
在本例示的實施例中，方法1300可更包含：提供一微影可製造檢查膜，將其置於上述重分布層與上述印刷電路板之間。在本例示的實施例中，方法1300可更包含：提供一記憶體，藉由使用一堆疊封裝構造而將上述記憶體置於上述半導體封裝的上方並連接於上述半導體封裝。在本例示的實施例中，上述操作1308可更包含：藉由上述直接曝露模封製程而未作一研磨製程來提供上述模封劑，而使上述模封劑包含不具一 劈開形狀的球填充物。
根據一例示的實施例，提供一種形成半導體裝置的方法。上述方法包含下列操作：將至少一個晶片與至少一個構件模封於一相同的模封體中。
根據一例示的實施例，提供一種半導體裝置。上述半導體裝置包含：一半導體封裝、一印刷電路板及一底填充層。上述半導體封裝包含：至少一個晶片；至少一個構件，其相鄰於上述至少一晶片，其中上述至少一個晶片與上述至少一個構件是被模封在一相同的模封體中；一模封劑，置於上述至少一個晶片與上述至少一個構件之間，以形成一模封體；一重分布層，連接於上述至少一個晶片與上述至少一個構件；及複數個金屬凸塊，藉由上述重分布層而連接於上述至少一個晶片與上述至少一個構件。上述印刷電路板是藉由上述金屬凸塊連接於上述半導體封裝。上述底填充層是置於上述印刷電路板與上述半導體封裝之間。
根據一例示的實施例，提供一種半導體封裝。上述半導體封裝包含：至少一個晶片；至少一個構件，其相鄰於上述至少一晶片；以及一模封劑，置於上述至少一個晶片與上述至少一個構件之間，其中上述至少一個晶片、上述至少一個構件與上述模封劑形成一模封體。
本書面敘述在揭露中使用數個例子是為了：揭露最佳模式且亦使在本領域具有通常技藝者能製造並使用本揭露。可專利範圍可包含本領域的技術人員達成的其他例子。
正在閱讀這份揭露的相關領域的技術人員將瞭解 其可在不需一項或多項特定的細節、或加入其他置換及/或額外的方法、材料、或構件之下，實行各種實施例。廣為人知的結構、材料、或操作並未顯示或敘述，以避免模糊了各種實施例的形貌。示於圖式中的各種實施例是用以說明的例子的代表，且不需要按比例繪製。特定的組件、結構、或特性，可能會在一或多個實施例中以任何適當形式組合。在其他實施例中，可納入各種附加的層及/或結構、及/或已敘述過的組件可以省略。各種操作可被敘述為按順序的複數個分離的操作，以最有助於瞭解本揭露的形式。然而，敘述的順序不應被解釋為意指這些操作是必須依存於順序。尤其，這些操作不需要依照呈現的順序來執行。此處敘述的操作可以不同的順序執行、先後執行或一併執行，與所述的實施例不同。可執行及/或敘述各種額外的操作。在附加的實施例中，操作可以被省略。
本書面敘述及後續的申請專利範圍可能包含例如左、右、頂、底、上方、下方、上、下、第一、第二等詞彙，期僅用來作為敘述的目的，而不應被解釋為限制。例如指定為相對垂直位置的詞彙可視為以下情況：一基底或積體電路的一裝置側(或主動表面)是此基底的「頂」表面，此基底可能事實上是在任何方位，而使一基底的一「頂」側在參考的一標準地球架構中低於「底」側，而仍可能落入「頂」這個詞彙的意義。此處(包含在申請專利範圍中)使用的詞彙「在......上」，除非有特別申明，可以並非指的是：一第一層「在」一第二層「上」就是直接在此第二層上並直接接觸此第二層；可能會有一第三層會在上述第一層與在上述第一層上的上述第二層之間。此處 敘述的一裝置或物品的實施例可能被製造、使用、或運送於許多位置或方位。本領域的技術人員會理解為了示於圖式中的各種構件所作的等効結合與替換。

Claims (20)

  1. 一種半導體封裝，包含：至少一個晶片；至少一個構件，其相鄰於上述至少一晶片；以及一模封劑，置於上述至少一個晶片與上述至少一個構件之間，其中上述至少一個晶片、上述至少一個構件與該模封劑形成一模封體。
  2. 如申請專利範圍第1項所述之封裝，更包含一重分布層，該重分布層連接於上述至少一個晶片與上述至少一個構件。
  3. 如申請專利範圍第1項所述之封裝，更包含複數個金屬凸塊，該些金屬凸塊藉由該重分布層而連接於上述至少一個晶片與上述至少一個構件。
  4. 如申請專利範圍第1項所述之封裝，更包含一罩幕層，該罩幕層置於上述至少一個晶片與上述至少一個構件之間。
  5. 如申請專利範圍第1項所述之封裝，其中該模封劑包含環氧樹脂與球填充物，上述球填充物不具一劈開形狀(cleaved shape)。
  6. 如申請專利範圍第1項所述之封裝，其中上述至少一個構件是置於該半導體封裝的一展開(fan-out)區域。
  7. 如申請專利範圍第1項所述之封裝，其中上述至少一個晶片包含一材料，該材料選自矽半導體或iii-v族半導體所組成之族群。
  8. 如申請專利範圍第1項所述之封裝，其中上述至少一個晶片 包含微機電系統(microelectromechanical systems；MEMS)。
  9. 如申請專利範圍第1項所述之封裝，更包含一貼附膜，該模封體是置於該貼附膜上。
  10. 一種半導體裝置，包含：一半導體封裝，包含：至少一個晶片；至少一個構件，其相鄰於上述至少一晶片，其中上述至少一個晶片與上述至少一個構件是被模封在一相同的模封體中；一模封劑，置於上述至少一個晶片與上述至少一個構件之間，以形成一模封體；一重分布層，連接於上述至少一個晶片與上述至少一個構件；複數個金屬凸塊，藉由該重分布層而連接於上述至少一個晶片與上述至少一個構件；一印刷電路板，藉由該些金屬凸塊連接於該半導體封裝；以及一底填充層，置於該印刷電路板與該半導體封裝之間。
  11. 如申請專利範圍第10項所述之裝置，其中該半導體封裝更包含一微影可製造檢查膜(lithography manufacturability check layer)，該微影可製造檢查膜是置於該重分布層與該印刷電路板之間。
  12. 如申請專利範圍第10項所述之裝置，其中上述至少一個晶片是應用處理器(application processor)。
  13. 如申請專利範圍第10項所述之裝置，更包含一記憶體，該記憶體是藉由使用一堆疊封裝構造(package-on-package structure)而置於該半導體封裝的上方並連接於該半導體封裝。
  14. 如申請專利範圍第10項所述之裝置，更包含一蓋體，該蓋體是置於該半導體封裝的上方。
  15. 一種形成半導體裝置的方法，包含將至少一個晶片與至少一個構件模封於一模封體中。
  16. 如申請專利範圍第15項所述之方法，更包含：在一載體上提供一暫時性的連接層；在該暫時性的連接層的上方提供上述至少一個晶片與上述至少一個構件；在上述至少一個晶片與上述至少一個構件之間提供一罩幕層；藉由使用一直接曝露模封製程將一模封劑提供於該罩幕層的一凹部中，以形成該模封體；在上述至少一個晶片與上述至少一個構件的上方提供一重分布層，該重分布層連接於上述至少一個晶片與上述至少一個構件；提供複數個金屬凸塊，該些金屬凸塊藉由該重分布層而連接於上述至少一個晶片與上述至少一個構件；將該半導體封裝從該載體分離；以及將該半導體封裝提供於一印刷電路板的上方且連接於該印刷電路板。
  17. 如申請專利範圍第16項所述之方法，更包含提供一微影可製造檢查膜，將其置於該重分布層與該印刷電路板之間。
  18. 如申請專利範圍第16項所述之方法，更包含提供一記憶體，藉由使用一堆疊封裝構造而將該記憶體置於該半導體封裝的上方並連接於該半導體封裝。
  19. 如申請專利範圍第16項所述之方法，更包含提供一蓋體，將其置於該半導體封裝的上方。
  20. 如申請專利範圍第16項所述之方法，其中藉由使用該直接曝露模封製程將該模封劑提供於該罩幕層的該凹部中更包含：藉由該直接曝露模封製程而未作一研磨製程來提供該模封劑，而使該模封劑包含不具一劈開形狀的球填充物。
TW103146013A 2014-01-10 2014-12-29 半導體封裝，半導體裝置及其形成方法 TWI618671B (zh)

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