TW201535547A - 晶片整列方法 - Google Patents

晶片整列方法 Download PDF

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Publication number
TW201535547A
TW201535547A TW104104246A TW104104246A TW201535547A TW 201535547 A TW201535547 A TW 201535547A TW 104104246 A TW104104246 A TW 104104246A TW 104104246 A TW104104246 A TW 104104246A TW 201535547 A TW201535547 A TW 201535547A
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Taiwan
Prior art keywords
wafer
liquid
wafers
wafer mounting
mounting region
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TW104104246A
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English (en)
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TWI649814B (zh
Inventor
Kazuma Sekiya
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Disco Corp
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Publication of TW201535547A publication Critical patent/TW201535547A/zh
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Publication of TWI649814B publication Critical patent/TWI649814B/zh

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Abstract

本發明的課題為提供一種能夠以高精度整列晶片的晶片整列方法。解決手段為在晶圓上整列複數個晶片的晶片整列方法，並做成具備以下步驟的構成：溝形成步驟，在晶圓之表面側形成分別劃分出晶片載置區域之交叉的複數條溝；液體供給步驟，對晶片載置區域供給液體；晶片載置步驟，在已實施液體供給步驟後，在液體上載置晶片以用液體的表面張力將晶片定位於晶片載置區域；以及，液體去除步驟，在已實施晶片載置步驟後，藉由去除液體而使複數個晶片整列在晶圓上。

Description

晶片整列方法 發明領域
本發明是有關用於使複數個晶片整列的晶片整列方法。
發明背景
近年來，使用晶圓級之再配線技術而在裝置晶片(晶片)外形成再配線層之被稱為FOWLP(Fan-Out Wafer Level Package)的封裝的製造已經起步(參照例如，專利文獻1)。FOWLP由於是在薄膜的配線層進行晶片與封裝基板的連接，因此與使用打線接合等之以往的封裝相比較，更有利於小型化。
在FOWLP的製造中，可採用例如被稱為晶片優先(Chip-first)法的製程。在晶片優先法中，首先，是以樹脂等密封以任意間隔排列的晶片以形成仿真晶圓，並在這個仿真晶圓上設置配線層。之後，藉由沿著晶片之間的分割預定線分割仿真晶圓，就能得到複數個封裝。
又，有時候也會採用被稱為RDL優先(再配線層優先(Redistribution Layer-first))法的製程，其為在設置有配線層的支撐晶圓上排列晶片而用樹脂等進行密封，之後去 除支撐晶圓以分割成複數個封裝。在這個RDL法中，因為可以例如避開配線層之不良部分而排列晶片，因此與晶片優先法相比較更易於提高成品率。
先前技術文獻 專利文獻
專利文獻1：日本專利特開2013-58520號公報
發明概要
可是，在上述的晶片優先法或RDL優先法中，為了要確實地進行與高密度地形成之配線層的連接，必須以高精度來整列晶片。然而，整列晶片的移載裝置，由於是以例如，各個晶片的外周緣作為基準來判斷移載前的位置而決定移載後的位置，因此會發生在移載後的晶片位置上產生數10μm左右之偏離的情況。
本發明是有鑒於所述問題點而所作成的，其目的在於提供能夠做到以高精度整列晶片的晶片整列方法。
依據本發明所提供的晶片整列方法，是使複數個晶片整列在晶圓上的晶片整列方法，其特徵在於包括：溝形成步驟，在晶圓之表面側上形成分別劃分出晶片載置區域之交叉的複數條溝；液體供給步驟，對該晶片載置區域供給液體；晶片載置步驟，在已實施該液體供給步驟後，在該液體上載置晶片以用該液體的表面張力將晶片定位於 該晶片載置區域；及，液體去除步驟，在已實施該晶片載置步驟後，藉由去除該液體而使複數個晶片整列在該晶圓上。
又，在本發明中，較理想的是，該液體去除步驟是藉由將透過該液體而載置有複數個晶片的晶圓載置於真空中來實施。
又，在本發明中，較理想的是，該液體含有可將晶片固定在該晶圓上的接著劑成分。
在本發明的晶片整列方法中，由於在晶圓的表面側上形成了劃分出晶片載置區域的複數條溝之後，再對這個晶片載置區域供給液體而載置晶片，所以被載置的晶片會因液體的表面張力而被定位在晶片載置區域上。
之後，只要去除晶片載置區域的液體，就能夠使複數個晶片整列於晶圓上。像這樣，依據本發明的晶片整列方法，能夠利用液體的表面張力而使晶片以高精度整列。
11‧‧‧晶圓
11a‧‧‧表面
11b‧‧‧背面
13‧‧‧溝
15‧‧‧晶片載置區域
15a‧‧‧第1晶片載置區域
15b‧‧‧第2晶片載置區域
17‧‧‧液體
19‧‧‧晶片
19a‧‧‧第1晶片
19b‧‧‧第2晶片
2‧‧‧噴嘴
圖1(A)是模式地表示實施形態1之溝形成步驟的立體圖，圖1(B)是模式地表示溝形成步驟的剖面圖。
圖2是模式地表示實施形態1之液體供給步驟的剖面圖。
圖3(A)是模式地表示實施形態1之晶片載置步驟的剖面圖，圖3(B)是模式地表示將晶片定位於晶片載置區域之狀 態的剖面圖。
圖4是模式地表示實施形態1之液體去除步驟的剖面圖。
圖5是模式地表示實施形態2之溝形成步驟的剖面圖。
圖6是模式地表示實施形態2之液體供給步驟的剖面圖。
圖7(A)是模式地表示實施形態2之晶片載置步驟的剖面圖，圖7(B)是模式地表示將晶片定位於晶片載置區域之狀態的剖面圖。
圖8是模式地表示實施形態2之液體去除步驟的剖面圖。
圖9是模式地表示變形例之晶片整列方法的剖面圖。
用以實施發明之形態
參照附加圖式，針對本發明之實施形態進行說明。本發明之晶片整列方法包含：溝形成步驟(參照圖1、圖5)、液體供給步驟(參照圖2、圖6)、晶片載置步驟(參照圖3、圖7)，及液體去除步驟(參照圖4、圖8)。
在溝形成步驟中，是在晶圓之表面側上形成劃分出晶片載置區域的複數條溝。在液體供給步驟中，是對被劃分而成的複數個晶片載置區域分別供給液體。在晶片載置步驟中，是以與所供給之液體接觸的方式載置晶片，以使液體的表面張力作用於晶片。在液體去除步驟中，是去除液體而使晶片整列在晶圓上。
以下，針對本發明之晶片整列方法進行詳細說明。再者，在以下所示之實施形態1中，是針對使大小相同的複數個晶片在晶圓上整列之晶片整列方法進行說明，且在實施形態2中，是針對使大小相異的複數個晶片在晶圓上整列之晶片整列方法進行說明。
(實施形態1)
在本實施形態中，是針對使大小相同的複數個晶片在晶圓上整列之晶片整列方法進行說明。在本實施形態的晶片整列方法中，首先，是實施溝形成步驟，在使晶片整列之晶圓的表面側形成劃分出晶片載置區域的複數條溝。
圖1(A)是模式地表示溝形成步驟的立體圖，圖1(B)是模式地表示溝形成步驟的剖面圖。如圖1(A)以及圖1(B)所示，晶圓11為圓盤狀的半導體晶圓等，並包括有用於使晶片整列的大致平坦之表面11a。
在溝形成步驟中，是在這個晶圓11之表面11a側上形成交叉的複數條溝13。晶圓11之表面11a側是藉由複數條溝13而被劃分成用於載置晶片的複數個晶片載置區域15。
溝13是藉由使例如旋轉的圓環狀切削刀從晶圓11的表面11a切入預定的深度，並使切削刀與晶圓11相對地移動而形成。又，也可以藉由照射容易被晶圓11吸收之波長的雷射光束，對表面11a側進行燒蝕而形成溝13。
溝13的寬度、深度、位置、數量等條件，會視要使其進行整列的晶片之形狀、大小、重量、配置(間隔)等而 進行變更。例如，在本實施形態中，是使所形成之溝13的寬度與鄰接的晶片之間隔(亦即，晶片載置區域15的間隔)相配合，而形成2條一組的平行的溝13。
又，在本實施形態中，為了使複數個晶片以相等間隔整列，形成有以相等間隔劃分出複數個晶片載置區域15的複數條溝13。另一方面，在使複數個晶片以相異的間隔整列的情況中，只要形成以相異的間隔劃分出複數個晶片載置區域15的複數條溝13即可。
平面視圖中的晶片載置區域15的形狀是具代表性的矩形。只是，平面視圖中的晶片載置區域15之形狀，可因應平面視圖中的晶片形狀而適當地進行變更。例如，只要晶片的平面視圖是多角形，則可將晶片載置區域15的平面視圖也形成多角形，只要晶片的平面視圖是圓形，則可將晶片載置區域15的平面視圖也形成圓形。
平面視圖中的晶片載置區域15的大小(面積)，是與例如平面視圖中的晶片的大小(面積)同等。但是，平面視圖中的晶片載置區域15的大小，在可以將晶片適當地整列的範圍內可以任意地變更。亦即，也可以將平面視圖中的晶片載置區域15的大小做成比平面視圖中的晶片19的大小還要小，或是還要大。
再者，在圖1(A)以及圖1(B)中，雖然形成有形狀以及大小均相同的複數個晶片載置區域15，但是晶片載置區域15的形狀以及大小不是單1種亦可。例如，在要整列相異種類的晶片的情況中，只要對應晶片的種類，而設置形 狀以及大小不同的晶片載置區域15即可。
在溝形成步驟之後，可實施對複數個晶片載置區域15分別供給液體的液體供給步驟。圖2是模式地表示液體供給步驟的剖面圖。如圖2所示，在液體供給步驟中，首先，以使表面11a側露出的方式固定晶圓11的背面11b側之後，再將液體供給用的噴嘴2定位到作為對象的晶片載置區域15的上方處。
接著，從噴嘴2滴下液體17以供給至對象的晶片載置區域15。此液體17可以使用例如水(純水)。以噴嘴2所供給的液體17的量是設定在使液體17不流出於包圍對象之晶片載置區域15的溝13的外側的程度。
在將液體17供給至對象之晶片載置區域15之後，會使噴嘴2與晶圓11相對地移動，以將液體供給用之噴嘴2定位在鄰接的晶片載置區域15的上方處。然後，從噴嘴2滴下液體17以供給至鄰接的晶片載置區域15。重複這個動作，一旦將液體17供給至全部的晶片載置區域15後，即可結束液體供給步驟。
再者，在本實施形態中，雖然是使用水(純水)作為液體17，但是也可以使用具有某種程度的表面張力的其他液體。又，也可以在液體17中混合用於控制黏度或接著性的其他物質。
例如，若是在液體17中加入添加劑以增大接觸角時，則液體17就會變得難以流出到溝13的外側。又，在例如，將整列後的晶片密封在晶圓11上的情況等中，若事先 在液體17中混合接著劑(接著劑成分)時，就能將晶片固定在晶圓11上而可以限制隨著密封劑的收縮等而形成的晶片的移動。
在液體供給步驟之後，即可實施晶片載置步驟，以接觸所供給之液體17的方式載置晶片，以使液體17的表面張力作用在晶片上。圖3(A)為模式地表示晶片載置步驟的剖面圖，圖3(B)為模式地表示將晶片定位於晶片載置區域15上的狀態的剖面圖。
如圖3(A)所示，在晶片載置步驟中，是將複數個晶片19載置在晶圓11的表面11a側。具體來說，是在與各個晶片載置區域15的液體17重疊的位置(液體17上面)上分別載置晶片19。但是，要做成使各個晶片載置區域15上所載置的晶片19不與其他的晶片載置區域15的液體17接觸。
其結果為，藉著液體17的表面張力(以及浮力)的作用晶片19會移動，並如圖3(B)所示，定位到與晶片載置區域15重疊的位置上。亦即，晶片19會以對應於晶片載置區域15的排列的態樣進行整列。
在晶片載置步驟之後，可實施去除液體17的液體去除步驟。圖4是模式地表示液體去除步驟的剖面圖。在這個液體去除步驟中，是將例如，載置有複數個晶片19的晶圓11配置在真空(減壓)環境中，使液體17蒸發。
其結果為，如圖4所示，能夠使複數個晶片19在晶圓11的表面11a上整列。再者，在這個液體去除步驟中，也可以將載置有複數個晶片19的晶圓11配置在加熱環境中， 使液體17蒸發。又，也可以藉由自然乾燥去除液體17。
在液體去除步驟之後，可以實施任意的處理工序。例如，也可以用移載裝置將在晶圓11上整列的複數個晶片19移載至其他區域。因為藉由本實施形態的晶圓整列方法可讓移載前的晶片19以高精度整列，所以能夠充分地抑制移載後的晶片之位置偏移等。
又，也能夠以樹脂等將整列在晶圓11上的複數個晶片19密封，形成晶片優先法的仿真晶圓。此外，也可以使用形成有配線層的晶圓11，或者是在晶圓11上形成配線層而以RDL優先法形成封裝。
如以上所述，在本實施形態之晶片整列方法中，由於是在晶圓11的表面11a側形成了劃分出晶片載置區域15的複數條溝13之後，才對這個晶片載置區域15供給液體17而載置晶片19，所以可將所載置的晶片19藉著液體17的表面張力定位到晶片載置區域15上。
之後，只要去除晶片載置區域15的液體，即可使複數個晶片19整列在晶圓11上。像這樣，依據本實施形態之晶片整列方法，可以做到利用液體17的表面張力而以高精度整列晶片19。
(實施形態2)
在本實施形態中，針對使大小相異的複數個晶片19整列在晶圓11上之晶片整列方法進行說明。再者，本實施形態之晶片整列方法在大多數的點上與實施形態1之晶片整列方法是共通的。據此，在本實施形態中，會省略共通部 分的詳細說明。
首先，實施溝形成步驟，在使晶片19整列之晶圓11的表面11a側，形成劃分出晶片載置區域15的複數條溝13。圖5是模式地表示溝形成步驟的剖面圖。在本實施形態的溝形成步驟中，是在晶圓11的表面11a側形成交叉的複數條溝13，並將晶圓11的表面11a劃分成形狀、大小等相異的第1晶片載置區域15a以及第2晶片載置區域15b。
再者，在圖5中，雖然形成有形狀、大小等相異的2種晶片載置區域15，但是也可以形成3種以上的晶片載置區域15。晶片載置區域15的種類，可因應整列的晶片19的種類而任意地變更。
在溝形成步驟之後，即可實施對複數個晶片載置區域15分別供給液體的液體供給步驟。圖6是模式地表示液體供給步驟的剖面圖。如圖6所示，在本實施形態的液體供給步驟中，是做成因應晶片載置區域15的大小等而調整供給液體17的量，使液體17不會流出到包圍晶片載置區域15的溝13的外側區域。
在液體供給步驟之後，可實施晶片載置步驟，以和所供給之液體17接觸的方式載置晶片，以使液體17的表面張力作用在晶片上。圖7(A)是模式地表示晶片載置步驟的剖面圖，圖7(B)是模式地表示將晶片定位於晶片載置區域15之狀態的剖面圖。
如圖7(A)所示，在本實施形態的晶片載置步驟中，在與第1晶片載置區域15a的液體17形成重疊的位置(液體 17上面)上，載置對應於第1晶片載置區域15a的第1晶片19a。又，在與第2晶片載置區域15b的液體17形成重疊的位置(液體17上面)上，載置對應於第2晶片載置區域15b的第2晶片19b。
其結果為，藉著液體17的表面張力(以及浮力)的作用，2種晶片19會分別移動，並如圖7(B)所示，第1晶片19a會定位於與第1晶片載置區域15a形成重疊的位置，且第2晶片19b會定位於與第2晶片載置區域15b形成重疊的位置。亦即，2種晶片19是以對應於2種晶片載置區域15之排列的態樣進行整列。
在晶片載置步驟之後，則實施去除液體17的液體去除步驟。圖8是模式地表示液體去除步驟的剖面圖。如圖8所示，藉由去除液體17，就能使2種晶片19整列於晶圓11的表面11a上。
像這樣，本實施形態之晶片整列方法也可以利用液體17的表面張力使晶片19以高精度整列。本實施形態中所示之構成、方法等，也可以與其他實施形態之構成、方法等進行適當組合。
再者，本發明並不受限於上述實施形態的記載，並可以進行各種變更而實施。例如，在以RDL優先法形成封裝的情況等中，當在包括有配線層的晶圓11上形成深的溝13時，配線層與溝13就會產生干涉。又，有時也有晶圓11的強度因深的溝13而降低的情形。因此，像這樣的現象成為問題時，只要形成淺且寬度寬的溝13來代替深的溝13 即可。
圖9是模式地表示變形例之晶片整列方法的剖面圖。在圖9中，藉由形成淺且寬度寬的溝13，就能將溝13的內周緣定位在比晶片19的外周緣還要內側的位置。此時，平面視圖中的晶片載置區域15的大小，會變得比平面視圖中的晶片19的大小還要稍微來得小。
如圖9所示，只要將溝13做淺且將寬度做寬，即使是在以RDL優先法形成封裝的情況等中，仍然可以充分地確保溝13之容積。藉此，被供給至晶片載置區域15的液體17就會變得難以流出到溝13之外側。又，能夠防止晶圓11的強度降低。
此外，在將整列後的晶片19密封在晶圓11上的情況等中，也可以在溝形成步驟或是液體供給步驟之前，在晶圓11的表面11a形成以接著劑或雙面膠等所構成的黏著層。藉此，由於可將晶片19固定在晶圓11上，所以能限制伴隨著密封劑的收縮等而形成的晶片19的移動。
另外，上述實施形態之構成、方法等，只要在不脫離本發明之目的的範圍內，皆可進行適當變更而實施。
11‧‧‧晶圓
11a‧‧‧表面
11b‧‧‧背面
13‧‧‧溝
15‧‧‧晶片載置區域

Claims (3)

  1. 一種晶片整列方法，是使複數個晶片整列在晶圓上的晶片整列方法，其特徵在於包括：溝形成步驟，在晶圓之表面側形成分別劃分出晶片載置區域之交叉的複數條溝；液體供給步驟，對該晶片載置區域供給液體；晶片載置步驟，在已實施該液體供給步驟後，在該液體上載置晶片以用該液體的表面張力將晶片定位於該晶片載置區域；及液體去除步驟，在已實施該晶片載置步驟後，藉由去除該液體而使複數個晶片整列在該晶圓上。
  2. 如請求項1的晶片整列方法，其中，該液體去除步驟是藉由將透過該液體載置有複數個晶片的晶圓載置於真空中來實施。
  3. 如請求項1或2的晶片整列方法，其中，該液體含有可將晶片固定在該晶圓上的接著劑成分。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI708313B (zh) * 2016-03-17 2020-10-21 日商東京威力科創股份有限公司 使用液體對基板進行晶片零件之對準之方法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6055525B1 (ja) 2015-09-02 2016-12-27 富士重工業株式会社 車両の走行制御装置
JP2018064077A (ja) * 2016-10-14 2018-04-19 株式会社ディスコ デバイスチップ、収容トレイ、及び、デバイスチップの収容方法
JP6887722B2 (ja) * 2016-10-25 2021-06-16 株式会社ディスコ ウェーハの加工方法及び切削装置
KR101902566B1 (ko) 2017-07-25 2018-09-28 엘지디스플레이 주식회사 발광 표시 장치 및 이의 제조 방법
JP6899293B2 (ja) * 2017-09-13 2021-07-07 株式会社ディスコ 積層ウェーハの製造方法
CN110854057B (zh) * 2019-11-14 2022-07-12 京东方科技集团股份有限公司 一种转移基板及其制作方法、转移方法
CN112992759B (zh) * 2020-10-16 2022-04-19 重庆康佳光电技术研究院有限公司 一种器件转移设备及其制备方法、器件转移方法
US20220415847A1 (en) * 2021-06-24 2022-12-29 Intel Corporation Features for improving die size and orientation differentiation in hybrid bonding self assembly

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8283208B2 (en) * 2004-12-28 2012-10-09 Mitsumasa Koyanagi Method and apparatus for fabricating integrated circuit device using self-organizing function
KR101298225B1 (ko) * 2005-06-30 2013-08-27 페어차일드 세미컨덕터 코포레이션 반도체 다이 패키지 및 그의 제조 방법
TWI281717B (en) * 2006-05-17 2007-05-21 Univ Tsinghua Apparatus for aligning microchips on substrate and method for the same
JP2010087066A (ja) * 2008-09-30 2010-04-15 Hitachi Ltd 半導体チップ、実装基板及び半導体装置の製造方法
JP5389490B2 (ja) * 2009-03-23 2014-01-15 東京エレクトロン株式会社 三次元集積回路の製造方法及び装置
US20100248424A1 (en) * 2009-03-27 2010-09-30 Intellectual Business Machines Corporation Self-Aligned Chip Stacking
EP2299486B1 (de) * 2009-09-18 2015-02-18 EV Group E. Thallner GmbH Verfahren zum Bonden von Chips auf Wafer
MY171813A (en) * 2009-11-13 2019-10-31 Semiconductor Components Ind Llc Electronic device including a packaging substrate having a trench
JP5021098B2 (ja) * 2009-12-11 2012-09-05 パイオニア株式会社 半導体基板の接合方法およびｍｅｍｓデバイス
JP5411689B2 (ja) * 2009-12-28 2014-02-12 東京エレクトロン株式会社 実装方法及び実装装置
US20120056228A1 (en) * 2010-09-07 2012-03-08 Phostek, Inc. Led chip modules, method for packaging the led chip modules, and moving fixture thereof
JP5803276B2 (ja) * 2011-05-26 2015-11-04 富士通株式会社 半導体装置の製造方法
JP2013058520A (ja) 2011-09-07 2013-03-28 Dainippon Screen Mfg Co Ltd 描画装置、データ補正装置、再配線層の形成方法、および、データ補正方法
US8557631B2 (en) * 2011-12-01 2013-10-15 Taiwan Semiconductor Manufacturing Co., Ltd. Interposer wafer bonding method and apparatus
US9142532B2 (en) * 2012-04-24 2015-09-22 Bondtech Co., Ltd. Chip-on-wafer bonding method and bonding device, and structure comprising chip and wafer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI708313B (zh) * 2016-03-17 2020-10-21 日商東京威力科創股份有限公司 使用液體對基板進行晶片零件之對準之方法

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