TW201530728A - 具有嵌設元件的積體電路封裝系統及製造該積體電路封裝系統的方法 - Google Patents

具有嵌設元件的積體電路封裝系統及製造該積體電路封裝系統的方法 Download PDF

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TW201530728A
TW201530728A TW103142554A TW103142554A TW201530728A TW 201530728 A TW201530728 A TW 201530728A TW 103142554 A TW103142554 A TW 103142554A TW 103142554 A TW103142554 A TW 103142554A TW 201530728 A TW201530728 A TW 201530728A
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integrated circuit
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TWI628772B (zh
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Dong-Ju Jeon
Kyoung-Hee Park
Young-Dal Roh
Jin-Hee Jung
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Stats Chippac Ltd
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Abstract

一種積體電路封裝系統及一種積體電路封裝系統之積體電路封裝系統的製造方法，係包括：嵌入材料，係在組件上；遮蔽層，係在該嵌入材料上；埋藏圖案，係在該遮蔽層中，該埋藏圖案之外表面係與該遮蔽層之外表面共平面，該埋藏圖案電性連接該組件；圖案化介電質，係在該埋藏圖案之一部分上；以及積體電路晶粒，係在該埋藏圖案上。

Description

具有嵌設元件的積體電路封裝系統及製造該積體電路封裝系統的方法 相關申請案的交互參照
本申請案主張於2013年12月16日提出申請的美國第61/916,405號的臨時專利申請案之優先權，且該申請案之標的係藉由參照該案而含括於本文。
本發明一般與一種積體電路封裝系統相關，且尤指具有嵌入電子組件的系統。
電腦工業的持續目標是增加組件的小型化、較大之積體電路(IC)的封裝密度、更高性能及降低成本。半導體封裝結構繼續推進向著小型化，以在減少封裝件之製作的產品尺寸時增加封裝其中之組件密度。這樣回應了在沿著不斷增加的性能上用於不斷縮小尺寸、厚度及成本之資訊及通信產品的持續增加之需求。
舉例而言，在如蜂巢電話、免持蜂巢電話 耳機、個人數位助理(PDA)、攝像機、筆記型電腦等手持便攜式訊息及通信裝置中這些針對小型化之增加的要求是特別值得注意的。所有這些裝置繼續做得更小及更薄，以提高它們的可手持性。相應地，融入這些裝置之大型積體電路(LSI)的封裝件係需要做得更小及更薄。容置及保護LSI之封裝件配置要求它們盡量做得更小及更薄。
在提供用於增加的積體電路含量之系統中較少的實體空間之矛盾的同時，消費類電子產品之需求須要在積體電路封裝件中更加集積的電路。不斷降低成本則係另一項要求。有些技術主要集中在將更多的功能集積到每個積體電路內。其他技術集中在堆疊這些積體電路在單一封裝件內。雖然這些方法在積體電路內提供更多的功能，它們沒有完全解決整合和降低成本的要求。
因此，仍保持用於提供集積、節省空間及低成本之支持系統之製法的需求。鑑於日益增長的商業競爭壓力、不斷增長的消費預期及在市場上有意義的產品差異化的機會逐漸減少，找到針對這些問題之答案是至關重要的。另外，對於降低成本、提高效率和性能之需要及滿足競爭的壓力增加對於針對尋找解答這些問題之日益增長的緊迫性。
對於這些已長期尋求但現有的發展沒有教示或建議任何解決方案之問題的解決方案，且因此對於這些問題的解答已長期難倒所屬技術領域中具有通常知識者。
本發明提供一種積體電路封裝系統之積體電路封裝系統的製造方法，係包括：在被動裝置上形成嵌入材料；在該嵌入材料上沉積乾膜層；圖案化該乾膜層；在該乾膜層中沉積埋藏圖案，該埋藏圖案之外表面係與該乾膜層之外表面共平面，該埋藏圖案電性連接該被動裝置；在該埋藏圖案之一部分上形成圖案化介電質；以及在該埋藏圖案上安置積體電路晶粒。
本發明提供一種積體電路封裝系統，係包括：在被動裝置上的嵌入材料；在該嵌入材料上的乾膜層；在該乾膜層中的埋藏圖案，該埋藏圖案之外表面係與該乾膜層之外表面共平面，該埋藏圖案電性連接該被動裝置；在該埋藏圖案之一部分上的圖案化介電質；以及安置在該埋藏圖案上的積體電路晶粒。
本發明之某些實施例係具有附加或取代這些上文所提到之其它步驟或元件。該步驟或元件對於所屬技術領域中具有通常知識者在參照所附圖式時從閱讀以下詳細描述而將會變得清楚明白。
2-2‧‧‧剖面線
100、300‧‧‧積體電路封裝系統
102、302‧‧‧嵌入式組件基板
104、304‧‧‧積體電路晶粒
106‧‧‧上表面
208、308‧‧‧組件
210、310‧‧‧嵌入材料
212、312‧‧‧埋藏圖案
214、314‧‧‧遮蔽層
216、316‧‧‧嵌入式組件穿孔
218、318‧‧‧裝置黏著物
220‧‧‧導電圖案
222、322‧‧‧圖案化介電質
224、324‧‧‧埋藏接觸墊
226、326‧‧‧外層接觸墊
228、328‧‧‧走線
230、330‧‧‧垂直穿孔
331‧‧‧層狀導電圖案
332‧‧‧內層接觸墊
434‧‧‧雙側承載板
436‧‧‧導電層
838‧‧‧基礎導電材料
1140‧‧‧圖案遮蔽
1542‧‧‧外基礎導電層
1840‧‧‧圖案化遮蔽
2200‧‧‧方法
2202、2204、2206、2208、2210、2212‧‧‧方塊
第1圖係本發明之第一實施例中的積體電路封裝系統的上視圖；第2圖係第1圖的積體電路封裝系統沿剖面線2-2之之一部分的剖視圖； 第3圖係本發明之第二實施例中積體電路封裝系統的剖視圖；第4圖係在製造之開始階段中第2圖的積體電路封裝系統；第5圖係在製造之第一鍍覆階段中第4圖的結構；第6圖係於製造之黏著物沉積階段中第5圖的結構；第7圖係於製造之被動裝置附接階段中第6圖的結構；第8圖係於製造之層積階段中第7圖的結構；第9圖係於製造之第一圖案化階段中第8圖的結構；第10圖係於製造之脫離階段中第9圖的結構；第11圖係於製造之穿孔形成階段中第10圖的結構；第12圖係於製造之穿孔開口階段中第11圖的結構；第13圖係顯示於製造之沉積階段中第12圖的結構；第14圖係於製造之移除階段中第13圖的結構；第15圖係用於第3圖之積體電路封裝系統的於製造之可替換形成層階段中第9圖的結構；第16圖係於製造之穿孔形成階段中第15圖的結構；第17圖係於製造之脫離階段中第16圖的結構；第18圖係於製造之進一步穿孔形成階段中第17圖的結構；第19圖係於製造之穿孔開口階段中第18圖的結構；第20圖係於製造之沉積階段中第19圖的結構；第21圖係於製造之移除階段中第20圖的結構；以及第22圖係本發明之進一步實施例中的積體電路封裝 系統之製造的方法之流程圖。
下文之實施例係足夠詳細地描述，以使所屬技術領域中具有通常知識者能製作及使用本發明。應該理解的是，其他實施例將基於本發明而為顯而易見，且系統、製程或機構之改變可不悖離本發明的範圍而作出。
在下文的描述中，給出許多特定細節以提供本發明的通透理解。然而，將顯而易見的是，本發明可在沒有這些特定細節的情況下實施。為了避免模糊本發明，未詳細披露一些習知的電路、系統配置和製程步驟。
示出系統之實施例的圖式係半示意性的而非按比例，特別地，一些尺寸係用於清晰度的呈現且係在圖式附圖中誇大。類似地，儘管圖式中用於容易描述的視角通常以類似方向顯示，附圖中之本發明的描繪係任意用於絕大部分。一般而言，本發明可以任何方向進行操作。所揭示及描述之多個實施例具有共同之一些特徵，為了清楚和便於說明、描述及理解它們，一對另一類似及相似的特徵將會通常以類似之參照號碼描述。已編號第一實施例、第二實施例等的實施例係作為方便描述的目的，且不傾向具有任何其它意義或用於提供對本發明的限制。
用於解釋的目的，如本文所用的術語「水平」係定義為平行於平面或平行於最低導電圖案之表面的平面，而不管其方向如何。術語「垂直」意指與如前所述之水平正交的方向。術語「上方」、「下方」、「底」、「項」、 「側」(如在「側壁」)、「較高」、「較低」、「上」、「上面」及「在...之上」係考慮水平平面而定義，如附圖中所顯示。術語「在...上」意謂於元件之間直接接觸。術語「直接在...上」意謂於一元件與另一元件之間直接接觸而無中介元件。
術語「主動側」係稱呼具有製造在該晶粒、模組、封裝件或電子結構上之主動電路的晶粒、模組、封裝件或電子結構之側部，或者具有用於連接該晶粒、模組、封裝件或電子結構內部之主動電路的元件。本文使用之術語「處理」係包含材料或抗蝕劑之沉積、圖案化、曝光、顯影、蝕刻、清洗及/或形成所描述結構要求時的移除該材料或抗蝕劑。
現在參照第1圖，在其中係顯示本發明之第一實施例中的積體電路封裝系統100的上視圖。該上視圖顯示嵌入式組件基板102具有積體電路晶粒104之一部分，積體電路晶粒104係安置在嵌入式組件基板102之頂部上。應瞭解的是，更多晶粒可視要求而安置在嵌入式組件基板102上，但出於說明的目的而僅顯示一個。如暴露之墊或走線的其它特徵亦出於清楚的目的而忽略。嵌入式組件基板102之上表面106可視為環繞積體電路晶粒104。
現在參照第2圖，在其中係顯示第1圖的積體電路封裝系統100沿剖面線2-2之一部分的剖視圖。積體電路晶粒104及嵌入式組件基板102被顯示。嵌入式組件基板102包含如嵌入式組件之組件208，而組件208係直接接觸嵌入材料210並由嵌入材料210所環繞，嵌入 材料210可例如為預浸材(pre-impregnated material(PPG))。組件208可為主動或被動裝置，舉例而言如積體電路晶粒、電容器或電阻器。
上述之嵌入在嵌入材料210中的組件208係為埋藏圖案212，而圖案212為埋藏於遮蔽層214中之導電圖案，以使埋藏圖案212之外表面與遮蔽層214之外表面共平面。舉例而言，遮蔽層214可為抗蝕劑、乾膜、光可成像介電質(photo imageable dielectric)。積體電路晶粒104係通過埋藏圖案212而連接組件208，而埋藏圖案212通過嵌入式組件穿孔216而連接組件208，且嵌入式組件穿孔216通過裝置黏著物218向下延伸以直接連接組件208。組件208下方係為置於嵌入材科210上且位於嵌入材科210外的導電圖案220。嵌入式組件穿孔216將組件208連接至導電圖案220。人們已經發現，埋藏圖案212可在相同圖案中具有如建立於介電質之表面上之具有導電圖案的墊、線段、走線及穿孔，如此，並無伴隨埋藏圖案212的拉線能力損失。
如防焊材之圖案化介電質222係覆蓋埋藏圖案212及導電圖案220，以保護非接觸區域免於腐蝕、偶然的電性短路或其它不欲之外部力量。一些埋藏圖案212之埋藏接觸墊224及導電圖案220之外層接觸墊226係通過圖案化介電質222而暴露。走線228僅通過所顯示之走線228的一部分而連接個別導電圖案之各種接觸墊。
在嵌入式組件基板102之一些部分中，埋藏 接觸墊224係通過穿過嵌入材料210之垂直穿孔230而直接連接外層接觸墊226。舉例而言，埋藏接觸墊224與外層接觸墊226之間的直接連接允許較佳之電訊號的拉線彈性。在此範例中，垂直穿孔230及嵌入式組件穿孔216係以一端較另一端為薄而為錐形(tapered)，但應瞭解的是，此僅係用於說明的目的。舉例而言，若通過與雷射鑽孔相反之機械鑽孔而製作，則垂直穿孔230可為從頭至尾具有相同厚度。
人們已經發現，遮蔽層214中之埋藏圖案212允許於走線228與埋藏接觸墊224之間及於其它走線之間的良好間距控制。舉例而言，藉由使用遮蔽層214以幫助作出埋藏圖案212，具有線寬(LW)或導線寬(WW)之導電圖案導線或走線及具有線段之間的線段間隔(亦稱L/S)可分別為15微米(μm)及15微米(15/15)。稱作LW/LS之該項良好間距為15/15微米或更小。
人們亦已經發現，相較於兩組件表面皆安置，直接附接積體電路晶粒104於組件208上方改進了電性性能。由於通過埋藏圖案212及嵌入式組件穿孔216的在積體電路晶粒104與組件208之間的更短及更直接的電性路徑，舉例而言，大量減少電壓噪訊及阻抗中之壓降，故亦可要求更低電源。
現在參照第3圖，在其中係顯示本發明之第二實施例中積體電路封裝系統300的剖視圖。積體電路晶粒304及嵌入式組件基板302被顯示。嵌入式組件基板302 包含如嵌入式組件的組件308，而組件308係直接接觸嵌入材料310並由嵌入材料310所環繞，嵌入材料310可例如為預浸材。組件308可為主動或被動裝置，舉例而言如積體電路晶粒、電容器或電阻器。
上述之嵌入在嵌入材料310中的組件308係為埋藏圖案312，而埋藏圖案312為埋藏於遮蔽層314中之導電圖案，以使埋藏圖案312之外表面與遮蔽層314之外表面共平面。舉例而言，遮蔽層314可為抗蝕劑、乾膜、光可成像介電質。
積體電路晶粒304係通過埋藏圖案312而連接組件308，而埋藏圖案312通過嵌入式組件穿孔316而連接組件308，且嵌入式組件穿孔316通過裝置黏著物318向下延伸以直接連接組件308。
組件308下方係為具有嵌入材科310之外層上及外部之層狀導電圖案331，且層狀導電圖案331之內層完全由嵌入材科310覆蓋。嵌入式組件穿孔316將組件308連接至層狀導電圖案331。層狀導電圖案331係顯示成通過內部穿孔而連接的雙層結構，雖然應瞭解的是，可使用依需求之任何數目的層。舉例而言，層狀導電圖案331可為三或更多層以增加拉線彈性。
如防焊材之圖案化介電質322係覆蓋埋藏圖案312及層狀導電圖案331的外層，以保護非接觸區域免於腐蝕、偶然的電性短路或其它不欲之外部力量。埋藏圖案312之埋藏接觸墊324及層狀導電圖案331之外層接 觸墊326係通過圖案化介電質322而暴露。走線328僅通過所顯示之走線328的一部分而連接個別導電圖案之各種接觸墊。
在嵌入式組件基板302之一些部分中，埋藏接觸墊324係通過穿過嵌入材料310之垂直穿孔330而直接連接內層接觸墊332。舉例而言，埋藏接觸墊324與內層接觸墊332之間的直接連接允許較佳之電訊號的拉線彈性。在此範例中，垂直穿孔330係以垂直穿孔330之一端較另一端為薄而為錐形，但應瞭解的是，此僅係用於說明的目的。舉例而言，若通過與雷射鑽孔相反之機械鑽孔而製作，則垂直穿孔330可為從頭至尾具有相同厚度。
內部穿孔係連接一些內層接觸墊332至外層接觸墊326，且應瞭解的是，可於針對拉線要求的必需性時調整內部穿孔之位置。層狀導電圖案331之外層的走線328可由圖案化介電質322覆蓋。
現在參照第4圖，在其中係顯示在製造之開始階段中第2圖的積體電路封裝系統100。可看到雙側承載板434，其中例如銅之導電層436可看到同時位在雙側承載板434的二側上。舉例而言，雙側承載板434可為具有介電核心的銅箔基板(CCL)。
現在參照第5圖，在其中係顯示在製造之第一鍍覆階段中第4圖的結構。針對將變成第2圖之埋藏圖案212的沉積而施加遮蔽層214至導電層436並圖案化。舉例而言，用於埋藏圖案212之所使用材料可與導電層436 之材料相同。在所有使用雙側承載板434之步驟中，應瞭解的是，製程之描述係進行在雙側承載板434的兩側。
人們已經發現，藉由針對第2圖之嵌入材料的允許具有PPG積層(laminate)之CCL的替換，在形成積體電路封裝系統100中之本發明的各種實施例提供材料的成本降低。人們亦已經發現，起因於具有對稱結構，雙側承載板434之使用及在二層上的同時處理提供對於高溫片材翹曲的壓抑。
人們亦已經發現，針對形成埋藏圖案212之遮蔽層214的使用可增加可靠性及減少孔穴問題的可能性。當黏著性絕緣體係塗覆或印刷在與遮蔽層214共平面之埋藏圖案212上時，孔穴形成之風險較少。舉例而言，藉由使用環繞導電圖案之光可成像圖案保護性材料，該黏著性絕緣體可塗覆或印刷在較平緩表面上，以減低或消除孔穴問題的風險。在基板或封裝件中之孔穴係引起可靠性技術問題的主要根因。
現在參照第6圖，在其中係顯示於製造之黏著物沉積階段中第5圖的結構。裝置黏著物218係在用於第2圖之組件208的安置之預備中沉積在遮蔽層214及埋藏圖案212上。舉例而言，該沉積可通過例如為塗覆或印刷之製程。
現在參照第7圖，在其中係顯示於製造之被動裝置附接階段中第6圖的結構。組件208係通過裝置黏著物218而附接至埋藏圖案212。裝置黏著物218係水平 地大於組件208。
現在參照第8圖，在其中係顯示於製造之層積階段中第7圖的結構。在此階段，沉積嵌入材料210及一部分將變成第2圖之導電圖案220的基礎導電材料838。該沉積或層積製程可以各種方式發生，且嵌入材料210之部分之間的分離係僅為了清楚明白而顯示。
現在參照第9圖，在其中係顯示於製造之第一圖案化階段中第8圖的結構。舉例而言，可通過例如為遮蔽及鍍覆之製程在嵌入材料210上的基礎導電材料838之頂部圖案化導電圖案220。在形成導電圖案220之前，可通過沉積導電材料之後的例如為鑽孔(雷射或機械)或蝕刻之製程而形成嵌入組件穿孔216及垂直穿孔230。可通過基礎導電材料838及嵌入材料210而形成嵌入組件穿孔216及垂直穿孔230。舉例而言，可通過鍍附而完成該沉積。可接著圖案化導電圖案220以接觸垂直穿孔230、嵌入組件穿孔216及基礎導電材料838。
現在參照第10圖，在其中係顯示於製造之脫離階段中第9圖的結構。在此階段，導電層436可從第4圖之雙側承載板434的核心脫離。應瞭解的是，可以相同方式處理在雙側承載板434之兩側的結構，該方式係於本圖之後描述。亦應瞭解的是，本圖及那些係接著顯示結構，而該結構相較第2圖之積體電路封裝系統100而言為覆晶倒置。應瞭解的是，所顯示結構之方向係僅用於範例，且製程不限於該所顯示方向。
現在參照第11圖，在其中係顯示於製造之穿孔形成階段中第10圖的結構。在此階段，通過例如為蝕刻或鑽孔之製程而將嵌入組件穿孔216形成為穿過導電層及埋藏圖案212。在此範例中，圖案遮蔽1140係用於通過該導電材料的保角(conformal)蝕刻，但停止於裝置黏著物218處。
現在參照第12圖，在其中係顯示於製造之穿孔開口階段中第11圖的結構。在此階段，嵌入組件穿孔216係藉由在裝置黏著物218中使孔洞開口而完成，以暴露組件208的接觸。在此範例中，係藉由雷射鑽孔而將裝置黏著物218開口。
現在參照第13圖，在其中係顯示於製造之沉積階段中第12圖的結構。在此階段，通過裝置黏著物218之嵌入組件穿孔216係以直接接觸組件208之例如為銅的導電材料填充。另外，第11圖之圖案遮蔽1140係在嵌入組件穿孔216填充後移除。
現在參照第14圖，在其中係顯示於製造之移除階段中第13圖的結構。移除第4圖之導電層436及第8圖之基礎導電材料838，完全形成埋藏圖案212及導電圖案。
人們已經發現，埋藏圖案212可在相同圖案中具有如建立於介電質之表面上之具有導電圖案的墊、線段、走線及通孔，如此，並無拉線能力損失伴隨埋藏圖案212。舉例而言，該移除可通過例如為蝕刻的方法。
於該移除階段之後，第2圖之圖案化介電質222係沉積在埋藏圖案212、導電圖案220及嵌入材料210上。這樣完成了第2圖之嵌入式組件基板102的形成。第2圖之積體電路晶粒104係安置在嵌入式組件基板102上，以完成第2圖之積體電路封裝系統100。人們已經發現，通過使用遮蔽層214而形成埋藏圖案212係減少製程缺陷，從而增加產出及可靠性。已發覺的是，先前穿孔在凸塊上(VOB)之結構由於不均勻之電鍍而具有穿孔上方之導電圖案中的不均勻凹坑。以具有與遮蔽層214共平面之表面的埋藏圖案212，將使形成平整之該VOB結構變得更為容易，而減少缺陷的發生率。
現在參照第15圖，在其中係顯示用於第3圖之積體電路封裝系統300的於製造之可替換形成層階段中第9圖的結構。在此階段，完成蝕刻以移除第8圖的基礎導電材料838，且嵌入材料310的另一層層積在導電圖案的頂部上，而該導電圖案將會變成第3圖之層狀導電圖案331的內層。可接著沉積另一外基礎導電層1542在嵌入材料310上。
現在參照第16圖，在其中係顯示於製造之穿孔形成階段中第15圖的結構。內部穿孔可在嵌入材料310中作出，且通過外基礎導電層1542以與連接組件308之嵌入式組件穿孔316排列。該內部穿孔可接著於圖案化在外基礎導電層1542之表面上的層狀導電圖案331之外層的同時以例如為銅的導電材料填充。應瞭解的是，該內部 穿孔中之填充及沉積層狀導電圖案331之該外層可同時或分開完成。
現在參照第17圖，在其中係顯示於製造之脫離階段中第16圖的結構。該結構係以相較於第3圖之積體電路封裝系統300的方向而以覆晶方向顯示，但應瞭解的是，該方向係僅用於說明而顯示，且任何方向都有可能。
現在參照第18圖，在其中係顯示於製造之進一步穿孔形成階段中第17圖的結構。在此階段中，嵌入式組件穿孔316係通過例如為蝕刻或鑽孔之製程穿過導電層436及埋藏圖案312而形成。在此範例中，針對通過該導電材料之保角蝕刻而使用圖案化遮蔽1840，但停止於裝置黏著物318處。
現在參照第19圖，在其中係顯示於製造之穿孔開口階段中第18圖的結構。在此階段中，嵌入式組件穿孔316係藉由在裝置黏著物318中將孔洞開口以暴露組件308之接觸而完成。在此範例中，裝置黏著物318係由雷射鑽孔開口。
現在參照第20圖，在其中係顯示於製造之沉積階段中第19圖的結構。通過裝置黏著物318之嵌入式組件穿孔316係以直接接觸組件308之例如為銅的導電材料填充。圖案化遮蔽1840可於填充嵌入式組件穿孔316之後移除。
現在參照第21圖，在其中係顯示於製造之移除階段中第20圖的結構。移除第4圖之導電層436及第 8圖之基礎導電材料838，完全形成埋藏圖案312及層狀導電圖案331。舉例而言，該移除可通過例如為蝕刻的方法。
接著該移除階段，第3圖之圖案化介電質322係沉積在埋藏圖案312、層狀導電圖案331及嵌入材料310上。這樣完成了第3圖之嵌入式組件基板302的形成。第3圖之積體電路晶粒304的安置完成了第3圖之積體電路封裝系統300。
人們已經發現，上述描述之用於形成積體電路封裝系統300的無核心製程流程允許層狀導電圖案331之層的輕易延伸。由於嵌入材料310係組合為僅有必需厚度，且額外厚度可輕易增加，層狀導電圖案331之額外層係藉由添加另一層嵌入材料310及接著在頂部圖案化導電層而相對簡單添加。這樣允許只有少許成本增加的較佳之拉線選擇。
現在參照第22圖，在其中係顯示本發明之進一步實施例中的積體電路封裝系統100之製造的方法2200之流程圖。方法2200包含：在方塊2202中於被動裝置上形成嵌入材料；在方塊2204中於該嵌入材料上沉積乾膜層；在方塊2206中圖案化該乾膜層；在方塊2208中於該乾膜層中沉積埋藏圖案，該埋藏圖案之外表面係與該乾膜層之外表面共平面，該埋藏圖案電性連接該被動裝置；在方塊2210中於該埋藏圖案之一部分上形成圖案化介電質；以及在方塊2212中於該埋藏圖案上安置積體電路。
作為結果之方法、製程、設備、裝置、產 品及/或系統係為簡單、具有成本效益、不複雜、高度通用、準確、靈敏及有效的，並且可藉由為準備、高效及經濟製造、應用及利用的適應已知組件而實現。
本發明之另一重要態樣係它有價值地對降低成本、簡化系統及增加性能的歷史趨勢支持及服務。
本發明的這些及其它有價值的態樣因此促進技術狀態至至少下一新的階段。
雖然本發明已與特定最佳模式結合，但應當理解的是，許多替代、修飾及變化將對所屬技術領域中具有通常知識者於對上文描述之啟示中為清楚明白的。因此，意在含括所有這樣落入所附申請專利範圍之範疇內的替代、修飾及變化。所有本文闡述或在所附圖式中示出之標的是以說明性及非限制性的意義而解釋。
102‧‧‧嵌入式組件基板
104‧‧‧積體電路晶粒
208‧‧‧組件
210‧‧‧嵌入材料
212‧‧‧埋藏圖案
214‧‧‧遮蔽層
216‧‧‧嵌入式組件穿孔
218‧‧‧裝置黏著物
220‧‧‧導電圖案
222‧‧‧圖案化介電質
224‧‧‧埋藏接觸墊
226‧‧‧外層接觸墊
228‧‧‧走線
230‧‧‧垂直穿孔

Claims (10)

  1. 一種製造積體電路封裝系統之方法，係包括：在組件上形成嵌入材料；在該嵌入材料上沉積遮蔽層；圖案化該遮蔽層；在該遮蔽層中沉積埋藏圖案，該埋藏圖案之外表面係與該遮蔽層之外表面共平面，該埋藏圖案電性連接該組件；在該埋藏圖案之一部分上形成圖案化介電質；以及在該埋藏圖案上安置積體電路晶粒。
  2. 如申請專利範圍第1項所述之方法，其中，該嵌入材料係預浸材(pre-impregnated material)。
  3. 如申請專利範圍第1項所述之方法，其中，沉積該埋藏圖案包含沉積具有埋藏接觸墊之該埋藏圖案；以及形成該圖案化介電質包含形成讓該埋藏接觸墊暴露的該圖案化介電質。
  4. 如申請專利範圍第1項所述之方法，復包括在該嵌入材料上形成導電圖案，該導電圖案在該組件反向於該該埋藏圖案的一側上電性連接於該組件。
  5. 如申請專利範圍第1項所述之方法，復包括形成用以將該埋藏圖案電性連接至該組件的嵌入組件穿孔。
  6. 一種積體電路封裝系統，係包括：嵌入材料，係在組件上； 遮蔽層，係在該嵌入材料上；埋藏圖案，係在該遮蔽層中，該埋藏圖案之外表面係與該遮蔽層之外表面共平面，該埋藏圖案電性連接該組件；圖案化介電質，係在該埋藏圖案之一部分上；以及積體電路晶粒，係在該埋藏圖案上。
  7. 如申請專利範圍第6項所述之系統，其中，該嵌入材料係預浸材。
  8. 如申請專利範圍第6項所述之系統，其中，該埋藏圖案係具有通過該圖案化介電質所暴露的埋藏接觸墊。
  9. 如申請專利範圍第6項所述之系統，復包括在該嵌入材料上的導電圖案，該導電圖案電性連接在該組件反向於該埋藏圖案之一側上的該組件。
  10. 如申請專利範圍第6項所述之系統，復包括將該埋藏圖案電性連接至該組件的嵌入組件穿孔。
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US20150171002A1 (en) 2015-06-18
CN104716057A (zh) 2015-06-17
US9171795B2 (en) 2015-10-27
TWI628772B (zh) 2018-07-01
KR20150070012A (ko) 2015-06-24

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