TW201530205A - 積體模組及其形成方法 - Google Patents
積體模組及其形成方法 Download PDFInfo
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- TW201530205A TW201530205A TW103141865A TW103141865A TW201530205A TW 201530205 A TW201530205 A TW 201530205A TW 103141865 A TW103141865 A TW 103141865A TW 103141865 A TW103141865 A TW 103141865A TW 201530205 A TW201530205 A TW 201530205A
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- 230000005693 optoelectronics Effects 0.000 title description 60
- 230000003287 optical effect Effects 0.000 claims abstract description 99
- 239000000758 substrate Substances 0.000 claims description 105
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Classifications
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- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
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- H—ELECTRICITY
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- H01L31/12—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto
- H01L31/14—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the light source or sources being controlled by the semiconductor device sensitive to radiation, e.g. image converters, image amplifiers or image storage devices
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- G02B6/42—Coupling light guides with opto-electronic elements
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
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- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
- G02B6/4228—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements
- G02B6/4232—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements using the surface tension of fluid solder to align the elements, e.g. solder bump techniques
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- G02B6/24—Coupling light guides
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- G02B6/4274—Electrical aspects
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- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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Abstract
一種積體模組,包含至少兩個單元,其中一第一單元包含在第一面之一光元件及電接墊及一相對之一第二面,一第二單元具有電接墊且該第二單元藉由匹配第一單元之電接墊而和第一單元接合。一光訊號自一外部介質經由一部份蝕刻開口,一蝕穿開口,或一位於該第一單元之第二面之抗反射層而進入光元件。該部分蝕刻開口可在第一單元以使光訊號由相對第一面之第二面表面入射到光元件;該蝕穿開口可在第二單元,以使光線經由第二單元一部份而入射到光元件。在將第一單元接合到第二單元時,可使用突起/凹陷成對結構以增加對準精確度。
Description
本發明是關於一種積體模組,特別是關於一種有助於光耦合之積體模組。
光耦合為光電元件之重要課題。如圖1A所示,相關技術之光電元件通常係直接由上方將光耦合到光學元件,其中可用一透鏡(未圖示)以將光束聚焦於元件。
光學元件,如同大多電子元件,係位在晶圓之上表面,因此傳統上係由上方耦合光線。但是光電訊號一般需要高頻寬,對於高資料傳輸應用,覆晶封裝可提供更細節距及更高可靠度,因此逐漸取代傳統的導線封裝。然而,傳統之製程中都在晶圓表面製作光學元件及電子元件,若光學元件覆晶封裝在另一晶片上,光路徑會被遮蓋。因此如圖1B所示,在導線封裝架構下,電訊號係藉由焊接線而由光IC102傳遞到基板103。
依據本發明之一目的,本發明提供一種積體模組,包含:一第一單元包含在第一面之一光元件及電接墊,及在第二面之抗反射包覆層,該第二面與該第一面相對;一第二單元包含在一第一面之電接墊,及與該第一面相對之第二面;一光訊號自一外部介質進入該第一單元之該第二面;其中藉由對準該第一單元及該第二單元至少一對電接墊,該第一單元之該第一面接合到該第二單元之該第一面。
依據本發明之另一目的,本發明提供一種積體模組,包含:一第一單元包含在第一面之一光元件及電接墊,及與該第一面相對之一第二面;一第二單元包含在一第一面之電接墊,及與該第一面相對之第二面;一光訊號自一外部介質進入該第一單元之該第一面;其中該第一單元之該第一面係接合到該第二單元之該第一面,且該第一單元之該光元件上之區域係露出以提供一未被該第二區域覆蓋之開口。
依據本發明之另一目的,本發明提供形成一種積體模組之方法,包含:在一第一半導體基板形成一表面突起結構及一第一電接墊;在一第二半導體基板形成一表面凹陷結構及一第二電接墊;將該第一半導體基板置於該第二半導體基板之上且使該表面突起結構大致上與該表面凹陷結構匹配,並使該第一電接墊與該第二電接墊對準;施加包含加熱、加壓或其組合之化學或是物理力以接合該第一半導體基板及該第二半導體基板。
藉由上述之積體模組及其形成方法,即可將光線由光元件所在側面的相對另一面耦合進來,避免光路徑被遮蔽。
102‧‧‧光IC
103‧‧‧基板
100‧‧‧基板
102‧‧‧焊接線
108‧‧‧凹槽
130‧‧‧焊球
200‧‧‧光電IC
202‧‧‧光元件
208‧‧‧切口區
220,320‧‧‧電接墊
240,340,440‧‧‧TSV
250,309,22‧‧‧OTSV
300‧‧‧電子IC
400‧‧‧中介層
260‧‧‧突起結構
360‧‧‧凹陷結構
10a‧‧‧光電元件
10‧‧‧鍺層
14‧‧‧鈍化層
12a‧‧‧第一接點
12b‧‧‧第二接點
20‧‧‧矽晶圓
24‧‧‧可選擇性層
32‧‧‧矽層
30‧‧‧除絕緣層
14a‧‧‧第一鈍化層
14b‧‧‧第二鈍化層
圖1A及1B為相關技術之光電元件封裝。
圖2A顯示本發明一實現方式之光電積體電路之側視圖。圖2B則為此光電積體電路之上視圖。
圖3顯示另一側向耦合封裝架構,其使用具有矽導孔(TSV)之中介層。
圖4A顯示另一側向耦合封裝架構之立體圖,圖4B顯示圖4A之側視圖。
圖5A及5B顯示依據另一耦合方式之封裝架構,亦即前面正向耦合架構。
圖6A,6B,6C顯示依據其他範例之前面正向入射封裝架構之側視圖。
圖7顯示另一範例之前面正向入射封裝架構之側視圖,其中光電IC沒有覆晶所需的TSV。
圖8A及8B顯示其他範例之前面正向入射封裝架構之側視圖。
圖9A及9B顯示其他範例封裝架構之側視圖,其中電子IC具有一蝕穿OTSV。
圖10及10B顯示其他範例之封裝架構之側視圖。
圖11A顯示另一範例封裝架構之側視圖;而圖11B為對應之立體圖。
圖11C顯示另一範例封裝架構之側視圖。
圖12A-12D顯示依據一實施方式之製作具有OTSV之光電IC流程側視圖。
圖13A-13E顯示依據另一實施方式之製作具有OTSV之光電IC流程側視圖。
圖14A-14G顯示依據另一實施方式之製作具有OTSV之被動光學元件流程側視圖。
圖15A-15C顯示依據其他範例的積體模組之側視圖。
圖16A-16E顯示依據其他範例的積體模組之側視圖。
圖17A-17C顯示數個三維對準標記範例之立體圖,其可增加接合過程的對準精確度。
本發明之其他目的、特徵及優點將自以下詳細揭示內容、自隨附申請專利範圍及自圖式顯現。此外,如第一、第二、上方、左方、以及類似用語是描述相對位置用,且在相對於圖示中以圖繪說明的範例實施方式中使用該等術語,並且該等術語可在特定情況下交互使用。
在本發明中,光電IC係界定為具有至少一個光元件(如光偵測器、雷射、光調變器、波導或是光耦合器)之晶片。光電IC中也可包含(但是不須一定要有)電子元件(如電晶體);或也可包含(但是不须一定要有)微機電元件(如多軸微調器可用於光纖對準)。另一方面,電子IC則為具有至少一電子元件(如CMOS電晶體或BJT)之晶片。電子IC可包含諸多智財單元如HDMI控制器(物理層或MAC層)、USB控制器(物理層或MAC層)、轉阻放大器、等化器、DSP單元,電力管理單元、PCle控制器、無線連接電路單元(如WiFi, 藍牙、Zigbee,4G/5G及後續技術)。換言之,一電子IC可為高整合電路以將原始電訊號(在由光電IC將光訊號轉換成電訊號後)轉換成多種有線或無線連接協定。基於此定義,光電IC範疇較電子IC更為廣泛,此因光電IC也可包含前述電路方塊。
圖2A顯示本發明一實現方式之光電積體電路200之側視圖。圖2B則為此光電積體電路200之上視圖。
如圖2A所示,一種傳統將光訊號與電訊號分開方法是將光線由晶片側面耦合進來。在製作後,光電晶圓會切成多個晶片,每一晶片側面需拋光(研磨)以形成光學晶面(通常覆上抗反射包覆層)。隨後光線會由光纖(未圖示)耦合到光電IC 200,並由拋光面206之波導204進入。在一些封裝架構,光線不會直接耦合到主動光元件(如光偵測器或是雷射),而是經由一被動光元件如波導204(如矽或是三五材料條狀波導)耦合。側向耦合之優點為封裝整體高度可降低。此外,如圖2B所示,一切口區208界定於光電IC之光進入側,以協助光纖對準。對於其他耦合方式,光線可直接耦合到主動光電元件(正向耦合)或光線可經由波導耦合後再導光至主動光線元件(如前述之側向耦合方式)。
圖3顯示另一側向耦合封裝架構,其使用具有矽導孔(TSV)之中介層。具有光元件202(如光偵測器)之光電IC200安裝在具有TSV440之中介層400之上。一電子IC300也安裝在中介層400之上,並且可和光電IC200共平面。光電IC200及電子IC300分別在其安裝面具有電連接至TSV440之電接點220及320。中介層400經由焊球130或其他接合機制而安裝在一基板100之上,TSV40也電連接至對應之焊球130。光線由光電IC200之拋光面進入且經由一波導(未圖示)行進至此光偵測器202。光偵測器202產生對應接收光線之電訊號,且經由中介層400之電路徑傳送到電子IC300。
圖4A顯示另一側向耦合封裝架構之立體圖。與圖3範例相比,係在電子IC300之中而非在中介層400之中設立TSV,且電子IC300係直接覆晶安裝在光電IC200上,圖4B顯示圖4A之側視圖,具有光元件202(如光偵測器)之光電IC200安裝在具有TSV340之電子IC300(如TIA)之上。此電子IC300係經由焊球130或其他焊接機制(如銅導柱)而安裝在基板100之上。光線由光電IC200之研磨面入射且經由一波導(未圖示)而行進到光偵測器202。光偵測器202產生對應接收光線之電信號且將電訊號傳送至電子IC300。如圖4A所示,在光電IC200之光進入面上有一切口區208以輔助光纖耦合。在電子IC200中使用TSV可不須使用額外之中介層,然因額外之TSV製程,電子IC之製作費用可能會提高。
圖5A及5B顯示依據另一耦合方式之封裝架構,亦即前面正向耦合架構(前面即定義為最接近光電元件之側面)。如圖5A所示,在第一面上具有光元件202(如光偵測器)之光電IC200更包含TSV延伸於第一面及第二面(在第一面對面)之間。如圖5B所示,光電IC200例如可以覆晶方式安裝於電子IC300之上。此電子IC300係藉由電接墊320而電連接至基板100之上。在此封裝架構中,光線由大致垂直於第一面方向入射到光偵測器202中。光偵測器202產生對應接收光線之電訊號且將此電訊號經由TSV 240而傳送到電子IC300。在此實例中,信號最敏感之路徑係由光電IC200到電子IC300,所以此兩個IC之間連接採取覆晶封裝。經過電子IC處理後較為不敏感之電訊號(如經由TIA放大及濾波之訊號)可經由焊接線而連接到基板100(如印刷電路板)。
圖6A,6B,6C顯示依據其他範例之前面正向入射封裝架構之側視圖。如圖6A所示,在第一面上具有光元件202(如光偵測器)之光電IC200更包含TSV240延伸於第一面及第二面(在第一面對面)之間。此光電IC200經由焊球130或是其他接合機制(如AuSn或是Au柱)而安置在基板100之上,且TSV240也電連接至對應之焊球130。一電子IC300(如TIA)係由焊球130而安置在基板100之上且大致上與光電IC200共平面。電子IC300具有對應於焊球130之電接墊320。光線由大致垂直於第一面方向入射到光偵測器202中。光偵測器202產生對應接收光線之電訊號且將此電訊號經由TSV240、焊球130及電接墊320而傳送到電子IC300。在此實例中,光電IC200及電子IC300皆以覆晶方式安裝在基板100之上而非使用焊接線,但此種架構佔據較大空間。此外,在光電IC200中加入TSV可能降低良率,且TSV之高速效能仍須驗證。
如圖6B所示,此封裝架構包含在光電IC200及電子IC300之間的中介層400。此中介層400可提供光電IC200及電子IC300與基板100之間的低成本橋接。和圖6A架構相比,此中介層400可將IC(如光電IC200及/或電子IC300)之較小節距(如小於50um)接墊橋接至基板100(如印刷電路板)之較大節距(如大於50um)焊墊。此中介層400在與IC接合那面具有較小節距之焊墊,且經由內部繞線440而再與具有較大節距焊墊的基板連接。
圖6C顯示另一範例之前面正向入射封裝架構之側視圖。和前面幾個範例比較,此範例有較小尺寸但是光電IC200及電子IC300都需有TSV,因此可能會提高製程難度及降低製程良率。但是此範例可藉由覆晶封裝而降低互連距離及提高整體效能。如果需要,此電子IC也可以將由光電IC端之較小節距接墊傳來的訊號轉接到基板較大節距的接墊上。整體而言,在光電IC200及電子IC300兩者上加入TSV可能會降低良率,然有助於降低尺寸及提升訊號耦合。因此依據設計者權衡成本及效能,本實例可作為設計選項之一。
圖7顯示另一範例之前面正向入射封裝架構之側視圖,其中光電IC200沒有覆晶所需的TSV。在圖7中,具有光元件202(如光偵測器)及電接墊220之光電IC200係經由焊球130而懸掛在基板100之下,其中光元件202上面露出之區域即為光纖耦合區域。具有電接墊320之電子IC300 (如TIA)也經由焊球130懸掛於基板100之下。此電子IC300大致上與光電IC200共平面。光線自光元件202上方大致以垂直光元件202所在側面方向入射。在一些實施方式中,光線係射入光檢測器202且光檢測器202產生對應入射光之電訊號;此電訊號經由電接墊220、焊球130、基板100及電接墊320而傳送到電子IC300。
圖8A及8B顯示其他範例之前面正向入射封裝架構之側視圖。在圖8A中,具有光元件202(如光偵測器)及電接墊220之光電IC200係經由電接墊而懸掛於電子IC300(例如TIA)之下,其中光元件202上面露出之區域即為光纖耦合區域。具有TSV 340之電子IC300係分別電連接至光電IC200之電接墊220及基板100。
在圖8B之中,具有光元件202(如光偵測器)及電接墊220之光電IC200係經由電接墊而懸掛於具有TSV440之中介層400之下。此中介層400再經由焊球130而懸掛於一基板100之下。具有電接墊320之電子IC300也連接於中介層400之下,且可與光電IC200共平面。與圖8A相比,光電IC200及電子IC300都不需要TSV,且光電IC200及電子IC300都以覆晶方式懸掛於中介層400之下以達成高資料傳輸率應用。光線自光元件202上方大致以垂直光元件202所在側面方向入射。在一些實施方式中,光線係射入光檢測器202且光檢測器202產生對應入射光之電訊號此電訊號經由電接墊220、中介層400之TSV及內部繞線440及電接墊320而傳送到電子IC 300。
光電IC耦合之重要課題為光訊號及電訊號通常皆位於同側。若為了高資料傳輸率而採取覆晶接合,光耦合區必須暴露出來或是需由TSV將電訊號傳送到晶片之另一側。採取如圖7,8A,8B所示之懸掛式架構可將光耦合區露出,然會使整體結構強度減弱。本發明提出一光學TSV(OTSV)架構以解決此問題。在下列說明中將配合圖示說明數個OTSV架構,及本發明之OTSV與傳統之TSV之不同處。傳統之TSV係用於傳遞電訊號或是導熱,因此需填充金屬。然而對於本發明之OTSV,其功能為通過光線,因此可不需充填。再者,TSV因為要傳送不同電訊號而需要龐大數量;然需傳遞光訊號之數量遠比電訊號少,因此OTSV數量會較少。再者,TSV之製程控制需求較高,因為電訊號(尤其高頻訊號)會受尺寸變化影響;而OTSV則不受尺寸變化影響。為了在覆晶應用中使光耦合與電耦合分開,OTSV之製程可更為簡易且可提供高資料傳輸率。本發明提供兩種OTSV架構:蝕穿(etch-through)OTSV及部份蝕刻(partially etched)OTSV。
圖9A及9B顯示其他範例封裝架構之側視圖,其中電子IC300(例如TIA)具有一蝕穿OTSV(亦可稱為蝕穿凹槽)以將光電IC之光耦合區域暴露出來,此光電IC200係覆晶接合到電子IC300。在圖9A所示架構中,電子IC300具有OTSV308,其與光電IC200之光元件202對準,該光電IC200更具有電接墊220。光電IC200之光元件202及電接墊220都位於此光電IC200之第一面。光電IC200另具有和第一面相對之第二面且此第二面係安置在一基板100之上。電子IC300之OTSV308例如可由光阻佈形及蝕刻而形成,且其半徑可經設計而與光耦合裝置(如光纖)匹配。在覆晶安裝步驟中,開口區域係與在光電IC200之光元件202對齊。在蝕刻步驟前,可對此電子IC 300可選擇性地進行一薄化製程,以有利於蝕刻製程。光線自大致上和光元件202設置表面垂直之方向射入此OTSV308。在一些實施方式中,光線射入光偵測器且光偵測器將接收光線轉換成電訊號。此電訊號經由焊接線102傳送到基板100,或是經由光電IC200之電接墊220及電子IC300之電接墊320而傳送到TIA300。再者,此電訊號可先傳送至電子IC300,經過放大後再傳回光電IC200,再經由焊接線送到基板。
在圖9B中,具有OTSV308之電子IC300係安置在具有光元件202(如光檢測器)之光電IC200上。光電IC200之光元件202及電接墊220都位在光電IC200之第一面上,且透過TSV經由焊球130連接到基板100。和圖9A之範例相較,此範例之光電IC200更包含TSV240,以提供第一面及第二面間之電連接。電子IC300之OTSV308例如可由光阻佈形及蝕刻而形成,以露出在其下之光電IC200之光耦合區。光線自大致上和光元件202設置表面垂直之方向射入此OTSV308。在一些實施方式中,光線射入光偵測器且光偵測器將接收光線轉換成電訊號。此電訊號經由TSV240及焊球130傳送到基板100,或是經由光電IC200之電接墊220及TIA300之電接墊320而傳送到TIA300,經過放大後再傳回光電IC,再經由覆晶接合送到基板。
接續前述範例,TSV也可用於電子IC而非用於光電IC,且焊接線可用來將電訊號自電子IC傳送到基板。在圖10A所示範例中,具有OTSV308之電子IC300係安置於具有光元件202及電接墊220之光電IC200之上。電子IC300之OTSV308例如可由光阻佈形及蝕刻而形成,以露出在其下之光電IC200之光耦合區域。電子IC300更包含電連接到其下光電IC200電接墊220之TSV340。光電IC200之光元件202及電接墊220係位在其第一表面上,且光電IC200具有與第一表面相對且安置於基板100之上的第二表面。光線自大致上和光元件202(如光偵測器)設置表面垂直之方向射入此OTSV308。在一些實施方式中,光線射入光偵測器且光偵測器將接收光線轉換成電訊號。此電訊號經由電子IC300之TSV340及焊接線102傳送到基板100。在一些實施方式中,此光元件202可為雷射、且電訊號係由基板100經由焊接線102傳送至電子IC (雷射驅動器)300再經由TSV340傳送至雷射202,且在圖10A範例中的焊接線102長度可由圖10B所示基板的凹槽108而縮短。
前述幾個範例中的蝕穿OTSV都涉及在兩個IC其中之一的焊接線或是傳統TSV。此處更進一步揭露使用在基板上之凹槽,以使電子IC可以覆晶接合方式安裝在基板上的封裝實例。在此實例中,光電IC或是電子IC不具有傳統TSV且使用覆晶接合。圖11A顯示此範例封裝架構之側視圖;而圖11B為對應之立體圖。在圖11A中,具有一OTSV308之電子IC300係安裝在具有光元件202(如光檢測器或是雷射)及電接墊220之光電IC200上。電子IC300之OTSV308例如可由光阻佈形及蝕刻而形成,以露出在其下之光電IC200之光耦合區域。電子IC300更包含電連接到其下光電IC200電接墊220及基板100之電接墊320。光電IC200之光元件202及電接墊220係位於光電IC200之一第一面上,光電IC200具有與第二面相對且面對基板100之第二面。光電IC200及於其上的電子IC 300係位於界定在基板100上的凹槽108中。凹槽108之深度可使電子IC300可安置在基板100上,且電子IC300之電接墊320可藉由接合機制(如焊球、銅導柱、金或其他具有適當高度之機制)而與基板100之電接墊接觸,且光電IC200可至少部份被崁入凹槽108之中。光線自大致上和光偵測器元件202設置表面垂直之方向射入此OTSV308。在一些實施方式中,光線射入光偵測器202且光偵測器202將接收光線轉換成電訊號。此電訊號經由電子IC300傳送到基板100。基本上,電子IC 300係以覆晶方式接合到基板,且此架構中沒有任何傳統TSV。在此封裝架構中也可使用光發射元件。例如,此光電IC可包含LED或是雷射,且電子IC可包含驅動此LED或是雷射之驅動器。光線由光電IC射出此OTSV308。
此外,圖11A之架構可經修改而得到如圖11C所示之架構。一電子IC300係安置於一光電IC200之上,此光電IC200包含光元件202(例如光檢測器或是雷射)及電接墊220。此電子IC300更包含電連接到光電IC200之電接墊220及其下基板100之電接墊320。光電IC200之光元件202及電接墊220係位於此光電IC200之第一面,而光電IC200具有與第二面相對且面對基板100之第二面。光電IC200係位於界定在基板100的凹槽108中。凹槽108之深度可使電子IC300可安置在基板100上且電子IC300之電接墊320可藉由接合機制而與基板100之電接墊接觸,且光電IC200可至少部份被崁入凹槽108之中。在光元件202之上的區域被露出以做光耦合。在光電IC200及電子IC300之間訊號可藉由電接墊220,320及內部繞線而傳送,此電訊號可傳送到基板以做更進一步處理。
傳統上大多使用主動對準方式達成光纖及元件之間的對準。此種對準需要機器輔助回授系統以移動光纖且在同時量測由光纖進入元件之耦合光量;藉此在耦合光量滿足一臨界條件時,即可固定光纖。此種傳統主動式對準係為一種遞迴過程且產能較低。為了達成大量生產需求,實有被動對準方法需求,亦即在不藉由遞迴量測及回授系統,即可使光纖藉由***動作而得到對準之架構。一種用於前面正向入射之耦合封裝架構係在光電元件頂面成長厚材料層,再藉由蝕刻形成凹洞以露出元件(如光偵測器),以有利於光纖***。然而,由於應力因素,在元件頂面成長之材料層不能太厚,因此上述方式僅能提供有限的光纖支撐(通常光纖直徑大於10um)。因此對於前面耦合封裝架構而言,較為實際方式係要使用外部模組以提供機械支撐並穩定光纖位置。此外部模組再藉由元件外部的尖針及在矽基板洞孔之間的配合而固定在晶片上。然而此種方式仍未能提供光纖及光電元件之間的直接對準;此方式僅能提供非直接對準,亦即由光纖至模組之對準,接著由模組至光電元件之對準實現。在下列說明中,可由部份蝕刻光學TSV提供直接之光纖對光電元件對準,且此說明由製作程序開始說明。
圖12A-12D顯示依據一實施方式之製作具有OTSV之光電IC流程側視圖。如圖12A所示,在步驟S10首先提供一矽晶圓20、並於矽晶圓20表面上可由磊晶成長、接合、或是其他方式形成一鍺層10。
如圖12B所示,在步驟S12,前段製程(FEOL)及後段製程(BEOL)進行後可形成鍺光檢測器10a,例如可佈形一鍺平台,然後將此平台覆上一層鈍化層14及形成第一接點12a與第二接點12b。第一接點(例如電接墊)12a提供鍺光檢測器10a之電連接;而第二接點12b提供矽晶圓20一面之電連接(在部份鍺層被蝕去後)。BEOL如金屬化、CMP亦可在步驟S10及S12之間進行。在此說明中,形成光電元件之FEOL及BEOL之詳細順序並未界定,本說明要旨在說明形成光電元件之FEOL及BOEL大部分進行完後之製作OTSV的關鍵步驟。
如圖12C所示,在步驟S14,此晶圓10係翻轉過來,使背面對準參考至一前面對準標記(未圖示)。待形成之光耦合區即變成位於光電元件10a之上,且隨後進行圖形化及蝕刻。此蝕刻製程可採用乾蝕刻、溼蝕刻或兩者組合。依據一種實現方式, 蝕刻時間需良好控制以避免蝕刻到光電元件區域。例如對於鍺光偵測器10a,可採用對於矽-鍺有選擇性之蝕刻程序。參考圖12C,若有部分之矽層覆蓋於該鍺光偵測器10a上,該部份之矽可作為光纖(外部媒介)***OTSV22時作為聚光之透鏡。在鍺光偵測器10a上之矽晶圓20部份厚度,例如可小於250um。依據另一實例,在鍺光偵測器10a上之矽晶圓20部份厚度,例如可小於200um。OTSV22及前述在鍺光偵測器10a上之矽晶圓20部份總體而言可在鍺光偵測器10a上提供一結構上之盲溝槽(盲孔)。然而就光學觀點,OTSV22及矽晶圓10功效上可作為光學通孔,以將光線傳導至鍺光偵測器10a。在步驟S14之後, OTSV22基本上已經界定於矽晶圓10上。步驟S16為一選擇性步驟,可提供更加耦合效率。如圖12D所示,在步驟S16,一可選擇性層24,例如氮化矽層,係沈積於矽晶圓10上,以作為抗反射覆層或部份鏡面層,使光線可更有效耦合到光元件。此OTSV22不僅可如前所述將光線耦合到主動元件(如鍺光偵測器10a或是雷射),也可以將光線耦合到被動元件,如波導、光柵耦合器、陣列波導光柵(AWG)或用於WDM之Echelle光柵。
圖13A-13E顯示依據另一實施方式之製作具有OTSV之光電IC流程側視圖,其中使用了SOI晶圓及使用埋入氧化層作為蝕刻阻止層。如圖13A所示,在步驟S20首先提供一SOI晶圓20、一絕緣層30及一矽層32。於矽層32表面上可由磊晶成長、接合、或是其他方式形成一鍺層10。
如圖13B所示,在步驟S22,進行FEOL及BEOL製程後可形成一鍺光偵測器10a,例如鍺層圖案。然後將此鍺層佈形並覆上一層鈍化層14及形成第一接點12a與第二接點12b。第一接點(例如電接墊)12a提供鍺光檢測器10a之電連接;而第二接點12b提供矽晶圓20一面之電連接(在部份鍺層被蝕去後)。BEOL如金屬化、CMP亦可在步驟S10及S12之間進行。在此說明中,形成光電元件之FEOL及BEOL之詳細順序並未界定,本說明要旨在說明形成光電元件之FEOL及BEOL大部分進行完後之製作OTSV的關鍵步驟。
如圖13C所示,在步驟S24,此SOI基板係翻轉過來,使背面對準參考至一前面對準標記(未圖示)。待形成之光耦合區即變成位於光電元件10a之上,且隨後被進行圖形化及蝕刻。此蝕刻製程可採用乾蝕刻、溼蝕刻或兩者組合。此絕緣層30可作為蝕刻阻止層,再者,採用對於矽-絕緣體(如氧化物或是氮化物)有選擇性之蝕刻程序較佳。
在步驟S24,若絕緣層30及矽層32之厚度未調整到匹配入射光波長,光耦合效率仍然不佳。如圖13D所示,於步驟S26,一個可選擇之第二次蝕刻可隨後進行以修正絕緣層30厚度。雖然在上文中使用“第二次蝕刻“,但是實際上可由和第一次蝕刻相同之配方,或在同一蝕刻槽進行完第一次蝕刻後立即進行第二次蝕刻。此蝕刻可為乾蝕刻、溼蝕刻或兩者組合。例如,可用單一溼蝕刻步驟即可在不使下面矽層32粗糙化的狀況下移除絕緣層30。若絕緣層30完全被移除,可選擇性地進行另一溼蝕刻以使矽層32厚度變薄。如前所述,絕緣層30及矽層32之厚度也是設計參數,並取決於入射波長及材料等參數。此種厚度校調僅會影響效能,但是不影響本發明實質功能。上述厚度選擇為元件最佳化程序一部份,且基於上述概念的厚度變化皆在本發明範圍內。
如圖13E所示,在步驟S26,一可選擇性層24係沈積以作為抗反射覆層或部份鏡面層,使光線可更有效耦合到光元件。
圖14A-14G顯示依據另一實施方式之製作具有OTSV之被動光學元件流程側視圖。如圖14A所示,在步驟S30首先提供一SOI晶圓20、一絕緣層30及一矽層32。於矽層32表面上可由磊晶成長、接合、或是其他方式形成一鍺層10。
如圖14B所示,在步驟S23,可進行FEOL及BEOL製程(該些製程包含光阻佈形、蝕刻及沈積等)以形成一被動光電元件12a(例如矽條狀波導,或是光柵耦合器,或是45度角鏡)。BEOL如金屬化、CMP亦可在步驟S30及S32之間進行。在此說明中,形成矽波導(或其他被動元件)之FEOL及BEOL之詳細順序並未界定,本說明要旨在說明形成被動元件之FEOL及BEOL大部分進行完後之製作OTSV的關鍵步驟。再者,雖然在圖示中將第一鈍化層14a及第二鈍化層14b畫成不同之層,但是可用相同材料製成(例如使用氧化物)。
如圖14C所示,如不採取步驟S32,可採取替代的步驟S32’,亦即進行FEOL及BEOL以製作另一種矽波導(脊狀波導12b),其中在波導兩側仍有部份之矽殘留部份。對於步驟S32及S32’,隨後之步驟大致相同。為了簡化說明,在下面說明係以矽條狀波導12a作為範例。
如圖14D所示,在步驟S34,此SOI基板係翻轉過來,使背面對準參考至一前面對準標記(未圖示)。待形成之光耦合區即變成位於被動光電元件12a之上,且隨後被進行圖形化及蝕刻。此蝕刻製程可採用乾蝕刻、溼蝕刻或兩者組合。此絕緣層30可作為蝕刻阻止層,再者,採用對於矽-絕緣體(如氧化物或是氮化物)有選擇性之蝕刻程序較佳。
如圖14E所示,在步驟S36,進行一第二次蝕刻步驟以移除絕緣層30。雖然在上文中使用“第二次蝕刻“,但是實際上可由和第一次蝕刻相同之配方,或在同一蝕刻槽進行完第一次蝕刻後立即進行第二次蝕刻。此蝕刻可為乾蝕刻、溼蝕刻或兩者組合。例如,可用一以氫氟酸為基底(例如:BOE)之溼蝕刻步驟即可在不使下面矽層32粗糙化的狀況下移除絕緣層30。再者可選擇性地進行另一蝕刻步驟以使矽波導12a厚度更薄。
如圖14F所示,在步驟S38,一可選擇性層24係以沈積方式形成以作為抗反射覆層或部份鏡面層,使光線可更有效耦合到光元件。依據另一實施方式,可進行另一蝕刻製程以形成一光柵結構或是形成反射鏡面,以將正向入射光耦合至側向波導。再者,依據使用光纖類型及元件尺寸,可決定OTSV22相對於光電元件12a之相對尺寸,因此OTSV22大小非為本發明專利範圍之限制。如圖14G(步驟S38’)所示,為另一種矽波導12b(脊狀波導)。由於在步驟S32之後對於兩種不同波導之製程類似,因此在此僅示出於步驟S38執行後所完成之對應側面。
總而言之,OSTV之基本特徵為使用半導體製程及位在半導體元件晶片上,包含光電元件或電子元件。該半導體製程包含光阻佈形以界定將耦合到光電元件之OTSV,及至少一蝕刻步驟以移除矽或其他絕緣材料。
此外,本發明尚有其他選擇性特徵。例如,在光電元件跟光纖交接處尚可有界面層(或多層),或是光柵/鏡面結構以使光線可耦合至光電元件。這些界面層或是結構可為抗反射層,部份鏡面,或是光柵。在光纖安置後,可用其他材料填補OSTV及光纖之間的間隙。
OSTV光耦合之一個重要特徵為相對昂貴的光電IC不需要傳統電TSV。雖然在相同IC中使用傳統TSV及OTSV架構仍可同時運作,然而本發明整體目標為將光訊號與電訊號分離於晶片相反側面,因此分別使用TSV或OTSV即可達成此目的。再者,只要光線可有效地經由OTSV耦合到光電元件,OTSV之區域可大於、等於、或是小於待耦合之光電元件區域。通常而言,一OTSV尺寸會大於元件尺寸,大多數光纖直徑大於20um且光線僅在內部約10um之核心部份行進(上述尺寸係對於單模光纖而言,多模光纖尺寸會更大)。光電元件之尺寸可和輸入光纖核心尺寸接近;OTSV之尺寸要大於光纖尺寸以接收此光纖。然而,如需配合不同尺寸光纖或他種光耦合元件,OTSV之尺寸也可做調整(調整蝕刻罩幕)。此外,基於實際製程考量,OTSV之側壁可能非為理想之直線(例如可由頂部至底部寬度漸變),然而此種製程導致之非理想問題可以藉由製成調整降到最低。
在前述說明係介紹數種形成OTSV之製程,其中光線可由光電IC的背面耦合進來。下面說明書將說明幾個基於OTSV或是抗反射包覆(ARC)層之封裝架構(光線由光電元件背面進來),亦同時包含基於在背面之OTSV及ARC之架構。圖15A顯示一積體模組之側視圖,此積體模組具有一第一單元(例如一電子IC300)及一第二單元(例如一光電IC200),其中光線由光電元件背面進來,且背面係為光元件202所在位置的對面。為了達成有效耦合,光電IC可包含一OTSV(例如為圖12A-12D,圖13A-13E或其餘圖示所繪示之OTSV,也稱為部份蝕刻凹槽)。以將光線導入;光電IC也可拋光或是研磨至較薄厚度。依據一些實施方式,光電IC可以拋光到200um至250um。積體模組包含、一光電IC200、一電子IC300及一中介層400。此中介層400包含TSV400及可作為在光電IC200、電子IC300及基板100之間的低成本橋接。此中介層可將IC上較小節距的接墊橋接到基板(如印刷電路板)上較大節距的接墊。此光電IC200包含位在一第一面上之一光元件202(例如光偵測器)及電接墊220。依據一些實施方式,此光電IC200可更包含設立在第二面(背面)之OTSV250(或稱為部份蝕刻凹槽),此第二面係在第一面(正面)之對面。OTSV250之底部耦合到光元件202。依據一些實施方式,若無OTSV,亦可在光電元件背面可有抗反射包覆層(ARC層),以使光線有效耦合至背面。依據一些實施方式,光電IC200可安置在中介層400上且電接墊220電耦接至TSV400。電子IC300也安置在中介層400上且電接墊320電耦接至TSV400。中介層400經由接合機制(如焊球或是銅導柱130)而安置在基板100之上。依據一些實施方式,一光纖(未圖示)可***OTSV250及經由OTSV250而與光元件202對準。光線係由大致和第一面垂直之方向入射,且經由OTSV250或是ARC層(覆蓋在矽基板背面)而入射到光元件202。依據一些實施方式,光元件可為光偵測器且將接收光線轉換成電訊號。此電訊號經由電接墊220、TSV440(含內部繞線)及電接墊320而傳送到電子IC300。
圖15B顯示一積體模組之側視圖,此積體模組具有一第一單元(例如一電子IC)及一第二單元(例如一具有OTSV之光電IC)。積體模組包含一光電IC200、及一具有TSV340之電子IC300。光電IC200疊在電子IC300之頂面且此電子IC300經由焊球130(或其他接合機制如銅導柱)而連接到其下的基板100。光電IC200包含在第一面上之一光元件202(如光偵測器)及電接墊220。光電IC200更包含於第二面上設立之OTSV250,此第二面係在第一面對面。OTSV250之底面耦合到光元件202,以使圖15B所示架構可用於正向耦合機制。
在光電IC200疊在電子IC300上時,光電IC200之電接墊202電連接到電子IC300之TSV340。一光纖(未圖示)***此OTSV250並經由OTSV250與光元件202對準。光線係由大致和第一面垂直之方向入射,且經由OTSV250或是ARC層(覆蓋在矽基板背面)而入射到光元件202。依據一些實施方式,光元件可為光偵測器且將接收光線轉換成電訊號。此電訊號經由電接墊220、TSV340而傳送到電子IC300(例如TIA)。因為不需中介層且傳統TSV及內部繞線係在電子IC中,此封裝架構與圖15A15A架構相比具有較小尺寸。
圖15C顯示一積體模組之側視圖,此積體模組與圖15B所示者接近,但是光電IC200不具有OTSV且在背面上有一ARC層255。依據一些實施方式,光電IC200亦可有較薄之基板厚度,例如可薄於200um且在基板之背面亦有一ARC層以利光耦合。依據一些實施方式,基板為矽基板,且若此矽基板和入射光線來自之外部介質有不同折射率,則此矽基板可作為聚光、散光或是準直光線之透鏡。
圖16A顯示一積體模組之側視圖,此積體模組具有一第一單元(例如一電子IC)及一第二單元(例如一具有OTSV之光電IC)。積體模組包含一具有OTSV250之光電IC200、及一電子IC300。光電IC200疊在電子IC300之頂面且此電子IC300經由焊接線102而連接到其下的基板100。光電IC200包含在第一面上之一光元件202(如光偵測器)及電接墊220。光電IC200更包含於第二面上設立之OTSV250,此第二面係在第一面對面。OTSV250之底面耦合到光元件202,類似圖15B所示架構可用於正向耦合機制。光電IC200之電接墊220係電連接到電子IC300之電接墊320,且此電連接可為如圖所示之直接方式,或是其他接合機制,如在將光電IC200疊在電子IC300之上時,可用化學鎳金(Electroless nickel immersion gold,ENIG)、銅導柱或金凸塊(Au stub bump)接合機制。一光纖(未圖示)***此OTSV250並經由OTSV250與光元件202對準。與圖15B之範例相比,此圖所示之封裝之電子IC不需TSV,但是需有焊接線以將電子IC電連接到基板。
圖16B顯示依據另一實例之積體模組之側視圖。此積體模組包含一具有OTSV250之光電IC200、及一電子IC300。和圖16A之範例比較,電子IC300係經由焊球130而懸掛於基板100之下,且光電IC200疊在電子IC300之頂面。在此封裝架構,光電IC200及電子IC300之間、與電子IC300及基板100之間的接合可採覆晶接合,但是其與基板之間封裝強度可能會受影響。在圖16A,16B所示範例中,不需要傳遞電訊號的傳統TSV。在其他一些實施方式中,如圖16A及16B所示之光電IC可以不需有OTSV而僅需在其背面有ARC層以使光線可以耦合進來,這些範例將配合圖16C及16D說明。
圖16C顯示一積體模組之側視圖,此積體模組具有一第一單元(例如一電子IC)及一第二單元(例如一光電IC)。積體模組包含一光電IC200、及一電子IC300。光電IC200疊在電子IC300之頂面且此電子IC300經由焊接線102而連接到其下的基板100。光電IC200包含在第一面上之一光元件202(如光偵測器)及電接墊220。光電IC200之電接墊220係電連接到電子IC300之電接墊320,且此電連接可為如圖所示之直接方式,或是其他接合機制,如在將光電IC200疊在電子IC 300之上時,可用化學鎳金(Electroless nickel immersion gold,ENIG)、銅導柱或金凸塊(Au stub bump)接合機制。依據一些實施方式,此光電IC可經拋光而有較薄厚度,例如小於300um。依據其他實施方式,該基板為矽基板,且在基板之背面亦可有一ARC層255以利光耦合。且若此矽基板和入射光線來自之外部介質有不同折射率,則此矽基板可作為聚光、散光或是準直光線之透鏡。此矽基板厚度可以依需要調整以提供足夠的機械支撐及/或具有適當光學路徑以提供透鏡效果。
圖16D顯示一積體模組之側視圖,此積體模組具有一第一單元(例如一電子IC)及一第二單元(例如一光電IC)。圖16D顯示之積體模組近似於圖16C所示,但其基板100亦包含一凹槽108。凹槽108之深度可使電子IC300可安置在基板100上且電子IC300之電接墊320可藉由接合機制例如焊接線102而與基板100之電接墊接觸,且該電子IC300可至少部份被崁入凹槽108之中。
圖16E顯示一積體模組之側視圖,此積體模組具有一第一單元(例如一電子IC)及一第二單元(例如一光電IC)。此圖所示之封裝架構類似圖11A所示之封裝架構,但是此圖所示架構中的光電IC200沒有OTSV,且在其基板背面具有一ARC層255。依據一些實施方式,基板為矽基板,且若此矽基板和入射光線來自之外部介質有不同折射率,則此矽基板可作為聚光、散光或是準直光線之透鏡。此矽基板厚度可以依需要調整以提供足夠的機械支撐及/或具有適當光學路徑以提供透鏡效果。
圖16F顯示一積體模組之側視圖,此積體模組具有一第一單元(例如一電子IC)及一第二單元(例如一光電IC)。 積體模組包含一具有OTSV250之光電IC200、及一電子IC300。具有OTSV250之光電IC200疊在電子IC300之頂面。光電IC200包含在第一面上之一光元件202(如光偵測器)及電接墊220。光電IC200更包含於第二面上設立之OTSV250,此第二面係在第一面對面。OTSV250之背面係耦合到光元件202,以使其可用於背面正向入射耦合機制。光電IC200之電接墊220係電連接到電子IC300之電接墊320,且此電連接可為如圖所示之直接方式,或是其他接合機制,如在將光電IC200疊在電子IC300之上時,可用化學鎳金(Electroless nickel immersion gold,ENIG)、銅導柱或金凸塊(Au stub bump)接合機制。一光纖(未圖示)***此OTSV 250並經由OTSV250與光元件202對準。光電IC200係疊在電子IC300上,且位於基板100之凹槽108之深度可使光電IC200可安置在基板100上且該光電IC200之電接墊220可與基板100之電接墊接觸,且電子IC300可至少部份被崁入凹槽108之中。
如前所述,在有凹槽基板的覆晶封裝架構中,仍有對準問題(直接對準與非直接對準的比較)。為了克服此問題,本發明提出一三維對準方法以增進覆晶接合或是晶圓-晶圓接合之精確度。此三維對準標記(3D alignment mark)可用半導體製程如光阻佈形、蝕刻、CVD薄膜沈積及成長而界定。圖17A-17C顯示不同三維對準標記之立體圖,且部份實施方式可視為傳統平面對準標記之三維版本。在圖17A之中,一突起結構為圓柱形狀,而凹陷結構則為對應之圓槽形狀。在圖17B之中,一突起結構為方柱形狀,而凹陷結構則為對應之方槽形狀。在圖17C之中,一突起結構為十字柱形狀,而凹陷結構則為對應之十字槽形狀。除了在圖17A-17C所示範例之外,其餘之突起/凹陷成對結構皆可用作三維對準標記,只要這些結構可用半導體製程(如光阻佈形、蝕刻、CVD薄膜沈積及成長)製作,且在蝕刻後實際之形狀與罩幕設計形狀之失真度小於1um,且突起/凹陷成對結構彼此互相匹配。依據一些實施方式,可用多對的三維對準標記。在一些實施方式,突起/凹陷成對結構之厚度/深度可為數百奈米到數百微米。若突起/凹陷成對結構具有較大厚度或是較大深度,且可以彼此匹配/拴鎖,則可以增加在接合時之穩定度,但是會增加製作這些結構的製程時間。設計者可依據製程時間需求(和產能相關)及機械穩定度規格而選擇適當厚度/深度。這些設計選擇或許會變更對準的機械強健度,但是不會變更本發明的基本功能。因此上述設計考量為基於本發明概念的製程最佳化過程,亦都在本發明的專利範圍內,只要對準標記包含前述的基本元素,亦即突起/凹陷成對結構。
在接合過程中,突起/凹陷成對結構可藉由拴鎖而得到更加對準強健度。參考圖11A,使用三維對準標記可改善電子IC與光電IC間的對準,因此有益於整體的光纖與光電IC對準。更具體而言,光電IC200及電子IC300一開始係由接合工具做起始對準。隨後,光電IC200及電子IC300在任意方向稍微移動(例如沿著圓弧方向輕微震動或移動,並加大半徑),直到兩者間隔降低,此意味突起/凹陷成對結構260/360係為匹配且凹陷結構360已經大致被突起結構260充填。在部份的在拴鎖之後的接合程序中,接墊220/320可暫時呈現液相,因此在其冷卻為固相之前,此三維對準標記可避免接墊之間的滑動。
在實際製作上,此三維對準標記可由光阻佈形界定且蝕刻通過鈍化層並進入矽層,或僅蝕刻進入矽基板。在一些實施方式中,突起結構可由自我組合成長技術(self-assembly growth techniques)製作,例如可沈積一種子層或是催化劑層(如鋁或金),然後將反應劑(如SiH4或是GeH4)流過此種子層或是催化劑層區域,使得部份元素(如矽或是鍺)可與其下種子層或是催化劑層反應並在種子層或是催化劑層之上自我組合成長。依據其他實施方式,若突起結構無法與凹陷結構匹配,一突起結構可先沈積或成長一種可輕易移除材料(如聚化物材料或是鍺)以利後續當該結構無法相互匹配後之移除。依據其他實施方式,凹陷結構可由濕蝕刻、乾蝕刻或兩者組合來製作。
然以上所述者,僅為本發明之部份實施方式,並不能限定本發明實施之範圍,即凡依本發明申請專利範圍所作之均等變化與修飾等,皆應仍屬本發明之專利涵蓋範圍意圖保護之範疇。
102‧‧‧焊接線
200‧‧‧光電IC
202‧‧‧光元件
220,320‧‧‧電接墊
250‧‧‧OTSV
300‧‧‧電子IC
Claims (20)
- 【第1項】一種積體模組,包含:
一第一單元包含在第一面之一光元件及電接墊,及在第二面之抗反射包覆層,該第二面與該第一面相對;
一第二單元包含在一第一面之電接墊,及與該第一面相對之第二面;
一光訊號自一外部介質進入該第一單元之該第二面;
其中藉由對準該第一單元及該第二單元至少一對電接墊,該第一單元之該第一面接合到該第二單元之該第一面。 - 【第2項】如請求項1之積體模組,其中該第一單元更包含界定在該第二面之部份蝕刻凹槽,該部份蝕刻凹槽向著該第一單元之第一面與該光元件對準,該光訊號可經由該部份蝕刻凹槽耦合到該光元件。
- 【第3項】如請求項1之積體模組,其中該抗反射包覆層係在該外部介質及該光元件之間。
- 【第4項】如請求項1之積體模組,其中該第一單元及該第二單元之接合面更包含一突起及凹陷成對結構。
- 【第5項】如請求項1之積體模組,其中該光元件為光檢測器、雷射、光柵耦合器或光波導。
- 【第6項】如請求項1之積體模組,其中該第二單元可包含一半導體基板或是一印刷電路板。
- 【第7項】如請求項1之積體模組,其中該第二單元更包含由該第一面延伸到該第二面之一矽導孔(TSV)。
- 【第8項】如請求項1之積體模組,其中更包含一第三單元電連接至該模組,其中該第三單元之一面係連接到該模組且包含一凹槽以崁入至少部份之該模組。
- 【第9項】如請求項1之積體模組,其中該第一單元係覆晶結合到一第三單元,該第三單元可包含矽基板或是印刷電路板。
- 【第10項】如請求項1之積體模組,其中該第二單元係以焊接線或是覆晶接合到一第三單元,該第三單元可包含矽基板或是印刷電路板。
- 【第11項】一種積體模組,包含:
一第一單元包含在第一面之一光元件及電接墊,及與該第一面相對之一第二面;
一第二單元包含在一第一面之電接墊,及與該第一面相對之第二面;
一光訊號自一外部介質進入該第一單元之該第一面;
其中該第一單元之該第一面係接合到該第二單元之該第一面,且該第一單元之該光元件上之區域係露出以提供一未被該第二區域覆蓋之開口。 - 【第12項】如請求項11之積體模組,其中該開口係由穿過該第二單元之第一面及第二面之一蝕穿凹槽所形成,且光線係經由此蝕穿凹槽穿過該第二單元而耦合到於該第一單元之該光元件。
- 【第13項】如請求項11之積體模組,其中該第一單元或該第二單元包含一矽導孔(TSV),該矽導孔由該第一面延伸到該第二面。
- 【第14項】如請求項11之積體模組,其中該第一單元及該第二單元之接合面更包含一突起及凹陷成對結構。
- 【第15項】如請求項11之積體模組,其中更包含一第三單元,該第三單元直接電連接到該第一單元,或是經由該第二單元而連接到該第一單元。
- 【第16項】如請求項15之積體模組,其中該第二單元具有至少一電接墊,該電接墊未被該第一單元覆蓋且覆晶接合到該第三單元,該第三單元具有一凹槽以包容至少一部份之該第一單元。
- 【第17項】如請求項15之積體模組,其中該第一單元之電接墊係以焊接線而電連接到該第三單元。
- 【第18項】一種形成積體模組之方法,包含:
在一第一半導體基板形成一表面突起結構及一第一電接墊;
在一第二半導體基板形成一表面凹陷結構及一第二電接墊;
將該第一半導體基板置於該第二半導體基板之上且使該表面突起結構大致上與該表面凹陷結構匹配,並使該第一電接墊與該第二電接墊對準;
施加包含加熱、加壓或其組合之化學或是物理力以接合該第一半導體基板及該第二半導體基板。 - 【第19項】如請求項第18項之形成積體模組之方法,其中該突起結構係以自我組合成長技術(self-assembly growth techniques)製作,且使用金屬作為催化劑。
- 【第20項】如請求項第18項之形成積體模組之方法,其中該突起結構或該凹陷結構係以成長或是沈積與基板表面不同之材料而形成。
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- 2014-12-02 TW TW103141865A patent/TWI648563B/zh active
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2018
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2019
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US11031381B2 (en) | 2018-10-30 | 2021-06-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Optical transceiver and manufacturing method thereof |
Also Published As
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EP2887388A1 (en) | 2015-06-24 |
US20190384022A1 (en) | 2019-12-19 |
US20150153524A1 (en) | 2015-06-04 |
CN104766903B (zh) | 2018-06-29 |
US20190113696A1 (en) | 2019-04-18 |
TWI648563B (zh) | 2019-01-21 |
CN104766903A (zh) | 2015-07-08 |
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