TW201526080A

TW201526080A - Low threading dislocation density GaN hetero-epitaxy technology by molecular beam epitaxy

Info

Publication number: TW201526080A
Application number: TW102148389A
Authority: TW
Inventors: ke-yong Cheng; you-li Wang; Wei-Chen Yang; Shao-Yan Chiu
Original assignee: Nat Univ Tsing Hua
Priority date: 2013-12-26
Filing date: 2013-12-26
Publication date: 2015-07-01

Abstract

By using nano-scale patterned process, the threading dislocation of gallium nitride epitaxy layer can be reduced. Because nano-scale epitaxy structure can reduce the strain energy, which is come from lattice mismatch, it can decrease the probability of generating defect. It is proven that the gallium nitride grown on nano-scale patterned sapphire can reduced the threading dislocation density. To transfer this method to large scale wafer with uniformity and reproducibility, it will be made by soft mask NIL patterned method. This method have been succeed to produce uniform InAs quatumn dot on GaAs substrate. Furthurmore, the nano-scale pattern is going to work on different substrate, like silicon and sapphire, with NIL technology and dry etch. Finally, we expect this technology can avoid threading dislocation grown up with epitaxy layer on non-plane substrate, so the lower defect density GaN can be produced.

Description

分子束磊晶生長異質磊晶低缺陷氮化鎵技術 Molecular beam epitaxy growth heterogeneous epitaxial low defect gallium nitride technology

本發明所揭係與一種軟性奈米壓印有關，特別是與軟性奈米壓印具可應用異質基板上(如Si、GaAs等)及其非破壞性原生磊晶基板。應用軟性奈米壓印技術，輔以乾式蝕刻，進行奈米級圖案化，從而利用非平面基板來控制、沈積III-N之磊晶結構，抑制差排缺陷密度向上延伸，預期將可獲致低缺陷密度。 The invention is related to a soft nanoimprinting, in particular to a soft nanoimprinting tool, which can be applied to a heterogeneous substrate (such as Si, GaAs, etc.) and its non-destructive native epitaxial substrate. Applying soft nanoimprint technology, combined with dry etching, to perform nano-scale patterning, so as to control and deposit the epitaxial structure of III-N by using non-planar substrate, and inhibit the extension of the defect density, which is expected to be low. Defect density.

於同質、物性匹配之GaN磊晶基板上進行功率元件的結構磊晶與製程有助於建立元件指標特性；而採用異質基板(如Sapphire、Si等)則有助於降低研發及產製成本，然受物性失配的影響，須進一步研發「低缺陷」之異質磊晶技術；此源於異質磊晶引入之晶格常數與熱脹係數差異必然影響磊晶結構品質，造成磊晶層的缺陷與應力。於元件應用上，將嚴重影響元件的耐壓性；而磊晶層應力導致晶圓翹曲，影響元件製程精確度，於大晶圓尺寸下，特別是採用高溫生長之MOCVD磊晶技術，此現象益形嚴重。以Si基板為例，其與GaN存在著高達16.2%的晶格失配、113%的熱脹係數差異、以及Si與氮(N)原子間高反應活性等不利因素。因此，採取以較低温生長之MBE磊晶技術，為實現「低缺陷」異質磊晶技術之關鍵；如以實現垂直式元件，耐壓將與GaN磊晶層厚度(可達4μm以上)與品質極為相關 Structural epitaxy and process of power components on homogeneous and physical matching GaN epitaxial substrates can help to establish component index characteristics; and the use of heterogeneous substrates (such as Sapphire, Si, etc.) can help reduce R&D and production costs. However, due to the influence of physical mismatch, it is necessary to further develop the "low defect" heterogeneous epitaxial technology; the difference between the lattice constant and the thermal expansion coefficient derived from heterogeneous epitaxy will inevitably affect the quality of the epitaxial structure and cause defects in the epitaxial layer. With stress. In the application of components, it will seriously affect the pressure resistance of the components; while the stress of the epitaxial layer causes warpage of the wafer, which affects the accuracy of the component process. Under the large wafer size, especially the MOCVD epitaxial technology using high temperature growth, this The phenomenon is serious. Taking a Si substrate as an example, it has a lattice mismatch of up to 16.2%, a difference in thermal expansion coefficient of 113%, and a high atomic ratio between Si and nitrogen (N). Unfavorable factors such as reactivity. Therefore, adopting the MBE epitaxial technology with lower temperature growth is the key to realize the "low defect" heterogeneous epitaxial technology; if the vertical element is realized, the withstand voltage will be the thickness of the GaN epitaxial layer (up to 4 μm or more) and quality. Extremely relevant

無論是分子束磊晶(MBE)或有機金屬化學氣相沉積(MOCVD)等磊晶技術，皆已於Si(111)基板上實現六方晶構氮化鎵(GaN)之磊晶成長。以文獻[C.W.Nieh,Y.J.Lee,W.C.Lee,Z.K.Yang,A.R.Kortan,M.Hong,J.Kwo,and C.H.Hsu,Appl.Phys.Lett.,92,061914(2008)]為例，藉於Si(111)上先行沈積數奈米結晶良好之單晶氧化層，並以此作為單晶GaN的磊晶樣底，此樣底不僅有效防止Si與GaN間的相互擴散，亦為成長GaN的關鍵晶種層(Seeding Layer)。考量主流矽晶圓技術與未來整合III-N與矽元件的潛力，Si(001)實為較務實、偏好的選擇。此外，相較於現下泛用之六方晶系纖鋅礦(Wurtzite)結構，立方晶系之閃鋅礦(Zinc-blende)結構之III-N具有非極化、高量子效率、高p-type導電率等優勢。然於Si(001)上成長GaN，因晶面對稱性的差異促使GaN的成長存在多個偏好晶向，導致多晶結構或粗糙表面；此外，如前述之熱脹係數差異與晶格失配亦導致磊晶層存在高旋線差排(Threading Dislocation，TD)密度，甚而形成晶裂鏈(Crack Networks)。為降低TD密度，III-N LED產業習於Sapphire磊晶基板上先行圖案化(Patterned Sapphire)。同樣作法亦見用於Si(111)基板上。必須強調的是，此習知圖案化製程的特徵尺寸皆屬微米(μm)等級。近來，藉由採用奈米(nm)等級之圖案化製程，GaN磊晶層的TD密度可以進一步降低，此歸因於奈米級的磊晶結構尺寸有助於降低失配晶格累積之應變能(Strain Energy)，降低缺陷的產生機率。 Whether it is epitaxial technology such as molecular beam epitaxy (MBE) or organometallic chemical vapor deposition (MOCVD), the epitaxial growth of hexagonal crystal gallium nitride (GaN) has been achieved on a Si (111) substrate. Taking the literature [CWNieh, YJ Lee, WCLee, ZK Yang, ARKortan, M. Hong, J. Kwo, and CHHsu, Appl. Phys. Lett., 92 , 061914 (2008)] as an example, by depositing on Si(111) A single crystal oxide layer with good crystallinity is used as the epitaxial bottom of single crystal GaN. This kind of substrate not only effectively prevents the interdiffusion between Si and GaN, but also is the key seed layer for growing GaN (Seeding Layer). ). Taking into account the potential of mainstream silicon wafer technology and future integration of III-N and germanium components, Si(001) is a more pragmatic and preferred choice. In addition, the cubic-type Zinc-blende III-N has non-polarization, high quantum efficiency, and high p-type compared to the currently used hexagonal wurtzite structure. Advantages such as conductivity. However, when GaN is grown on Si(001), the difference in crystal plane symmetry causes the growth of GaN to have multiple preferred crystal orientations, resulting in polycrystalline structures or rough surfaces. In addition, the difference in thermal expansion coefficient and lattice mismatch are as described above. It also causes the epitaxial layer to have a high Threading Dislocation (TD) density, and even a crack chain. To reduce TD density, the III-N LED industry is familiar with Patterned Sapphire on Sapphire epitaxial substrates. The same is also seen for use on Si (111) substrates. It must be emphasized that the feature sizes of this conventional patterning process are on the order of micrometers (μm). Recently, the TD density of GaN epitaxial layers can be further reduced by using a nanometer (nm) grade patterning process, which is attributed to the fact that the nanoscale epitaxial structure size helps to reduce the strain of mismatched lattice accumulation. Strain Energy reduces the chance of defects.

本發明所揭係與一種軟性奈米壓印有關，特別是與軟性奈米壓印具可應用異質基板上(如Si、GaAs等)及其非破壞性原生磊晶基板。應用NIL技術，輔以乾式蝕刻，進行奈米級圖案化，從而利用非平面基板來控制、沈積III-N之磊晶結構，抑制差排缺陷密度向上延伸，預期將可獲致低缺陷密度。為使本發明更易於瞭解及實施，請參見以下實施例說明。 The invention is related to a soft nanoimprinting, in particular to a soft nanoimprinting tool, which can be applied to a heterogeneous substrate (such as Si, GaAs, etc.) and its non-destructive native epitaxial substrate. NIL technology is applied, and dry etching is used to perform nano-scale patterning, thereby controlling and depositing the epitaxial structure of III-N by using a non-planar substrate, and suppressing the extension of the defect density to be extended upward, and it is expected that a low defect density can be obtained. In order to make the invention easier to understand and implement, please refer to the following description of the embodiments.

圖一：軟性奈米壓印轉印於任意基板上 Figure 1: Soft nanoimprint is transferred onto any substrate

圖二：轉印後之奈米洞和奈米柱 Figure 2: Nano-hole and nano column after transfer

圖三：轉印奈米洞後之磊晶成長氮化鎵品質量測結果 Figure 3: Quality measurement results of epitaxial growth of GaN after transfer of nanometer holes

軟性奈米壓印模組反印於任意基板上，請先參考第一(a)-(f)圖先在矽母片的奈米流程，先在基板(或磊晶片)上沉積氮化矽(或二氧化矽)，隨後旋轉塗佈紫外光固化光阻(UV-curable photoresist)；再將奈米模具壓印於光阻之上。基板(或磊晶片)和奈米模具一同暴露於紫外光下進行光阻固化，(圖一(a))；待奈米光阻固化之後再移除奈米模具，(圖一(b))。此時，再以反應式離子蝕刻機的氧電漿(O₂ plasma)將圖案底部光阻殘餘層蝕刻至氮化矽(圖一(c))，以將圖形完整的轉印到奈米光阻層，而後使用三氟甲烷電漿蝕刻氮化矽，使基板層暴露出奈米圖形(圖一(d))，再使用乾/濕蝕刻將圖形轉移至基板(圖一(e))，最後，使用氫氟酸移除氮化矽(圖一(f))，既完成奈米圖案之轉印。軟性奈米壓印技術在研究上分別有三種應用：一為在磊晶片上製作出量子結構晶格，二則是利用軟性奈米壓印技術在藍寶石基板、氮化鎵或矽基板(111)上製作出週期性排列之奈米孔洞；並配合分子束磊晶成長低缺陷之氮化鎵磊晶層，最後則是利用軟性奈米壓印技術在鍍上鈦薄膜的基板上製作出奈米孔洞如圖二(a)所示，並搭配分子束磊晶成長可控制成長區域的量子點(Site-controlled quantum dot)或奈米柱圖二(b)。 The soft nanoimprinting module is reverse printed on any substrate. Please refer to the first (a)-(f) diagram first to deposit the tantalum nitride on the substrate (or epitaxial wafer) in the nano process of the master wafer. (or cerium oxide), followed by spin coating of UV-curable photoresist; and then imprinting the nano-mold on the photoresist. The substrate (or epitaxial wafer) and the nano-mold are exposed to ultraviolet light for photoresist curing (Fig. 1(a)); after the photoresist is cured, the nano-mold is removed (Fig. 1(b)). At this time, the residual photoresist layer at the bottom of the pattern is etched to the tantalum nitride by the oxygen plasma (O ₂ plasma) of the reactive ion etching machine (Fig. 1(c)) to transfer the pattern to the nano photoresist. a layer, and then ramming the tantalum nitride with a trifluoromethane plasma, exposing the substrate layer to a nano-pattern (Fig. 1(d)), and then transferring the pattern to the substrate using dry/wet etching (Fig. 1(e)), and finally The use of hydrofluoric acid to remove tantalum nitride (Fig. 1 (f)), which completes the transfer of the nano pattern. Soft nanoimprint technology has three applications in research: one is to fabricate a quantum structure lattice on the epitaxial wafer, and the other is to use soft nanoimprint technology on the sapphire substrate, gallium nitride or germanium substrate (111). A periodically arranged nanopore is formed on the substrate; and a low-defect gallium nitride epitaxial layer is grown by molecular beam epitaxy, and finally a nano-imprint technique is used to fabricate a nano-substrate on the substrate coated with the titanium thin film. The hole is shown in Figure 2(a) and can be controlled by molecular beam epitaxy to control the site-controlled quantum dot or the nano-column diagram (b).

接著，成功製作出軟性奈米壓印反轉任何基板上，利用分子束磊晶(MBE)，基板溫度780℃與III-V比約1：1成長氮化鎵材料之條件，可由光致發光儀器與蝕刻(KOH)後AFM儀器觀察缺陷密度，由圖三(a)-(b)得知奈米壓印技術應用於低缺陷磊晶成長可以降低缺陷密度原10⁸下降至10⁷cm^-2。 Subsequently, the soft nanoimprint was successfully fabricated on any substrate, using molecular beam epitaxy (MBE), substrate temperature of 780 ° C and III-V ratio of about 1:1 growth of gallium nitride material, photoluminescence After the instrument and etching (KOH), the AFM instrument observes the defect density. It is known from Fig. 3(a)-(b) that the nanoimprint technology applied to the low defect epitaxial growth can reduce the defect density from 10 ⁸ to 10 ⁷ cm ^{. 2} .

Claims

一種低缺陷氮化鎵磊晶生長之技術，其包含以下步驟：(1)提供一半導體積層(或異質基板)；(2)形成一位於該基板上之半導體積層(或異質基板)以作為軟性奈米壓印之平臺；(3)形成位於該半導體積層上(或異質基板)並與該半導體積層(或異質基板)構成奈米柱(洞)；(4)形成一位於位於該半導體積層(或基板)上並與該半導體積層(或基板)構成異質磊晶區域其中，步驟(3)中之該奈米柱(洞)的形成又包括：(i)以軟性奈米光罩之模型(週期50200nm、350nm)，將一預定週期軟性奈米光罩壓印於半導體積層(或異質基板)上；(ii)對該半導體積層(或異質基板)上執行一次乾式蝕刻，以轉印奈米圖案；以及(iii)進行剝離製程以形成奈米柱(洞)圖案化於半導體積層(或異質基板)上。 A low-defect gallium nitride epitaxial growth technique comprising the steps of: (1) providing a semiconductor laminate (or a heterogeneous substrate); (2) forming a semiconductor laminate (or a heterogeneous substrate) on the substrate as a soft a nanoimprinted platform; (3) formed on the semiconductor laminate (or a heterogeneous substrate) and formed with a semiconductor pillar (or a heterogeneous substrate) as a nanocolumn (hole); (4) formed on the semiconductor laminate ( Or a substrate (and a substrate) to form a heterogeneous epitaxial region, wherein the formation of the nanocolumn (hole) in step (3) further comprises: (i) a model of a soft nanomask (cycle) 50200nm, 350nm), a predetermined period of soft nano-mask is imprinted on the semiconductor laminate (or heterogeneous substrate); (ii) performing a dry etching on the semiconductor laminate (or heterogeneous substrate) to transfer the nano pattern; And (iii) performing a lift-off process to form a nano-pillar (hole) patterned on the semiconductor laminate (or heterogeneous substrate).

如申請專利範圍第1項之製造方法，其中、該半導體積層(或異質基板)包含上、下兩區塊，緊鄰半導體積層(或異質基板)上表面之下區塊為軟性奈米壓印之平臺，而一體成型且連續性銜接該半導體積層(或異質基板)之上區塊為一奈米級奈米柱(洞)圖案化層。 The manufacturing method of claim 1, wherein the semiconductor laminate (or heterogeneous substrate) comprises upper and lower blocks, and the block below the upper surface of the semiconductor laminate (or heterogeneous substrate) is a soft nanoimprint. The platform is integrally formed and continuously connected to the semiconductor laminate (or heterogeneous substrate). The block is a nanometer-sized nano-pillar (hole) patterned layer.

如申請專利範圍第2項之製造方法，其中、上區塊係由其間之軟性奈米壓印於奈米光阻層近似完全移除之半導體積層 (或異質基板)部份，而該奈米光阻層則係由氧電漿蝕刻奈米柱(洞)模型。 The manufacturing method of claim 2, wherein the upper block is imprinted with a soft nano-imprinted nano-imprinted layer of the semiconductor layer which is approximately completely removed. The (or heterogeneous substrate) portion, and the nano-resistive layer is an oxygen plasma-etched nanocolumn (hole) model.

如申請專利範圍第1至3項中任一項之製造方法，其中、該介電層化成係選自氮化矽之一或Ti、Au其等之合金者，而氧化物則為二氧化矽。 The manufacturing method according to any one of claims 1 to 3, wherein the dielectric layer is selected from one of tantalum nitride or an alloy of Ti, Au, etc., and the oxide is cerium oxide. .

一種低缺陷氮化鎵磊晶生長之技術，其係藉由如申請專利範圍第1項所揭之製造方法來完成者，其特徵在於包含：一半導體積層(或異質基板)；一提供一半導體積層(或異質基板)；形成一位於該基板上之半導體積層(或異質基板)以作為軟性奈米壓印之平臺；形成位於該半導體積層上(或異質基板)並與該半導體積(或異質基板)構成奈米柱(洞)；形成一位於位於該半導體積層(或基板)上並與該半導體積層(或基板)構成異質磊晶區域其中、該半導體積層(或異質基板)包含上、下兩區塊，緊鄰半導體積層(或異質基板)上表面之下區塊為軟性奈米壓印之平臺，而一體成型且連續性銜接該半導體積層(或異質基板)之上區塊為一奈米級奈米柱(洞)圖案化層。 A low-defect gallium nitride epitaxial growth technique, which is completed by the manufacturing method as disclosed in claim 1, characterized in that it comprises: a semiconductor laminate (or a heterogeneous substrate); a layered (or heterogeneous substrate); a semiconductor laminate (or a heterogeneous substrate) on the substrate is formed as a platform for soft nanoimprint; formed on the semiconductor laminate (or a heterogeneous substrate) and integrated with the semiconductor (or heterogeneous) a substrate) forming a nano-pillar (hole); forming a heterogeneous epitaxial region on the semiconductor laminate (or substrate) and the semiconductor laminate (or substrate), wherein the semiconductor laminate (or heterogeneous substrate) comprises upper and lower In the two blocks, the block below the upper surface of the semiconductor laminate (or heterogeneous substrate) is a platform of soft nanoimprint, and the block above the semiconductor laminate (or heterogeneous substrate) is integrally formed and continuously connected to one nanometer. Grade nano column (hole) patterned layer.

如申請專利範圍第4項之低缺陷氮化鎵磊晶生長之技術，其中、該半導體積層(或異質基板)平臺係將PECVD(或熱蒸鍍)所沉積獲得之介電層與氧化物經奈米光阻層，再行軟性奈米壓印於奈米光阻層，接著；氧電漿蝕刻奈米柱(洞)模型後而形成者。 The low-defect gallium nitride epitaxial growth technique of claim 4, wherein the semiconductor laminate (or heterogeneous substrate) platform is a dielectric layer and an oxide obtained by PECVD (or thermal evaporation) deposition. The nano-resistive layer is further printed with a soft nano-imprinted layer on the nano-resistive layer, followed by an oxygen plasma etching of the nano-pillar (hole) model.

如申請專利範圍第6項之低缺陷氮化鎵磊晶生長之技術，其中，上區塊係由其間之介電層或氧化物被完全或近似完全移除，在乾式蝕刻除去介電層或氧化物層之奈米柱(洞)模型。 A technique for low-defect gallium nitride epitaxial growth according to claim 6 wherein the upper block is completely or nearly completely shifted by a dielectric layer or oxide therebetween. In addition, the nano-pillar (hole) model of the dielectric layer or oxide layer is removed by dry etching.

如申請專利範圍第7項之低缺陷氮化鎵磊晶生長之技術，其中，上區塊係由其間之奈米柱(洞)模型，在乾式/濕式蝕刻除去半導體積層(或異質基板)，而成功轉印之奈米柱(洞)於該半導體積層(或異質基板)。 A technique for low-defect gallium nitride epitaxial growth according to claim 7 of the patent application, wherein the upper block is a nano-column (hole) model in between, and the semiconductor laminate (or heterogeneous substrate) is removed by dry/wet etching. And successfully transfer the nano column (hole) to the semiconductor laminate (or heterogeneous substrate).

一種低缺陷氮化鎵磊晶生長之技術，其包括成功轉印之奈米柱(洞)，再以分子速磊晶(MBE)生長氮化鎵材料轉印之奈米柱(洞)之半導體積層(或異質基板)，其特徵在於該低缺陷氮化鎵磊晶生長之技術為如申請專利範圍第5項所揭之低缺陷氮化鎵磊晶生長之技術，而包含：一半導體積層(或異質基板)；一位於該半導體積層(或異質基板)上並作為一軟性奈米壓印之平臺之半導體積層(或異質基板)；位於該半導體積層(或異質基板)上並與該半導體積層(或異質基板)構成接觸氮化鎵材料之介面品質。 A low-defect gallium nitride epitaxial growth technique comprising a nano column (hole) for successful transfer, and a semiconductor column (hole) semiconductor for transferring gallium nitride material by molecular velocity epitaxy (MBE) a layered (or heterogeneous substrate) characterized in that the low-defective gallium nitride epitaxial growth technique is a low-defect gallium nitride epitaxial growth technique as disclosed in claim 5, and includes: a semiconductor laminate ( Or a heterogeneous substrate; a semiconductor laminate (or a heterogeneous substrate) on the semiconductor laminate (or a heterogeneous substrate) and acting as a platform for a soft nanoimprint; on the semiconductor laminate (or heterogeneous substrate) and laminated with the semiconductor (or a heterogeneous substrate) constitutes the interface quality of the contact GaN material.

如申請專利範圍第9項之低缺陷氮化鎵磊晶生長之技術，其中、該乾式/濕式蝕刻除去半導體積層(或異質基板)，而成功轉印之奈米柱(洞)於該半導體積層(或異質基板)獲得之深度為200nm與隨後生長之氮化鎵層於該半導體積層(或異質基板)而形成者，抑制差排缺陷密度向上延伸，預期將可獲致低缺陷密度。 A technique for low-defect gallium nitride epitaxial growth according to claim 9 in which the dry/wet etching removes a semiconductor laminate (or a heterogeneous substrate), and a successfully transferred nanocolumn (hole) is used in the semiconductor When a laminate (or a heterogeneous substrate) is formed to have a depth of 200 nm and a subsequently grown gallium nitride layer is formed on the semiconductor laminate (or a heterogeneous substrate), the density of the defective defect is suppressed from extending upward, and it is expected that a low defect density will be obtained.