TW201517242A - Three dimensional stacked semiconductor structure and method for manufacturing the same - Google Patents
Three dimensional stacked semiconductor structure and method for manufacturing the same Download PDFInfo
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Abstract
Description
本發明是有關於一種三維堆疊半導體結構及其製造方法,且特別是有關於一種具有一導電條連接源極接點(source contacts)之三維堆疊半導體結構及其製造方法。The present invention relates to a three-dimensional stacked semiconductor structure and a method of fabricating the same, and more particularly to a three-dimensional stacked semiconductor structure having a conductive strip connected to source contacts and a method of fabricating the same.
非揮發性記憶體元件在設計上有一個很大的特性是,當記憶體元件失去或移除電源後仍能保存資料狀態的完整性。目前業界已有許多不同型態的非揮發性記憶體元件被提出。不過相關業者仍不斷研發新的設計或是結合現有技術,進行記憶胞平面的堆疊以達到具有更高儲存容量的記憶體結構。例如已有一些三維堆疊反及閘(NAND)型快閃記憶體結構被提出。然而,傳統的三維堆疊記憶體結構仍有一些問題需要被解決。A very important feature of non-volatile memory components is the ability to preserve the integrity of the data state when the memory component loses or removes power. Many different types of non-volatile memory components have been proposed in the industry. However, related companies continue to develop new designs or combine existing technologies to stack memory cell planes to achieve a memory structure with higher storage capacity. For example, some three-dimensional stacked NAND (NAND) type flash memory structures have been proposed. However, there are still some problems that need to be solved in the traditional three-dimensional stacked memory structure.
第1圖係為一種3D堆疊半導體結構之立體圖。第1圖中係繪示一種3D NAND記憶體陣列結構為例做說明。3D堆疊半導體結構包括陣列區域11和扇出區域(fan-out region)13。多層陣列係形成於一絕緣層上,並包括複數條字元線125-1 WL、...、125-N WL,其與複數個堆疊等向性地形成。複數個堆疊包括半導體條112、113、114、115。相同平面中的半導體條係藉由階梯結構(亦稱為位元線結構)而電性耦接在一起。階梯結構102B、103B、104B、105B終結半導體條(例如半導體條102、103、104、105)。如圖中顯示的,這些階梯結構102B、103B、104B、105B係電連接至不同的位元線,以供連接至解碼電路,用於選擇此陣列之內的平面。堆疊之半導體條102、103、104、105具有源極線端至位元線端方向。堆疊之半導體條102、103、104、105於一端由階梯結構102B、103B、104B、105B所終結,通過SSL閘極結構109、接地選擇線GSL 127、字元線125-N WL至125-1 WL、接地選擇線GSL 126,而於另一端由一源極線所終結(被圖之其他部分遮住)。堆疊之半導體條112、113、114、115於一端由階梯結構112A、113A、114A、115A所終結,通過SSL閘極結構119、接地選擇線GSL 126、字元線125-1 WL至125-N WL、接地選擇線GSL 127,而於另一端由源極線128所終結。Figure 1 is a perspective view of a 3D stacked semiconductor structure. In the first figure, a 3D NAND memory array structure is illustrated as an example. The 3D stacked semiconductor structure includes an array region 11 and a fan-out region 13. The multilayer array is formed on an insulating layer and includes a plurality of word lines 125-1 WL, ..., 125-N WL which are formed isotropically formed with a plurality of stacks. The plurality of stacks includes semiconductor strips 112, 113, 114, 115. The semiconductor strips in the same plane are electrically coupled together by a step structure (also referred to as a bit line structure). The ladder structures 102B, 103B, 104B, 105B terminate semiconductor strips (eg, semiconductor strips 102, 103, 104, 105). As shown in the figure, these stepped structures 102B, 103B, 104B, 105B are electrically connected to different bit lines for connection to a decoding circuit for selecting a plane within the array. The stacked semiconductor strips 102, 103, 104, 105 have a source line end to a bit line end direction. The stacked semiconductor strips 102, 103, 104, 105 are terminated at one end by step structures 102B, 103B, 104B, 105B, through SSL gate structure 109, ground select line GSL 127, word line 125-N WL to 125-1 WL, ground select line GSL 126, and terminated at the other end by a source line (covered by other parts of the figure). The stacked semiconductor strips 112, 113, 114, 115 are terminated at one end by stepped structures 112A, 113A, 114A, 115A, through SSL gate structure 119, ground select line GSL 126, word lines 125-1 WL through 125-N WL, ground select line GSL 127, and terminated by source line 128 at the other end.
以一源極線128為例。源極線128包括交錯堆疊的絕緣層(如氧化層)和導電層(如多晶矽作為閘極材料),並有垂直於堆疊結構的接觸孔與孔內填充的導電材料以使各層的導電層外接。傳統上為了自對準,接觸孔內填充導電材料是在位元線硬質遮罩層沉積之前完成,然而,硬質遮罩材料可能會再沉積於接觸孔內。這可能會造成接載源極接點製程(SC pick-up process)上的問題。再者,傳統3D堆疊半導體結構在字元線蝕刻(例如離子反應性蝕刻)時其源極接點區域是一個開放區域(open area),字元線製程對於源極接點區域的影響(WL loading effect)比記憶胞區域的影響更嚴重。傳統上,源極接點區域需要更厚的硬質遮罩層作防護字元線蝕刻時可能的傷害。再者,傳統堆疊結構的源極接點和位元線是建構在同一水平面上,這會增加接載源極接點製程時源極接點和上方導電栓塞之間對準的困難度。Take a source line 128 as an example. The source line 128 includes a staggered stacked insulating layer (such as an oxide layer) and a conductive layer (such as a polysilicon as a gate material), and has a contact hole perpendicular to the stacked structure and a conductive material filled in the hole to externally connect the conductive layers of the layers. . Traditionally, for self-alignment, filling the conductive material in the contact hole is done before the deposition of the bit line hard mask layer, however, the hard mask material may be redeposited in the contact hole. This can cause problems in the SC pick-up process. Furthermore, in a conventional 3D stacked semiconductor structure, the source contact region is an open area during word line etching (eg, ion reactive etching), and the influence of the word line process on the source contact region (WL) The loading effect is more severe than the effect of the memory cell area. Traditionally, the source contact area requires a thicker hard mask layer to protect against damage that may occur when the word line is etched. Moreover, the source contact and the bit line of the conventional stacked structure are constructed on the same horizontal surface, which increases the difficulty in alignment between the source contact and the upper conductive plug when the source contact process is performed.
本發明係有關於一種三維堆疊半導體結構及相關之製造方法。根據實施例,源極接點的圖案化步驟(接觸孔內填充導電材料)係在位元線之硬質遮罩層(如介電層)沉積之後進行,因此接觸孔內的導電材料係與硬質遮罩層(如介電層)同水平面。再者,實施例之一導電條(conductive strap)橫跨於多個源極接點之上。因此,實施例之三維堆疊半導體結構具有較低的源極接點阻值、能減少字元線製程影響(WL loading effect)之穩固的建構、和具有可靠度(reliability)良好的電子特性。The present invention relates to a three-dimensional stacked semiconductor structure and related fabrication methods. According to an embodiment, the patterning step of the source contact (filling the conductive material in the contact hole) is performed after the deposition of the hard mask layer (such as the dielectric layer) of the bit line, so that the conductive material in the contact hole is rigid and hard. The mask layer (such as the dielectric layer) is the same as the horizontal plane. Furthermore, one of the embodiments has a conductive strap that spans over a plurality of source contacts. Therefore, the three-dimensional stacked semiconductor structure of the embodiment has a lower source contact resistance, a stable construction capable of reducing the word line effect (WL loading effect), and an electronic property having good reliability.
根據一實施例,係提出一種三維堆疊半導體結構,包括:複數個堆疊(stacks)形成於一基板上、至少一接觸孔(contact hole)垂直形成於該些堆疊其中之一、一導電體(conductor)形成於接觸孔內、一電荷補捉層(charging trapping layer)至少形成於該些堆疊之側壁處。其中之一堆疊包括一多層柱體(multi-layered pillar)包括複數層絕緣層和複數層導電層交替堆疊而成,和一介電層(dielectric layer)形成於多層柱體上。接觸孔係穿過對應堆疊的介電層、該些絕緣層和該些導電層。接觸孔內的導電體(conductor)連接對應堆疊的該些導電層。其中,導電體之上表面係高過於對應堆疊的多層柱體之上表面。According to an embodiment, a three-dimensional stacked semiconductor structure is provided, including: a plurality of stacks formed on a substrate, at least one contact hole formed vertically on one of the stacks, and a conductor (conductor) Formed in the contact hole, a charging trapping layer is formed at least at the sidewalls of the stack. One of the stacks includes a multi-layered pillar including a plurality of insulating layers and a plurality of conductive layers alternately stacked, and a dielectric layer formed on the plurality of pillars. The contact holes pass through the corresponding stacked dielectric layers, the insulating layers, and the conductive layers. Conductors in the contact holes are connected to the conductive layers of the stack. Wherein, the upper surface of the electrical conductor is higher than the upper surface of the stacked multi-layer cylinder.
根據實施例,係提出一種三維堆疊半導體結構之製造方法,包括:形成複數個堆疊於一基板上,其中該些堆疊之一係包括一多層柱體具有複數層絕緣層和複數層導電層交替堆疊而成,和一介電層形成於該多層柱體上;形成至少一接觸孔垂直於該些堆疊其中之一,且接觸孔係穿過對應堆疊的介電層、該些絕緣層和該些導電層;填充一導電體於接觸孔內並連接對應堆疊的該些導電層,其中導電體之一上表面係高過於對應堆疊的多層柱體之一上表面;形成一電荷補捉層至少位於該些堆疊之側壁處。According to an embodiment, a method for fabricating a three-dimensional stacked semiconductor structure is provided, comprising: forming a plurality of stacked on a substrate, wherein one of the stacks comprises a plurality of pillars having a plurality of insulating layers and a plurality of conductive layers alternately Stacked, and a dielectric layer is formed on the multi-layered pillar; forming at least one contact hole perpendicular to one of the stacks, and the contact hole is passed through the corresponding stacked dielectric layer, the insulating layers, and the a conductive layer; filling a conductive body in the contact hole and connecting the conductive layers corresponding to the stack, wherein an upper surface of the conductive body is higher than an upper surface of the stacked multi-layer cylinder; forming a charge trapping layer Located at the side walls of the stacks.
為了對本發明之上述及其他方面有更佳的瞭解,下文特舉實施例,並配合所附圖式,作詳細說明如下。然而,本發明之保護範圍當視後附之申請專利範圍所界定者為準。In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings are set forth below. However, the scope of the invention is defined by the scope of the appended claims.
11‧‧‧陣列區域
13‧‧‧扇出區域
102、103、104、105、112、113、114、115‧‧‧半導體條
102B、103B、104B、105B、112A、113A、114A、115A‧‧‧階梯結構
128‧‧‧源極線
20、40‧‧‧基板
21、41‧‧‧堆疊
21P、41P‧‧‧多層柱體
211、411‧‧‧絕緣層
213、413‧‧‧導電層
23、43‧‧‧硬質遮罩層
23a、43a‧‧‧硬質遮罩層之上表面
24、44‧‧‧接觸孔
25、45‧‧‧導電體
25a、45a‧‧‧導電體之上表面
26、46‧‧‧電荷補捉層
27、47‧‧‧導電條
48‧‧‧隔離層
49‧‧‧導電栓塞
49’‧‧‧導電走線
Rsc‧‧‧源極接點區域
125-1 WL、...、125-N WL、WL‧‧‧字元線
BL‧‧‧位元線
109、119、SSL‧‧‧串列選擇線
126、127、GSL‧‧‧接地選擇線11‧‧‧Array area
13‧‧‧Fan area
102, 103, 104, 105, 112, 113, 114, 115‧‧ ‧ semiconductor strips
102B, 103B, 104B, 105B, 112A, 113A, 114A, 115A‧‧‧ ladder structure
128‧‧‧ source line
20, 40‧‧‧ substrate
21, 41‧‧‧ Stacking
21P, 41P‧‧‧ multilayer cylinder
211, 411‧‧‧ insulation
213, 413‧‧‧ conductive layer
23, 43‧‧‧ hard mask layer
23a, 43a‧‧‧Top surface of hard mask layer
24, 44‧‧‧ contact holes
25, 45‧‧‧ Electrical conductors
25a, 45a‧‧‧ Upper surface of electrical conductor
26, 46‧‧‧ Charge trapping layer
27, 47‧‧‧ Conductive strips
48‧‧‧Isolation
49‧‧‧ Conductive embolization
49'‧‧‧ Conductive trace
Rsc‧‧‧ source contact area
125-1 WL,...,125-N WL, WL‧‧‧ character line
BL‧‧‧ bit line
109, 119, SSL‧‧‧ tandem selection line
126, 127, GSL‧‧‧ grounding selection line
第1圖係為一種3D堆疊半導體結構之立體圖。
第2圖係為本發明一實施例之部份三維堆疊半導體結構的源極接點區域之剖面示意圖。
第3圖係為本發明一實施例之部份三維堆疊半導體結構的上視圖。
第4A ~11A圖和第4B ~ 11B圖係繪示本發明一實施例之三維堆疊半導體結構之製造方法。
第12圖繪示接載源極接點的另一種方式之示意圖。Figure 1 is a perspective view of a 3D stacked semiconductor structure.
2 is a cross-sectional view showing a source contact region of a portion of a three-dimensional stacked semiconductor structure according to an embodiment of the present invention.
Figure 3 is a top plan view of a portion of a three-dimensional stacked semiconductor structure in accordance with an embodiment of the present invention.
4A to 11A and 4B to 11B are diagrams showing a method of fabricating a three-dimensional stacked semiconductor structure according to an embodiment of the present invention.
Figure 12 is a schematic diagram showing another way of carrying the source contacts.
在此揭露內容之實施例中,係提出三維堆疊半導體結構及相關之製造方法。實施例提出之三維堆疊半導體結構,具有較低的源極接點(source contacts)阻值、能減少字元線製程影響(WL loading effect)之穩固的建構、和可靠度(reliability)良好的電子特性。而且,實施例之三維堆疊半導體結構在製作上係具有簡單的步驟,無需採用耗時和昂貴的製程,即可完成。In an embodiment of the present disclosure, a three-dimensional stacked semiconductor structure and associated fabrication method are presented. The three-dimensional stacked semiconductor structure proposed in the embodiment has a low source contact resistance, a stable construction capable of reducing the WL loading effect, and an electron with good reliability. characteristic. Moreover, the three-dimensional stacked semiconductor structure of the embodiment has a simple process of fabrication, which can be accomplished without the use of time consuming and expensive processes.
本揭露之實施例其應用十分廣泛。例如可應用於一三維快閃記憶體,如三維反及閘(NAND)型快閃記憶體的一扇出區域,但本揭露並不以此應用為限。以下係提出相關實施例,配合圖示以詳細說明本揭露所提出之三維堆疊半導體結構及其相關之製造方法。然而本揭露並不僅限於此。實施例中之敘述,如細部結構、製程步驟和材料應用等等,僅為舉例說明之用,並非對本揭露欲保護之範圍做限縮。The embodiments of the present disclosure are widely used. For example, it can be applied to a three-dimensional flash memory, such as a fan-out area of a three-dimensional NAND type flash memory, but the disclosure is not limited to this application. The related embodiments are presented below in conjunction with the drawings to explain in detail the three-dimensional stacked semiconductor structure proposed in the present disclosure and related manufacturing methods. However, the disclosure is not limited to this. The description of the embodiments, such as the detailed structure, the process steps, the application of the materials, and the like, are for illustrative purposes only and are not intended to limit the scope of the disclosure.
再者,本揭露並非顯示出所有可能的實施例。可在不脫離本揭露之精神和範圍內對結構和製程加以變化與修飾,以符合實際應用製程之需要。因此,未於本揭露提出的其他實施態樣也可能可以應用。再者,圖式上的尺寸比例並非按照實際產品等比例繪製。因此,說明書和圖示內容僅作敘述實施例之用,而非作為限縮本揭露保護範圍之用。Furthermore, the disclosure does not show all possible embodiments. The structure and process may be modified and modified to meet the needs of the actual application process without departing from the spirit and scope of the disclosure. Therefore, other implementations not presented in the present disclosure may also be applicable. Furthermore, the dimensional ratios on the drawings are not drawn in proportion to the actual product. Therefore, the description and illustration are for illustrative purposes only and are not intended to be limiting.
根據實施例,三維堆疊半導體結構之源極接點(source contacts)的圖案化步驟係在位元線之硬質遮罩沉積之後進行,硬質遮罩層之材料例如是一介電層材料。第2圖係為本發明一實施例之部份三維堆疊半導體結構的源極接點區域之剖面示意圖。實施例之一半導體結構包括複數個堆疊(stacks)21形成於一基板20上,且其中之一堆疊21包括一多層柱體(multi-layered pillar)21P和一硬質遮罩層(hard mask layer)23形成於多層柱體21P上。多層柱體21P係包括複數層絕緣層211(例如氧化層)和複數層導電層213(例如多晶矽層)交替堆疊而成。硬質遮罩層23則形成於多層柱體21P之最上層的絕緣層211上。硬質遮罩層23之材料例如是一介電層(dielectric layer)之材料,但本揭露並不以此為限制。According to an embodiment, the patterning step of the source contacts of the three-dimensional stacked semiconductor structure is performed after the hard mask deposition of the bit lines, the material of the hard mask layer being, for example, a dielectric layer material. 2 is a cross-sectional view showing a source contact region of a portion of a three-dimensional stacked semiconductor structure according to an embodiment of the present invention. A semiconductor structure of an embodiment includes a plurality of stacks 21 formed on a substrate 20, and one of the stacks 21 includes a multi-layered pillar 21P and a hard mask layer. 23 is formed on the multilayer cylinder 21P. The multilayer pillar 21P includes a plurality of insulating layers 211 (for example, an oxide layer) and a plurality of conductive layers 213 (for example, a polysilicon layer) alternately stacked. The hard mask layer 23 is formed on the insulating layer 211 of the uppermost layer of the multilayer pillar 21P. The material of the hard mask layer 23 is, for example, a material of a dielectric layer, but the disclosure is not limited thereto.
實施例之半導體結構亦包括至少一接觸孔(contact hole)24垂直形成於其中之一堆疊21,且接觸孔24係穿過對應之堆疊21的硬質遮罩層23、該些絕緣層211和該些導電層213。如第2圖所繪示的兩個接觸孔24,但當然本揭露並不對接觸孔的數目多作限制。再者,一導電體(conductor)25係形成於接觸孔24內,並連接對應堆疊21的該些導電層213(即接觸孔24延伸所到之處)。The semiconductor structure of the embodiment also includes at least one contact hole 24 formed vertically in one of the stacks 21, and the contact holes 24 are passed through the hard mask layer 23 of the corresponding stack 21, the insulating layers 211 and the Some conductive layers 213. The two contact holes 24 are as shown in Fig. 2, but of course, the disclosure does not limit the number of contact holes. Furthermore, a conductor 25 is formed in the contact hole 24 and connected to the conductive layers 213 of the corresponding stack 21 (i.e. where the contact holes 24 extend).
實施例之半導體結構亦包括一電荷補捉層(charging trapping layer)26,如一ONO層(氧化層-氮化層-氧化層)或一ONONO層(氧化層-氮化層-氧化層-氮化層-氧化層),至少形成於該些堆疊21之側壁處。如第2圖所示,電荷補捉層26形成於堆疊21之側壁處,且導電體25之一上表面25a和硬質遮罩層23之一上表面23a係暴露出來,並沒有被電荷補捉層26覆蓋。The semiconductor structure of the embodiment also includes a charging trapping layer 26, such as an ONO layer (oxide layer-nitride layer-oxide layer) or an ONONO layer (oxide layer-nitride layer-oxide layer-nitridation layer). A layer-oxide layer is formed at least at the sidewalls of the stacks 21. As shown in Fig. 2, a charge trapping layer 26 is formed at the sidewall of the stack 21, and an upper surface 25a of the conductor 25 and an upper surface 23a of the hard mask layer 23 are exposed and are not trapped by the charge. Layer 26 is covered.
上述導電體25可做為一實施例之三維堆疊半導體結構的一源極接點(source contacts)。如第2圖所示,導電體25之一上表面25a係高過於對應堆疊21的多層柱體21P之一上表面。在一實施例中,導電體25之上表面25a係實質上與硬質遮罩層23之上表面23a對齊。The above-mentioned electrical conductor 25 can be used as a source contact of the three-dimensional stacked semiconductor structure of an embodiment. As shown in Fig. 2, one upper surface 25a of the conductor 25 is higher than the upper surface of one of the multilayer cylinders 21P of the stack 21. In one embodiment, the upper surface 25a of the electrical conductor 25 is substantially aligned with the upper surface 23a of the hard mask layer 23.
根據實施例,一導電條(conductive strap)27更形成於該些堆疊21之上方且接觸電荷補捉層26。其中,導電條27係形成於和橫跨(across)於接觸孔24內之導電體25的上方。導電條27係與接觸孔24內之導電體25和堆疊21側壁處之電荷補捉層26電性連接。第3圖係為本發明一實施例之部份三維堆疊半導體結構的上視圖,其中係顯示導電條27形成於接觸孔24內之導電體25上,且與多條字元線(WL)平行。According to an embodiment, a conductive strap 27 is formed over the stacks 21 and contacts the charge trapping layer 26. The conductive strips 27 are formed over and across the electrical conductors 25 in the contact holes 24. The conductive strips 27 are electrically connected to the conductors 25 in the contact holes 24 and the charge trapping layer 26 at the sidewalls of the stack 21. 3 is a top view of a portion of a three-dimensional stacked semiconductor structure in accordance with an embodiment of the present invention, wherein the conductive strips 27 are formed on the conductors 25 in the contact holes 24 and are parallel to the plurality of word lines (WL). .
根據實施例,導電條27係為一接觸接點之導電條(source contact strap),藉此可降低接觸接點之阻值。在一實施例中,導電條27可以和字元線以相同材料同時製作。再者,實施例之導電條27係建構於源極接點區域(SC region),因此,源極接點(即導電體25)係受導電條27覆蓋和保護(而非傳統結構中源極接點是受位元線硬質遮罩層(/介電層)覆蓋),藉此可降低字元線製程對源極接點區域的影響(WL loading effect)。再者,既然實施例之源極接點的圖案化步驟是在位元線硬質遮罩層沉積之後進行,則源極接點中不會沉積有硬質遮罩層之材料。According to an embodiment, the conductive strip 27 is a source contact strap that reduces the resistance of the contact contacts. In an embodiment, the conductive strips 27 can be fabricated simultaneously with the word lines in the same material. Furthermore, the conductive strip 27 of the embodiment is constructed in the source region (SC region), and therefore, the source contact (ie, the conductor 25) is covered and protected by the conductive strip 27 (rather than the source in the conventional structure) The contacts are covered by a bit line hard mask layer (/dielectric layer), thereby reducing the effect of the word line process on the source contact area (WL loading effect). Moreover, since the patterning step of the source contact of the embodiment is performed after the deposition of the bit line hard mask layer, the material of the hard mask layer is not deposited in the source contact.
以下係提出三維堆疊半導體結構之一製造方法。但本揭露並不以此結構和步驟之細節為限,而是可視製程或實際應用所需做適當調整和變化。The following is a method of manufacturing a three-dimensional stacked semiconductor structure. However, the disclosure is not limited to the details of the structure and the steps, but may be appropriately adjusted and changed as needed for the process or the actual application.
第4A ~11A圖和第4B ~ 11B圖係繪示本發明一實施例之三維堆疊半導體結構之製造方法。其中,標記為A的圖示如第4A, 5A, 6A,…11A圖係繪示實施例之三維堆疊半導體結構之上視圖。標記為B的圖示如第4B, 5B, 6B,…11B圖係分別為沿著第4A, 5A, 6A,…11A圖之剖面線AA的剖面圖。其中,剖面線AA的位置係對應於一源極接點區域(source contact region)。4A to 11A and 4B to 11B are diagrams showing a method of fabricating a three-dimensional stacked semiconductor structure according to an embodiment of the present invention. Here, the illustration labeled A is as shown in Figs. 4A, 5A, 6A, ..., 11A, and is a top view of the three-dimensional stacked semiconductor structure of the embodiment. The diagrams labeled B are as shown in sections 4B, 5B, 6B, ... 11B, respectively, along the section line AA of Figs. 4A, 5A, 6A, ... 11A. The position of the hatching AA corresponds to a source contact region.
如第4A圖和第4B圖所示,係形成複數個堆疊41於一基板40上,包括複數層絕緣層411(例如氧化層)和複數層導電層413(例如多晶矽層)交替堆疊而成為一堆疊41中之一多層柱體(multi-layered pillar)41P,並形成一硬質遮罩層(hard mask layer)43於多層柱體41P之最上層的絕緣層411上。硬質遮罩層43的材料可以是一介電層材料,例如是包括氮化矽或氧化物,沉積於絕緣層411上方。As shown in FIG. 4A and FIG. 4B, a plurality of stacks 41 are formed on a substrate 40, and a plurality of insulating layers 411 (eg, an oxide layer) and a plurality of conductive layers 413 (eg, polysilicon layers) are alternately stacked to form a stack. A multi-layered pillar 41P of the stack 41 is formed, and a hard mask layer 43 is formed on the uppermost insulating layer 411 of the multilayer pillar 41P. The material of the hard mask layer 43 may be a dielectric layer material, for example, including tantalum nitride or oxide, deposited over the insulating layer 411.
如第5A圖和第5B圖所示,垂直形成至少一接觸孔(contact hole)44,且接觸孔44係穿過硬質遮罩層43、該些絕緣層411和該些導電層413。As shown in FIGS. 5A and 5B, at least one contact hole 44 is formed vertically, and the contact hole 44 passes through the hard mask layer 43, the insulating layer 411, and the conductive layers 413.
在如第5A圖和第5B圖所示之源極接點圖案化的步驟後,係填充一導電材料於接觸孔44處以建構一源極接點。在一實施例中,一導電層(材料例如是N+ 多晶矽)係沉積於硬質遮罩層43上並填滿接觸孔44,接著對導電層進行平坦化以形成接觸孔44內之導電體45。在一實施例中,係以化學機械研磨(chemical mechanical polishing,CMP)或其它適當步驟進行導電層的平坦化。如第6A圖和第6B圖所示,導電體45之上表面45a係實質上與硬質遮罩層43之上表面43a對齊。根據實施例之製造方法,導電體45之上表面45a係高過於最上層絕緣層411之上表面。After the step of patterning the source contacts as shown in FIGS. 5A and 5B, a conductive material is filled at the contact holes 44 to construct a source contact. In one embodiment, a conductive layer (such as N+ polysilicon) is deposited on the hard mask layer 43 and fills the contact holes 44, and then the conductive layer is planarized to form the conductors 45 in the contact holes 44. In one embodiment, the planarization of the conductive layer is performed by chemical mechanical polishing (CMP) or other suitable steps. As shown in FIGS. 6A and 6B, the upper surface 45a of the conductor 45 is substantially aligned with the upper surface 43a of the hard mask layer 43. According to the manufacturing method of the embodiment, the upper surface 45a of the conductor 45 is higher than the upper surface of the uppermost insulating layer 411.
如第7A圖和第7B圖所示,接著圖案化第6B圖之結構以形成位元線(bit lines,BL)和堆疊41。在一實施例中,使用APF製程進行位元線之圖案化時,將不會對位元線之硬質遮罩層(/介電層)造成損傷。如第7B圖所示,一位元線(BL)係形成於兩個堆疊41 之間,各堆疊41係具有源極接點(即導電體45)。其中,各堆疊41包括一多層柱體(multi-layered pillar)41P和一硬質遮罩層43形成於多層柱體41P上,一多層柱體41P包括數層絕緣層411和數層導電層413交替堆疊而成;填充於接觸孔44內的導電體45係垂直地穿過對應堆疊41的硬質遮罩層43、絕緣層411和導電層413。As shown in FIGS. 7A and 7B, the structure of FIG. 6B is then patterned to form bit lines (BL) and stack 41. In one embodiment, when the ATF process is used to pattern the bit lines, the hard mask layer (/dielectric layer) of the bit lines will not be damaged. As shown in FIG. 7B, one bit line (BL) is formed between the two stacks 41, and each stack 41 has a source contact (ie, conductor 45). Each of the stacks 41 includes a multi-layered pillar 41P and a hard mask layer 43 formed on the multilayer pillar 41P. The multilayer pillar 41P includes a plurality of insulating layers 411 and a plurality of conductive layers. The 413 is alternately stacked; the electric conductor 45 filled in the contact hole 44 passes through the hard mask layer 43, the insulating layer 411, and the conductive layer 413 of the corresponding stack 41 vertically.
之後,一電荷補捉層46(如一ONO層或一ONONO層)形成於該些堆疊41和位元線之至少側壁處。本揭露中,係可應用不同步驟來製得此結構,例如第8B圖和第9B圖之步驟。Thereafter, a charge trapping layer 46 (such as an ONO layer or an ONONO layer) is formed on the stack 41 and at least sidewalls of the bit lines. In the present disclosure, different steps can be applied to make the structure, such as steps 8B and 9B.
如第8A圖和第8B圖所示,一電荷補捉層46(如一ONO層或一ONONO層)係沉積以覆蓋堆疊41、位元線(BL)和基板。之後,移除電荷補捉層46的一部份(例如上部),以暴露出導電體45的上表面45a、位元線的上表面和硬質遮罩層43的上表面43a,如第9A圖和第9B圖所示。在一實施例中,可應用一微影製程於一光阻以定義(打開)源極接點區域Rsc,且僅對應源極接點區域Rsc之電荷補捉層46的上部被移除,如第9A圖所示。而源極接點區域Rsc之外的區域仍被電荷補捉層46所覆蓋。在另一實施例中,不使用光阻,而是所有堆疊41和位元線(BL)的電荷補捉層46之上部都被移除,亦可應用。本揭露對此並不多作限制。電荷補捉層46例如是以反應性離子蝕刻(Reactive-ion etching,RIE)所移除以暴露出接觸孔44內的導電體45。再者,可應用一有機介電層(ODL,organic dielectric layer)/SHB之製程來克服導電體45結構高度上的問題。As shown in FIGS. 8A and 8B, a charge trapping layer 46 (such as an ONO layer or an ONONO layer) is deposited to cover the stack 41, the bit line (BL), and the substrate. Thereafter, a portion (eg, upper portion) of the charge trapping layer 46 is removed to expose the upper surface 45a of the conductor 45, the upper surface of the bit line, and the upper surface 43a of the hard mask layer 43, as shown in FIG. And Figure 9B shows. In one embodiment, a lithography process can be applied to a photoresist to define (turn on) the source contact region Rsc, and only the upper portion of the charge trapping layer 46 corresponding to the source contact region Rsc is removed, such as Figure 9A shows. The region other than the source contact region Rsc is still covered by the charge trapping layer 46. In another embodiment, instead of photoresist, all of the stack 41 and the upper portion of the charge trapping layer 46 of the bit line (BL) are removed and may be applied. This disclosure does not limit this much. The charge trapping layer 46 is removed, for example, by reactive ion etching (RIE) to expose the electrical conductors 45 within the contact holes 44. Furthermore, an organic dielectric layer (ODL)/SHB process can be applied to overcome the problem of the structural height of the conductor 45.
之後,一導電條(conductive strap)47係形成於和橫跨(如第3圖所示)該些堆疊41之上方,且對應源極接點區域Rsc。如第10A圖和第10B圖所示,導電條47和多條字元線(WL)可同時形成於堆疊41和位元線(BL)上方。因此,實施例之導電條47和字元線係可用相同材料製成。在一實施例中,導電條47和字元線例如是包括多晶矽(以自對準金屬矽化物製程製作)。然而,本揭露對此並不多作限制,導電條47和字元線的材料可以相同可以不同,可以同時製作或不同時製作,其材料可以依實際應用情況所需而作適當選擇。Thereafter, a conductive strap 47 is formed over and across (as shown in FIG. 3) the stacks 41 and corresponding to the source contact regions Rsc. As shown in FIGS. 10A and 10B, the conductive strip 47 and the plurality of word lines (WL) may be simultaneously formed over the stack 41 and the bit line (BL). Therefore, the conductive strip 47 and the word line system of the embodiment can be made of the same material. In one embodiment, the conductive strips 47 and the word lines are, for example, polycrystalline germanium (made in a self-aligned metal germanide process). However, the disclosure does not limit this. The materials of the conductive strips 47 and the word lines may be the same or different, and may be made at the same time or at different times, and the materials may be appropriately selected according to actual application requirements.
如第10A圖所示,導電條47係和字元線(WL)平行設置,且彼此間隔開一距離。如第10B圖所示,導電條47 係電性連接接觸孔44內之導電體45(例如接觸導電體45的上表面45a) 和電荷補捉層46。導電條47也接觸硬質遮罩層43之上表面43a。As shown in Fig. 10A, the conductive strips 47 are arranged in parallel with the word lines (WL) and spaced apart from each other by a distance. As shown in FIG. 10B, the conductive strip 47 is electrically connected to the conductor 45 (for example, the upper surface 45a of the contact conductor 45) and the charge trapping layer 46 in the contact hole 44. The conductive strip 47 also contacts the upper surface 43a of the hard mask layer 43.
之後,一導電部(conducting portion)係形成於導電條47上,以接載來自源極接點(如導電體45)之訊號。其中,導電部係與導電體45和硬質遮罩層43相隔一距離。實施例中,導電部可以是一導電走線(conductive line)或導電栓塞(conductive plug)。Thereafter, a conducting portion is formed on the conductive strip 47 to receive the signal from the source contact (e.g., the electrical conductor 45). The conductive portion is separated from the conductor 45 and the hard mask layer 43 by a distance. In an embodiment, the conductive portion may be a conductive line or a conductive plug.
如第11A圖和第11B圖所示,形成一隔離層(如內層介電層ILD)48於導電條47上,並形成多個孔洞於隔離層48內並穿過隔離層48,接著以一導電材料如鎢或其他適合之金屬填充孔洞。如第11B圖所示,係於隔離層48之孔洞中形成導電栓塞(conductive plug)49。其中,導電栓塞49係藉由導電條47與接觸孔44內之導電體45電性連接。另外,如第12圖所示,其繪示接載源極接點的另一種方式之示意圖,其中導電部係為一導電走線49’形成於導電條47上方且橫跨該些堆疊41。導電走線49’例如是鎢、或是與字元線同樣的材料、或其他適合之導電材料。As shown in FIGS. 11A and 11B, an isolation layer (such as an inner dielectric layer ILD) 48 is formed on the conductive strip 47, and a plurality of holes are formed in the isolation layer 48 and through the isolation layer 48, and then A conductive material such as tungsten or other suitable metal fills the holes. As shown in FIG. 11B, a conductive plug 49 is formed in the hole of the isolation layer 48. The conductive plugs 49 are electrically connected to the electrical conductors 45 in the contact holes 44 by the conductive strips 47. Further, as shown in Fig. 12, there is shown a schematic view of another manner of receiving the source contacts, wherein the conductive portions are formed by a conductive trace 49' over the conductive strips 47 and across the stacks 41. The conductive trace 49' is, for example, tungsten, or the same material as the word line, or other suitable conductive material.
根據實施例之結構,即導電體45、導電條47和導電部(49/49’)的建構,無須考慮是否有導電栓塞和源極接點之間無法對準之問題。因此,實施例提出之三維堆疊半導體結構具有可靠度(reliability)良好的電子特性。According to the structure of the embodiment, that is, the construction of the conductor 45, the bus bar 47, and the conductive portion (49/49'), it is not necessary to consider whether or not there is a problem of misalignment between the conductive plug and the source contact. Therefore, the three-dimensional stacked semiconductor structure proposed in the embodiment has good electronic properties with good reliability.
根據上述實施例,三維堆疊半導體結構中的源極接點圖案化係於位元線硬質遮罩層(介電材料)沈積之後才進行,源極接點中不會沉積有硬質遮罩層之材料。再者,作為實施例之三維堆疊半導體結構的一源極接點的導電體25/45係突出於多層柱體21P/41P之上表面,亦即高於傳統源極接點之高度,因而降低源極接點的阻值。再者,實施例之導電條strap 27/47係建構於源極接點區域,使源極接點(即導電體25)受到導電條27的保護(而非傳統結構中源極接點是受位元線硬質遮罩層覆蓋),因而降低字元線製程對源極接點區域的影響(WL loading effect)。再者,實施例之導電條27/47可以和字元線以相同材料同時製作,在製作步驟上簡單省時,適合量產。According to the above embodiment, the source contact patterning in the three-dimensional stacked semiconductor structure is performed after the deposition of the bit line hard mask layer (dielectric material), and the hard mask layer is not deposited in the source contact. material. Furthermore, the conductor 25/45 of a source contact of the three-dimensional stacked semiconductor structure of the embodiment protrudes from the upper surface of the multilayer pillar 21P/41P, that is, higher than the height of the conventional source contact, thereby reducing The resistance of the source contact. Furthermore, the conductive strips 27/47 of the embodiment are constructed in the source contact region, so that the source contact (ie, the conductor 25) is protected by the conductive strip 27 (instead of the source contact in the conventional structure is subject to The bit line is covered by a hard mask layer, thereby reducing the effect of the word line process on the source contact area (WL loading effect). Furthermore, the conductive strips 27/47 of the embodiment can be fabricated simultaneously with the word lines in the same material, which is simple and time-saving in the production steps, and is suitable for mass production.
綜上所述,雖然本發明已以實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
25‧‧‧導電體 25‧‧‧Electric conductor
27‧‧‧導電條 27‧‧‧ Conductive strip
WL‧‧‧字元線 WL‧‧‧ character line
SSL‧‧‧串列選擇線 SSL‧‧‧ tandem selection line
GSL‧‧‧接地選擇線 GSL‧‧‧ Grounding selection line
Claims (1)
(1)
一種三維堆疊半導體結構(3D stacked semiconductor structure),包括:
複數個堆疊(stacks)形成於一基板上,且該些堆疊其中之一包括:
一多層柱體(multi-layered pillar)包括複數層絕緣層和複數層導電層交替堆疊而成;
一介電層(dielectric layer)形成於該多層柱體上;
至少一接觸孔(contact hole)垂直形成於該些堆疊其中之一,且該接觸孔係穿過對應之該堆疊的該介電層、該些絕緣層和該些導電層;
一導電體(conductor)形成於該接觸孔內並連接對應之該堆疊的該些導電層;和
一電荷補捉層(charging trapping layer)至少形成於該些堆疊之側壁處;
其中該導電體之一上表面係高過於對應之該堆疊的該多層柱體之一上表面。
(2)
如申請專利範圍第1項所述之三維堆疊半導體結構,更包括一導電條(conductive strap)形成於該些堆疊上方且接觸該電荷補捉層。
(3)
如申請專利範圍第2項所述之三維堆疊半導體結構,其中該導電條接觸該導電體之該上表面和該介電層之一上表面。
(4)
如申請專利範圍第2項所述之三維堆疊半導體結構,更包括一導電部(conducting portion)形成於該導電條上,其中該導電部係與該介電層和該接觸孔內之該導電體相隔開一距離。
(5)
如申請專利範圍第2項所述之三維堆疊半導體結構,更包括:
一隔離層(isolating layer)形成於該導電條上;和
至少一導電栓塞(conductive plug)形成於該隔離層內並穿過該隔離層,
其中該導電栓塞係藉由該導電條與該接觸孔內之該導電體電性連接。
(6)
一種三維堆疊半導體結構之製造方法,包括:
形成複數個堆疊(stacks)於一基板上,該些堆疊其中之一係包括:
一多層柱體(multi-layered pillar)包括複數層絕緣層和複數層導電層交替堆疊而成;
一介電層(dielectric layer)形成於該多層柱體上;
形成至少一接觸孔(contact hole)垂直於該些堆疊其中之一,且該接觸孔係穿過對應之該堆疊的該介電層、該些絕緣層和該些導電層;
填充一導電體(conductor)於該接觸孔內並連接對應之該堆疊的該些導電層,其中該導電體之一上表面係高過於對應之該堆疊的該多層柱體之一上表面;
形成一電荷補捉層(charging trapping layer)至少位於該些堆疊之側壁處。
(7)
如申請專利範圍第6項所述之方法,其中該導電條接觸該導電體之該上表面和該介電層之一上表面。
(8)
如申請專利範圍第7項所述之方法,其中該導電條係與該些字元線係以相同材料製成。
(9)
如申請專利範圍第6項所述之方法,更包括形成一導電部(conducting portion)於該導電條上,其中該導電部係與該介電層和該接觸孔內之該導電體相隔開一距離。
(10)
如申請專利範圍第6項所述之方法,更包括
形成一隔離層(isolating layer)於該導電條上;
形成至少一孔洞於該隔離層內並穿過該隔離層;和
形成一導電栓塞(conductive plug)於該隔離層之該孔洞中,
其中,該導電栓塞係藉由該導電條與該接觸孔內之該導電體電性連接。
(1)
A three-dimensional stacked semiconductor structure includes:
A plurality of stacks are formed on a substrate, and one of the stacks includes:
A multi-layered pillar includes a plurality of layers of insulating layers and a plurality of layers of conductive layers alternately stacked;
A dielectric layer is formed on the multilayer pillar;
At least one contact hole is formed vertically on one of the stacks, and the contact hole is passed through the dielectric layer, the insulating layer and the conductive layers corresponding to the stack;
a conductor formed in the contact hole and connecting the conductive layers corresponding to the stack; and
A charging trapping layer is formed at least at sidewalls of the stacks;
Wherein an upper surface of the electrical conductor is higher than an upper surface of the stacked multi-layer cylinder.
(2)
The three-dimensional stacked semiconductor structure of claim 1, further comprising a conductive strap formed over the stack and contacting the charge trapping layer.
(3)
The three-dimensional stacked semiconductor structure of claim 2, wherein the conductive strip contacts the upper surface of the electrical conductor and an upper surface of the dielectric layer.
(4)
The three-dimensional stacked semiconductor structure of claim 2, further comprising a conducting portion formed on the conductive strip, wherein the conductive portion and the dielectric layer and the conductive body in the contact hole Separated by a distance.
(5)
The three-dimensional stacked semiconductor structure as described in claim 2, further comprising:
An isolating layer is formed on the conductive strip; and
At least one conductive plug is formed in the isolation layer and passes through the isolation layer.
The conductive plug is electrically connected to the conductive body in the contact hole by the conductive strip.
(6)
A method of fabricating a three-dimensional stacked semiconductor structure, comprising:
Forming a plurality of stacks on a substrate, one of the stacks comprising:
A multi-layered pillar includes a plurality of layers of insulating layers and a plurality of layers of conductive layers alternately stacked;
A dielectric layer is formed on the multilayer pillar;
Forming at least one contact hole perpendicular to one of the stacks, and the contact hole passes through the dielectric layer, the insulating layer and the conductive layers corresponding to the stack;
Filling a conductor in the contact hole and connecting the conductive layers corresponding to the stack, wherein an upper surface of the conductive body is higher than an upper surface of the stacked multi-layer cylinder;
A charging trapping layer is formed at least at the sidewalls of the stacks.
(7)
The method of claim 6, wherein the conductive strip contacts the upper surface of the electrical conductor and an upper surface of the dielectric layer.
(8)
The method of claim 7, wherein the conductive strip is made of the same material as the word lines.
(9)
The method of claim 6, further comprising forming a conducting portion on the conductive strip, wherein the conductive portion is separated from the dielectric layer and the conductive body in the contact hole distance.
(10)
For example, the method described in claim 6 of the patent scope includes
Forming an isolating layer on the conductive strip;
Forming at least one hole in the isolation layer and passing through the isolation layer; and
Forming a conductive plug in the hole of the isolation layer,
The conductive plug is electrically connected to the conductive body in the contact hole by the conductive strip.
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US9437611B1 (en) | 2015-02-24 | 2016-09-06 | Macronix International Co., Ltd. | Semiconductor device and manufacturing method thereof |
TWI555127B (en) * | 2015-05-15 | 2016-10-21 | 旺宏電子股份有限公司 | Memory device and method for fabricating the same |
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US9437611B1 (en) | 2015-02-24 | 2016-09-06 | Macronix International Co., Ltd. | Semiconductor device and manufacturing method thereof |
US9576972B2 (en) | 2015-02-24 | 2017-02-21 | Macronix International Co., Ltd. | Semiconductor device and manufacturing method thereof |
US9754790B2 (en) | 2015-05-14 | 2017-09-05 | Macronix International Co., Ltd. | Memory device and method for fabricating the same |
TWI555127B (en) * | 2015-05-15 | 2016-10-21 | 旺宏電子股份有限公司 | Memory device and method for fabricating the same |
TWI607528B (en) * | 2015-06-05 | 2017-12-01 | 旺宏電子股份有限公司 | Semiconductor device and manufacturing method thereof |
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