TWI616986B

TWI616986B - Semiconductor structure and method for manufacturing the same

Info

Publication number: TWI616986B
Application number: TW106105147A
Authority: TW
Inventors: 陳晟弘; 廖廷豐
Original assignee: 旺宏電子股份有限公司
Priority date: 2017-02-16
Filing date: 2017-02-16
Publication date: 2018-03-01
Also published as: TW201832321A

Abstract

一種半導體結構包括一基板和複數個次陣列結構，次陣列結構設置在基板上並藉由複數個溝槽彼此分離。此種半導體結構包括複數個記憶胞構成的一三維陣列。該些記憶胞包括複數個記憶胞群，分別設置在次陣列結構中。此種半導體結構更包括複數個支撐柱和複數個導電柱，設置在溝槽中。每一溝槽中的支撐柱和導電柱在溝槽的一延伸方向上交替配置。此種半導體結構更包括複數個導電線，設置在溝槽中，並位在支撐柱和導電柱上。每一導電線連接位在其下方的導電柱。 A semiconductor structure includes a substrate and a plurality of sub-array structures disposed on the substrate and separated from each other by a plurality of trenches. Such a semiconductor structure includes a three-dimensional array of a plurality of memory cells. The memory cells include a plurality of memory cell groups, respectively disposed in the sub-array structure. The semiconductor structure further includes a plurality of support columns and a plurality of conductive columns disposed in the trenches. The support columns and the conductive pillars in each of the grooves are alternately arranged in an extending direction of the grooves. The semiconductor structure further includes a plurality of conductive lines disposed in the trenches and positioned on the support pillars and the conductive pillars. Each conductive line is connected to a conductive post below it.

Description

半導體結構及其製造方法 Semiconductor structure and method of manufacturing same

本揭露是關於一種半導體結構及其製造方法。本揭露特別是關於一種包括記憶胞的半導體結構及其製造方法。 The present disclosure relates to a semiconductor structure and a method of fabricating the same. The present disclosure relates in particular to a semiconductor structure including a memory cell and a method of fabricating the same.

為了減少體積、降低重量、增加功率密度和改善可攜帶性等等理由，發展出了三維的(3-D)半導體結構。此外，半導體裝置中的元件和空間持續地被縮減。這可能導致一些問題。例如，在3-D記憶裝置的製程中，可能為了記憶胞和/或其他元件的建造而形成具有高深寬比的堆疊。這樣的堆疊可能會因其高深寬比而彎曲或倒塌。因此，仍希望對於半導體結構及其製造方法有各種不同的改善。 In order to reduce the volume, reduce the weight, increase the power density, and improve the portability, a three-dimensional (3-D) semiconductor structure has been developed. Furthermore, components and spaces in semiconductor devices are continuously reduced. This can cause some problems. For example, in the fabrication of a 3-D memory device, a stack having a high aspect ratio may be formed for the construction of memory cells and/or other components. Such a stack may bend or collapse due to its high aspect ratio. Therefore, it is still desirable to have various improvements to the semiconductor structure and its method of fabrication.

本揭露是關於半導體結構及其製造方法，特別是關於包括記憶胞的半導體結構及其製造方法。 The present disclosure relates to semiconductor structures and methods of fabricating the same, and more particularly to semiconductor structures including memory cells and methods of fabricating the same.

根據一些實施例，一種半導體結構包括一基板和複數個次陣列結構，次陣列結構設置在基板上並藉由複數個溝槽彼此分離。此種半導體結構包括複數個記憶胞構成的一三維陣列。該些記憶胞包括複數個記憶胞群，分別設置在次陣列結構中。此種半導體結構更包括複數個支撐柱和複數個導電柱，設置在溝槽中。該些溝槽的每一者中的支撐柱和導電柱在溝槽的一延伸方向上交替配置。此種半導體結構更包括複數個導電線，設置在溝槽中，並位在支撐柱和導電柱上。該些導電線的每一者連接位在其下方的導電柱。 In accordance with some embodiments, a semiconductor structure includes a substrate and a plurality of sub-array structures disposed on a substrate and separated from one another by a plurality of trenches. Such a semiconductor structure includes a three-dimensional array of a plurality of memory cells. The memory cells include a plurality of memory cell groups, respectively disposed in the sub-array structure. The semiconductor structure further includes a plurality of support columns and a plurality of conductive columns disposed in the trenches. The support post and the conductive post in each of the trenches are alternately arranged in an extending direction of the trench. The semiconductor structure further includes a plurality of conductive lines disposed in the trenches and positioned on the support pillars and the conductive pillars. Each of the electrically conductive wires is connected to a conductive post below it.

根據一些實施例，一種半導體結構的製造方法包括下列步驟。首先，提供一起始結構。起始結構包括一基板和形成在基板上的一初步陣列結構。初步陣列結構包括一堆疊和穿過堆疊的複數個主動結構。該些主動結構的每一者包括一通道層和形成在通道層和堆疊之間的一記憶層。在配置成用於將初步陣列結構分離成複數個次陣列結構之複數個溝槽的複數個預定溝槽位置形成複數個支撐柱。該些預定溝槽位置的每一者中的支撐柱彼此分離。接著，在預定溝槽位置形成複數個導電柱，使得該些預定溝槽位置的每一者中的導電柱和支撐柱在預定溝槽位置的一延伸方向上交替配置。在支撐柱和導電柱上形成複數個導電線。 According to some embodiments, a method of fabricating a semiconductor structure includes the following steps. First, a starting structure is provided. The starting structure includes a substrate and a preliminary array structure formed on the substrate. The preliminary array structure includes a plurality of active structures stacked and passed through the stack. Each of the active structures includes a channel layer and a memory layer formed between the channel layer and the stack. A plurality of support pillars are formed at a plurality of predetermined trench locations configured to separate the preliminary array structure into a plurality of trenches of the plurality of sub-array structures. The support columns in each of the predetermined groove positions are separated from each other. Next, a plurality of conductive pillars are formed at predetermined groove positions such that the conductive pillars and the support pillars in each of the predetermined trench locations are alternately arranged in an extending direction of the predetermined trench position. A plurality of conductive lines are formed on the support post and the conductive post.

為了對本發明之上述及其他方面有更佳的瞭解，下文特舉實施例，並配合所附圖式詳細說明如下： In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

102‧‧‧基板 102‧‧‧Substrate

104‧‧‧埋層 104‧‧‧ buried layer

108‧‧‧堆疊 108‧‧‧Stacking

110‧‧‧導電層 110‧‧‧ Conductive layer

112‧‧‧高介電常數介電層 112‧‧‧High dielectric constant dielectric layer

114‧‧‧導電芯層 114‧‧‧ Conductive core layer

116‧‧‧絕緣層 116‧‧‧Insulation

118‧‧‧硬遮罩層 118‧‧‧hard mask layer

120‧‧‧主動結構 120‧‧‧Active structure

122‧‧‧通道層 122‧‧‧Channel layer

124‧‧‧記憶層 124‧‧‧ memory layer

126‧‧‧絕緣材料 126‧‧‧Insulation materials

128‧‧‧導電接墊 128‧‧‧Electrical pads

130‧‧‧記憶胞 130‧‧‧ memory cells

132‧‧‧層間介電層 132‧‧‧Interlayer dielectric layer

140‧‧‧次陣列結構 140‧‧‧ array structure

150‧‧‧溝槽 150‧‧‧ trench

152‧‧‧支撐柱 152‧‧‧Support column

153‧‧‧導電柱 153‧‧‧conductive column

154‧‧‧導電中央部分 154‧‧‧conductive central part

156‧‧‧絕緣襯層 156‧‧‧Insulation lining

158‧‧‧導電線 158‧‧‧Flexible wire

208‧‧‧堆疊 208‧‧‧Stacking

210‧‧‧犧牲層 210‧‧‧ Sacrifice layer

212‧‧‧高介電常數介電層 212‧‧‧High dielectric constant dielectric layer

216‧‧‧絕緣層 216‧‧‧Insulation

218‧‧‧硬遮罩層 218‧‧‧ hard mask layer

232‧‧‧層間介電層 232‧‧‧Interlayer dielectric layer

250‧‧‧預定溝槽位置 250‧‧‧Predetermined groove location

252‧‧‧支撐柱 252‧‧‧Support column

253‧‧‧導電柱 253‧‧‧conductive column

254‧‧‧導電中央部分 254‧‧‧conductive central part

256‧‧‧絕緣襯層 256‧‧‧Insulation lining

272‧‧‧第一開口 272‧‧‧ first opening

274‧‧‧光阻層 274‧‧‧Photoresist layer

276‧‧‧孔洞 276‧‧‧ holes

278‧‧‧第二開口 278‧‧‧second opening

第1A~1C圖繪示根據實施例的一種半導體結構。 1A-1C illustrate a semiconductor structure in accordance with an embodiment.

第2A~13C圖繪示根據實施例的一種半導體結構的製造方法。 2A-13C illustrate a method of fabricating a semiconductor structure in accordance with an embodiment.

以下將配合所附圖式對於各種不同的實施例進行更詳細的說明。所附圖式只用於描述和解釋目的，而不用於限制目的。為了清楚起見，元件可能並未依照實際比例繪示。此外，可能從圖式中省略一些元件和/或元件符號。可以預期的是，一實施例中的元件和特徵，能夠被有利地納入於另一實施例中，無須進一步的闡述。 Various embodiments will be described in more detail below in conjunction with the drawings. The drawings are for illustrative purposes only and are not intended to be limiting. For the sake of clarity, the components may not be shown in actual scale. In addition, some elements and/or component symbols may be omitted from the drawings. It is contemplated that elements and features of one embodiment can be advantageously included in another embodiment without further elaboration.

根據實施例的一種半導體結構包括一基板和複數個次陣列結構，次陣列結構設置在基板上並藉由複數個溝槽彼此分離。此種半導體結構包括複數個記憶胞構成的一三維陣列。該些記憶胞包括複數個記憶胞群，分別設置在次陣列結構中。此種半導體結構更包括複數個支撐柱和複數個導電柱，設置在溝槽中。每一溝槽中的支撐柱和導電柱在溝槽的一延伸方向上交替配置。此種半導體結構更包括複數個導電線，設置在溝槽中，並位在支撐柱和導電柱上。每一導電線連接位在其下方的導電柱，且沿延伸方向延伸。 A semiconductor structure according to an embodiment includes a substrate and a plurality of sub-array structures disposed on the substrate and separated from each other by a plurality of trenches. Such a semiconductor structure includes a three-dimensional array of a plurality of memory cells. The memory cells include a plurality of memory cell groups, respectively disposed in the sub-array structure. The semiconductor structure further includes a plurality of support columns and a plurality of conductive columns disposed in the trenches. The support columns and the conductive pillars in each of the grooves are alternately arranged in an extending direction of the grooves. The semiconductor structure further includes a plurality of conductive lines disposed in the trenches and positioned on the support pillars and the conductive pillars. Each of the conductive lines is connected to a conductive post located below it and extends in an extending direction.

請參照第1A~1C圖，其示出這樣的一半導體結構。在所附圖式中，為了便於理解，半導體結構被繪示成3-D垂直通道反及(NAND)記憶結構。 Please refer to FIGS. 1A-1C for a semiconductor structure. In the drawings, for ease of understanding, the semiconductor structure is illustrated as a 3-D vertical channel inverse (NAND) memory structure.

所述半導體結構包括一基板102。基板102可包括形成在其中和/或其上的結構和元件等等。例如，基板102可包括設置在其上的一埋層104。 The semiconductor structure includes a substrate 102. The substrate 102 can include Structures and elements and the like formed therein and/or thereon. For example, substrate 102 can include a buried layer 104 disposed thereon.

所述半導體結構包括複數個次陣列結構140，設置在基板102上。該些次陣列結構140藉由複數個溝槽150彼此分離。根據一些實施例，每一次陣列結構140可包括一堆疊108和穿過堆疊108的一或多個主動結構。雖然第1A~1C圖繪示每一記憶胞群包括二列的主動結構120的例子，實施例並不受限於此。堆疊108包括交替堆疊的複數個導電層110和複數個絕緣層116。在一些實施例中，每一導電層110包括二個高介電常數介電層112和設置在其間的一導電芯層114，如第1B圖所示。在這樣的例子中，導電芯層114可由一金屬材料形成。二個高介電常數介電層112可彼此連接。在一些其他的實施例中，每一導電層110可由單一層構成。在這樣的例子中，導電芯層114可由摻雜多晶矽形成。在一些實施例中，堆疊108更包括一硬遮罩層118，設置在導電層110和絕緣層116上。根據一些實施例，每一主動結構120可形成為柱狀型態。在這樣的例子中，每一主動結構120可包括一通道層122和設置在通道層122和堆疊108之間的一記憶層124。在一些實施例中，每一主動結構120更包括一絕緣材料126，填充到由通道層122所形成的空間。在一些實施例中，每一次陣列結構140更包括一或多個導電接墊128，分別耦接到一或多個主動結構120。在一些實施例中，每一次陣列結構140更包括一層間介電層132，設置在堆疊108上。根據一些實施例，次陣列結構140可具有高深寬比。 The semiconductor structure includes a plurality of sub-array structures 140 disposed on the substrate 102. The sub-array structures 140 are separated from one another by a plurality of trenches 150. According to some embodiments, each array structure 140 may include a stack 108 and one or more active structures that pass through the stack 108. Although FIGS. 1A-1C illustrate an example in which each memory cell group includes two columns of active structures 120, the embodiment is not limited thereto. The stack 108 includes a plurality of conductive layers 110 and a plurality of insulating layers 116 that are alternately stacked. In some embodiments, each conductive layer 110 includes two high-k dielectric layers 112 and a conductive core layer 114 disposed therebetween, as shown in FIG. 1B. In such an example, the conductive core layer 114 can be formed from a metallic material. The two high-k dielectric layers 112 may be connected to each other. In some other embodiments, each conductive layer 110 can be comprised of a single layer. In such an example, the conductive core layer 114 can be formed of doped polysilicon. In some embodiments, the stack 108 further includes a hard mask layer 118 disposed on the conductive layer 110 and the insulating layer 116. According to some embodiments, each active structure 120 may be formed in a columnar configuration. In such an example, each active structure 120 can include a channel layer 122 and a memory layer 124 disposed between the channel layer 122 and the stack 108. In some embodiments, each active structure 120 further includes an insulating material 126 that fills the space formed by the channel layer 122. In some embodiments, each array structure 140 further includes one or more conductive pads 128 coupled to one or more active structures 120, respectively. In some embodiments, each array structure 140 further includes an interlevel dielectric layer 132 disposed on the stack 108. Sub-array according to some embodiments Structure 140 can have a high aspect ratio.

所述半導體結構包括複數個支撐柱152和複數個導電柱153，設置在溝槽150中。每一溝槽150中的支撐柱152和導電柱153在溝槽150的一延伸方向(圖式中的X方向)上交替配置。根據一些實施例，支撐柱152可由一絕緣材料形成，例如由一氧化物材料形成。根據一些實施例，每一導電柱153可包括一導電中央部分154和環繞導電中央部分154的一絕緣襯層156。所述半導體結構更包括複數個導電線158，設置在溝槽150中，並位在支撐柱152和導電柱153上。每一導電線158連接位在其下方的導電柱153。在一些實施例中，導電線158和導電柱153是由相同的材料形成。 The semiconductor structure includes a plurality of support pillars 152 and a plurality of conductive pillars 153 disposed in the trenches 150. The support pillars 152 and the conductive pillars 153 in each of the trenches 150 are alternately arranged in an extending direction of the trench 150 (X direction in the drawing). According to some embodiments, the support post 152 may be formed from an insulative material, such as an oxide material. According to some embodiments, each of the conductive posts 153 can include a conductive central portion 154 and an insulating liner 156 surrounding the conductive central portion 154. The semiconductor structure further includes a plurality of conductive lines 158 disposed in the trenches 150 and positioned on the support pillars 152 and the conductive pillars 153. Each conductive line 158 is connected to a conductive post 153 located below it. In some embodiments, the conductive lines 158 and the conductive posts 153 are formed from the same material.

所述半導體結構包括複數個記憶胞130構成的一三維陣列。該些記憶胞130包括複數個記憶胞群(圖式中未加以指示)，分別設置在次陣列結構140中。更具體地說，設置在次陣列結構140的每一者中的記憶胞群的記憶胞130，能夠藉由堆疊108的導電層110和所述一或多個主動結構120之間的交點來定義。根據一些實施例，次陣列結構140的堆疊108的導電層110可配置成用於字元線，次陣列結構140的導電接墊128可配置成用於位元線，導電柱153和導電線158可配置成用於共同源極線。 The semiconductor structure includes a three-dimensional array of a plurality of memory cells 130. The memory cells 130 include a plurality of memory cell groups (not indicated in the drawings), which are respectively disposed in the sub-array structure 140. More specifically, the memory cells 130 of the memory cell population disposed in each of the sub-array structures 140 can be defined by the intersection between the conductive layer 110 of the stack 108 and the one or more active structures 120. . According to some embodiments, the conductive layer 110 of the stack 108 of the sub-array structure 140 may be configured for word lines, and the conductive pads 128 of the sub-array structure 140 may be configured for bit lines, conductive pillars 153 and conductive lines 158 Can be configured for common source lines.

現在說明根據實施例的一種半導體結構的製造方法。其包括下列步驟。首先，提供一起始結構。起始結構包括一基板和形成在基板上的一初步陣列結構。初步陣列結構包括一堆疊和穿過堆疊的複數個主動結構。每一主動結構包括一通道層和形成在通道層和堆疊之間的一記憶層。在配置成用於將初步陣列結構分離成複數個次陣列結構之複數個溝槽的複數個預定溝槽位置形成複數個支撐柱。每一預定溝槽位置中的支撐柱彼此分離。接著，在預定溝槽位置形成複數個導電柱，使得每一預定溝槽位置中的導電柱和支撐柱在預定溝槽位置的一延伸方向上交替配置。在支撐柱和導電柱上形成複數個導電線。 A method of fabricating a semiconductor structure in accordance with an embodiment will now be described. It includes the following steps. First, a starting structure is provided. The starting structure includes a substrate and a preliminary array structure formed on the substrate. The preliminary array structure includes a pile Stack and pass through a plurality of active structures stacked. Each active structure includes a channel layer and a memory layer formed between the channel layer and the stack. A plurality of support pillars are formed at a plurality of predetermined trench locations configured to separate the preliminary array structure into a plurality of trenches of the plurality of sub-array structures. The support columns in each predetermined groove position are separated from each other. Next, a plurality of conductive pillars are formed at predetermined groove positions such that the conductive pillars and the support pillars in each predetermined trench position are alternately arranged in an extending direction of the predetermined trench position. A plurality of conductive lines are formed on the support post and the conductive post.

請參照第2A~13C圖，其示出這樣的一方法。為了便於理解，該方法被繪示成採用使用犧牲層的製程來形成如第1A~1C圖所示的半導體結構，其中所述犧牲層將在後續步驟中被導電層取代。以「B」和「C」所指示的圖式分別為取自於由「A」所指示的圖式中的B-B線和C-C線的剖面圖。 Please refer to Figures 2A-13C for a method such as this. For ease of understanding, the method is illustrated as forming a semiconductor structure as shown in FIGS. 1A-1C using a process using a sacrificial layer, wherein the sacrificial layer will be replaced by a conductive layer in a subsequent step. The drawings indicated by "B" and "C" are cross-sectional views taken from the B-B line and the C-C line in the pattern indicated by "A".

如第2A~2B圖所示，提供一基板102基板102可包括形成在其中和/或其上的結構和元件等等。例如，基板102可包括設置在其上的一埋層104，如第2B圖所示。埋層104可由氧化物形成。在基板102上形成一堆疊208。堆疊208包括交替堆疊的複數個犧牲層210和複數個絕緣層216。犧牲層210可由氮化矽(SiN)形成。絕緣層216可由氧化物形成。在一些實施例中，如第2A~2B圖所示，堆疊208更包括一硬遮罩層218，形成在犧牲層210和絕緣層216上，其用於補償膜應力和避免堆疊倒塌或彎曲。 As shown in Figures 2A-2B, providing a substrate 102 substrate 102 can include structures and elements and the like formed therein and/or thereon. For example, substrate 102 can include a buried layer 104 disposed thereon as shown in FIG. 2B. The buried layer 104 may be formed of an oxide. A stack 208 is formed on the substrate 102. Stack 208 includes a plurality of sacrificial layers 210 and a plurality of insulating layers 216 that are alternately stacked. The sacrificial layer 210 may be formed of tantalum nitride (SiN). The insulating layer 216 may be formed of an oxide. In some embodiments, as shown in FIGS. 2A-2B, the stack 208 further includes a hard mask layer 218 formed on the sacrificial layer 210 and the insulating layer 216 for compensating for film stress and avoiding stack collapse or bending.

如第3A~3B圖所示，形成穿過堆疊208的複數個主動結構120。更具體地說，在一些實施例中，可形成穿過堆疊208的複數個孔洞。可對應地在孔洞的側壁上形成複數個記憶層124。記憶層可具有多層結構，例如ONO(氧化物/氮化物/氧化物)或ONONO(氧化物/氮化物/氧化物/氮化物/氧化物)等等。可對應地在記憶層124上形成複數個通道層122。通道層122也可形成在孔洞的底部上。通道層122可由多晶矽形成。可將一絕緣材料126填充到孔洞的剩餘空間中。在一些實施例中，在孔洞中的絕緣材料126上形成複數個導電接墊128。它們分別耦接到對應的主動結構120，特別是主動結構120的通道層122。接著，可在堆疊208和主動結構120上形成一層間介電層232。 As shown in Figures 3A-3B, a plurality of passes through the stack 208 are formed Active structure 120. More specifically, in some embodiments, a plurality of holes can be formed through the stack 208. A plurality of memory layers 124 can be formed correspondingly on the sidewalls of the holes. The memory layer may have a multilayer structure such as ONO (Oxide/Nitride/Oxide) or ONONO (Oxide/Nitride/Oxide/Nitride/Oxide) and the like. A plurality of channel layers 122 may be formed on the memory layer 124 correspondingly. A channel layer 122 can also be formed on the bottom of the hole. Channel layer 122 may be formed of polysilicon. An insulating material 126 can be filled into the remaining space of the hole. In some embodiments, a plurality of conductive pads 128 are formed on the insulating material 126 in the holes. They are each coupled to a corresponding active structure 120, particularly a channel layer 122 of the active structure 120. An interlevel dielectric layer 232 can then be formed over the stack 208 and the active structure 120.

如此一來，便形成所述「起始結構」。該起始結構包括一基板102和形成在基板102上的一初步陣列結構，其中初步陣列結構將在後續步驟中分離的包括複數個次陣列結構140。初步陣列結構包括一堆疊208和穿過堆疊208的複數個主動結構120。每一主動結構120包括一通道層122和形成在通道層122和堆疊208之間的一記憶層124。在一些實施例中，初步陣列結構更包括複數個導電接墊128，分別耦接到主動結構120。一些實施例中，初步陣列結構更包括一層間介電層232，形成在堆疊208上。 In this way, the "starting structure" is formed. The starting structure includes a substrate 102 and a preliminary array structure formed on the substrate 102, wherein the preliminary array structure includes a plurality of sub-array structures 140 that are separated in a subsequent step. The preliminary array structure includes a stack 208 and a plurality of active structures 120 that pass through the stack 208. Each active structure 120 includes a channel layer 122 and a memory layer 124 formed between the channel layer 122 and the stack 208. In some embodiments, the preliminary array structure further includes a plurality of conductive pads 128 coupled to the active structures 120, respectively. In some embodiments, the preliminary array structure further includes an interlevel dielectric layer 232 formed on the stack 208.

如第4A~4B圖所示，在配置成用於將初步陣列結構分離成次陣列結構140之複數個溝槽150的複數個預定溝槽位置250形成複數個第一開口272。如第5A~5B圖所示，將一第一絕緣材料填充到第一開口272中。如果需要的話，可進行一平坦化製程，例如一化學機械平坦化(chemical-mechanical planarization,CMP)製程。第一絕緣材料是和用在犧牲層210之材料不同的材料。例如，第一絕緣材料可以是一氧化物材料，例如是由電漿輔助製程形成的一氧化物材料。如此一來，複數個支撐柱252便形成在預定溝槽位置250，其中每一預定溝槽位置250中的支撐柱252彼此分離。 As shown in FIGS. 4A-4B, a plurality of first openings 272 are formed at a plurality of predetermined trench locations 250 configured to separate the preliminary array structure into a plurality of trenches 150 of the sub-array structure 140. As shown in Figures 5A-5B, An insulating material is filled into the first opening 272. If desired, a planarization process, such as a chemical-mechanical planarization (CMP) process, can be performed. The first insulating material is a material different from that used for the sacrificial layer 210. For example, the first insulating material may be an oxide material, such as an oxide material formed by a plasma assisted process. As such, a plurality of support posts 252 are formed at predetermined trench locations 250 wherein the support posts 252 in each predetermined trench location 250 are separated from each other.

在形成支撐柱252之後，如第6A~6C圖所示，在第5A~5B圖的結構上形成一光阻層274。光阻層274包括複數個孔洞276，對應到用於在預定溝槽位置250的剩餘部分形成複數個導電柱253(第12A~12C圖)的複數個第二開口278的形成。在一些實施例中，孔洞276暴露出部分的支撐柱252，以確保初步陣列結構在預定溝槽位置250中的部分將被完全移除。接著，如第7A~7C圖所示，使用光阻層274，在預定溝槽位置250於支撐柱252之間形成所述複數個第二開口278，例如是藉由一蝕刻製程。 After the support pillars 252 are formed, as shown in FIGS. 6A to 6C, a photoresist layer 274 is formed on the structures of FIGS. 5A to 5B. The photoresist layer 274 includes a plurality of holes 276 corresponding to the formation of a plurality of second openings 278 for forming a plurality of conductive pillars 253 (Figs. 12A-12C) for the remainder of the predetermined trench locations 250. In some embodiments, the holes 276 expose portions of the support posts 252 to ensure that portions of the preliminary array structure in the predetermined groove locations 250 will be completely removed. Next, as shown in FIGS. 7A-7C, the plurality of second openings 278 are formed between the support pillars 252 at predetermined trench locations 250 using a photoresist layer 274, such as by an etch process.

在為了形成導電柱253而將一第一導電材料填充到第二開口278中之前，可使用第二開口278進行一以複數個導電層110取代所述犧牲層210的製程。如第8A~8C圖所示，經由第二開口278第二開口移除犧牲層210，例如是藉由使用熱磷酸(HF)的一蝕刻製程。如第9A~9C圖所示，在絕緣層116的上側和下側形成複數個高介電常數介電層212。例如，可在第8A~8C 圖的結構上以共形的方式形成一高介電常數介電材料，如第9A~9C圖所示。該高介電常數介電材料可為氧化鋁(Al₂O₃)等等。接著，如第10A~10C圖所示，將一第二導電材料填充到移除犧牲層210所產生的空間的剩餘部分中。第二導電材料可以是鎢(W)。如此一來，便形成如第1A~1C圖所示的堆疊108。此外，並移除該高介電常數介電材料不需要的部分。 A second opening 278 may be used to replace the sacrificial layer 210 with a plurality of conductive layers 110 prior to filling a first conductive material into the second opening 278 in order to form the conductive pillars 253. As shown in FIGS. 8A-8C, the sacrificial layer 210 is removed through the second opening of the second opening 278, for example, by an etching process using hot phosphoric acid (HF). As shown in FIGS. 9A to 9C, a plurality of high-k dielectric layers 212 are formed on the upper and lower sides of the insulating layer 116. For example, a high-k dielectric material can be formed in a conformal manner on the structures of Figures 8A-8C, as shown in Figures 9A-9C. The high dielectric constant dielectric material may be aluminum oxide (Al ₂ O ₃ ) or the like. Next, as shown in FIGS. 10A-10C, a second conductive material is filled into the remaining portion of the space created by the removal of the sacrificial layer 210. The second conductive material may be tungsten (W). As a result, the stack 108 as shown in Figs. 1A to 1C is formed. In addition, and removing unwanted portions of the high-k dielectric material.

如第11A~11C圖所示，可在第二開口278中使用一第二絕緣材料對應地形成複數個絕緣襯層256。第二絕緣材料可以和用於形成支撐柱252的第一絕緣材料相同或不同。例如，第二絕緣材料可以是一氧化物材料。如第12A~12C圖所示，將一第一導電材料填充到第二開口278中。如此一來，便形成導電柱253的導電中央部分254，其藉由絕緣襯層256和導電層110隔絕。第一導電材料可以是鎢(W)。從而，分別包括一絕緣襯層256和一導電中央部分254的導電柱253形成在預定溝槽位置250，使得每一預定溝槽位置250中的導電柱253和支撐柱252在預定溝槽位置250的一延伸方向(圖式中的X方向)上交替配置。在一些實施例中，第一導電材料也用於在後續步驟形成複數個導電線158。 As shown in FIGS. 11A-11C, a plurality of insulating liners 256 may be correspondingly formed in the second opening 278 using a second insulating material. The second insulating material may be the same as or different from the first insulating material used to form the support post 252. For example, the second insulating material may be an oxide material. As shown in FIGS. 12A-12C, a first conductive material is filled into the second opening 278. As such, a conductive central portion 254 of the conductive post 253 is formed which is isolated by the insulating liner 256 and the conductive layer 110. The first conductive material may be tungsten (W). Thus, conductive pillars 253, each including an insulating liner 256 and a conductive central portion 254, are formed at predetermined trench locations 250 such that conductive pillars 253 and support pillars 252 in each predetermined trench location 250 are at predetermined trench locations 250. The one extension direction (the X direction in the drawing) is alternately arranged. In some embodiments, the first conductive material is also used to form a plurality of conductive lines 158 in subsequent steps.

如第13A~13C圖所示，在支撐柱(252)和導電柱(253)上形成複數個導電線158，例如是使用鎢(W)。在一些實施例中，在支撐柱252的頂部部分形成複數個導電連接層。因此，這些導電連接層和藉此連接的導電柱253的頂部部分構成導電線 158。支撐柱252和導電柱253的剩餘部分即是如第1A~1C圖所示的支撐柱152和導電柱153。在一些其他的實施例中，能夠直接在支撐柱252和導電柱253上沉積複數個導電線158。 As shown in Figs. 13A to 13C, a plurality of conductive lines 158 are formed on the support post (252) and the conductive post (253), for example, tungsten (W) is used. In some embodiments, a plurality of electrically conductive tie layers are formed on the top portion of the support post 252. Therefore, the conductive connection layer and the top portion of the conductive pillar 253 connected thereto constitute a conductive line 158. The remaining portions of the support post 252 and the conductive post 253 are the support post 152 and the conductive post 153 as shown in FIGS. 1A-1C. In some other embodiments, a plurality of conductive lines 158 can be deposited directly on support posts 252 and conductive posts 253.

之後，可進行其他典型用於製造半導體結構的製程，像是後段(BEOL)製程。例如，在BEOL製程中，使用導電層110定義字元線，使用導電接墊128定義位元線，使用導電柱153和導電線158定義共同源極線，並藉由字元線和通道層122之間的交點來定義記憶胞130。 Thereafter, other processes typically used to fabricate semiconductor structures, such as the back end (BEOL) process, can be performed. For example, in a BEOL process, a word line is defined using conductive layer 110, a bit line is defined using conductive pads 128, a common source line is defined using conductive posts 153 and conductive lines 158, and by word line and channel layer 122 The intersection between the points defines the memory cell 130.

在上述的方法中，由於形成支撐柱，且並未在製程中直接形成長溝槽，因此能夠提供機械性支撐給具有高深寬比的堆疊，從而能夠避免該些堆疊的傾斜。再者，還能夠避免由堆疊的傾斜所導致之在BEOL製程中形成的接觸件的位置偏差(dislocation)。雖然前述的例子是敘述使用3-D垂直通道NAND記憶結構和採用使用犧牲層的方法，實施例並不受限於此。在這裡敘述的概念，能夠應用到其他其中會形成具有高深寬比之堆疊的半導體結構的製造方法及藉由該些方法所製造出的半導體結構。 In the above method, since the support pillars are formed and the long trenches are not directly formed in the process, it is possible to provide mechanical support to the stack having a high aspect ratio, so that the tilt of the stacks can be avoided. Furthermore, it is also possible to avoid the positional dislocation of the contacts formed in the BEOL process caused by the tilt of the stack. Although the foregoing examples describe the use of a 3-D vertical channel NAND memory structure and a method of using a sacrificial layer, the embodiment is not limited thereto. The concepts described herein can be applied to other fabrication methods in which a stacked semiconductor structure having a high aspect ratio is formed and a semiconductor structure fabricated by the methods.

綜上所述，雖然本發明已以實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。 In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims

一種半導體結構，包括：一基板；複數個次陣列結構，設置在該基板上，並藉由複數個溝槽彼此分離；複數個記憶胞構成的一三維陣列，其中該些記憶胞包括複數個記憶胞群，分別設置在該些次陣列結構中；複數個支撐柱和複數個導電柱，設置在該些溝槽中，其中該些溝槽的每一者中的該些支撐柱和該些導電柱在該些溝槽的一延伸方向上交替配置；以及複數個導電線，設置在該些溝槽中，且沿該延伸方向延伸，並位在該些支撐柱和該些導電柱上，其中該些導電線的每一者連接位在其下方的該些導電柱。 A semiconductor structure comprising: a substrate; a plurality of sub-array structures disposed on the substrate and separated from each other by a plurality of trenches; a three-dimensional array of memory cells, wherein the memory cells comprise a plurality of memories The cell groups are respectively disposed in the sub-array structures; a plurality of support columns and a plurality of conductive columns are disposed in the trenches, wherein the support columns and the conductive layers in each of the trenches The pillars are alternately arranged in an extending direction of the trenches; and a plurality of conductive lines are disposed in the trenches and extend along the extending direction and are located on the support pillars and the conductive pillars, wherein Each of the conductive lines connects the conductive pillars below it.

如申請專利範圍第1項所述之半導體結構，其中該些支撐柱是由一氧化物材料形成。 The semiconductor structure of claim 1, wherein the support columns are formed of an oxide material.

如申請專利範圍第1項所述之半導體結構，其中該些導電柱的每一者包括一導電中央部分和環繞該導電中央部分的一絕緣襯層。 The semiconductor structure of claim 1, wherein each of the conductive pillars comprises a conductive central portion and an insulating liner surrounding the conductive central portion.

如申請專利範圍第1項所述之半導體結構，其中該些次陣列結構的每一者包括：一堆疊，包括交替堆疊的複數個導電層和複數個絕緣層；以及一或多個主動結構，穿過該堆疊，該一或多個主動結構的每一者包括：一通道層；及一記憶層，設置在該通道層和該堆疊之間；其中設置在該些次陣列結構的每一者中的該記憶胞群的該些記憶胞，是藉由該堆疊的該些導電層和該一或多個主動結構之間的交點來定義。 The semiconductor structure of claim 1, wherein each of the sub-array structures comprises: a stack comprising a plurality of electrically conductive layers and a plurality of insulating layers alternately stacked; One or more active structures passing through the stack, each of the one or more active structures including: a channel layer; and a memory layer disposed between the channel layer and the stack; wherein the The memory cells of the memory cell group in each of the sub-array structures are defined by intersections between the conductive layers of the stack and the one or more active structures.

如申請專利範圍第4項所述之半導體結構，其中該些導電層的每一者包括二個高介電常數介電層和設置在其間的一導電芯層。 The semiconductor structure of claim 4, wherein each of the conductive layers comprises two high-k dielectric layers and a conductive core layer disposed therebetween.

如申請專利範圍第4項所述之半導體結構，其中該些次陣列結構的每一者更包括：一或多個導電接墊，分別耦接到該一或多個主動結構；其中該些次陣列結構的該些堆疊的該些導電層是配置成用於字元線，該些次陣列結構的該些導電接墊是配置成用於位元線，該些導電柱和該些導電線是配置成用於共同源極線。 The semiconductor structure of claim 4, wherein each of the sub-array structures further comprises: one or more conductive pads respectively coupled to the one or more active structures; wherein the plurality of times The conductive layers of the stacked array structures are configured for word lines, and the conductive pads of the sub-array structures are configured for bit lines, and the conductive columns and the conductive lines are Configured for common source lines.

一種半導體結構的製造方法，包括：提供一起始結構，其中該起始結構包括一基板和形成在該基板上的一初步陣列結構，該初步陣列結構包括一堆疊和穿過該堆疊的複數個主動結構，該些主動結構的每一者包括一通道層和形成在該通道層和該堆疊之間的一記憶層；在配置成用於將該初步陣列結構分離成複數個次陣列結構之複數個溝槽的複數個預定溝槽位置形成複數個支撐柱，其中該些預定溝槽位置的每一者中的該些支撐柱彼此分離；在該些預定溝槽位置形成複數個導電柱，使得該些預定溝槽位置的每一者中的該些導電柱和該些支撐柱在該些預定溝槽位置的一延伸方向上交替配置；以及在該些支撐柱和該些導電柱上形成複數個導電線，該些導電線沿該延伸方向延伸。 A method of fabricating a semiconductor structure, comprising: providing a starting structure, wherein the starting structure comprises a substrate and a preliminary array structure formed on the substrate, the preliminary array structure comprising a stack and a plurality of actives passing through the stack a structure, each of the active structures including a channel layer and a memory layer formed between the channel layer and the stack; Forming a plurality of support pillars at a plurality of predetermined trench locations configured to separate the preliminary array structure into a plurality of trenches of the plurality of sub-array structures, wherein each of the predetermined trench locations Separating the support columns from each other; forming a plurality of conductive pillars at the predetermined groove locations such that the conductive pillars in each of the predetermined trench locations and an extension of the support pillars at the predetermined trench locations Alternatingly arranged in the direction; and forming a plurality of conductive lines on the support columns and the conductive posts, the conductive lines extending along the extending direction.

如申請專利範圍第7項所述之製造方法，其中形成該些支撐柱的步驟包括：在該些預定溝槽位置形成複數個第一開口；以及將一第一絕緣材料填充到該些第一開口中；且其中形成該些導電柱的步驟包括：在形成該些支撐柱之後，在該些預定溝槽位置於該些支撐柱之間形成複數個第二開口；在該些第二開口中使用一第二絕緣材料對應地形成複數個絕緣襯層；以及將一第一導電材料填充到該些第二開口中。 The manufacturing method of claim 7, wherein the forming the support columns comprises: forming a plurality of first openings at the predetermined groove positions; and filling a first insulating material to the first The step of forming the conductive pillars includes: forming a plurality of second openings between the support pillars at the predetermined groove positions after forming the support pillars; and in the second openings A plurality of insulating liners are correspondingly formed using a second insulating material; and a first conductive material is filled into the second openings.

如申請專利範圍第8項所述之製造方法，其中該堆疊包括交替堆疊的複數個犧牲層和複數個絕緣層，該製造方法更包括：以複數個導電層取代該些犧牲層，包括：經由該些第二開口移除該些犧牲層；在該些絕緣層的上側和下側形成複數個高介電常數介電層；以及將一第二導電材料填充到移除該些犧牲層所產生的空間的剩餘部分中。 The manufacturing method of claim 8, wherein the stacking comprises a plurality of sacrificial layers and a plurality of insulating layers stacked alternately, the manufacturing method further comprising: replacing the sacrificial layers with a plurality of conductive layers, including: Removing the sacrificial layers via the second openings; forming a plurality of high-k dielectric layers on the upper and lower sides of the insulating layers; and filling a second conductive material to remove the sacrificial layers The remainder of the resulting space.

如申請專利範圍第9項所述之製造方法，其中該初步陣列結構更包括：複數個導電接墊，分別耦接到該些主動結構；其中該些導電層是配置成用於字元線，該些導電接墊是配置成用於位元線，該些導電柱和該些導電線是配置成用於共同源極線。 The manufacturing method of claim 9, wherein the preliminary array structure further comprises: a plurality of conductive pads respectively coupled to the active structures; wherein the conductive layers are configured for word lines, The conductive pads are configured for bit lines, and the conductive posts and the conductive lines are configured for a common source line.