TW201515142A - 晶圓承載結構 - Google Patents
晶圓承載結構 Download PDFInfo
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- TW201515142A TW201515142A TW102146178A TW102146178A TW201515142A TW 201515142 A TW201515142 A TW 201515142A TW 102146178 A TW102146178 A TW 102146178A TW 102146178 A TW102146178 A TW 102146178A TW 201515142 A TW201515142 A TW 201515142A
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- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 239000011248 coating agent Substances 0.000 claims abstract description 12
- 238000000576 coating method Methods 0.000 claims abstract description 12
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 claims description 30
- 229910003468 tantalcarbide Inorganic materials 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 12
- 238000002844 melting Methods 0.000 claims description 7
- 230000008018 melting Effects 0.000 claims description 7
- 229910002601 GaN Inorganic materials 0.000 claims description 6
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 5
- 229910052738 indium Inorganic materials 0.000 claims description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 3
- 239000011810 insulating material Substances 0.000 claims description 3
- 239000007788 liquid Substances 0.000 claims description 3
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 claims description 2
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims description 2
- 229910002704 AlGaN Inorganic materials 0.000 claims 1
- 239000000853 adhesive Substances 0.000 abstract 2
- 230000001070 adhesive effect Effects 0.000 abstract 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 6
- 229910010271 silicon carbide Inorganic materials 0.000 description 6
- 239000013078 crystal Substances 0.000 description 4
- 239000000084 colloidal system Substances 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 230000032798 delamination Effects 0.000 description 3
- 238000009616 inductively coupled plasma Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- -1 AlGaN Chemical compound 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000012876 carrier material Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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- H01L21/30621—Vapour phase etching
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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Abstract
一種用於晶圓背面製程的晶圓承載結構,其中該晶圓包括一碳化矽基板以及一半導體元件層,前述碳化矽基板具有一背面及一正面,而前述半導體元件層係具有一第一表面及一第二表面,且該半導體元件層之第一表面係與前述碳化矽基板之正面接觸;前述晶圓承載結構包括一晶圓載具以及一膠質塗層,前述晶圓載具係以n型導電碳化矽材料製成,其熱膨脹係數係與前述碳化矽基板之熱膨脹係數匹配;前述晶圓載具係裝置於前述半導體元件層之第二表面,而前述膠質塗層係塗佈於該晶圓載具與該半導體元件層之第二表面之間。
Description
本發明係有關一種晶圓承載結構,尤指一種用於具有碳化矽基板之晶圓的背面製程之晶圓承載結構。
碳化矽(SiC)是一種化學穩定性佳且具有高硬度的化合物半導體材料,其優越的導電及導熱性能使其成為製作高頻及高功率元件的理想材料。在碳化矽基板上製作的半導體元件可在軍事及太空等需要高熱容性及高輻射耐受力的高溫環境中運作,如應用在軍事雷達、人造衛星、太空望遠鏡等設備中。
在晶圓背面製程中,係先將晶圓以背面朝上的方式放置於一晶圓載具上,再將其送入製程設備中。在整個晶圓背面製程中,晶圓應完好附著於晶圓載具上。然而,碳化矽之熱傳導特性與其他三五族化合物半導體材料不同,而且蝕刻高硬度的碳化矽基板時所造成的環境溫度亦高於其他如砷化鎵等常見的三五族化合物半導體,因此,本發明提供一種晶圓承載結構,以改善具有碳化矽基板的晶圓之背面製程。
本發明之主要目的在於提供一種用於晶圓背面製程的晶圓承載結構,能改善晶背製程中晶圓曲翹的問題以及預防晶圓脫層問題,並能避免晶背製程中膠質熔化以及回流(reflow)的問題。
為達上述目的,本發明提供一種用於晶圓背面製程的晶圓承載結構,其中該晶圓包括一碳化矽基板以及一半導體元件層,前述碳化矽基板係具有一背面及一正面,而前述半導體元件層係具有一第一表面及一第二表面,且該半導體元件層之第一表面係與前述碳化矽基板之正面接觸;前述晶圓承載結構包括一晶圓載具以及一膠質塗層,前述晶圓載具係以n型導電碳化矽材料製成,其熱膨脹係數係與前述碳化矽基板之熱膨脹係數匹配;前述晶圓載具係裝置於前述半導體元件層之第二表面,而前述膠質塗層係塗佈於該晶圓載具與該半導體元件層之第二表面之間。
於實施時,前述碳化矽基板為半絕緣性材料。
於實施時,前述碳化矽基板係被研磨至厚度為介於25至150微米之間。
於實施時,前述半導體元件層包括至少一磊晶層,該至少一磊晶層中的每一層係以係以氮化鎵(GaN)、氮化鋁鎵(AlGaN)、氮化鋁(AlN)或氮化銦鎵(InGaN)製成。
於實施時,前述晶圓載具之熱導率為大於250W/m/℃。
於實施時,前述晶圓載具之線性熱膨脹係數為大於2×10-6m/°C。
於實施時,前述晶圓載具之厚度為介於100至1000微米之間,且其曲翹度為小於50微米。
於實施時,前述膠質塗層之軟化及熔化溫度為大於100℃。
於實施時,前述膠質塗層係使用液態蠟。
為對於本發明之特點與作用能有更深入之瞭解,茲藉實施例配合圖式詳述於後。
100‧‧‧晶圓
110‧‧‧碳化矽基板
111‧‧‧碳化矽基板背面
112‧‧‧碳化矽基板正面
120‧‧‧半導體元件層
121‧‧‧第一表面
122‧‧‧第二表面
123,123’‧‧‧磊晶層
200‧‧‧晶圓承載結構
210‧‧‧晶圓載具
211‧‧‧曲翹範圍
220‧‧‧膠質塗層
第1圖係為本發明所提供的一種用於晶圓背面製程之晶圓承載結構之一實施例之剖面結構示意圖。
第2圖係為一種晶圓載具曲翹度測量之示意圖。
第1圖係為本發明所提供的一種用於晶圓背面製程之晶圓承載結構之一實施例之示意圖,其中晶圓100包括一碳化矽基板110以及一半導體元件層120,碳化矽基板110係具有一背面111及一正面112,而半導體元件層120係具有一第一表面121及一第二表面122,且半導體元件層120之第一表面121係與前述碳化矽基板110之正面112接觸;晶圓承載結構200包括一晶圓載具210以及一膠質塗層220,其中晶圓載具210係裝置於半導體元件層120之第二表面122,而膠質塗層220係塗佈於晶圓載具210與半導體元件層120之第二表面122之間。
於實施時,碳化矽基板110係為半絕緣性材料。為節省製程時間,在進行晶圓背面製程之前,會先將碳化矽基板100研磨處理。碳化矽基板100之較佳厚度為介於25至150微米之間。半導體元件層120可包括一或多層磊晶層(123,123’),其每一層係以係以氮化鎵(GaN)、氮化鋁鎵(AlGaN)、氮化鋁(AlN)或氮化銦鎵(InGaN)製成。
本發明所提供的晶圓載具之較佳厚度為介於100至1000微米之間,且其曲翹範圍為小於50微米。曲翹範圍211係以一接觸式厚度計(contact thickness meter)測量,如第2圖所示。晶圓載具材料的選擇對整個晶圓背面製程非常重要,晶圓載具的熱膨脹係數應與碳化矽晶圓之熱膨脹係數接近,以避免背面製程中產生晶圓曲翹。本發明所提供的晶圓載具其較佳線性熱膨脹係數為大於2×10-6m/℃。此外,具有較佳熱導率的晶圓載具有
助於降低電漿蝕刻製程中的製程溫度。明所提供的晶圓載具之熱導率較佳為大於250W/m/℃。同時,對用於感應耦合電漿離子蝕刻機台(inductively coupled plasma reactive ion etch tool)中的靜電夾具(electrostatic clamp)而言,具有導電性的晶圓載具係為較佳選擇。n型摻雜碳化矽材料(n-type SiC)為一種導電性碳化矽材料,其具有良好的熱導率且其熱膨脹係數與碳化矽材料接近,因此,根據本發明之實施例,n型導電碳化矽材料為晶圓載具的一種較佳材料選擇。
膠質塗層材料的選擇是晶圓背面製程中另一個重要的課題。晶圓與晶圓載具間黏著性不佳可能會使晶圓在後續製程中從晶圓載具上脫落,而膠質塗層脫蠟可能會在晶圓薄化或其他製程中引起晶圓脫層。再者,膠質在例如感應耦合電漿離子蝕刻及濺鍍等高溫製程中可能會回流。為避免膠質脫蠟及回流,膠質塗層所使用的膠質應具有較高熔化溫度。膠質塗層之較佳軟化及熔化溫度為大於100℃。此外,膠質塗層應具有較高抗化學腐蝕性,同時又要能容易移除,因此本發明之一較佳實施例中,膠質塗層係使用液態蠟。
本發明具有以下優點:
1.本發明所提供的晶圓承載結構具有良好的熱導率,且其熱膨脹係數與碳化矽材料接近,因此,對具有碳化矽基板的晶圓而言,可降低在蝕刻製程中因高溫所造成之晶圓曲翹的發生機率。
2.本發明所提供的晶圓承載結構具有導電性,因此可用於使用靜電夾具的感應耦合電漿離子蝕刻機台中。
3.本發明所提供的晶圓承載結構,其膠質塗層使用的膠質具有高軟化及熔化溫度,因此能避免膠質脫蠟以及在濺鍍過程中膠質的回流。
綜上所述,本發明提供之晶圓承載結構確實可達到預期之目的,能改善晶背製程中晶圓曲翹的問題以及預防晶圓脫層問題,並能避免晶背製程中膠質熔化以及回流的問題。其確具產業利用之價值,爰依法提出發明專利申請。
又上述說明與圖示僅是用以說明本發明之實施例,凡熟於此業技藝之人士,仍可做等效的局部變化與修飾,其並未脫離本發明之技術與精神。
100‧‧‧晶圓
110‧‧‧碳化矽基板
111‧‧‧碳化矽基板背面
112‧‧‧碳化矽基板正面
120‧‧‧半導體元件層
121‧‧‧第一表面
122‧‧‧第二表面
123,123’‧‧‧磊晶層
200‧‧‧晶圓承載結構
210‧‧‧晶圓載具
220‧‧‧膠質塗層
Claims (9)
- 一種用於晶圓背面製程之晶圓承載結構,其中該晶圓包括一碳化矽基板,係具有一背面及一正面,以及一半導體元件層,係具有一第一表面及一第二表面,該半導體元件層之第一表面係與該碳化矽基板之正面接觸,該晶圓承載結構包括:一晶圓載具,係以n型導電碳化矽材料製成,裝置於該半導體元件層之第二表面,該晶圓載具之熱膨脹係數係與該碳化矽基板之熱膨脹係數匹配;一膠質塗層,係塗佈於該晶圓載具與該半導體元件層之第二表面之間。
- 如申請專利範圍第1項所述之晶圓承載結構,其中該碳化矽基板為半絕緣性材料。
- 如申請專利範圍第1項所述之晶圓承載結構,其中該碳化矽基板係被研磨至厚度為介於25至150微米之間。
- 如申請專利範圍第1項所述之晶圓承載結構,其中該半導體元件層包括至少一磊晶層,該至少一磊晶層中的每一層係以係以氮化鎵(GaN)、氮化鋁鎵(AlGaN)、氮化鋁(AlN)或氮化銦鎵(InGaN)製成。
- 如申請專利範圍第1項所述之晶圓承載結構,其中該晶圓載具之熱導率為大於250W/m/℃。
- 如申請專利範圍第1項所述之晶圓承載結構,其中該晶圓載具之線性熱膨脹係數為大於2×10-6m/℃。
- 如申請專利範圍第1項所述之晶圓承載結構,其中該晶圓載具之厚度為介於100至1000微米之間,且其曲翹度為小於50微米。
- 如申請專利範圍第1項所述之晶圓承載結構,其中該膠質塗層之軟化及熔化溫度為大於100℃。
- 如申請專利範圍第1項所述之晶圓承載結構,其中該該膠質塗層係使用液態蠟。
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US14/047,863 US20150099358A1 (en) | 2013-10-07 | 2013-10-07 | Method for forming through wafer vias in semiconductor devices |
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TW102146173A TW201515084A (zh) | 2013-10-07 | 2013-12-13 | 在半導體元件中形成晶圓貫孔之製程方法 |
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GB201620680D0 (en) * | 2016-12-05 | 2017-01-18 | Spts Technologies Ltd | Method of smoothing a surface |
US11437301B2 (en) | 2020-10-15 | 2022-09-06 | Nxp Usa, Inc. | Device with an etch stop layer and method therefor |
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- 2013-10-07 US US14/047,863 patent/US20150099358A1/en not_active Abandoned
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TW201515084A (zh) | 2015-04-16 |
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