TW201505150A - Electrostatic discharge protection device and manufacturing method thereof - Google Patents
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本發明係有關一種靜電防護元件及其製造方法,特別是指一種降低觸發電壓之靜電防護元件及其製造方法。 The present invention relates to an electrostatic protection element and a method of manufacturing the same, and more particularly to an electrostatic protection element for reducing a trigger voltage and a method of manufacturing the same.
第1A圖顯示一種典型的靜電防護元件100與被保護電路/元件1的電路示意圖。如第1A圖所示,靜電防護元件100與被保護電路/元件1並聯於接觸墊2與接地電位或電源供應電位之間。當靜電防護元件100與被保護電路/元件1耦接的其中一端接觸到靜電(如第1A圖中閃電符號所示意),靜電防護元件100被觸發,而將靜電中的高電壓與高電流釋放,以避免靜電破壞被保護電路/元件1。 Figure 1A shows a circuit schematic of a typical ESD protection component 100 and protected circuit/component 1. As shown in FIG. 1A, the ESD protection element 100 and the protected circuit/element 1 are connected in parallel between the contact pad 2 and a ground potential or a power supply potential. When one end of the ESD protection element 100 coupled to the protected circuit/element 1 is in contact with static electricity (as indicated by the lightning bolt in FIG. 1A), the ESD protection element 100 is triggered to release high voltage and high current in the static electricity. To avoid electrostatic damage to the protected circuit/component 1.
舉例而言,靜電防護元件100如第1B圖顯示,利用N型金屬氧化半導體(metal oxide semiconductor,MOS)元件作為靜電防護元件100。靜電防護元件100包含P型基板11、絕緣結構13、N型輕摻雜汲極14、閘極15、源極16、與汲極17。在其中一種應用中,基板11、閘極15與源極16電連接至接地電位,汲極17電連接至接觸墊2。於靜電發生時,電流I對N型輕摻雜汲極14與P型基板11接面所形成的電容充電。因此,高壓電場形成於N型輕摻雜汲極14與P型基板11之間。當靜電高電壓超過靜電防護元件100的崩潰防護電壓時,產生崩潰現象;此時靜電防護元件100中的寄生雙極性電晶體(如圖中虛線雙極性電晶體符號所示意)之基極電位上升,進而導通此寄生雙極性電晶體,而進入自我偏壓模式。當靜電高電壓(也就是汲極電壓)V達到觸發電壓後,電流(也就是汲極17流至基板11的電流)I大幅上升,如第1C圖所示。 For example, the static electricity protection element 100 is shown in FIG. 1B as an electrostatic protection element 100 using an N-type metal oxide semiconductor (MOS) element. The static electricity protection element 100 includes a P-type substrate 11 , an insulating structure 13 , an N-type lightly doped drain electrode 14 , a gate electrode 15 , a source electrode 16 , and a drain electrode 17 . In one of the applications, the substrate 11, the gate 15 and the source 16 are electrically connected to the ground potential, and the drain 17 is electrically connected to the contact pad 2. When static electricity occurs, the current I charges the capacitance formed by the junction of the N-type lightly doped drain 14 and the P-type substrate 11. Therefore, a high voltage electric field is formed between the N-type lightly doped gate 14 and the P-type substrate 11. When the electrostatic high voltage exceeds the collapse protection voltage of the static electricity protection element 100, a collapse phenomenon occurs; at this time, the base potential of the parasitic bipolar transistor (shown by the dotted bipolar transistor symbol in the figure) rises in the electrostatic protection element 100. In turn, the parasitic bipolar transistor is turned on and enters a self-bias mode. When the electrostatic high voltage (i.e., the drain voltage) V reaches the trigger voltage, the current (i.e., the current flowing from the drain 17 to the substrate 11) I rises sharply as shown in Fig. 1C.
第1C圖顯示靜電防護元件100的電壓V-電流I的特徵曲線。如圖所示,當靜電高電壓V超過觸發點後,可以釋放靜電的高電壓與 高電流。需注意的是,如第1C圖所示,靜電防護元件100的設計應根據被保護電路/元件1的需要。觸發點的觸發電壓須低於被保護電路/元件1的崩潰防護電壓,也就是說,在被保護電路/元件1發生崩潰以前,靜電防護元件100需要被觸發而釋放靜電的高電壓與高電流,以避免被保護電路/元件1發生崩潰;並且,靜電防護元件100的崩潰防護電壓(低於觸發電壓),須高於電源供應電壓,以避免被保護電路/元件1在正常操作時,靜電防護元件100發生崩潰現象。 FIG. 1C shows a characteristic curve of the voltage V-current I of the static electricity protection element 100. As shown in the figure, when the electrostatic high voltage V exceeds the trigger point, the high voltage of the static electricity can be released. High current. It should be noted that, as shown in FIG. 1C, the design of the ESD protection component 100 should be based on the needs of the circuit/component 1 to be protected. The trigger voltage of the trigger point must be lower than the breakdown protection voltage of the protected circuit/element 1, that is, the high voltage and high current of the ESD protection element 100 need to be triggered to discharge static electricity before the protected circuit/element 1 collapses. To avoid the collapse of the protected circuit/element 1; and the breakdown protection voltage (below the trigger voltage) of the ESD protection element 100 must be higher than the power supply voltage to avoid electrostatic protection of the protected circuit/component 1 during normal operation. Component 100 crashes.
第1D圖顯示第1B圖中,橢圓虛線所標示的局部示意圖。如圖所示,當汲極17接觸靜電的高電壓,高電場形成於N型輕摻雜汲極14與P型基板11之間。開始發生崩潰的位置,在接近P型基板11表面的N型輕摻雜汲極14與P型基板11之間,如圖中星型符號所示意。當電路的設計需要降低觸發電壓時,此先前技術所示之靜電防護元件100受限於P型基板11其他元件的製程,只能額外增加製程步驟加以調整,且在現有元件的架構下,觸發電壓所能降低的程度有限。 Fig. 1D shows a partial schematic view of the elliptical dashed line in Fig. 1B. As shown, when the drain 17 contacts a high voltage of static electricity, a high electric field is formed between the N-type lightly doped drain 14 and the P-type substrate 11. The position at which the collapse begins to occur is between the N-type lightly doped drain 14 and the P-type substrate 11 near the surface of the P-type substrate 11, as indicated by the star symbol in the figure. When the design of the circuit needs to lower the trigger voltage, the electrostatic protection component 100 shown in the prior art is limited by the process of other components of the P-type substrate 11, and can only be adjusted by additionally adding process steps, and triggered under the existing component architecture. The degree to which the voltage can be reduced is limited.
有鑑於此,本發明即針對上述先前技術之不足,提出一種靜電防護元件及其製造方法,在不增加製程步驟的情況下,可降低元件之觸發電壓,加強元件的保護與應用範圍。 In view of the above, the present invention is directed to the above-mentioned deficiencies of the prior art, and proposes an electrostatic protection component and a manufacturing method thereof, which can reduce the trigger voltage of the component and enhance the protection and application range of the component without increasing the process steps.
就其中一觀點言,本發明提供了一種靜電防護元件,形成於一半導體基板中,該半導體基板具有一上表面,該靜電防護元件包含:一P型井區,形成於該上表面下;一閘極,形成於該上表面上,且部分該P型井區位於該閘極下方;一N型源極,形成於該上表面下之該P型井區中,由上視圖視之,該N型源極位於該閘極一側之外;一N型汲極,形成於該上表面下之該P型井區中,由上視圖視之,該N型汲極位於該閘極另一側之外;其中,該閘極將該N型源極與該N型汲極分開,該閘極包括:一介電層,形成於該上表面上,與該上表面連接;一堆疊層,形成於該介電層上,用以作為該閘極電性接點;以及一間隔層,形成於該堆疊層之側壁外之該上表面上;以及一第一P型輕摻雜汲極,形成於該上表面下之該P型井區中,由上視圖視之,部分該第一P型輕摻雜汲極位於該間隔層下方。 In one aspect, the present invention provides an electrostatic protection component formed in a semiconductor substrate having an upper surface, the electrostatic protection component comprising: a P-type well region formed under the upper surface; a gate formed on the upper surface, and a portion of the P-type well region is located under the gate; an N-type source is formed in the P-type well region below the upper surface, as viewed from a top view, The N-type source is located outside the gate side; an N-type drain is formed in the P-type well region below the upper surface, as viewed from a top view, the N-type drain is located at the gate and the gate Outside the side; wherein the gate separates the N-type source from the N-type drain, the gate includes: a dielectric layer formed on the upper surface and connected to the upper surface; a stacked layer, Formed on the dielectric layer for the gate electrical contact; and a spacer layer formed on the upper surface outside the sidewall of the stacked layer; and a first P-type lightly doped drain, Formed in the P-type well region below the upper surface, viewed from a top view, a portion of the first P-type lightly doped bungee is located therebetween Below the compartment.
就另一觀點言,本發明也提供了一種靜電防護元件製造方法,包含:提供一半導體基板,且該半導體基板具有一上表面;形成一P型井區於該上表面下;形成一閘極於該上表面上,且部分該P型井區位於該閘極下方;形成一N型源極於該上表面下之該P型井區中,由上視圖視之,該N型源極位於該閘極一側之外;形成一N型汲極於該上表面下之該P型井區中,由上視圖視之,該N型汲極位於該閘極另一側之外,該閘極將該N型源極與該N型汲極分開,該閘極包括:一介電層,形成於該上表面上,與該上表面連接;一堆疊層,形成於該介電層上,用以作為該閘極電性接點;以及一間隔層,形成於該堆疊層之側壁外之該上表面上;以及形成一第一P型輕摻雜汲極於該上表面下之該P型井區中,由上視圖視之,部分該第一P型輕摻雜汲極位於該間隔層下方。 In another aspect, the present invention also provides a method of fabricating an electrostatic protection device, comprising: providing a semiconductor substrate having an upper surface; forming a P-type well region under the upper surface; forming a gate On the upper surface, and a portion of the P-type well region is located below the gate; forming an N-type source in the P-type well region below the upper surface, as viewed from a top view, the N-type source is located Outside the gate side; forming an N-type drain in the P-type well region below the upper surface, viewed from a top view, the N-type drain is located outside the other side of the gate, the gate The N-type source is separated from the N-type drain, the gate includes: a dielectric layer formed on the upper surface and connected to the upper surface; a stacked layer formed on the dielectric layer Used as the gate electrical contact; and a spacer layer formed on the upper surface outside the sidewall of the stacked layer; and forming a first P-type lightly doped drain under the upper surface In the well region, a portion of the first P-type lightly doped drain is located below the spacer layer as viewed from a top view.
在其中一種較佳的實施型態中,該第一P型輕摻雜汲極與一低壓元件中之一第二P型輕摻雜汲極,利用相同製程步驟形成。 In one preferred embodiment, the first P-type lightly doped drain and one of the second P-type lightly doped drains of a low voltage component are formed using the same process steps.
在其中一種較佳的實施型態中,該閘極於正常操作時與一接地電位電性連接。 In one preferred embodiment, the gate is electrically coupled to a ground potential during normal operation.
在其中一種較佳的實施型態中,該第一P型輕摻雜汲極由一P型輕摻雜汲極離子植入製程步驟以及一N型輕摻雜汲極離子植入製程步驟所形成,其中該P型輕摻雜汲極離子植入製程步驟係形成一低壓元件中之一第二P型輕摻雜汲極之相同製程步驟。 In a preferred embodiment, the first P-type lightly doped drain is formed by a P-type lightly doped dopant ion implantation process and an N-type lightly doped dopant ion implantation process step. Forming, wherein the P-type lightly doped dopant ion implantation process step forms the same process step of forming a second P-type lightly doped drain in one of the low voltage components.
在其中一種較佳的實施型態中,該第一P型輕摻雜汲極之P型雜質濃度高於該P型井區之P型雜質濃度。 In one preferred embodiment, the P-type impurity concentration of the first P-type lightly doped drain is higher than the P-type impurity concentration of the P-type well region.
底下藉由具體實施例詳加說明,當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。 The purpose, technical content, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.
1‧‧‧被保護電路/元件 1‧‧‧protected circuits/components
2‧‧‧接觸墊 2‧‧‧Contact pads
11,21‧‧‧半導體基板 11,21‧‧‧Semiconductor substrate
22‧‧‧P型井區 22‧‧‧P type well area
13,23‧‧‧絕緣結構 13,23‧‧‧Insulation structure
14,34‧‧‧N型輕摻雜汲極 14,34‧‧‧N type lightly doped bungee
15,25‧‧‧閘極 15,25‧‧‧ gate
25a‧‧‧介電層 25a‧‧‧ dielectric layer
25b‧‧‧堆疊層 25b‧‧‧Stacking
25c,35c,45c,55c‧‧‧間隔層 25c, 35c, 45c, 55c‧‧‧ spacer
16,26‧‧‧N型源極 16,26‧‧‧N source
17,27‧‧‧N型汲極 17,27‧‧‧N type bungee
24,44,54‧‧‧P型輕摻雜汲極 24,44,54‧‧‧P type lightly doped bungee
100,200,300,400,500‧‧‧靜電防護元件 100,200,300,400,500‧‧‧Electrical protection components
211‧‧‧上表面 211‧‧‧ upper surface
I‧‧‧電流 I‧‧‧current
V‧‧‧電壓 V‧‧‧ voltage
第1A圖顯示先前技術之靜電防護元件100與被保護電路/元件1的電路 示意圖。 FIG. 1A shows a circuit of the prior art electrostatic protection element 100 and the protected circuit/element 1 schematic diagram.
第1B圖顯示先前技術之靜電防護元件100之剖視示意圖。 Figure 1B shows a schematic cross-sectional view of a prior art electrostatic protection element 100.
第1C圖顯示靜電防護元件100的電壓V-電流I的特徵曲線。 FIG. 1C shows a characteristic curve of the voltage V-current I of the static electricity protection element 100.
第1D圖顯示第1B圖中,虛線橢圓所標示的局部示意圖。 Fig. 1D shows a partial schematic view of the dotted line ellipse in Fig. 1B.
第2A-2F圖顯示本發明的第一個實施例。 Fig. 2A-2F shows a first embodiment of the present invention.
第3A-3B圖顯示先前技術靜電防護元件的濃度分布示意圖與電壓-電流特徵曲線。 3A-3B shows a concentration distribution diagram and a voltage-current characteristic curve of the prior art electrostatic protection element.
第4A-4B圖顯示本發明的第二個實施例。 4A-4B shows a second embodiment of the present invention.
第5A-5B圖顯示本發明的第三個實施例。 Figures 5A-5B show a third embodiment of the invention.
本發明中的圖式均屬示意,主要意在表示製程步驟以及各層之間之上下次序關係,至於形狀、厚度與寬度則並未依照比例繪製。 The drawings in the present invention are schematic and are mainly intended to represent the process steps and the relationship between the layers, and the shapes, thicknesses, and widths are not drawn to scale.
請參閱第2A-2F圖,顯示本發明第一個實施例,本實施例顯示靜電防護元件200的製作流程剖面示意圖。如第2A圖所示,首先提供半導體基板21,其例如但不限於為矽基板,當然亦可以為具有絕緣層的SOI基板,或是其他半導體基板;其中,半導體基板21具有上表面211。接著於半導體基板21中上表面211下形成P型井區22,並於上表面211上形成絕緣結構23。其中,絕緣結構23例如為圖示之區域氧化(local oxidation of silicon,LOCOS)結構,但亦可為其他形式的隔離結構,如淺溝槽絕緣(shallow trench isolation,STI)結構。接著請參閱第2B圖,於上表面211上形成閘極25部分結構,首先形成介電層25a與上表面211連接;接著形成堆疊層25b於介電層25a上,用以作為閘極25電性接點。 Referring to FIGS. 2A-2F, a first embodiment of the present invention is shown. This embodiment shows a cross-sectional view of the manufacturing process of the ESD protection device 200. As shown in FIG. 2A, a semiconductor substrate 21 is provided first, for example, but not limited to, a germanium substrate, and may of course be an SOI substrate having an insulating layer or other semiconductor substrate; wherein the semiconductor substrate 21 has an upper surface 211. Next, a P-type well region 22 is formed under the upper surface 211 of the semiconductor substrate 21, and an insulating structure 23 is formed on the upper surface 211. The insulating structure 23 is, for example, a local oxidation of silicon (LOCOS) structure, but may be other forms of isolation structures, such as a shallow trench isolation (STI) structure. Referring to FIG. 2B, a portion of the gate 25 is formed on the upper surface 211. First, a dielectric layer 25a is formed to be connected to the upper surface 211. Then, a stacked layer 25b is formed on the dielectric layer 25a for use as the gate 25. Sexual contact.
接下來請參閱第2C圖,利用絕緣結構23與堆疊層25b為遮罩,將P型雜質摻雜至半導體基板21中,以形成分別位於堆疊層25b兩側之二P型輕摻雜汲極24,其中,可利用但不限於離子植入技術,將N型雜質,以加速離子的形式,如本圖中虛線箭號24a所示意,植入半導體基板21中,以形成P型輕摻雜汲極24於P型井區22中。 Next, referring to FIG. 2C, a P-type impurity is doped into the semiconductor substrate 21 by using the insulating structure 23 and the stacked layer 25b as a mask to form two P-type lightly doped drain electrodes respectively on both sides of the stacked layer 25b. 24, wherein the N-type impurity can be implanted into the semiconductor substrate 21 in the form of an accelerated ion, such as the dotted arrow 24a in the figure, by using, but not limited to, an ion implantation technique to form a P-type light doping. The drain 24 is in the P-type well region 22.
再接著請參閱第2D圖,於介電層25a與堆疊層25b外側,利用但不限於薄膜沉積技術,沉積形成間隔層25C,並以自我對準蝕刻技術形成閘極25。其中,閘極25形成於上表面211上,且部分P型井區22位 於閘極25下方,且部分P型輕摻雜汲極24位於間隔層25c下方。 Next, referring to FIG. 2D, on the outside of the dielectric layer 25a and the stacked layer 25b, the spacer layer 25C is deposited by using, but not limited to, a thin film deposition technique, and the gate 25 is formed by a self-aligned etching technique. Wherein, the gate 25 is formed on the upper surface 211, and a portion of the P-type well region is 22 bits. Below the gate 25, a portion of the P-type lightly doped drain 24 is located below the spacer layer 25c.
再接下來請參閱第2E圖,利用絕緣結構23與閘極25為遮罩,或由微影技術定義範圍,將N型雜質摻雜至基板21中,以形成位於基板21上表面211下閘極25下方之外部,分別與二P型輕摻雜汲極24連接之N型源極26與N型汲極27,其中,N型源極26與N型汲極27分別位於閘極25一側與另一側之外;其中,可利用但不限於離子植入技術,將N型雜質,以加速離子的形式,如本圖中虛線箭號26a所示意,植入基板21中,以形成N型源極26與N型汲極27。 Next, referring to FIG. 2E, the insulating structure 23 and the gate 25 are used as a mask, or a range defined by lithography is used to dope N-type impurities into the substrate 21 to form a gate on the upper surface 211 of the substrate 21. The N-type source 26 and the N-type drain 27 connected to the second P-type light-doped drain 24 are respectively disposed outside the pole 25, wherein the N-type source 26 and the N-type drain 27 are respectively located at the gate 25 Except for the side and the other side; wherein the N-type impurity can be implanted into the substrate 21 to form an N-type impurity in the form of an accelerated ion, as indicated by a broken arrow 26a in the figure, using, but not limited to, an ion implantation technique. N-type source 26 and N-type drain 27.
而當本實施例之靜電防護元件200整合於其他低壓元件製程、且該低壓元件亦具有P型輕摻雜汲極時,此時更可利用形成該低壓元件P型輕摻雜汲極之雜質摻雜製程來完成靜電防護元件200之P型輕摻雜汲極24,而不需要另外新增光罩或製程步驟,以降低製造成本。 When the electrostatic protection component 200 of the embodiment is integrated into other low-voltage component processes, and the low-voltage component also has a P-type lightly doped drain, the P-type lightly doped dopant of the low-voltage component can be utilized at this time. The doping process is performed to complete the P-type lightly doped drain 24 of the ESD protection component 200 without the need for additional reticle or process steps to reduce manufacturing costs.
第2F圖顯示第2E圖中,橢圓虛線所標示的局部示意圖。在其中一種應用中,基板21、閘極25與源極26電連接至接地電位,汲極27電連接至接觸墊(未示出)。當汲極27接觸靜電的高電壓時,與先前技術不同,以本實施例為例,靜電的高電場形成於P型輕摻雜汲極24與N型汲極27之間。開始發生崩潰的位置,在接近上211的P型輕摻雜汲極24與N型汲極27之間,如圖中星型符號所示意。當電路的設計需要降低觸發電壓時,應用本發明,可利用P型基板21中其他元件的P型輕摻雜汲極製程,不需要額外增加製程步驟,且在現有元件的架構下,大幅降低觸發電壓。這是因為在先前技術中,靜電防護元件發生崩潰,進而達於觸發點而引發釋放靜電程序的位置,在N型輕摻雜汲極與P型基板之間,而在本發明中,靜電防護元件發生崩潰,進而達於觸發點而引發釋放靜電程序的位置,在P型輕摻雜汲極與N型汲極之間。在先前技術中,發生崩潰的位置,其PN接面周圍的載濃度相對較低,因此其崩潰防護電壓較高;而在本發明中,發生崩潰的位置,其PN接面周圍的載濃度相對較高,因此其崩潰防護電壓較低。比較本實施例靜電防護元件200與先前技術靜電防護元件100,P型輕摻雜汲極24之P型雜質濃度高於P型井區22之P型雜質濃度,更高於先前技術中之P型半導體基板11之P型雜質濃度;而N型汲極27之N型 雜質濃度高於先前技術P型井區22之P型雜質濃度。 Fig. 2F shows a partial schematic view of the elliptical dotted line in Fig. 2E. In one application, the substrate 21, the gate 25 and the source 26 are electrically connected to a ground potential, and the drain 27 is electrically connected to a contact pad (not shown). When the drain electrode 27 is exposed to a high voltage of static electricity, unlike the prior art, in the present embodiment, a high electric field of static electricity is formed between the P-type lightly doped drain electrode 24 and the N-type drain electrode 27. The location where the collapse begins is between the P-type lightly doped drain 24 and the N-type drain 27 near the upper 211, as indicated by the star symbol in the figure. When the design of the circuit needs to lower the trigger voltage, the P-type lightly doped drain process of other components in the P-type substrate 21 can be utilized by using the present invention, without additionally adding process steps, and greatly reducing the structure of the existing components. Trigger voltage. This is because in the prior art, the electrostatic protection element collapses, and then reaches the trigger point to initiate the discharge of the electrostatic program between the N-type lightly doped drain and the P-type substrate, and in the present invention, the electrostatic protection The component collapses and then reaches the trigger point to initiate the release of the electrostatic program between the P-type lightly doped drain and the N-type drain. In the prior art, in the position where the collapse occurs, the load concentration around the PN junction is relatively low, so that the collapse protection voltage is high; and in the present invention, the position of the collapse occurs, and the concentration around the PN junction is relatively Higher, so its crash protection voltage is lower. Comparing the electrostatic protection component 200 of the present embodiment with the prior art electrostatic protection component 100, the P-type impurity concentration of the P-type lightly doped gate 24 is higher than the P-type impurity concentration of the P-type well region 22, which is higher than that of the prior art. P-type impurity concentration of the type semiconductor substrate 11; and N type of the N-type drain electrode 27 The impurity concentration is higher than the P-type impurity concentration of the prior art P-type well region 22.
第3A-3B圖分別顯示先前技術靜電防護元件300的濃度分布示意圖與電壓-電流特徵曲線。如第3A圖所示,靜電防護元件300中,間隔層35C下方為N型輕摻雜汲極34。第3B圖模擬示出靜電防護元件300的電壓-電流特徵曲線,其觸發點電壓約為13V。 The 3A-3B diagram shows a concentration distribution diagram and a voltage-current characteristic curve of the prior art electrostatic protection element 300, respectively. As shown in FIG. 3A, in the static electricity protection element 300, under the spacer layer 35C is an N-type lightly doped drain 34. Figure 3B simulates a voltage-current characteristic of the ESD protection element 300 with a trigger point voltage of approximately 13V.
第4A-4B圖顯示本發明第二個實施例,分別顯示本實施例靜電防護元件400的濃度分布示意圖與電壓-電流特徵曲線。如第4A圖所示,靜電防護元件400中,間隔層45C下方為P型輕摻雜汲極44,其例如由一P型輕摻雜汲極離子植入製程步驟以及一N型輕摻雜汲極離子植入製程步驟所形成,其中P型輕摻雜汲極離子植入製程步驟係形成於相同基板中,一低壓元件中之P型輕摻雜汲極之相同製程步驟。第4B圖模擬示出本實施例靜電防護元件400的電壓-電流特徵曲線,其觸發點電壓約為11V。 4A-4B are views showing a second embodiment of the present invention, respectively showing a concentration distribution diagram and a voltage-current characteristic curve of the electrostatic protection element 400 of the present embodiment. As shown in FIG. 4A, in the ESD device 400, under the spacer layer 45C is a P-type lightly doped drain 44, which is, for example, a P-type lightly doped gated ion implantation process step and an N-type light doping process. The step of forming a bungee ion implantation process is performed, wherein the P-type lightly doped dopant ion implantation process is formed in the same substrate, and the P-type lightly doped drain in a low voltage component is the same process step. Fig. 4B is a graph showing the voltage-current characteristic curve of the static electricity protection element 400 of the present embodiment, the trigger point voltage of which is about 11V.
第5A-5B圖顯示本發明第三個實施例,分別顯示本實施例靜電防護元件500的濃度分布示意圖與電壓-電流特徵曲線。如第5A圖所示,靜電防護元件500中,間隔層55C下方為P型輕摻雜汲極54,其例如由一P型輕摻雜汲極離子植入製程步驟所形成,其中P型輕摻雜汲極離子植入製程步驟例如為形成於相同基板中,一低壓元件中之P型輕摻雜汲極之相同製程步驟。第5B圖模擬示出本實施例靜電防護元件500的電壓-電流特徵曲線,其觸發點電壓約為10V。 5A-5B show a third embodiment of the present invention, respectively showing a concentration distribution diagram and a voltage-current characteristic curve of the electrostatic protection element 500 of the present embodiment. As shown in FIG. 5A, in the ESD device 500, under the spacer layer 55C is a P-type lightly doped drain 54 formed, for example, by a P-type lightly doped dopant ion implantation process step, wherein the P-type light is formed. The doped dopant ion implantation process step is, for example, the same process step of forming a P-type lightly doped drain in a low voltage component in the same substrate. Fig. 5B is a graph showing the voltage-current characteristic curve of the electrostatic protection element 500 of the present embodiment, the trigger point voltage of which is about 10V.
以上已針對較佳實施例來說明本發明,唯以上所述者,僅係為使熟悉本技術者易於了解本發明的內容而已,並非用來限定本發明之權利範圍。在本發明之相同精神下,熟悉本技術者可以思及各種等效變化。例如,在不影響元件主要的特性下,可加入其他製程步驟或結構,如深井區等;又如,微影技術並不限於光罩技術,亦可包含電子束微影技術;又如,P型輕摻雜汲極整合於其他元件製程時,不限於利用其他元件之P型輕摻雜汲極光罩與製程,當然也可以利用一專用於P型輕摻雜汲極之光罩與製程。本發明的範圍應涵蓋上述及其他所有等效變化。 The present invention has been described with reference to the preferred embodiments thereof, and the present invention is not intended to limit the scope of the present invention. In the same spirit of the invention, various equivalent changes can be conceived by those skilled in the art. For example, other process steps or structures, such as deep well areas, may be added without affecting the main characteristics of the components; for example, lithography is not limited to reticle technology, and may include electron beam lithography; for example, P When the lightly doped ruthenium is integrated into other component processes, it is not limited to the P-type lightly doped yttrium reticle and process using other components. Of course, a reticle and process dedicated to the P-type lightly doped ruthenium can also be utilized. The above and other equivalent variations are intended to be covered by the scope of the invention.
21‧‧‧半導體基板 21‧‧‧Semiconductor substrate
22‧‧‧P型井區 22‧‧‧P type well area
23‧‧‧絕緣結構 23‧‧‧Insulation structure
24‧‧‧P型輕摻雜汲極 24‧‧‧P type lightly doped bungee
25‧‧‧閘極 25‧‧‧ gate
25a‧‧‧介電層 25a‧‧‧ dielectric layer
25b‧‧‧堆疊層 25b‧‧‧Stacking
25c‧‧‧間隔層 25c‧‧‧ spacer
26‧‧‧N型源極 26‧‧‧N source
27‧‧‧N型汲極 27‧‧‧N type bungee
200‧‧‧靜電防護元件 200‧‧‧Electrical protection components
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