TW201501307A - Semiconductor device - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 244
- 239000003990 capacitor Substances 0.000 claims description 106
- 239000012535 impurity Substances 0.000 claims description 96
- 238000009792 diffusion process Methods 0.000 claims description 93
- 238000000926 separation method Methods 0.000 claims description 74
- 239000000758 substrate Substances 0.000 claims description 69
- 238000000034 method Methods 0.000 claims description 47
- 238000009413 insulation Methods 0.000 claims description 9
- 239000013078 crystal Substances 0.000 claims description 8
- 239000012212 insulator Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 121
- 239000011229 interlayer Substances 0.000 description 60
- 238000002955 isolation Methods 0.000 description 34
- 238000004519 manufacturing process Methods 0.000 description 26
- 229910004298 SiO 2 Inorganic materials 0.000 description 18
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 18
- 229910001936 tantalum oxide Inorganic materials 0.000 description 18
- 238000005530 etching Methods 0.000 description 15
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 13
- 230000006870 function Effects 0.000 description 13
- 230000008569 process Effects 0.000 description 11
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 11
- 230000004048 modification Effects 0.000 description 10
- 238000012986 modification Methods 0.000 description 10
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 9
- 229910052721 tungsten Inorganic materials 0.000 description 9
- 239000010937 tungsten Substances 0.000 description 9
- 238000010276 construction Methods 0.000 description 8
- 238000001312 dry etching Methods 0.000 description 7
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 229910052732 germanium Inorganic materials 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 239000000203 mixture Substances 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 230000014759 maintenance of location Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000005549 size reduction Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 241000270295 Serpentes Species 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- CFJRGWXELQQLSA-UHFFFAOYSA-N azanylidyneniobium Chemical compound [Nb]#N CFJRGWXELQQLSA-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000003623 enhancer Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/36—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being a FinFET
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
Description
本發明係有關半導體裝置。 The present invention relates to a semiconductor device.
近年，伴隨著半導體裝置(半導體元件)之細微化，有著亦加以縮小電晶體尺寸之傾向。經由此尺寸之縮小，電晶體(Tr)之短通道效果則變為更顯著。 In recent years, with the miniaturization of semiconductor devices (semiconductor elements), there has been a tendency to reduce the size of the transistors. As a result of this size reduction, the short channel effect of the transistor (Tr) becomes more pronounced.
例如，在半導體裝置之中之1個的DRAM(Dynamic Random Access Memory)中，經由記憶體單元尺寸之縮小化，亦加以縮小有電晶體的通道長度。因此，電晶體的性能則下降。隨之，記憶體單元的保持或寫入特性之惡化等則成為問題。 For example, in a DRAM (Dynamic Random Access Memory) of one of the semiconductor devices, the channel length of the transistor is also reduced by the size reduction of the memory cell. Therefore, the performance of the transistor is degraded. Along with this, deterioration of the retention or writing characteristics of the memory cell is a problem.
為了解決如此之問題，加以開發有經由形成溝(凹槽)於半導體基板之時而將通道作為3次元構造之凹槽(切口)型FET(Field Effect Transistor)、或經由形成翼片於溝之間之時而將通道作為3次元構造之翼片型FET等(例如，參照日本特開2005-064500號公報(專利文獻1)，日本特開2007-027753號公報(專利文獻2)及日本特開2007-305827號公報(專利文獻3))。 In order to solve such a problem, a FET (Field Effect Transistor) in which a channel is formed as a ternary structure by forming a groove (groove) on a semiconductor substrate, or by forming a fin in a groove is developed. For example, JP-A-2005-064500 (Patent Document 1), JP-A-2005-064753 (Patent Document 2), and JP-A-2007-027753 (Patent Document 2) Japanese Patent Publication No. 2007-305827 (Patent Document 3)).
上述凹槽型FET係於半導體基板形成溝，於該溝內，藉由閘極絕緣膜而配置閘極電極者，將通道作為3次元構造之電晶體。 The groove-type FET is formed by forming a trench in a semiconductor substrate, and a gate electrode is disposed in the trench by a gate insulating film, and the channel is a transistor of a three-dimensional structure.
另一方面，翼片型FET係由呈跨越從形成於半導體基板的溝之間突出之翼片地，藉由閘極絕緣膜而配置閘極電極者，將通道作為3次元構造之電晶體。 On the other hand, the fin FET is a transistor in which a gate electrode is arranged in a three-dimensional structure by a gate electrode that protrudes from a trench formed between the semiconductor substrate and is provided with a gate insulating film.
在上述凹槽型FET及翼片型FET中，對於通道寬度而言成為可加長閘極長度者。因此，可抑制短通道效果者。 In the above-described groove type FET and fin type FET, it is possible to lengthen the gate length with respect to the channel width. Therefore, the short channel effect can be suppressed.
另外，在DRAM中，伴隨著記憶體單元尺寸之縮小化，作為構成該記憶體單元之選擇用電晶體，亦加以檢討有採用具有埋入於半導體基板之主面側的埋入型閘極電極的電晶體者。 Further, in the DRAM, as the size of the memory cell is reduced, the selective transistor constituting the memory cell is also examined to have a buried gate electrode having a main surface side buried in the semiconductor substrate. The crystal of the person.
在作為如此構成之電晶體中，閘極電極(字元線)則加以埋入於半導體基板的主面側。因此，於較半導體基板之主面為上方未突出有閘極電極者。 In the transistor configured as described above, the gate electrode (character line) is buried on the main surface side of the semiconductor substrate. Therefore, the gate electrode is not protruded above the main surface of the semiconductor substrate.
另外，與記憶體單元加以連接之配線之中位置於半導體基板上方之情況係成為僅位元線。隨之，不僅形成構成記憶體單元於半導體基板上之電容器及接觸塞等時之配置變為容易，而亦有可減輕其加工的困難度之優點。 Further, in the case where the wiring connected to the memory cell is positioned above the semiconductor substrate, it is a bit line only. Accordingly, it is easy to arrange not only the capacitors and the contact plugs constituting the memory cell on the semiconductor substrate but also the difficulty in processing.
[專利文獻1]日本特開2005-064500號公報 [Patent Document 1] Japanese Patent Laid-Open Publication No. 2005-064500
[專利文獻2]日本特開2007-027753號公報 [Patent Document 2] Japanese Patent Laid-Open Publication No. 2007-027753
[專利文獻3]日本特開2007-305827號公報 [Patent Document 3] Japanese Patent Laid-Open Publication No. 2007-305827
在上述之具有埋入型閘極電極的電晶體(Tr)中，作為埋入於半導體基板之主面側的閘極電極(字元線)之材料，例如，加以使用金屬膜(與多結晶矽膜做比較為阻抗低的膜)之鎢膜(W膜)及氮化鈦膜(TiN膜)。了解到經由使用金屬膜之時，可得到閘極電極(字元線)及位元線之電容的降低，稱作GIDL(Gate-Induced-Drain-Leakage current)之電流的抑制，保持(Retention)特性的改善，及消耗電流之降低等之效果者。 In the above-described transistor (Tr) having a buried gate electrode, as a material of a gate electrode (character line) embedded in the main surface side of the semiconductor substrate, for example, a metal film (with polycrystal) is used. The tantalum film is a tungsten film (W film) and a titanium nitride film (TiN film) which are comparatively low in impedance. It is understood that the reduction of the capacitance of the gate electrode (character line) and the bit line can be obtained by using the metal film, and the suppression of the current called GIDL (Gate-Induced-Drain-Leakage current), retention (Retention) Improvements in characteristics, and reduction in current consumption, etc.
但，經由細微化而加以縮小有字元線之間隔時，如在後述之圖23所說明地，產生有在同一活性範圍內鄰接之記憶體單元彼此之動作產生干涉的干擾不良。 However, when the interval between the word lines is reduced by the miniaturization, as described later with reference to FIG. 23, interference failures in which the operations of the adjacent memory cells in the same active range interfere with each other occur.
圖23係模式性地顯示為了說明干擾不良之以往的半導體裝置之記憶體單元部的主要部之剖面圖。然而，在圖23中，模式性地圖示與第1及第2之閘極電極223，228交叉的位元線212。 FIG. 23 is a cross-sectional view schematically showing a main part of a memory cell unit of a conventional semiconductor device for explaining interference. However, in FIG. 23, the bit line 212 crossing the first and second gate electrodes 223, 228 is schematically illustrated.
於參照圖23，以往的半導體裝置200係具有：半導體基板201，和元件分離範圍202，和活性範圍204，和第1電晶體206，和第2電晶體207，和位元線接觸塞211，和位元線212，和第1電容接觸塞214(儲存節 點接點)，和第2電容接觸塞215(儲存節點接點)。 Referring to Fig. 23, a conventional semiconductor device 200 includes a semiconductor substrate 201, an element isolation range 202, and an active range 204, and a first transistor 206, a second transistor 207, and a bit line contact plug 211. And the bit line 212, and the first capacitor contact plug 214 (storage section) Point contact), and the second capacitor contact plug 215 (storage node contact).
元件分離範圍202係加以設置於半導體基板201之主面201a側，而區劃活性範圍204。對於活性範圍204係加以形成有第1及第2溝201A，201B。 The element separation range 202 is provided on the main surface 201a side of the semiconductor substrate 201 to define the active range 204. The first and second grooves 201A, 201B are formed in the active range 204.
第1電晶體206係具有：被覆第1溝201A內面之閘極絕緣膜222，和藉由閘極絕緣膜222，埋入第1溝201A下部之第1閘極電極223，和加以形成於位置在第1溝201A上部與元件分離範圍202之間的活性範圍204之第1不純物擴散範圍225，和加以形成於位置在第1及第2溝201A，201B之上部間的活性範圍204之第2不純物擴散範圍226。 The first transistor 206 has a gate insulating film 222 covering the inner surface of the first trench 201A, and a first gate electrode 223 buried in the lower portion of the first trench 201A by the gate insulating film 222, and is formed on the first transistor 206 The first impurity diffusion range 225 of the active range 204 between the upper portion of the first groove 201A and the element separation range 202, and the first range of the active range 204 formed between the upper portion of the first and second grooves 201A, 201B 2 Impurity diffusion range 226.
第2電晶體207係具有：被覆第2溝201B內面之閘極絕緣膜222，和藉由閘極絕緣膜222，埋入第2溝201B下部之第2閘極電極228，和加以形成於位置在第2溝201B上部與元件分離範圍202之間的活性範圍204之第1不純物擴散範圍227，和第2不純物擴散範圍226(與第1電晶體206共通之不純物擴散範圍)。 The second transistor 207 has a gate insulating film 222 covering the inner surface of the second trench 201B, and a second gate electrode 228 buried in the lower portion of the second trench 201B by the gate insulating film 222, and is formed on the second transistor 207. The first impurity diffusion range 227 of the active range 204 between the upper portion of the second groove 201B and the element separation range 202, and the second impurity diffusion range 226 (the impurity diffusion range common to the first transistor 206).
第2電晶體207係加以設置於設置有第1電晶體206之活性範圍204的電晶體。 The second transistor 207 is provided in a transistor in which the active range 204 of the first transistor 206 is provided.
位元線接觸塞211係加以設置於第2不純物擴散範圍226之上面226a。位元線212係加以設置於位元線接觸塞211上，與位元線接觸塞211之上端作為一體。 The bit line contact plug 211 is provided on the upper surface 226a of the second impurity diffusion range 226. The bit line 212 is provided on the bit line contact plug 211, and is integrated with the upper end of the bit line contact plug 211.
第1電容接觸塞214係與構成第1電晶體206之第1 不純物擴散範圍225的上面225a加以連接。 The first capacitor contact plug 214 is the first one that constitutes the first transistor 206 The upper 225a of the impurity diffusion range 225 is connected.
第2電容接觸塞215係與構成第2電晶體207之第1不純物擴散範圍227的上面227a加以連接。 The second capacitor contact plug 215 is connected to the upper surface 227a of the first impurity diffusion range 227 constituting the second transistor 207.
在作為上述構成之半導體裝置200中，將第2電容接觸塞215做成「High」之同時，將第2電晶體207作為off(關閉)狀態。在此狀態，反覆第1電晶體206之on-off(開啟關閉)動作時，由激發，且未捕獲於第1電晶體206之通道範圍231而成為浮遊狀態的電子(圖23所示之「e-」)則浮游在第2電晶體207之周圍。電子係在某機率而侵入至第2電容接觸塞215。 In the semiconductor device 200 having the above configuration, the second capacitor contact plug 215 is made "High", and the second transistor 207 is turned "off". In this state, when the on-off operation of the first transistor 206 is repeated, the electrons that are excited and are not captured in the channel range 231 of the first transistor 206 and become in a floating state (shown in FIG. 23) e - ") floats around the second transistor 207. The electrons intrude into the second capacitor contact plug 215 at a certain probability.
其結果，保持於第2電容接觸塞215之「High」的資訊則產生有由「Low」資訊所破壞之干擾不良。 As a result, the information held at the "High" of the second capacitive contact plug 215 causes interference failure caused by the "Low" information.
上述干擾不良係伴隨之半導體裝置之細微化，而成為更嚴峻之問題。 The above-mentioned interference is accompanied by the miniaturization of the semiconductor device, which is a more serious problem.
如根據本發明之一觀點，提供有具備：包含半導體基板主體，被覆該半導體基板主體之面的絕緣層，及被覆該絕緣層的一面之半導體層的SOI(Silicon on Insulator)基板，和將前述半導體層對於第1方向而言進行分斷成複數之複數的第1元件分離範圍，和將前述半導體層於對於前述第1方向而言進行交叉之第2方向而言分斷成複數之複數的第2元件分離範圍，和經由前述複數之第 1及第2元件分離範圍所區劃的同時，在前述第1及第2方向加以絕緣分離之複數的活性範圍，和對於各前述複數之活性範圍而言加以設置，延伸存在於前述第1方向之同時，作為未到達至前述絕緣層之深度的2個溝，和藉由被覆前述溝的內面之閘極絕緣膜，包含加以配置於前述溝內之閘極電極，加以配置於同一前述活性範圍之2個電晶體，而前述2個電晶體係各具有：前述活性範圍之中，在前述第2方向中配置於構成加以對向配置之前述溝之2個側面的部分之側壁部通道範圍，和前述活性範圍之中，加以配置於位置在前述溝的底面與前述絕緣層之間的部份之底部通道範圍的半導體裝置。 According to one aspect of the present invention, there is provided an SOI (Silicon on Insulator) substrate including a semiconductor substrate main body, an insulating layer covering a surface of the semiconductor substrate main body, and a semiconductor layer covering one surface of the insulating layer, and The semiconductor layer is divided into a plurality of first element isolation ranges in the first direction and a plurality of plural numbers in the second direction intersecting the first direction in the first direction. The second component separation range, and the 1 and the second element separation range are divided, and the plurality of active ranges in which the first and second directions are insulated and separated are provided for each of the plurality of active ranges, and are extended in the first direction. At the same time, the two gates that do not reach the depth of the insulating layer and the gate insulating film that covers the inner surface of the trench include a gate electrode disposed in the trench, and are disposed in the same active range. Each of the two electromorphic systems has a range of side wall portions of the portion constituting the two side faces of the groove disposed oppositely in the second direction; And a semiconductor device disposed in a bottom channel region of a portion between the bottom surface of the trench and the insulating layer, among the active ranges.
如根據經由本發明之一觀點之半導體裝置，加以設置於同一活性範圍之2個電晶體則具有：活性範圍中，在第2方向中配置於構成加以對向配置的溝之2個側面之部分的側壁部通道範圍，和活性範圍之中，加以配置於位置在溝的底面與絕緣層之間的部份之底部通道範圍。由加深溝的深度者，成為可薄化配置於溝的底面與絕緣層之間之半導體層的厚度，縮小成為電荷通路之底部通道範圍之剖面積者。 According to the semiconductor device of the aspect of the invention, the two transistors provided in the same active range have an active range, and are disposed in the second direction in the second side of the groove constituting the oppositely disposed groove. The range of the side wall passages and the range of the active range are disposed in the bottom passage portion of the portion between the bottom surface of the groove and the insulating layer. When the depth of the deep trench is increased, the thickness of the semiconductor layer which can be thinned between the bottom surface of the trench and the insulating layer can be reduced, and the cross-sectional area of the bottom channel region of the charge path can be reduced.
經由此，成為限制歷經底部通道範圍之浮遊電子的移動(換言之，經由底部通道範圍之浮遊電子的流通)者。隨之可抑制干擾不良者。 As a result, the movement of the floating electrons passing through the range of the bottom channel (in other words, the circulation of the floating electrons via the bottom channel range) is restricted. This can suppress the interference.
10，95，110，130，140‧‧‧半導體裝置 10,95,110,130,140‧‧‧ semiconductor devices
11，96，111，131，141‧‧‧記憶體單元部 11,96,111,131,141‧‧‧ memory unit
13‧‧‧SOI基板 13‧‧‧SOI substrate
13a‧‧‧主面 13a‧‧‧Main face
13-1‧‧‧半導體基板主體 13-1‧‧‧Semiconductor substrate body
13-1a，13-2a‧‧‧一面 13-1a, 13-2a‧‧‧ side
13-2‧‧‧絕緣層 13-2‧‧‧Insulation
13-3‧‧‧半導體層 13-3‧‧‧Semiconductor layer
14‧‧‧第1元件分離範圍 14‧‧‧1st component separation range
14-1‧‧‧第1元件分離用溝 14-1‧‧‧1st element separation trench
14-2‧‧‧第1元件分離用絕緣膜 14-2‧‧‧Insulation film for the first component separation
17‧‧‧第2元件分離範圍 17‧‧‧Second component separation range
17-1‧‧‧第2元件分離用溝 17-1‧‧‧Separation of the second component separation trench
17-2‧‧‧第2元件分離用絕緣膜 17-2‧‧‧Insulation film for second component separation
19‧‧‧活性範圍 19‧‧‧Active range
19a，66c，68a，71a，77c，78a，124c‧‧‧上面 19a, 66c, 68a, 71a, 77c, 78a, 124c‧‧‧ above
21，113，143‧‧‧第1溝 21,113,143‧‧‧1st ditch
21a，22a，113a，114a，121a，122a，143a，144a‧‧‧底面 21a, 22a, 113a, 114a, 121a, 122a, 143a, 144a‧‧‧ bottom
21b，21c，22b，22c，66a，66b，77a，77b，124a，124b，125a，125b‧‧‧側面 21b, 21c, 22b, 22c, 66a, 66b, 77a, 77b, 124a, 124b, 125a, 125b‧‧‧ side
22，114，144‧‧‧第2溝 22,114,144‧‧‧2nd ditch
25，116，146‧‧‧第1單元電晶體 25,116,146‧‧‧1st unit transistor
27，117，147‧‧‧第2單元電晶體 27,117,147‧‧‧2nd unit transistor
29‧‧‧第1層間絕緣膜 29‧‧‧1st interlayer insulating film
29A‧‧‧第1開口溝 29A‧‧‧1st open trench
29B‧‧‧第2開口溝 29B‧‧‧2nd open trench
32‧‧‧埋入絕緣膜 32‧‧‧Insert insulating film
33‧‧‧位元線接觸開口部 33‧‧‧ bit line contact opening
35‧‧‧位元線接觸塞 35‧‧‧ bit line contact plug
37‧‧‧位元線 37‧‧‧ bit line
39‧‧‧間隙絕緣膜 39‧‧‧Gap insulation film
41‧‧‧第1側壁膜 41‧‧‧1st sidewall film
42‧‧‧第2側壁膜 42‧‧‧2nd sidewall film
44‧‧‧第2層間絕緣膜 44‧‧‧Second interlayer insulating film
45-1‧‧‧第1電容接觸孔 45-1‧‧‧1st Capacitor Contact Hole
45-2‧‧‧第2電容接觸孔 45-2‧‧‧2nd capacitor contact hole
46-1‧‧‧第1電容接觸塞 46-1‧‧‧1st capacitive contact plug
46-2‧‧‧第2電容接觸塞 46-2‧‧‧2nd capacitive contact plug
48‧‧‧停止膜 48‧‧‧stop film
49‧‧‧第3層間絕緣膜 49‧‧‧3rd interlayer insulating film
51‧‧‧缸孔 51‧‧‧ cylinder bore
53‧‧‧電容器 53‧‧‧ capacitor
55‧‧‧第4層間絕緣膜 55‧‧‧4th interlayer insulating film
57‧‧‧保護膜 57‧‧‧Protective film
59-1‧‧‧第1閘極絕緣膜 59-1‧‧‧1st gate insulating film
59-2‧‧‧第2閘極絕緣膜 59-2‧‧‧2nd gate insulating film
61‧‧‧第1閘極電極 61‧‧‧1st gate electrode
63‧‧‧第1側壁部通道範圍 63‧‧‧1st side wall passage range
64‧‧‧第2側壁部通道範圍 64‧‧‧2nd side wall channel range
66，121，151‧‧‧第1底部通道範圍 66,121,151‧‧‧1st bottom channel range
66A，66B，77A，77B‧‧‧端部 66A, 66B, 77A, 77B‧‧‧ end
66d，77d，124d‧‧‧下面 66d, 77d, 124d‧‧‧ below
68‧‧‧第1電容用不純物擴散範圍 68‧‧‧The first capacitor uses impurity diffusion range
71‧‧‧位元線用不純物擴散範圍 71‧‧‧ bit line diffusion range of impurities
74‧‧‧第2閘極電極 74‧‧‧2nd gate electrode
76‧‧‧第3側壁部通道範圍 76‧‧‧3rd side wall passage range
77，122，152‧‧‧第2底部通道範圍 77,122,152‧‧‧2nd bottom channel range
78‧‧‧第2電容用不純物擴散範圍 78‧‧‧The second capacitor uses impurity diffusion range
84‧‧‧下部電極 84‧‧‧ lower electrode
85‧‧‧電容絕緣膜 85‧‧‧Capacitive insulation film
86‧‧‧上部電極 86‧‧‧Upper electrode
98‧‧‧不純物擴散層 98‧‧‧ impurity diffusion layer
101‧‧‧金屬膜 101‧‧‧Metal film
102‧‧‧矽氮化膜 102‧‧‧矽Nitride film
124‧‧‧平板狀通道範圍 124‧‧‧flat channel range
125‧‧‧突出通道範圍 125‧‧‧Outstanding channel range
H1‧‧‧突出量 H1‧‧‧ outstanding amount
H2‧‧‧高度 H2‧‧‧ Height
M1，M2，M3，M4‧‧‧厚度 M1, M2, M3, M4‧‧‧ thickness
W1，W2，W3‧‧‧寬度 W1, W2, W3‧‧‧ width
圖1係擴大構成有關本發明之第1實施形態之半導體裝置之記憶體單元部之一部分的平面圖，僅圖示記憶體單元部之構成要素之中，第1元件分離範圍，第2元件分離範圍，活性範圍，第1溝，第2溝，第1閘極電極，第2閘極電極，位元線接觸塞，及位元線的圖。 1 is a plan view showing a part of a memory cell unit constituting a semiconductor device according to a first embodiment of the present invention, and shows only a first element separation range and a second element separation range among the components of the memory cell unit. , the active range, the first trench, the second trench, the first gate electrode, the second gate electrode, the bit line contact plug, and the bit line.
圖2係圖1所示之半導體裝置之記憶體單元部之A-A線方向的剖面圖。 2 is a cross-sectional view taken along the line A-A of the memory cell unit of the semiconductor device shown in FIG. 1.
圖3係擴大圖2所示之記憶體單元部之中，由範圍A所圍繞之部分的剖面圖。 Fig. 3 is a cross-sectional view showing a portion of the memory cell unit shown in Fig. 2 surrounded by a range A.
圖4係經由等角圖法，圖示第1實施形態之半導體裝置之記憶體單元部之主要部的等角投影圖。 4 is an isometric view showing a main portion of a memory cell unit of the semiconductor device of the first embodiment via an isometric method.
圖5係圖1所示之半導體裝置之記憶體單元部之B-B線方向的剖面圖，僅擴大圖示配置於第1底部通道範圍之周圍的構成要素的圖。 5 is a cross-sectional view taken along the line B-B of the memory cell unit of the semiconductor device shown in FIG. 1, and only the components shown in the vicinity of the first bottom channel are enlarged.
圖6係為了說明構成第1實施形態之半導體裝置之記憶體單元部之第1元件分離範圍，第2元件分離範圍，活性範圍，第1底部通道範圍，及第2底部通道範圍的位置關係的平面圖。 6 is a view showing a first element separation range, a second element separation range, an active range, a first bottom passage range, and a second bottom passage range positional relationship of the memory unit portion of the semiconductor device according to the first embodiment. Floor plan.
圖7係擴大有關本發明之第1實施形態的變形例之半導體裝置之記憶體單元部之中，與第1實施形態之半導體裝置不同之部分的剖面圖。 FIG. 7 is a cross-sectional view showing a portion of the memory cell unit of the semiconductor device according to the modification of the first embodiment of the present invention, which is different from the semiconductor device of the first embodiment.
圖8係顯示本發明之第1實施形態之半導體裝置之製造工程的圖(其1)，為了說明SOI基板之製造工程之剖面圖。 8 is a view (1) showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention, and is a cross-sectional view for explaining a manufacturing process of the SOI substrate.
圖9A係顯示本發明之第1實施形態之半導體裝置之製造工程的圖(其2)，為了說明製造途中之半導體裝置之記憶體單元部的平面圖。 9A is a view (2) of a manufacturing process of a semiconductor device according to a first embodiment of the present invention, and is a plan view showing a memory cell unit of a semiconductor device in the middle of manufacturing.
圖9B係顯示本發明之第1實施形態之半導體裝置之製造工程的圖(其2)，為了說明圖9A所示之構造體的A-A線方向之剖面圖。 Fig. 9B is a view (2) showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention, and is a cross-sectional view taken along line A-A of the structure shown in Fig. 9A.
圖10係顯示本發明之第1實施形態之半導體裝置之製造工程的圖(其3)，為了說明製造途中之半導體裝置之記憶體單元部的剖面圖。 FIG. 10 is a view (No. 3) showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention, and is a cross-sectional view showing a memory cell unit of the semiconductor device in the middle of the manufacturing process.
圖11係顯示本發明之第1實施形態之半導體裝置之製造工程的圖(其4)，為了說明製造途中之半導體裝置之記憶體單元部的剖面圖。 FIG. 11 is a view (4) showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention, and is a cross-sectional view showing a memory cell unit of the semiconductor device in the middle of manufacturing.
圖12A係顯示本發明之第1實施形態之半導體裝置之製造工程的圖(其5)，為了說明製造途中之半導體裝置之記憶體單元部的平面圖。 FIG. 12 is a plan view (5) showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention, and is a plan view showing a memory cell unit of the semiconductor device in the middle of manufacturing.
圖12B係顯示本發明之第1實施形態之半導體裝置之製造工程的圖(其5)，為了說明圖12A所示之構造體的A-A線方向之剖面圖。 FIG. 12B is a view (5) showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention, and is a cross-sectional view taken along line A-A of the structure shown in FIG. 12A.
圖13係顯示本發明之第1實施形態之半導體裝置之製造工程的圖(其6)，為了說明製造途中之半導體裝置之記憶體單元部的剖面圖。 FIG. 13 is a view (6) showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention, and is a cross-sectional view showing a memory cell unit of the semiconductor device in the middle of manufacturing.
圖14係顯示本發明之第1實施形態之半導體裝置之製造工程的圖(其6)，為了說明製造途中之半導體裝置之記憶體單元部的剖面圖。 FIG. 14 is a view (6) showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention, and is a cross-sectional view showing a memory cell unit of the semiconductor device in the middle of manufacturing.
圖15係經由等角圖法，圖示第2實施形態之半導體裝置之記憶體單元部之主要部的等角投影圖。 Fig. 15 is an isometric view showing a main portion of a memory cell unit of the semiconductor device of the second embodiment, via an isometric method.
圖16係擴大由圖15所示之範圍B所圍繞之記憶體單元部的剖面圖。 Fig. 16 is a cross-sectional view showing the expansion of the memory unit portion surrounded by the range B shown in Fig. 15.
圖17係擴大有關本發明之第2實施形態的變形例之半導體裝置之記憶體單元部之中，與第2實施形態之半導體裝置不同之部分的剖面圖。 Fig. 17 is a cross-sectional view showing a portion of a memory cell unit of a semiconductor device according to a modification of the second embodiment of the present invention, which is different from the semiconductor device of the second embodiment.
圖18係顯示本發明之第2實施形態的半導體裝置之工程的剖面圖(其1)。 18 is a cross-sectional view (No. 1) showing the construction of a semiconductor device according to a second embodiment of the present invention.
圖19係顯示本發明之第2實施形態的半導體裝置之工程的剖面圖(其2)。 19 is a cross-sectional view (No. 2) showing the construction of a semiconductor device according to a second embodiment of the present invention.
圖20係經由等角圖法，圖示第3實施形態之半導體裝置之記憶體單元部之主要部的等角投影圖。 Fig. 20 is an isometric view showing a main portion of a memory cell unit of the semiconductor device of the third embodiment, via an isometric method.
圖21係擴大由圖20所示之範圍C所圍繞之記憶體單元部的剖面圖。 Fig. 21 is a cross-sectional view showing the expansion of the memory unit portion surrounded by the range C shown in Fig. 20.
圖22係顯示本發明之第3實施形態的半導體裝置之工程的剖面圖。 Fig. 22 is a cross-sectional view showing the construction of a semiconductor device according to a third embodiment of the present invention.
圖23係模式性地顯示為了說明干擾不良之以往的半導體裝置之主要部之剖面圖。 FIG. 23 is a cross-sectional view schematically showing a main part of a conventional semiconductor device for explaining interference failure.
以下，參照圖面而對於適用本發明之實施形態加以詳細說明。然而，在以下的說明所使用之圖面係為了容易了解特徵，在說明的方便上，有著擴大顯示成為特徵的部分情況，而各構成要素的尺寸比率等則不限於與實際相同。 Hereinafter, embodiments to which the present invention is applied will be described in detail with reference to the drawings. However, in the drawings used in the following description, in order to facilitate the understanding of the features, there is a case where the display is enlarged, and the size ratio of each component is not limited to the actual one.
另外，在以下說明所例示的材料，尺寸等係為一例，本發明係未必限定於此等，而在不變更其內容的範圍可做適宜變更而實施者。 In addition, the material, the size, and the like exemplified in the following description are examples, and the present invention is not limited thereto, and may be appropriately modified without departing from the scope of the contents.
圖1係擴大構成有關本發明之第1實施形態之半導體裝置之記憶體單元部之一部分的平面圖，僅圖示記憶體單元部之構成要素之中，第1元件分離範圍，第2元件分離範圍，活性範圍，第1溝，第2溝，第1閘極電極，第2閘極電極，位元線接觸塞，及位元線的圖。 1 is a plan view showing a part of a memory cell unit constituting a semiconductor device according to a first embodiment of the present invention, and shows only a first element separation range and a second element separation range among the components of the memory cell unit. , the active range, the first trench, the second trench, the first gate electrode, the second gate electrode, the bit line contact plug, and the bit line.
圖2係圖1所示之半導體裝置之記憶體單元部之A-A線方向的剖面圖。圖3係擴大圖2所示之記憶體單元部之中，由範圍A所圍繞之部分的剖面圖。圖4係經由等角圖法，圖示第1實施形態之半導體裝置之記憶體單元部之主要部的等角投影圖。 2 is a cross-sectional view taken along the line A-A of the memory cell unit of the semiconductor device shown in FIG. 1. Fig. 3 is a cross-sectional view showing a portion of the memory cell unit shown in Fig. 2 surrounded by a range A. 4 is an isometric view showing a main portion of a memory cell unit of the semiconductor device of the first embodiment via an isometric method.
在圖1~圖4中，作為第1實施形態之半導體裝置10的一例，舉例圖示DRAM(Dynamic Random Access Memory)。 In the example of the semiconductor device 10 of the first embodiment, a DRAM (Dynamic Random Access Memory) is exemplified as shown in FIG. 1 to FIG.
在圖1~圖4中，X方向(第2方向)係顯示第1元件 分離範圍14的延伸存在方向。Y方向(第1方向)係顯示與X方向交叉(圖1的情況，正交)之第2元件分離範圍17的延伸存在方向。Z方向係顯示對於X方向及Y方向而言正交之方向(換言之，半導體基板主體13-1之厚度方向)。 In FIGS. 1 to 4, the X element (the second direction) shows the first element. The extension of the separation range 14 exists in the direction. The Y direction (first direction) indicates the direction in which the second element separation range 17 intersects with the X direction (the case of FIG. 1 is orthogonal). The Z direction shows a direction orthogonal to the X direction and the Y direction (in other words, the thickness direction of the semiconductor substrate main body 13-1).
在圖1中，W1係顯示圖3所示，且未於圖1所圖示之第1底部通道範圍66之Y方向的寬度(以下，稱作「寬度W1」者)。W2係顯示圖3所示，且未於圖1所圖示之第2底部通道範圍77之Y方向的寬度(以下，稱作「寬度W2」者)。然而，寬度W1，W2係與在Y方向之活性範圍19的寬度相等。 In Fig. 1, W1 shows the width in the Y direction (hereinafter referred to as "width W1") of the first bottom channel range 66 shown in Fig. 3 and not shown in Fig. 1 . The W2 system is shown in FIG. 3 and is not in the Y-direction width of the second bottom channel range 77 (hereinafter referred to as "width W2") shown in FIG. However, the widths W1, W2 are equal to the width of the active range 19 in the Y direction.
另外，在圖2及圖4中模式性地圖示位元線37。位元線37係實際上如圖1所示地延伸存在於X方向。 In addition, the bit line 37 is schematically illustrated in FIGS. 2 and 4. The bit line 37 actually extends in the X direction as shown in FIG.
在圖1~圖4中，對於同一構成部分係附上同一符號。 In FIGS. 1 to 4, the same components are denoted by the same reference numerals.
對於參照圖1~圖4，第1實施形態之半導體裝置10係具有：加以設置於記憶體單元範圍之記憶體單元部11，和加以設置於位置在記憶體單元部11周圍之周邊電路範圍(未圖示)之周邊電路範圍(未圖示)。 Referring to FIGS. 1 to 4, the semiconductor device 10 of the first embodiment has a memory cell unit 11 provided in a range of a memory cell, and a peripheral circuit range provided at a position around the memory cell unit 11 ( Not shown in the peripheral circuit range (not shown).
對於記憶體單元部11係將複數之記憶體單元(單元)加以排列配置成矩陣狀。另一方面，對於周邊電路部(未圖示)係加以配置有為了控制各記憶體單元之動作的電路(亦包含有未圖示之周邊電路用電晶體)。 In the memory cell unit 11, a plurality of memory cells (cells) are arranged in a matrix. On the other hand, a circuit (not including a peripheral circuit transistor (not shown)) for controlling the operation of each memory cell is disposed in a peripheral circuit portion (not shown).
以下，主要對於構成第1實施形態之半導體裝置10之記憶體單元部11的構成加以說明。 Hereinafter, the configuration of the memory cell unit 11 constituting the semiconductor device 10 of the first embodiment will be mainly described.
第1實施形態之半導體裝置10之記憶體單元部11係具有：SOI(Silicon on Insulator)基板13，和第1元件分離範圍14，和第2元件分離範圍17，和活性範圍19，第1溝21，和第2溝22，和第1單元電晶體25(第1電晶體)，和第2單元電晶體27(第2電晶體)，和第1層間絕緣膜29，和埋入絕緣膜32，和位元線接觸開口部33，和位元線接觸塞35，和位元線37，和間隙絕緣膜39，和第1側壁膜41，和第2側壁膜42，和第2層間絕緣膜44，和第1電容接觸孔45-1，和第2電容接觸孔45-2，和第1電容接觸塞46-1，和第2電容接觸塞46-2，和停止膜48，和第3層間絕緣膜49，和缸孔51，和電容器53，和第4層間絕緣膜55，和保護膜57。 The memory cell unit 11 of the semiconductor device 10 of the first embodiment includes an SOI (Silicon on Insulator) substrate 13, a first element isolation range 14, a second element separation range 17, and an active range 19, and a first groove. 21, and the second trench 22, and the first unit transistor 25 (first transistor), and the second unit transistor 27 (second transistor), and the first interlayer insulating film 29, and the buried insulating film 32. And the bit line contact opening portion 33, and the bit line contact plug 35, and the bit line 37, and the gap insulating film 39, and the first side wall film 41, and the second side wall film 42, and the second interlayer insulating film 44, and the first capacitor contact hole 45-1, and the second capacitor contact hole 45-2, and the first capacitor contact plug 46-1, and the second capacitor contact plug 46-2, and the stop film 48, and the third An interlayer insulating film 49, and a cylinder bore 51, and a capacitor 53, and a fourth interlayer insulating film 55, and a protective film 57.
對於參照圖2及圖4，SOI基板13係作為依序加以層積半導體基板主體13-1，和被覆半導體基板主體13-1之一面13-1a的絕緣層13-2，和被覆絕緣層13-2之一面13-2a的半導體層13-3(SOI層)之構成。 2 and 4, the SOI substrate 13 is sequentially laminated with the semiconductor substrate main body 13-1, and the insulating layer 13-2 covering one surface 13-1a of the semiconductor substrate main body 13-1, and the insulating cover layer 13 -2 The structure of the semiconductor layer 13-3 (SOI layer) of one surface 13-2a.
半導體基板主體13-1係作為板狀之基板。作為半導體基板主體13-1係例如，可使用p型單結晶矽基板。 The semiconductor substrate main body 13-1 is a plate-shaped substrate. As the semiconductor substrate main body 13-1, for example, a p-type single crystal germanium substrate can be used.
絕緣層13-2係加以配置於半導體基板主體13-1與半導體層13-3之間的埋入絕緣層。絕緣層13-2係加以配置於從SOI基板13之主面13a(換言之，半導體層13-3之上面)為深之位置(例如，從SOI基板13之主面13a為250nm之深度的位置)。 The insulating layer 13-2 is a buried insulating layer disposed between the semiconductor substrate main body 13-1 and the semiconductor layer 13-3. The insulating layer 13-2 is disposed at a position deep from the main surface 13a of the SOI substrate 13 (in other words, the upper surface of the semiconductor layer 13-3) (for example, a position at a depth of 250 nm from the main surface 13a of the SOI substrate 13) .
作為絕緣層13-2係例如，可使用稱作埋入氧化(BOX； Buried Oxide)膜之矽氧化膜(SiO2膜)者。 As the insulating layer 13-2, for example, a tantalum oxide film (SiO 2 film) called a Buick Oxide film can be used.
半導體層13-3係加以形成有第1及第2單元電晶體25，27的層。作為半導體層13-3係例如，可使用p型之單結晶矽層者。 The semiconductor layer 13-3 is a layer in which the first and second unit transistors 25 and 27 are formed. As the semiconductor layer 13-3, for example, a p-type single crystal germanium layer can be used.
此情況，半導體層13-3之厚度M1係例如，可作為300nm者。 In this case, the thickness M1 of the semiconductor layer 13-3 is, for example, 300 nm.
然而，在以下的說明中，作為半導體層13-3之一例，舉例說明使用p型之單結晶矽層的情況。 However, in the following description, as an example of the semiconductor layer 13-3, a case where a p-type single crystal germanium layer is used will be exemplified.
對於參照圖1及圖4，第1元件分離範圍14係呈延伸存在於X方向(第2方向)地，加以複數設置於半導體層13-3。 Referring to FIGS. 1 and 4, the first element isolation range 14 is extended in the X direction (second direction), and is provided in plural in the semiconductor layer 13-3.
第1元件分離範圍14係具有延伸存在於X方向，且呈露出絕緣層13-2之一面13-2a地加以設置於半導體層13-3之第1元件分離用溝14-1，和埋入第1元件分離用溝14-1之第1元件分離用絕緣膜14-2(例如，矽氧化膜(SiO2膜))。 The first element isolation range 14 has a first element isolation trench 14-1 which is provided in the semiconductor layer 13-3 and which is extended in the X direction and which is exposed on one surface 13-2a of the insulating layer 13-2, and is buried. The first element isolation insulating film 14-2 (for example, a tantalum oxide film (SiO 2 film)) of the first element isolation trench 14-1.
經由此，第1元件分離範圍14係作為到達至絕緣層13-2之一面13-2a的深度。 Thereby, the first element separation range 14 serves as a depth reaching the one surface 13-2a of the insulating layer 13-2.
複數之第1元件分離範圍14係以特定的間隔加以配置於Y方向(第1方向)。經由此，複數之第1元件分離範圍14係將半導體層13-3對於Y方向而言分斷(分割)為複數。 The plurality of first element separation ranges 14 are arranged in the Y direction (first direction) at specific intervals. Thus, the plurality of first element separation ranges 14 divide (divide) the semiconductor layer 13-3 into a plurality in the Y direction.
第2元件分離範圍17係呈延伸存在於Y方向地，加以複數設置於半導體層13-3及第1元件分離範圍 14。第2元件分離範圍17係分斷加以配置於Y方向之複數之第1元件分離範圍14。 The second element separation range 17 is extended in the Y direction, and is provided in plural in the semiconductor layer 13-3 and the first element separation range. 14. The second element separation range 17 is divided into a plurality of first element separation ranges 14 arranged in the Y direction.
第2元件分離範圍17係具有第2元件分離用溝17-1，和第2元件分離用絕緣膜17-2(例如，矽氧化膜(SiO2膜))。第2元件分離用溝17-1係延伸存在於Y方向，且呈露出絕緣層13-2之一面13-2a地加以設置於半導體層13-3及第1元件分離範圍14。第2元件分離用絕緣膜17-2係埋入第2元件分離用溝17-1。 The second element isolation range 17 includes a second element isolation trench 17-1 and a second element isolation insulating film 17-2 (for example, a tantalum oxide film (SiO 2 film)). The second element isolation trench 17-1 is extended in the Y direction, and is provided on the semiconductor layer 13-3 and the first element isolation range 14 so as to expose one surface 13-2a of the insulating layer 13-2. The second element isolation insulating film 17-2 is buried in the second element isolation trench 17-1.
經由此，第2元件分離範圍17係作為到達至絕緣層13-2之一面13-2a的深度。 Thereby, the second element separation range 17 is taken as the depth reaching the one surface 13-2a of the insulating layer 13-2.
複數之第2元件分離範圍17係對於X方向而言加以複數配置。經由此，複數之第2元件分離範圍17係將半導體層13-3對於X方向而言分斷(分割)為複數。 The plurality of second element separation ranges 17 are arranged in plural for the X direction. Thus, the plurality of second element separation ranges 17 divide (divide) the semiconductor layer 13-3 into a plurality in the X direction.
對於參照圖1~圖3，活性範圍19係由以第1及第2元件分離範圍14，17所區劃之半導體層13-3加以構成。活性範圍19係呈對於X方向及Y方向而言排列地加以複數配置。複數之活性範圍19係經由第1及第2元件分離範圍14，17，與在X方向及Y方向加以配置於周圍之其他的活性範圍19加以絕緣分離。 Referring to Figs. 1 to 3, the active range 19 is composed of a semiconductor layer 13-3 partitioned by the first and second element separation ranges 14, 17. The active range 19 is arranged in a plurality of rows in the X direction and the Y direction. The plurality of active ranges 19 are insulated and separated from the other active ranges 19 arranged in the X direction and the Y direction via the first and second element separation ranges 14 and 17.
活性範圍19係作為加以形成有第1及第2單元電晶體25，27的元件形成層而發揮機能的範圍。 The active range 19 is a range in which the element forming layers of the first and second unit transistors 25 and 27 are formed to function.
第1及第2溝21，22係延伸存在於Y方向的溝，呈跨越配置於Y方向之複數之活性範圍19及第1元件分離範圍14地加以設置。第1及第2溝21，22係對於 1個活性範圍19而言，各加以設置1個。 The first and second grooves 21 and 22 are grooves extending in the Y direction and are provided across a plurality of active ranges 19 and a first element separation range 14 which are arranged in the Y direction. The first and second grooves 21, 22 are for One activity range 19 is set for each.
第1溝21係配置有第1閘極絕緣膜59-1及第1閘極電極31的溝。第2溝22係配置有第2閘極絕緣膜59-2及第2閘極電極74的溝。 The first trench 21 is provided with a trench of the first gate insulating film 59-1 and the first gate electrode 31. The second trench 22 is provided with a trench of the second gate insulating film 59-2 and the second gate electrode 74.
第1及第2溝21，22之深度(將SOI基板13之主面13a作為基準時之深度)係作為未到達至絕緣層13-2之一面13-2a的深度。也就是，第1及第2溝21，22的深度係作為殘存有半導體層13-3於第1及第2溝21，22之底面21a，22a與絕緣層13-2之一面13-2a之間的厚度。第1及第2溝21，22之底面21a，22a係呈接近於絕緣層13-2之一面13-2a地加以配置。 The depth of the first and second grooves 21, 22 (the depth at which the principal surface 13a of the SOI substrate 13 is used as a reference) is defined as the depth that does not reach the one surface 13-2a of the insulating layer 13-2. That is, the depths of the first and second grooves 21, 22 are such that the semiconductor layer 13-3 remains on the bottom surfaces 21a, 22a of the first and second grooves 21, 22 and one surface 13-2a of the insulating layer 13-2. The thickness between the two. The bottom surfaces 21a and 22a of the first and second grooves 21 and 22 are arranged close to one surface 13-2a of the insulating layer 13-2.
如此，使半導體層13-3殘存於第1溝21之底面21a與絕緣層13-2之一面13-2a之間。經由此，成為可使半導體層13-3作為第1單元電晶體25之後述之第1底部通道範圍66而發揮機能者。 In this manner, the semiconductor layer 13-3 remains between the bottom surface 21a of the first trench 21 and one surface 13-2a of the insulating layer 13-2. As a result, the semiconductor layer 13-3 can function as the first bottom channel range 66 described later in the first unit transistor 25.
另外，使半導體層13-3殘存於第2溝22之底面22a與絕緣層13-2之一面13-2a之間。經由此，成為可使該半導體層13-3作為第2單元電晶體27之後述之第2底部通道範圍77而發揮機能者。 Further, the semiconductor layer 13-3 remains between the bottom surface 22a of the second trench 22 and one surface 13-2a of the insulating layer 13-2. As a result, the semiconductor layer 13-3 can function as the second bottom channel range 77 described later as the second unit transistor 27.
另外，加深第1及第2溝21，22之深度。經由此，成為可由薄化作為第1及第2底部通道範圍66，77而發揮機能之半導體層13-3的厚度，縮小成為電荷的通路之第1及第2底部通道範圍66，77的剖面積者。 Further, the depths of the first and second grooves 21, 22 are deepened. As a result, the thickness of the semiconductor layer 13-3 which functions as the first and second bottom channel ranges 66, 77 can be reduced, and the first and second bottom channel ranges 66, 77 which are reduced to the path of the electric charge can be reduced. Area.
隨之，因成為可限制歷經第1及第2底部通道範圍 66，77之浮遊電子(e-)的移動(換言之，歷經第1及第2底部通道範圍66，77之浮遊電子的流通)者之故，可抑制干擾不良。 Accordingly, the movement of the floating electrons (e - ) passing through the first and second bottom channel ranges 66, 77 (in other words, the circulation of the floating electrons passing through the first and second bottom channel ranges 66, 77) can be restricted. Therefore, it is possible to suppress interference.
對於參照圖2~圖4，第1單元電晶體25(選擇電晶體)係對於複數之活性範圍19而言各加以設置1個。 Referring to FIGS. 2 to 4, the first unit transistor 25 (selective transistor) is provided for each of the plurality of active ranges 19.
第1單元電晶體25係具有：第1閘極絕緣膜59-1，和第1閘極電極61，和第1側壁部通道範圍63，和第2側壁部通道範圍64，和第1底部通道範圍66，和第1電容用不純物擴散範圍68，和位元線用不純物擴散範圍71。 The first unit transistor 25 has a first gate insulating film 59-1, a first gate electrode 61, and a first side wall portion channel range 63, and a second side wall portion channel range 64, and a first bottom channel. The range 66, and the first capacitor use the impurity diffusion range 68, and the bit line use the impurity diffusion range 71.
第1閘極絕緣膜59-1係呈被覆第1溝21內面地加以設置。作為第1閘極絕緣膜59-1係例如，可使用單層之矽氧化膜(SiO2膜)，氮化矽氧化膜的膜(SiON膜)，加以層積之矽氧化膜(SiO2膜)，於矽氧化膜(SiO2膜)上使矽氮化膜(SiN膜)層積之層積膜等者。 The first gate insulating film 59-1 is provided to cover the inner surface of the first trench 21. As the first gate insulating film 59-1, for example, a single-layer tantalum oxide film (SiO 2 film), a tantalum nitride oxide film (SiON film), and a stacked tantalum oxide film (SiO 2 film) can be used. A laminated film in which a tantalum nitride film (SiN film) is laminated on a tantalum oxide film (SiO 2 film).
第1閘極電極61係藉由第1閘極絕緣膜59-1，呈埋入第1溝21之下部地加以設置。作為第1閘極電極61之材料係可使用導電材料者。作為該導電材料係例如，可使用鎢(W)等之金屬，或者多結晶矽等者。 The first gate electrode 61 is provided by being buried in the lower portion of the first trench 21 by the first gate insulating film 59-1. As the material of the first gate electrode 61, a conductive material can be used. As the conductive material, for example, a metal such as tungsten (W) or a polycrystalline germanium can be used.
具體而言，第1閘極電極61係例如，可以依序層積氮化鈦膜(TiN膜)，和鎢膜(W膜)之層積膜而構成者。 Specifically, the first gate electrode 61 can be formed by, for example, laminating a titanium nitride film (TiN film) and a laminated film of a tungsten film (W film).
對於參照圖3及圖4，第1側壁部通道範圍63係經由活性範圍19(半導體層13-3)而加以構成。活性 範圍19(半導體層13-3)係位置於第1溝21之側面21b(與X方向交叉(第1實施形態之情況，正交)之側面)與第2元件分離範圍17之間。 Referring to FIGS. 3 and 4, the first side wall portion passage region 63 is configured via the active range 19 (semiconductor layer 13-3). active The range 19 (semiconductor layer 13-3) is located between the side surface 21b of the first groove 21 (the side surface intersecting the X direction (the case where the first embodiment is orthogonal)) and the second element separation range 17.
第2側壁部通道範圍64係經由活性範圍19(半導體層13-3)而加以構成。活性範圍19(半導體層13-3)係位置於第1溝21之側面21c(在X方向與側面21b對向的側面)，與第2溝22之側面22b(與X方向交叉(第1實施形態之情況，正交)之側面)之間。 The second side wall portion passage range 64 is configured via the active range 19 (semiconductor layer 13-3). The active range 19 (semiconductor layer 13-3) is located on the side surface 21c of the first groove 21 (the side surface facing the side surface 21b in the X direction), and the side surface 22b of the second groove 22 (crossing the X direction (first implementation) In the case of the form, the side of the orthogonal) is between.
第2側壁部通道範圍64係在第1及第2單元電晶體25，27間加以共有之側壁部通道範圍。 The second side wall portion channel range 64 is a range of the side wall portion channels shared between the first and second unit transistors 25 and 27.
圖5係圖1所示之半導體裝置之記憶體單元部之B-B線方向的剖面圖，僅擴大圖示配置於第1底部通道範圍之周圍的構成要素的圖。 5 is a cross-sectional view taken along the line B-B of the memory cell unit of the semiconductor device shown in FIG. 1, and only the components shown in the vicinity of the first bottom channel are enlarged.
圖6係為了說明構成第1實施形態之半導體裝置之記憶體單元部之第1元件分離範圍，第2元件分離範圍，活性範圍，第1底部通道範圍，及第2底部通道範圍的位置關係的平面圖。在圖6中，僅圖示第1實施形態之半導體裝置10之記憶體單元部11的構成要素之中，第1元件分離範圍14，第2元件分離範圍17，活性範圍19，第1底部通道範圍66，及第2底部通道範圍77。 6 is a view showing a first element separation range, a second element separation range, an active range, a first bottom passage range, and a second bottom passage range positional relationship of the memory unit portion of the semiconductor device according to the first embodiment. Floor plan. In FIG. 6, only the first element separation range 14, the second element separation range 17, the active range 19, and the first bottom channel are shown among the components of the memory unit portion 11 of the semiconductor device 10 of the first embodiment. Range 66, and the second bottom channel range 77.
然而，在圖5及圖6中，對於與圖1~圖4所示之構造體同一構成部分係附上同一符號。 In FIGS. 5 and 6, the same components as those of the structures shown in FIGS. 1 to 4 are denoted by the same reference numerals.
接著，參照圖3~圖6，對於第1底部通道範圍66加以說明。 Next, the first bottom channel range 66 will be described with reference to Figs. 3 to 6 .
第1底部通道範圍66係經由活性範圍19而加以構成。活性範圍19係加以配置於第1溝21之底面21a與絕緣層13-2之一面13-2a之間。 The first bottom channel range 66 is configured via the active range 19. The active range 19 is disposed between the bottom surface 21a of the first groove 21 and one surface 13-2a of the insulating layer 13-2.
第1底部通道範圍66之側面66a，66b(2個側面)係在Y方向加以對向配置之同時，與第1元件分離範圍14接觸。另外，第1底部通道範圍66之上面66c係與第1閘極絕緣膜59-1接觸。 The side faces 66a, 66b (two side faces) of the first bottom channel range 66 are opposed to each other in the Y direction and are in contact with the first element separation range 14. Further, the upper surface 66c of the first bottom channel range 66 is in contact with the first gate insulating film 59-1.
如此，在第1底部通道範圍66中，作為使在Y方向加以對向配置之第1底部通道範圍66之側面66a，66b(2個側面)，與第1元件分離範圍14接觸之構成。更且，在第1底部通道範圍66中，作為使第1底部通道範圍66之上面66c，與第1閘極絕緣膜59-1接觸之構成。更且，在第1底部通道範圍66中，作為使第1底部通道範圍66之下面66d，與絕緣層13-2之一面13-2a(上面)接觸之構成。 As described above, in the first bottom channel range 66, the side faces 66a, 66b (two side faces) of the first bottom channel range 66 disposed opposite to each other in the Y direction are in contact with the first element separation range 14. Further, in the first bottom channel range 66, the upper surface 66c of the first bottom channel range 66 is brought into contact with the first gate insulating film 59-1. Further, in the first bottom channel range 66, the lower surface 66d of the first bottom channel range 66 is brought into contact with one surface 13-2a (upper surface) of the insulating layer 13-2.
經由此，可縮窄底部通道範圍66之剖面積者。隨之，成為可限制歷經第1底部通道範圍66之浮遊電子的移動，即，歷經第1底部通道範圍66之浮遊電子的流通者。因此，可抑制干擾不良。 Thereby, the cross-sectional area of the bottom channel range 66 can be narrowed. Accordingly, it is possible to restrict the movement of the floating electrons passing through the first bottom channel range 66, that is, the flow of the floating electrons passing through the first bottom channel range 66. Therefore, interference can be suppressed.
第1底部通道範圍66係具有加以配置於X方向之端部66A，66B(2個端部)。端部66A(一方的端部)係與第1側壁部通道範圍63加以連接(一體化)。端部66B係與第2側壁部通道範圍64加以連接(一體化)。 The first bottom channel range 66 has end portions 66A, 66B (two end portions) arranged in the X direction. The end portion 66A (one end portion) is connected (integrated) to the first side wall portion passage range 63. The end portion 66B is connected (integrated) to the second side wall portion passage range 64.
經由此，第1側壁部通道範圍63，第2側壁部通道 範圍64，及第1底部通道範圍66係構成從第1電容用不純物擴散範圍68連續至位元線用不純物擴散範圍71為止之通道。 Thereby, the first side wall portion passage range 63, the second side wall portion passage The range 64 and the first bottom channel range 66 constitute a channel from the first capacitance impurity diffusion range 68 to the bit line impurity diffusion range 71.
第1底部通道範圍66係具有平行於半導體基板主體13-1之一面13-1a的上面66c及下面66d的平板狀通道範圍。 The first bottom channel range 66 has a flat channel range parallel to the upper surface 66c and the lower surface 66d of one surface 13-1a of the semiconductor substrate main body 13-1.
如此，將第1底部通道範圍66作為具有平行於半導體基板主體13-1之一面13-1a的上面66c及下面66d的平板狀通道範圍。經由此，如圖23所示之以往技術，比較於未限制有流通路徑之構成，成為可限制歷經第1底部通道範圍66之浮遊電子的流通路徑者。隨之可抑制干擾不良者。 Thus, the first bottom channel range 66 is defined as a flat channel having parallel to the upper surface 66c and the lower surface 66d of one surface 13-1a of the semiconductor substrate main body 13-1. As a result, as in the prior art shown in FIG. 23, the flow path of the floating electrons passing through the first bottom passage range 66 can be restricted as compared with the configuration in which the flow path is not limited. This can suppress the interference.
第1底部通道範圍66之厚度M2(在對於半導體基板主體13-1之一面13-1a而言正交之方向的厚度)則較半導體層13-3之厚度M1之1/20為薄時，底部通道範圍66之剖面積則變為過小。因此，不僅限制歷經第1底部通道範圍66之浮遊電子的移動，加以限制至正常的電子之流動。隨之，產生有ON電流下降之問題。 When the thickness M2 of the first bottom channel range 66 (the thickness in the direction orthogonal to the one surface 13-1a of the semiconductor substrate main body 13-1) is thinner than 1/20 of the thickness M1 of the semiconductor layer 13-3, The cross-sectional area of the bottom channel range 66 becomes too small. Therefore, not only the movement of the floating electrons passing through the first bottom channel range 66 but also the flow of normal electrons is restricted. Along with this, there is a problem that the ON current is lowered.
另外，當第1底部通道範圍66之厚度M2則較半導體層13-3之厚度M1之1/5為厚時，因底部通道範圍66之剖面積變大之故，成為無法限制歷經第1底部通道範圍66之浮遊電子的移動者。隨之，產生有無法抑制干擾不良之問題。 Further, when the thickness M2 of the first bottom channel range 66 is thicker than 1/5 of the thickness M1 of the semiconductor layer 13-3, since the sectional area of the bottom channel range 66 becomes large, the first bottom portion cannot be restricted. The mover of the floating electrons in the channel range 66. Along with this, there is a problem that the interference cannot be suppressed.
經由上述理由，第1底部通道範圍66之厚度M2係 作為在半導體層13-3之厚度M1之1/20~1/5的範圍內為佳。 For the above reasons, the thickness of the first bottom channel range 66 is M2 It is preferably in the range of 1/20 to 1/5 of the thickness M1 of the semiconductor layer 13-3.
另外，理想為第1底部通道範圍66之厚度M2係作為在半導體層13-3之厚度M1之1/15~1/10的範圍內為佳。如此，由將第1底部通道範圍66之厚度M2作為在半導體層13-3之厚度M1之1/15~1/10的範圍內者，可更有效果地抑制干擾不良。 Further, it is preferable that the thickness M2 of the first bottom channel range 66 is preferably in the range of 1/15 to 1/10 of the thickness M1 of the semiconductor layer 13-3. As described above, by setting the thickness M2 of the first bottom channel range 66 to be within the range of 1/15 to 1/10 of the thickness M1 of the semiconductor layer 13-3, it is possible to more effectively suppress the interference failure.
具體而言，半導體層13-3之厚度M1為300nm之情況，第1底部通道範圍66之厚度M2係例如，設定為20~30nm之範圍內為佳。 Specifically, the thickness M1 of the semiconductor layer 13-3 is 300 nm, and the thickness M2 of the first bottom channel range 66 is preferably in the range of 20 to 30 nm, for example.
成為電荷的通路之第1底部通道範圍66係經由存在有SOI基板13之絕緣層13-2之時，成為加以限定為規定在第1底部通道範圍之寬度W1×厚度M2之剖面積者。 When the first bottom channel range 66 which becomes the path of the electric charge passes through the insulating layer 13-2 in which the SOI substrate 13 is present, it is limited to the cross-sectional area defined by the width W1 × thickness M2 of the first bottom channel range.
另外，成為電荷的通路之第2底部通道範圍77係經由存在有SOI基板13之絕緣層13-2之時，成為加以限定為規定在第2底部通道範圍77之寬度W2×厚度M3之剖面積者。 In addition, when the second bottom channel range 77 which is a path of the electric charge passes through the insulating layer 13-2 in which the SOI substrate 13 is present, the cross-sectional area defined by the width W2 × thickness M3 defined in the second bottom channel range 77 is defined. By.
對於參照圖2~圖4，第1電容用不純物擴散範圍68係加以設置於位置在第2元件分離範圍17上部與第1溝21上部之間的活性範圍19。經由此，第1電容用不純物擴散範圍68係加以配置於第1側壁部通道範圍63上。 Referring to FIGS. 2 to 4, the first capacitance impurity diffusion range 68 is provided in the active range 19 between the upper portion of the second element separation range 17 and the upper portion of the first groove 21. Thereby, the first capacitance diffusion range 68 is disposed on the first side wall passage region 63.
第1電容用不純物擴散範圍68係作為源極/汲極領域 而發揮機能。第1電容用不純物擴散範圍68之上面68a係與SOI基板13之主面13a一致。 The first capacitor uses the impurity diffusion range 68 as the source/drainage field. And play the function. The upper surface 68a of the first capacitance diffusion range 68 is identical to the main surface 13a of the SOI substrate 13.
第1電容用不純物擴散範圍68係由摻雜不純物(例如，半導體層13-3為p型半導體之情況，n型不純物)於活性範圍19者而加以形成之範圍。 The first capacitance impurity diffusion range 68 is formed by doping impurities (for example, a case where the semiconductor layer 13-3 is a p-type semiconductor, and an n-type impurity) in an active range of 19.
位元線用不純物擴散範圍71係加以設置於位置在第1溝21之上部與第2溝22之上部之間的活性範圍19。經由此，位元線用不純物擴散範圍71係加以配置於第2側壁部通道範圍64上。 The bit line is provided in an active range 19 between the upper portion of the first groove 21 and the upper portion of the second groove 22 by the impurity diffusion range 71. Thereby, the bit line is disposed on the second side wall portion channel range 64 by the impurity diffusion range 71.
位元線用不純物擴散範圍71係作為第1及第2單元電晶體25，27之共通的源極/汲極領域而發揮機能。位元線用不純物擴散範圍71上面71a係與SOI基板13之主面13a一致。 The bit line diffusion function range 71 functions as a common source/drain region of the first and second unit transistors 25 and 27. The position line 71a of the impurity line diffusion range 71 coincides with the main surface 13a of the SOI substrate 13.
位元線用不純物擴散範圍71係由摻雜不純物(例如，半導體層13-3為p型半導體之情況，n型不純物)於活性範圍19者而加以形成之範圍。 The bit line impurity diffusion range 71 is formed by doping impurities (for example, the case where the semiconductor layer 13-3 is a p-type semiconductor, n-type impurity) in the active range of 19.
第2單元電晶體27(選擇電晶體)係對於複數之活性範圍19各加以設置1個。 The second unit transistor 27 (selective transistor) is provided for each of the plurality of active ranges 19 .
第2單元電晶體27係具有：第2閘極絕緣膜59-2，和第2閘極電極74，和第2側壁部通道範圍64，和第3側壁部通道範圍76，和第2底部通道範圍77，和位元線用不純物擴散範圍71，和第2電容用不純物擴散範圍78。 The second unit transistor 27 has a second gate insulating film 59-2, a second gate electrode 74, and a second side wall channel range 64, and a third side wall channel range 76, and a second bottom channel. The range 77, and the bit line use the impurity diffusion range 71, and the second capacitance use impurity diffusion range 78.
第2閘極絕緣膜59-2係呈被覆第2溝22內 面地加以設置以外係與先前說明之第1閘極絕緣膜59-1同樣地加以構成。 The second gate insulating film 59-2 is covered in the second trench 22 The surface is provided in the same manner as the first gate insulating film 59-1 described above.
第2閘極電極74係藉由第2閘極絕緣膜59-2，呈埋入第2溝22之下部地加以設置。作為第2閘極電極74之材料，係可使用與先前說明之第1閘極電極61之材料同樣的材料者。 The second gate electrode 74 is provided by being buried in the lower portion of the second trench 22 by the second gate insulating film 59-2. As the material of the second gate electrode 74, the same material as that of the first gate electrode 61 described above can be used.
對於參照圖3及圖4，第3側壁部通道範圍76係經由位置在第2溝22之側面22c(與X方向交叉(第1實施形態之情況，正交)之側面)，和第2元件分離範圍17之間的活性範圍19(半導體層13-3)而加以構成。 Referring to FIGS. 3 and 4, the third side wall portion passage range 76 passes through the side surface 22c of the second groove 22 (the side surface intersecting the X direction (the case where the first embodiment is orthogonal)), and the second element. The active range 19 (semiconductor layer 13-3) between the ranges 17 is separated and configured.
接著，參照圖3，圖4，及圖6，對於第2底部通道範圍77加以說明。 Next, the second bottom channel range 77 will be described with reference to FIGS. 3, 4, and 6.
第2底部通道範圍77係經由加以配置於第2溝22之底面22a與絕緣層13-2之一面13-2a之間的活性範圍19而加以構成。 The second bottom passage region 77 is configured by being disposed in the active range 19 between the bottom surface 22a of the second groove 22 and one surface 13-2a of the insulating layer 13-2.
第2底部通道範圍77之側面77a，77b(2個側面)係在Y方向加以對向配置之同時，與第1元件分離範圍14接觸。另外，第2底部通道範圍77之上面77c係與第2閘極絕緣膜59-2接觸。 The side faces 77a and 77b (two side faces) of the second bottom channel range 77 are opposed to each other in the Y direction, and are in contact with the first element separation range 14. Further, the upper surface 77c of the second bottom passage region 77 is in contact with the second gate insulating film 59-2.
第2底部通道範圍77係具有加以配置於X方向之端部77A，77B(2個端部)。端部77A(一方的端部)係與第2側壁部通道範圍64加以連接(一體化)。端部77B係與第3側壁部通道範圍76加以連接(一體化)。 The second bottom channel range 77 has end portions 77A and 77B (two end portions) arranged in the X direction. The end portion 77A (one end portion) is connected (integrated) to the second side wall portion passage range 64. The end portion 77B is connected (integrated) to the third side wall portion passage range 76.
經由此，第2側壁部通道範圍64，第3側壁部通道 範圍76，及第2底部通道範圍77係構成從第2電容用不純物擴散範圍78連續至位元線用不純物擴散範圍71為止之通道。 Thereby, the second side wall passage range 64, the third side wall passage The range 76 and the second bottom channel range 77 constitute a channel from the second capacitance impurity diffusion range 78 to the bit line impurity diffusion range 71.
第2底部通道範圍77係具有平行於半導體基板主體13-1之一面13-1a的上面77c及下面77d的平板狀通道範圍。 The second bottom channel range 77 has a flat channel range parallel to the upper surface 77c and the lower surface 77d of one surface 13-1a of the semiconductor substrate main body 13-1.
第2底部通道範圍77之厚度M3(在對於半導體基板主體13-1之一面13-1a而言正交之方向的厚度)係設定在半導體層13-3之厚度M1的1/20~1/5之範圍內者為佳，而更理想為適宜設定在半導體層13-3之厚度M1的1/15~1/10之範圍內者為佳。 The thickness M3 of the second bottom channel range 77 (the thickness in the direction orthogonal to the one surface 13-1a of the semiconductor substrate main body 13-1) is set at 1/20 to 1/ of the thickness M1 of the semiconductor layer 13-3. A range of 5 is preferable, and more preferably, it is preferably set within a range of 1/15 to 1/10 of the thickness M1 of the semiconductor layer 13-3.
第2底部通道範圍77之厚度M3係例如，可作為與第1底部通道範圍66之厚度M2相同之厚度者。 The thickness M3 of the second bottom passage range 77 can be, for example, the same thickness as the thickness M2 of the first bottom passage range 66.
另外，第2底部通道範圍77之寬度W2係呈與第1底部通道範圍66之寬度W1相等地加以構成。 Further, the width W2 of the second bottom passage region 77 is configured to be equal to the width W1 of the first bottom passage region 66.
對於參照圖2~圖4，第2電容用不純物擴散範圍78係加以設置於位置在第2元件分離範圍17上部與第2溝22上部之間的活性範圍19。經由此，第2電容用不純物擴散範圍78係加以配置於第3側壁部通道範圍76上。 Referring to FIGS. 2 to 4, the second capacitance impurity diffusion range 78 is provided at an active range 19 between the upper portion of the second element separation range 17 and the upper portion of the second groove 22. Thereby, the second capacitance diffusion range 78 is placed on the third side wall passage region 76.
第2電容用不純物擴散範圍78係作為源極/汲極領域而發揮機能。第2電容用不純物擴散範圍78之上面78a係與SOI基板13之主面13a一致。 The second capacitance diffusion type range 78 functions as a source/drainage field. The upper surface 78a of the second capacitance impurity diffusion range 78 coincides with the main surface 13a of the SOI substrate 13.
第2電容用不純物擴散範圍78係由摻雜不純物(例 如，半導體層13-3為p型半導體之情況，n型不純物)於活性範圍19者而加以形成之範圍。 The second capacitor uses an impurity diffusion range of 78 to be doped with impurities (for example) For example, in the case where the semiconductor layer 13-3 is a p-type semiconductor, the n-type impurity is formed in the range of the active range of 19.
第1層間絕緣膜29係加以設置於第1及第2元件分離範圍14，17上。作為第1層間絕緣膜29係例如，可使用厚度為20nm之矽氮化膜(SiN膜)者。 The first interlayer insulating film 29 is provided on the first and second element separation ranges 14, 17. As the first interlayer insulating film 29, for example, a tantalum nitride film (SiN film) having a thickness of 20 nm can be used.
第1層間絕緣膜29係由加以圖案化者，經由向異性乾蝕刻，作為形成第2元件分離用溝17-1於半導體層13-3時之蝕刻光罩而發揮機能。 The first interlayer insulating film 29 is patterned by being subjected to an isotropic dry etching to function as an etching mask for forming the second element isolation trench 17-1 in the semiconductor layer 13-3.
埋入絕緣膜32係呈埋入第1溝21，22上部地加以配置。經由此，第1及第2閘極電極61，74之上面係由埋入絕緣膜32加以被覆。 The buried insulating film 32 is placed in the upper portion of the first trenches 21 and 22, and is disposed. Thereby, the upper surfaces of the first and second gate electrodes 61, 74 are covered by the buried insulating film 32.
埋入絕緣膜32之上面係對於第1層間絕緣膜29之上面作為拉平。作為埋入絕緣膜32係例如，可使用矽氧化膜(SiO2膜)者。 The upper surface of the buried insulating film 32 is flattened on the upper surface of the first interlayer insulating film 29. As the buried insulating film 32, for example, a tantalum oxide film (SiO 2 film) can be used.
位元線接觸開口部33係加以設置於位元線用不純物擴散範圍71上，露出位元線用不純物擴散範圍71之上面71a。 The bit line contact opening portion 33 is provided on the bit line impurity diffusion range 71 to expose the upper surface 71a of the bit line impurity diffusion range 71.
位元線接觸開口部33經由向異性乾蝕刻之時，由除去位置於位元線用不純物擴散範圍71上之第1層間絕緣膜29者而加以形成之開口部。 When the bit line contact opening portion 33 is dry-etched by the opposite polarity, the opening portion formed by removing the first interlayer insulating film 29 on the impurity line diffusion range 71 of the bit line is removed.
位元線接觸塞35係呈充填位元線接觸開口部33地加以設置。經由此，位元線接觸塞35之下端係與位元線用不純物擴散範圍71之上面71a接觸。 The bit line contact plug 35 is provided to fill the bit line contact opening portion 33. Thereby, the lower end of the bit line contact plug 35 is in contact with the upper line 71a of the impurity diffusion range 71 with the bit line.
位元線接觸塞35係例如，可經由多結晶矽膜而構成 者。 The bit line contact plug 35 is, for example, formed by a polycrystalline germanium film By.
參照圖2及圖4，位元線37係加以設置於第1層間絕緣膜29上。位元線37之下端則與位元線接觸塞35加以作為一體。經由此，位元線37係藉由位元線接觸塞35而與位元線用不純物擴散範圍71加以電性連接。 Referring to FIGS. 2 and 4, the bit line 37 is provided on the first interlayer insulating film 29. The lower end of the bit line 37 is integrated with the bit line contact plug 35. Thus, the bit line 37 is electrically connected to the bit line by the impurity diffusion range 71 by the bit line contact plug 35.
如圖1所示，位元線37之形狀係作為蛇圖案。該蛇圖案係指呈與排列於X方向之位元線接觸塞35之上端加以連接地，交互具有構成與X方向某角度θ之第3方向(V方向)，和與X方向某角度-θ之第4方向(W方向)之傾斜，在第1元件分離範圍14之上方沿著X方向而蛇行的圖案者。 As shown in FIG. 1, the shape of the bit line 37 is a snake pattern. The serpentine pattern is connected to the upper end of the contact line plug 35 arranged in the X direction, and has a third direction (V direction) constituting an angle θ with respect to the X direction, and an angle θ with the X direction. The inclination of the fourth direction (W direction) is a pattern that is meandering in the X direction above the first element separation range 14.
作為構成位元線37的膜係例如，可使用依序層積氮化鈦膜，及鎢膜之層積膜，或氮化鈦膜等者。 As the film constituting the bit line 37, for example, a titanium nitride film in this order, a laminated film of a tungsten film, or a titanium nitride film can be used.
對於參照圖2及圖4，間隙絕緣膜39係呈被覆位元線37之上面地加以設置。間隙絕緣膜39係保護位元線37之上面的同時，作為經由向異性蝕刻(具體而言係乾蝕刻)而圖案化成為位元線37之母材時之蝕刻光罩而發揮機能。 Referring to FIGS. 2 and 4, the gap insulating film 39 is provided on the upper surface of the covered bit line 37. The gap insulating film 39 protects the upper surface of the bit line 37 and functions as an etching mask when patterned into a base material of the bit line 37 by anisotropic etching (specifically, dry etching).
作為間隙絕緣膜39係例如，可使用矽氮化膜(SiN膜)者。 As the gap insulating film 39, for example, a tantalum nitride film (SiN film) can be used.
第1側壁膜41係呈被覆位元線37之側面，及間隙絕緣膜39之側面地加以設置。 The first side wall film 41 is provided on the side surface of the covered bit line 37 and on the side surface of the gap insulating film 39.
第2側壁膜42係呈被覆第1側壁膜41之外壁面地加以設置。作為第1及第2側壁膜41，42係例如，可使用 矽氮化膜(SiN膜)者。 The second side wall film 42 is provided to cover the outer wall surface of the first side wall film 41. As the first and second side wall films 41, 42 can be used, for example, Niobium nitride film (SiN film).
第2層間絕緣膜44係藉由第1及第2側壁膜41，42，呈埋入位元線37間的空間地加以設置於第1層間絕緣膜29上。第2層間絕緣膜44之上面係加以作為對於間隙絕緣膜39之上面。 The second interlayer insulating film 44 is provided on the first interlayer insulating film 29 by the first and second sidewall films 41 and 42 so as to be buried in the space between the bit lines 37. The upper surface of the second interlayer insulating film 44 is applied as the upper surface of the gap insulating film 39.
作為第2層間絕緣膜44係例如，可使用經由CVD(Chemical Vapor Deposition)法加以形成之矽氧化膜(SiO2膜)，或經由SOG(Spin On Glass)法而加以形成之塗佈系統的絕緣膜(矽氧化膜(SiO2膜))等者。 As the second interlayer insulating film 44, for example, a tantalum oxide film (SiO 2 film) formed by a CVD (Chemical Vapor Deposition) method or an insulating layer formed by a SOG (Spin On Glass) method can be used. Film (tantalum oxide film (SiO 2 film)) and the like.
第1電容接觸孔45-1係呈露出第1電容用不純物擴散範圍68之上面68a地形成於第1層間絕緣膜29，埋入絕緣膜32，及第2層間絕緣膜44。 The first capacitor contact hole 45-1 is formed in the first interlayer insulating film 29 so as to expose the upper surface 68a of the impurity diffusion range 68 of the first capacitor, and the buried insulating film 32 and the second interlayer insulating film 44 are buried.
第2電容接觸孔45-2係呈露出第2電容用不純物擴散範圍78之上面78a地形成於第1層間絕緣膜29，埋入絕緣膜32，及第2層間絕緣膜44。 The second capacitor contact hole 45-2 is formed on the first interlayer insulating film 29, the buried insulating film 32, and the second interlayer insulating film 44 so as to expose the upper surface 78a of the second capacitance impurity diffusion range 78.
第1電容接觸塞46-1係呈埋入第1電容接觸孔45-1地加以設置。第1電容接觸塞46-1之下端係與第1電容用不純物擴散範圍68之上面68a接觸。 The first capacitor contact plug 46-1 is provided to be buried in the first capacitor contact hole 45-1. The lower end of the first capacitor contact plug 46-1 is in contact with the upper surface 68a of the impurity diffusion range 68 of the first capacitor.
經由此，第1電容接觸塞46-1係與第1電容用不純物擴散範圍68加以電性連接。第1電容接觸塞46-1之上面係對於第2層間絕緣膜44之上面而言作為拉平。第1電容接觸塞46-1係例如，可作為依序層積氮化鈦膜，和鎢膜之層積構造者。 Thereby, the first capacitor contact plug 46-1 is electrically connected to the first capacitor impurity diffusion range 68. The upper surface of the first capacitor contact plug 46-1 is flattened on the upper surface of the second interlayer insulating film 44. The first capacitor contact plug 46-1 is, for example, a laminated structure of a titanium nitride film in this order and a tungsten film.
第2電容接觸塞46-2係呈埋入第2電容接觸 孔45-2地加以設置。第2電容接觸塞46-2之下端係與第2電容用不純物擴散範圍78之上面78a接觸。 The second capacitor contact plug 46-2 is buried in the second capacitor contact The holes 45-2 are provided. The lower end of the second capacitor contact plug 46-2 is in contact with the upper surface 78a of the impurity diffusion range 78 of the second capacitor.
經由此，第2電容接觸塞46-2係與第2電容用不純物擴散範圍78加以電性連接。第2電容接觸塞46-2之上面係對於第2層間絕緣膜44之上面而言作為拉平。第2電容接觸塞46-2係例如，可作為依序層積氮化鈦膜，和鎢膜之層積構造者。 Thereby, the second capacitor contact plug 46-2 is electrically connected to the second capacitor impurity diffusion range 78. The upper surface of the second capacitor contact plug 46-2 is flattened on the upper surface of the second interlayer insulating film 44. The second capacitor contact plug 46-2 is, for example, a laminated structure of a titanium nitride film in this order and a tungsten film.
對於參照圖2，停止膜48係加以設置於間隙絕緣膜39之上面，及第2層間絕緣膜44之上面。停止膜48係具有保護加以配置於下層的元件(例如，第1及第2單元電晶體25，27)之機能。 Referring to Fig. 2, a stopper film 48 is provided on the upper surface of the gap insulating film 39 and on the upper surface of the second interlayer insulating film 44. The stop film 48 has a function of protecting elements disposed in the lower layer (for example, the first and second unit transistors 25, 27).
作為停止膜48係例如，可使用矽氮化膜(SiN膜)者。 As the stopper film 48, for example, a tantalum nitride film (SiN film) can be used.
第3層間絕緣膜49係加以設置於停止膜48上。作為第3層間絕緣膜49係例如，可使用矽氧化膜(SiO2膜)者。 The third interlayer insulating film 49 is provided on the stopper film 48. As the third interlayer insulating film 49, for example, a tantalum oxide film (SiO 2 film) can be used.
缸孔51係呈貫通位置在第1電容接觸塞46-1上，及第2電容接觸塞46-2上之停止膜48及第3層間絕緣膜49地加以設置。 The cylinder bore 51 is provided in a through position at the first capacitor contact plug 46-1, and the stop film 48 and the third interlayer insulating film 49 on the second capacitor contact plug 46-2.
加以配置於第1電容接觸塞46-1上之缸孔51係露出第1電容接觸塞46-1之上面。加以配置於第2電容接觸塞46-2上之缸孔51係露出第2電容接觸塞46-2之上面。 The cylinder hole 51 disposed in the first capacitor contact plug 46-1 exposes the upper surface of the first capacitor contact plug 46-1. The cylinder hole 51 disposed in the second capacitor contact plug 46-2 exposes the upper surface of the second capacitor contact plug 46-2.
電容器53係對於第1及第2電容接觸塞46-1，46-2而言各加以設置1個。1個電容器53係具有：1 個下部電極84，和對於複數之下部電極84而言共通之電容絕緣膜85，和對於複數之下部電極84而言為共通的電極之上部電極86。 The capacitor 53 is provided for each of the first and second capacitive contact plugs 46-1 and 46-2. 1 capacitor 53 has: 1 The lower electrode 84, and the capacitor insulating film 85 common to the plurality of lower electrodes 84, and the electrode upper electrode 86 common to the plurality of lower electrodes 84.
下部電極84係作為王冠形狀，各加以設置於第1及第2電容接觸塞46-1，46-2上。 The lower electrodes 84 are formed in a crown shape, and are provided on the first and second capacitor contact plugs 46-1 and 46-2, respectively.
經由此，加以配置於第1電容接觸塞46-1上之下部電極84係藉由第1電容接觸塞46-1，而與第1電容用不純物擴散範圍68加以電性連接。 Thereby, the lower electrode 84 disposed on the first capacitor contact plug 46-1 is electrically connected to the first capacitor impurity diffusion range 68 by the first capacitor contact plug 46-1.
另外，加以配置於第2電容接觸塞46-2上之下部電極84係藉由第2電容接觸塞46-2，而與第2電容用不純物擴散範圍78加以電性連接。 Further, the lower electrode 84 disposed on the second capacitor contact plug 46-2 is electrically connected to the second capacitor impurity diffusion range 78 by the second capacitor contact plug 46-2.
電容絕緣膜85係呈被覆下部電極84之表面，及第3層間絕緣膜49之上面地加以配置。電容絕緣膜85係作為未埋入缸孔51之厚度。 The capacitor insulating film 85 is disposed so as to cover the surface of the lower electrode 84 and the upper surface of the third interlayer insulating film 49. The capacitor insulating film 85 is formed to have a thickness that is not buried in the cylinder bore 51.
上部電極86係呈被覆電容絕緣膜85表面地加以設置。上部電極86係呈埋入形成有電容絕緣膜85之下部電極84的內部地加以配置。上部電極86之上面係加以配置於較複數之下部電極84上端為上方。 The upper electrode 86 is provided to cover the surface of the capacitor insulating film 85. The upper electrode 86 is disposed so as to be buried inside the electrode 84 on the lower surface of which the capacitor insulating film 85 is formed. The upper surface of the upper electrode 86 is disposed above the upper end of the plurality of lower electrodes 84.
在記憶體單元部11中，1個單元係由1個單元電晶體(第1單元電晶體25，或第2單元電晶體27)，和1個電容器53而加以構成。因而，對於1個活性範圍19係加以設置有2個單元。具體而言，2個單元係第1單元電晶體25與電容器53所成之單元，和第2單元電晶體27與電容器53所成之單元。 In the memory cell unit 11, one cell is constituted by one cell transistor (first cell transistor 25 or second cell transistor 27) and one capacitor 53. Therefore, two units of one active range 19 are provided. Specifically, the two cells are a unit formed by the first unit transistor 25 and the capacitor 53, and a unit formed by the second unit transistor 27 and the capacitor 53.
第4層間絕緣膜55係呈被覆上部電極膜86之上面地加以設置。作為第4層間絕緣膜55係例如，可使用矽氧化膜(SiO2膜)者。 The fourth interlayer insulating film 55 is provided to cover the upper surface of the upper electrode film 86. As the fourth interlayer insulating film 55, for example, a tantalum oxide film (SiO 2 film) can be used.
然而，雖未圖示，但亦可設置貫通第4層間絕緣膜55，下端則與上部電極86加以連接的貫孔。另外，於第4層間絕緣膜55上，亦可設置與該貫孔的上端加以連接之未圖示的配線。 However, although not shown, a through hole penetrating the fourth interlayer insulating film 55 and connecting the lower end to the upper electrode 86 may be provided. Further, a wiring (not shown) connected to the upper end of the through hole may be provided on the fourth interlayer insulating film 55.
保護膜57係加以設置於第4層間絕緣膜55上。保護膜57係於第4層間絕緣膜55上設置未圖示之配線的情況，具有保護該配線之機能。 The protective film 57 is provided on the fourth interlayer insulating film 55. The protective film 57 is provided with a wiring (not shown) provided on the fourth interlayer insulating film 55, and has a function of protecting the wiring.
第1實施形態之半導體裝置係具有：第1單元電晶體25，和第2單元電晶體27。第1單元電晶體25係包含：經由位置在第1溝21與第2元件分離範圍17之間的活性範圍19而加以構成之第1側壁部通道範圍63，和加以配置於第1側壁部通道範圍63上之第1電容用不純物擴散範圍68，和經由位置於第1及第2溝21，22間之活性範圍19而加以構成之第2側壁部通道範圍64，和加以配置於第2側壁部通道範圍64上之位元線用不純物擴散範圍71，和經由加以配置於第1溝21之底面21a與絕緣層13-2之間的活性範圍19而加以構成之第1底部通道範圍66。第2單元電晶體27係包含：經由位置在第2溝22與第2元件分離範圍17之間的活性範圍19而加以構成之第3側壁部通道範圍76，和加以配置於第3側壁部通道範圍76上部之第2電容用不純物擴散範圍78，和 第2側壁部通道範圍64，和位元線用不純物擴散範圍71，和經由加以配置於第2溝22之底面22a與絕緣層13-2之間的活性範圍19而加以構成之第2底部通道範圍77。第2單元電晶體27係加以設置於與第1單元電晶體25同一之活性範圍19。由加深第1及第2溝21，22之深度者，加以配置於第1及第2溝21，22之底面與絕緣層之間的半導體層13-3(換言之，第1及第2底部通道範圍66，77)之厚度則變小。隨之，成為可縮小成為電荷的通路之第1及第2底部通道範圍66，77的剖面積者。 The semiconductor device of the first embodiment includes a first unit transistor 25 and a second unit transistor 27. The first unit transistor 25 includes a first side wall passage region 63 configured to pass through an active range 19 between the first groove 21 and the second element separation range 17, and is disposed in the first side wall passage. The first capacitor impurity range 68 in the range 63 and the second side wall channel range 64 formed via the active range 19 between the first and second trenches 21 and 22, and disposed on the second sidewall The bit line on the channel portion 64 has an impurity diffusion range 71 and a first bottom channel range 66 which is formed via an active range 19 disposed between the bottom surface 21a of the first trench 21 and the insulating layer 13-2. The second unit transistor 27 includes a third side wall passage region 76 configured to pass through an active range 19 between the second groove 22 and the second element separation range 17, and is disposed in the third side wall passage. The second capacitor of the upper portion of the range 76 uses the impurity diffusion range 78, and The second side wall portion channel range 64, and the bit line impurity diffusion range 71, and the second bottom channel formed by the active range 19 disposed between the bottom surface 22a of the second groove 22 and the insulating layer 13-2 Range 77. The second unit transistor 27 is provided in the same active range 19 as the first unit transistor 25. The semiconductor layer 13-3 disposed between the bottom surface of the first and second trenches 21, 22 and the insulating layer is formed by deepening the depths of the first and second trenches 21, 22 (in other words, the first and second bottom channels) The thickness of the range 66, 77) becomes smaller. Accordingly, the cross-sectional area of the first and second bottom channel ranges 66, 77 which can reduce the path of the electric charge can be reduced.
經由此，成為可限制歷經第1及第2底部通道範圍66，77之浮遊電子(e-)的移動(換言之，歷經第1及第2底部通道範圍66，77之浮遊電子的流通)者。隨之可抑制干擾不良者。 Thereby, it is possible to restrict the movement of the floating electrons (e - ) passing through the first and second bottom channel ranges 66, 77 (in other words, the flow of the floating electrons through the first and second bottom channel ranges 66, 77). This can suppress the interference.
先前說明之圖23所示的構造情況，未包含有限制電荷的通路之構造。因此，在第1電晶體206產生的浮遊電子係具有以任何路徑到達至鄰接單元之第2電容接觸塞215的可能性。 The configuration shown in Fig. 23 described earlier does not include the configuration of the path for limiting the charge. Therefore, the floating electrons generated in the first transistor 206 have the possibility of reaching the second capacitor contact plug 215 of the adjacent cell in any path.
另一方面，在第1實施形態之半導體裝置10(具體而言，係記憶體單元部11)之構成中，經由第1及第2底部通道範圍66，77而加以限制電荷的路徑。因此，可使電子到達至鄰接單元之電容接觸塞(第1電容接觸塞46-1或第2電容接觸塞46-2)之機率，減少為1/10~1/100程度者。 On the other hand, in the configuration of the semiconductor device 10 (specifically, the memory cell unit 11) of the first embodiment, the path for limiting the electric charge is limited via the first and second bottom channel ranges 66, 77. Therefore, the probability of the electrons reaching the capacitance contact plug (the first capacitor contact plug 46-1 or the second capacitor contact plug 46-2) of the adjacent unit can be reduced to the range of 1/10 to 1/100.
例如，在將與第2單元電晶體27加以電性連 接之第2電容接觸塞46-2作為「High」而將第2單元電晶體27保持成關閉的狀態，反覆第1單元電晶體25之開啟/關閉。此情況，即使於位置在位元線用不純物擴散範圍71下方之活性範圍19產生有浮遊電子，位置在第2單元電晶體27之第2溝22下方之第2底部通道範圍77的剖面積為小之情況亦成為障礙。隨之，電荷可流通的機率係變為極小。 For example, it will be electrically connected to the second unit transistor 27. The second capacitor contact plug 46-2 is connected to the second unit transistor 27 in a state of being "High", and the first unit transistor 25 is turned on/off. In this case, even if the floating electrons are generated in the active range 19 below the bit line diffusion region 71, the second bottom channel region 77 below the second trench 22 of the second cell transistor 27 has a sectional area of Small situations have also become obstacles. As a result, the probability of charge flow can be minimized.
另外，對於產生有浮遊電子於位置在第1電容用不純物擴散範圍68下方的活性範圍19之情況，係位置在第1及第2溝21，22下方之第1及第2底部通道範圍66，77則作為電荷流通的障礙而發揮機能。因此，浮遊電子到達至第2電容接觸塞46-2之機率係變為更小。 Further, in the case where the floating electrons are generated in the active range 19 below the first capacitance impurity diffusion range 68, the first and second bottom channel ranges 66 below the first and second grooves 21, 22 are located. 77 functions as an obstacle to the circulation of electric charge. Therefore, the probability that the floating electrons reach the second capacitance contact plug 46-2 becomes smaller.
隨之，第1實施形態之半導體裝置10係可抑制配置於同一活性範圍19內之2個單元間之干擾不良者。 According to the semiconductor device 10 of the first embodiment, it is possible to suppress interference between two cells disposed in the same active range 19.
另外，經由薄膜化第1及第2底部通道範圍66，77之厚度M2，M3之時，在單元電晶體(第1單元電晶體25或第2單元電晶體27)之動作時，成為可使第1及第2底部通道範圍66，77完全空乏化者。 Further, when the thicknesses M2 and M3 of the first and second bottom channel ranges 66 and 77 are thinned, the operation of the unit cell (the first cell transistor 25 or the second cell transistor 27) can be performed. The first and second bottom channel ranges 66, 77 are completely empty.
如此，由第1及第2單元電晶體25，27具有完全空乏化型之通道構造者，可使經由第1及第2閘極電極61，74之第1及第2單元電晶體25，27之臨界值控制特性提升者。 As described above, the first and second unit transistors 25 and 27 have a completely depleted channel structure, and the first and second unit transistors 25 and 27 passing through the first and second gate electrodes 61 and 74 can be used. The threshold value control feature enhancer.
圖7係擴大有關本發明之第1實施形態的變形例之半導體裝置之記憶體單元部之中，與第1實施形態 之半導體裝置不同之部分的剖面圖。圖7係對應於圖5之剖面圖。在圖7中，對於與圖5所示之構造體同一構成部分係附上同一符號。 FIG. 7 is a view showing a first embodiment of the memory cell unit of the semiconductor device according to the modification of the first embodiment of the present invention. A cross-sectional view of a different portion of a semiconductor device. Figure 7 is a cross-sectional view corresponding to Figure 5. In FIG. 7, the same components as those of the structure shown in FIG. 5 are denoted by the same reference numerals.
在此，參照圖7，對於有關第1實施形態之變形例的半導體裝置95的記憶體單元部96之主要部加以說明。 Here, the main part of the memory cell unit 96 of the semiconductor device 95 according to the modification of the first embodiment will be described with reference to FIG.
對於參照圖7，有關第1實施形態之變形例的半導體裝置95係第1閘極絕緣膜59-1則呈被覆第1底部通道範圍66之側面66a，66b地加以配置。藉由第1閘極絕緣膜59-1，加以對向配置第1底部通道範圍66之側面66a，66b與第1閘極電極61。 With reference to Fig. 7, the first gate insulating film 59-1 of the semiconductor device 95 according to the modification of the first embodiment is disposed so as to cover the side faces 66a and 66b of the first bottom channel region 66. The side faces 66a and 66b of the first bottom channel range 66 and the first gate electrode 61 are opposed to each other by the first gate insulating film 59-1.
另外，雖未圖示，但第2閘極絕緣膜59-2係呈被覆第2底部通道範圍77之側面77a，77b地加以配置。藉由第2閘極絕緣膜59-2，加以對向配置第2底部通道範圍77之側面77a，77b與第2閘極電極74。 Further, although not shown, the second gate insulating film 59-2 is disposed so as to cover the side faces 77a and 77b of the second bottom channel range 77. The side faces 77a, 77b and the second gate electrode 74 of the second bottom channel range 77 are opposed to each other by the second gate insulating film 59-2.
有關第1實施形態之變形例的半導體裝置95係上述說明之構成則與第1實施形態之半導體裝置100不同以外，係與半導體裝置10同樣地加以構成。 The semiconductor device 95 according to the modification of the first embodiment is configured similarly to the semiconductor device 10 except that the semiconductor device 100 of the first embodiment is different from the semiconductor device 100 of the first embodiment.
具有上述鞍狀翼片構造之半導體裝置95係可得到與第1實施形態之半導體裝置10同樣的效果者。 The semiconductor device 95 having the above-described saddle-shaped fin structure can obtain the same effects as those of the semiconductor device 10 of the first embodiment.
圖8~圖14係顯示本發明之第1實施形態之半導體裝置之製造工程的圖。具體而言，圖8係為了說明SOI基板之製造工程的剖面圖。圖9A係顯示製造途中之半導體裝置的記憶體單元部之平面圖。圖9B係圖9A所 示之構造體之A-A線方向的剖面圖。 8 to 14 are views showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention. Specifically, FIG. 8 is a cross-sectional view for explaining a manufacturing process of the SOI substrate. Fig. 9A is a plan view showing a memory cell portion of a semiconductor device in the middle of manufacturing. Figure 9B is Figure 9A A cross-sectional view of the structure shown in the A-A line direction.
圖10及圖11係顯示製造途中之半導體裝置的記憶體單元部之剖面圖。圖12A係顯示製造途中之半導體裝置的記憶體單元部之平面圖。圖12B係圖12A所示之構造體之A-A線方向的剖面圖。圖13及圖14係顯示製造途中之半導體裝置的記憶體單元部之剖面圖。 10 and 11 are cross-sectional views showing a memory cell unit of a semiconductor device in the middle of manufacturing. Fig. 12A is a plan view showing a memory cell unit of a semiconductor device in the middle of manufacturing. Fig. 12B is a cross-sectional view taken along the line A-A of the structure shown in Fig. 12A. 13 and 14 are cross-sectional views showing a memory cell unit of a semiconductor device in the middle of manufacturing.
接著，參照圖8~圖14，對於第1實施形態之半導體裝置10之記憶體單元部11的製造方法加以說明。 Next, a method of manufacturing the memory cell unit 11 of the semiconductor device 10 of the first embodiment will be described with reference to FIGS. 8 to 14.
首先，在圖8所示之工程中，準備半導體基板(例如，p型單結晶矽晶圓)。對於從該半導體基板之主面(SOI基板13之主面13a)特定的深度(例如，250~350nm)，經由離子注入法而注入氧。之後，加熱該半導體基板，形成絕緣層13-2(此情況，矽氧化膜(SiO2膜))。 First, in the process shown in FIG. 8, a semiconductor substrate (for example, a p-type single crystal germanium wafer) is prepared. Oxygen is injected through an ion implantation method from a specific depth (for example, 250 to 350 nm) of the main surface of the semiconductor substrate (main surface 13a of the SOI substrate 13). Thereafter, the semiconductor substrate is heated to form an insulating layer 13-2 (in this case, a tantalum oxide film (SiO 2 film)).
經由此，依序層積有位置於絕緣層13-2下方的上述半導體基板所成之半導體基板主體13-1，和絕緣層13-2，位置於絕緣層13-2上方之上述半導體基板所成之半導體層13-3之SOI基板13則加以形成。 Thus, the semiconductor substrate main body 13-1 formed of the semiconductor substrate under the insulating layer 13-2 and the insulating layer 13-2 are laminated in this order, and the semiconductor substrate is positioned above the insulating layer 13-2. The SOI substrate 13 of the semiconductor layer 13-3 is formed.
此時，半導體層13-3之厚度M1係例如，可作為300nm者。此情況，絕緣層13-2之厚度M4係例如，可作為10nm者。 At this time, the thickness M1 of the semiconductor layer 13-3 is, for example, 300 nm. In this case, the thickness M4 of the insulating layer 13-2 is, for example, 10 nm.
然而，亦可使用周知之所市售知SOI基板。 However, a commercially available SOI substrate known in the art can also be used.
以下，作為一例，舉例說明半導體基板主體13-1及半導體層13-3則由p型單結晶矽所成之情況。 Hereinafter, as an example, a case where the semiconductor substrate main body 13-1 and the semiconductor layer 13-3 are formed of a p-type single crystal germanium will be described as an example.
接著，在圖9A及圖9B所示的工程中，經由周知之手法(例如，STI(Shallow trench isolation)法)，形成延伸存在於SOI基板13之X方向，且到達至絕緣層13-2之一面13-2a的第1元件分離範圍14-1，和埋入第1元件分離範圍14-1之第1元件分離用絕緣膜14-2(例如，矽氧化膜(SiO2膜))所成之第1元件分離範圍14。 Next, in the process shown in FIG. 9A and FIG. 9B, a well-known method (for example, STI (Shallow trench isolation) method) is formed to extend in the X direction of the SOI substrate 13 and reach the insulating layer 13-2. The first element isolation range 14-1 of the one surface 13-2a and the first element isolation insulating film 14-2 (for example, a tantalum oxide film (SiO 2 film)) embedded in the first element isolation range 14-1 are formed. The first element is separated by a range of 14.
此時，第1元件分離範圍14係複數形成於Y方向。另外，複數之第1元件分離範圍14係其上面則對於SOI基板13之主面13a而言呈拉平地形成。 At this time, the first element separation range 14 is formed in plural in the Y direction. Further, the plurality of first element separation ranges 14 are formed on the upper surface of the SOI substrate 13 in a flat manner.
接著，經由與第1元件分離範圍14同樣的形成方法，形成延伸存在於形成有第1元件分離範圍14之SOI基板13之Y方向，且到達至絕緣層13-2之一面13-2a之第2元件分離範圍17-1，和埋入第2元件分離範圍17-1之第2元件分離用絕緣膜17-2(例如，矽氧化膜(SiO2膜))所成之第2元件分離範圍17。 Then, by the formation method similar to the first element isolation range 14, the Y direction extending in the SOI substrate 13 in which the first element isolation range 14 is formed is formed, and the first surface 13-2a of the insulating layer 13-2 is formed. 2 element separation range 17-1, and a second element separation range formed by the second element isolation insulating film 17-2 (for example, a tantalum oxide film (SiO 2 film)) embedded in the second element isolation range 17-1 17.
此時，第2元件分離範圍17係複數形成於X方向。另外，複數之第2元件分離範圍17係其上面則對於SOI基板13之主面13a而言呈拉平地形成。 At this time, the second element separation range 17 is formed in plural in the X direction. Further, the plurality of second element separation ranges 17 are formed on the upper surface of the SOI substrate 13 in a flat manner.
經由此，加以複數形成由第1及第2元件分離範圍14，17所區劃，且半導體層13-3所成之活性範圍19。Y方向之活性範圍19的寬度W3係例如，可作為40nm者。 Thereby, the plural range is formed by the first and second element separation ranges 14, 17 and the active range 19 of the semiconductor layer 13-3. The width W3 of the active range 19 in the Y direction is, for example, 40 nm.
接著，經由離子注入法，由注入n型不純物於複數之活性範圍19之上面19a(SOI基板13之主面13a)者，形成不純物擴散層98於複數之活性範圍19上部。 Next, the impurity diffusion layer 98 is formed on the upper portion of the plurality of active ranges 19 by the ion implantation method by implanting the n-type impurity on the upper surface 19a of the complex active range 19 (the main surface 13a of the SOI substrate 13).
不純物擴散層98係由加以分割之情況，成為圖2所示之第1電容用不純物擴散範圍68，位元線用不純物擴散範圍71，及第2電容用不純物擴散範圍78。 The impurity diffusion layer 98 is divided into the impurity diffusion range 68 of the first capacitance shown in FIG. 2, the impurity diffusion range 71 for the bit line, and the impurity diffusion range 78 for the second capacitance.
接著，在圖10所示之工程中，經由周知的手法，形成被覆圖9A及圖9B所示之構造體上(具體而言，第1元件分離範圍14之上面，第2元件分離範圍17之上面，及活性範圍19之上面19a)的第1層間絕緣膜29。 Next, in the process shown in FIG. 10, the structure shown in FIG. 9A and FIG. 9B is formed by a well-known technique (specifically, the upper surface of the first element separation range 14 and the second element separation range 17 are formed. Above, and the first interlayer insulating film 29 of the upper surface 19a) of the active range 19.
具體而言，例如，由將作為40nm之厚度之矽氮化膜(SiN膜)成膜者，形成該矽氮化膜(SiN膜)所成之第1層間絕緣膜29。 Specifically, for example, a first interlayer insulating film 29 made of the tantalum nitride film (SiN film) is formed by forming a tantalum nitride film (SiN film) having a thickness of 40 nm.
接著，經由光微影技術及乾蝕刻技術，由除 去對應於第1及第2溝21，22之形成範圍而言之第1層間絕緣膜29者，形成第1及第2開口溝29A，29B。 Then, by photolithography and dry etching, The first and second opening grooves 29A and 29B are formed in the first interlayer insulating film 29 corresponding to the range in which the first and second grooves 21 and 22 are formed.
此時，第1開口溝29A係呈對應於第1溝21之形成範圍地形成。另外，第2開口溝29B係呈對應於第2溝22之形成範圍地形成。 At this time, the first opening groove 29A is formed to correspond to the formation range of the first groove 21. Further, the second opening groove 29B is formed to correspond to the formation range of the second groove 22.
接著，經由將形成有第1及第2開口溝29A，29B之第1層間絕緣膜29作為蝕刻光罩之向異性乾蝕刻之時，由蝕刻複數之活性範圍19及第1元件分離範圍14者，形成作為未到達至絕緣層13-2之一面13-2a之深度的第1及第2溝21，22。 Next, when the first interlayer insulating film 29 on which the first and second opening grooves 29A and 29B are formed is dry-etched as an etching mask, the active range 19 and the first element separation range 14 are etched. The first and second grooves 21, 22 which are not reached to the depth of one surface 13-2a of the insulating layer 13-2 are formed.
經由此，一括形成有加以配置於第1溝21之側面21b與第2元件分離範圍17之間的第1電容用不純物擴散範圍68，和加以配置於第1溝21與第2溝22之 間的位元線用不純物擴散範圍71，和加以配置於第2溝22之側面22c與第2元件分離範圍17之間的第2電容用不純物擴散範圍78，和加以配置於第1電容用不純物擴散範圍68與絕緣層13-2之間的第1側壁部通道範圍63，和加以配置於位元線用不純物擴散範圍71與絕緣層13-2之間的第2側壁部通道範圍64，和加以配置於第2電容用不純物擴散範圍78與絕緣層13-2之間的第3側壁部通道範圍76，和加以配置於第1溝21之底面21a與絕緣層13-2之間的第1底部通道範圍66，和加以配置於第2溝22之底面22a與絕緣層13-2之間的第2底部通道範圍77。 Thus, the first capacitance impurity diffusion range 68 disposed between the side surface 21b of the first trench 21 and the second element isolation range 17 is formed, and is disposed in the first trench 21 and the second trench 22; The impurity line diffusion range 71 between the bit lines and the second impurity diffusion range 78 disposed between the side surface 22c of the second trench 22 and the second element isolation range 17 and the impurities for the first capacitance are disposed. a first side wall passage range 63 between the diffusion range 68 and the insulating layer 13-2, and a second side wall passage range 64 disposed between the bit line impurity diffusion range 71 and the insulating layer 13-2, and The third side wall passage region 76 disposed between the second capacitor impurity diffusion range 78 and the insulating layer 13-2, and the first portion disposed between the bottom surface 21a of the first trench 21 and the insulating layer 13-2 The bottom channel range 66 and the second bottom channel range 77 disposed between the bottom surface 22a of the second trench 22 and the insulating layer 13-2.
此時，如在圖3所說明地，第1及第2溝21，22係第1及第2底部通道範圍66，77之厚度M2，M3則呈成為半導體層13-3之厚度M1的1/20~1/5之範圍內地形成。 At this time, as described with reference to FIG. 3, the first and second grooves 21, 22 are the first and second bottom channel ranges 66, 77, and the thickness M2, M3 is 1 which is the thickness M1 of the semiconductor layer 13-3. Formed within the range of /20~1/5.
更理想為第1及第2溝21，22係第1及第2底部通道範圍66，77之厚度M2，M3則呈成為半導體層13-3之厚度M1的1/15~1/10之範圍內地形成為佳。 More preferably, the first and second grooves 21, 22 are the first and second bottom channel ranges 66, 77, and the thickness M2, M3 is in the range of 1/15 to 1/10 of the thickness M1 of the semiconductor layer 13-3. The inner terrain is better.
具體而言，半導體層13-3之厚度M1為300nm之情況，第1及第2溝21，22係例如，第1及第2底部通道範圍66，77之厚度M2，M3則呈成為20~30nm之範圍內地形成為佳。 Specifically, the thickness M1 of the semiconductor layer 13-3 is 300 nm, and the first and second grooves 21 and 22 are, for example, the thicknesses M2 and M3 of the first and second bottom channel ranges 66, 77 are 20~ Terrain is better in the 30nm range.
如圖3所示，經由上述方法而加以形成之第1底部通道範圍66係具有平行於半導體基板主體13-1之一 面13-1a的上面66c及下面66d的平板狀通道範圍。配置於X方向之端部66A則與第1側壁部通道範圍63加以連接(一體化)。配置於X方向之端部66B則與第2側壁部通道範圍64加以連接(一體化)。 As shown in FIG. 3, the first bottom channel range 66 formed by the above method has one of parallel to the semiconductor substrate main body 13-1. The upper channel 66c of the face 13-1a and the flat channel range of the lower 66d. The end portion 66A disposed in the X direction is connected (integrated) to the first side wall portion passage range 63. The end portion 66B disposed in the X direction is connected (integrated) to the second side wall portion passage range 64.
另外，經由上述方法而加以形成之第2底部通道範圍77係具有平行於半導體基板主體13-1之一面13-1a的上面77c及下面77d的平板狀通道範圍。配置於X方向之端部77A則與第2側壁部通道範圍64加以連接(一體化)。配置於X方向之端部77B則與第3側壁部通道範圍76加以連接(一體化)。 Further, the second bottom channel range 77 formed by the above method has a flat channel range parallel to the upper surface 77c and the lower surface 77d of one surface 13-1a of the semiconductor substrate main body 13-1. The end portion 77A disposed in the X direction is connected (integrated) to the second side wall portion passage range 64. The end portion 77B disposed in the X direction is connected (integrated) to the third side wall portion passage range 76.
接著，經由周知的手法(例如，熱氧化法)，一括形成被覆第1溝21內面之第1閘極絕緣膜59-1(此情況，矽氧化膜(SiO2膜))，和被覆第2溝22內面之第2閘極絕緣膜59-2(此情況，矽氧化膜(SiO2膜))。 Then, a first gate insulating film 59-1 covering the inner surface of the first trench 21 (in this case, a tantalum oxide film (SiO 2 film)) and a coating layer are formed by a well-known method (for example, a thermal oxidation method). The second gate insulating film 59-2 on the inner surface of the trench 22 (in this case, a tantalum oxide film (SiO 2 film)).
接著，經由周知的手法，藉由第1閘極絕緣膜59-1，一括形成埋入第1溝21之下部的第1閘極電極61，和藉由第2閘極絕緣膜59-2，一括形成埋入第2溝22之下部的第2閘極電極74。 Then, the first gate insulating film 59-1 is formed by the first gate insulating film 59-1, and the first gate electrode 61 buried under the first trench 21 and the second gate insulating film 59-2 are formed by a known method. The second gate electrode 74 that is buried in the lower portion of the second trench 22 is formed.
具體而言，例如，作為埋入第1及第2溝21，22之導電膜，將氮化鈦膜(TiN膜)，和鎢膜(W膜)依序成膜之後，由回蝕該導電膜者，一括形成第1及第2閘極電極61，74。 Specifically, for example, as a conductive film in which the first and second trenches 21 and 22 are buried, a titanium nitride film (TiN film) and a tungsten film (W film) are sequentially formed, and then the conductive film is etched back. The film includes all of the first and second gate electrodes 61, 74.
經由此，對於1個活性範圍19而言，加以形成1個第1單元電晶體25，和1個第2單元電晶體27。 第1單元電晶體25係具有：第1閘極絕緣膜59-1，和第1閘極電極61，和第1側壁部通道範圍63，和第2側壁部通道範圍64，和第1底部通道範圍66，和第1電容用不純物擴散範圍68，和位元線用不純物擴散範圍71。第2單元電晶體27係具有：第2閘極絕緣膜59-2，和第2閘極電極74，和第2側壁部通道範圍64，和第3側壁部通道範圍76，和第2底部通道範圍77，和位元線用不純物擴散範圍71，和第2電容用不純物擴散範圍78。 Thus, for one active range 19, one first unit transistor 25 and one second unit transistor 27 are formed. The first unit transistor 25 has a first gate insulating film 59-1, a first gate electrode 61, and a first side wall portion channel range 63, and a second side wall portion channel range 64, and a first bottom channel. The range 66, and the first capacitor use the impurity diffusion range 68, and the bit line use the impurity diffusion range 71. The second unit transistor 27 has a second gate insulating film 59-2, a second gate electrode 74, and a second side wall channel range 64, and a third side wall channel range 76, and a second bottom channel. The range 77, and the bit line use the impurity diffusion range 71, and the second capacitance use impurity diffusion range 78.
接著，經由周知的手法，形成埋入第1及第2溝21，22之上部的埋入絕緣膜32。此時，埋入絕緣膜32係其上面則呈對於第1層間絕緣膜29之上面成為拉平地形成。 Next, the buried insulating film 32 embedded in the upper portions of the first and second trenches 21, 22 is formed by a well-known method. At this time, the buried insulating film 32 is formed on the upper surface of the first interlayer insulating film 29 to be flattened.
接著，經由光微影技術及乾蝕刻技術，由除去位置在位元線用不純物擴散範圍71上之第1層間絕緣膜29者，形成露出位元線用不純物擴散範圍71之上面71a的位元線接觸開口部33。 Then, by removing the first interlayer insulating film 29 on the impurity line diffusion range 71 of the bit line by the photolithography technique and the dry etching technique, a bit which exposes the upper surface 71a of the impurity diffusion range 71 of the bit line is formed. The line contacts the opening portion 33.
接著，經由周知的手法，充填位元線接觸開口部33，形成下端則與位元線用不純物擴散範圍71之上面71a加以連接之位元線接觸塞35。 Next, the bit line contact opening portion 33 is filled by a well-known technique, and the bit line contact plug 35 whose lower end is connected to the upper surface 71a of the bit line impurity diffusion range 71 is formed.
此時，位元線接觸塞35係其上面則呈對於埋入絕緣膜32之上面及第1層間絕緣膜29之上面成為拉平地形成。 At this time, the bit line contact plug 35 is formed on the upper surface of the buried insulating film 32 and the upper surface of the first interlayer insulating film 29 to be flattened.
作為構成位元線接觸塞35之導電膜係例如，可使用依序層積氮化鈦(TiN)膜，及鎢(W)膜之層積膜。 As the conductive film constituting the bit line contact plug 35, for example, a laminated film of a titanium nitride (TiN) film and a tungsten (W) film may be laminated in this order.
接著，在圖12A及圖12B所示之工程中，依序層積形成被覆圖11所示之構造體的上面之金屬膜101(例如，依序層積氮化鈦膜(TiN膜)，和鎢(W膜)之層積膜)，和矽氮化膜102。 Next, in the process shown in FIG. 12A and FIG. 12B, the metal film 101 covering the upper surface of the structure shown in FIG. 11 is sequentially laminated (for example, a titanium nitride film (TiN film) is sequentially laminated, and A laminated film of tungsten (W film), and a tantalum nitride film 102.
接著，經由光微影技術及乾蝕刻技術，由圖案化矽氮化膜102者，形成矽氮化膜102所成之間隙絕緣膜39。此時，間隙絕緣膜39係呈成為蛇圖案地形成。 Next, the gap insulating film 39 made of the tantalum nitride film 102 is formed by patterning the tantalum nitride film 102 by photolithography and dry etching. At this time, the gap insulating film 39 is formed in a serpentine pattern.
接著，經由將間隙絕緣膜39作為光罩之向異性乾蝕刻之時，由圖案化金屬膜101者，形成有將形狀作為蛇圖案，且金屬膜101所成之位元線37。 Next, when the gap insulating film 39 is dry-etched as a mask, the bit line 37 formed of the metal film 101 is formed by patterning the metal film 101.
位元線37之下端係與位元線接觸塞35加以連接。經由此，位元線37係藉由位元線接觸塞35而與位元線用不純物擴散範圍71加以電性連接。 The lower end of the bit line 37 is connected to the bit line contact plug 35. Thus, the bit line 37 is electrically connected to the bit line by the impurity diffusion range 71 by the bit line contact plug 35.
接著，經由周知的手法，依序形成被覆間隙絕緣膜39之側面，及位元線37之側面的第1側壁膜41，和第2側壁膜42。 Next, the side surface covering the gap insulating film 39, the first side wall film 41 on the side surface of the bit line 37, and the second side wall film 42 are sequentially formed by a well-known method.
接著，在圖13所示之工程中，經由周知的手法，於第1層間絕緣膜29上，藉由第1及第2側壁膜41，42而形成埋入位元線37間的空間之第2層間絕緣膜44。 Next, in the process shown in FIG. 13, the space between the buried bit lines 37 is formed by the first and second side wall films 41, 42 on the first interlayer insulating film 29 by a well-known method. 2 interlayer insulating film 44.
此時，第2層間絕緣膜44係其上面則呈對於間隙絕緣膜39之上面而言成為拉平地形成。 At this time, the second interlayer insulating film 44 is formed on the upper surface thereof so as to be flattened on the upper surface of the gap insulating film 39.
接著，經由自動對準接觸法(SAC法)，而除去位置在第1電容用不純物擴散範圍68上之第1及第2層 間絕緣膜29，44，和位置在第2電容用不純物擴散範圍78上之第1及第2層間絕緣膜29，44。經由此，一括形成露出第1電容用不純物擴散範圍68之上面68a的第1電容接觸孔45-1，和露出第2電容用不純物擴散範圍78之上面78a的第2電容接觸孔45-2。 Then, the first and second layers positioned at the impurity diffusion range 68 for the first capacitor are removed by the automatic alignment contact method (SAC method). The interlayer insulating films 29 and 44 and the first and second interlayer insulating films 29 and 44 positioned on the second capacitor impurity diffusion range 78. Thus, the first capacitance contact hole 45-1 exposing the upper surface 68a of the impurity diffusion range 68 of the first capacitance and the second capacitance contact hole 45-2 exposing the upper surface 78a of the impurity diffusion range 78 of the second capacitance are formed.
接著，經由周知的手法，一括形成埋入第1電容接觸孔45-1，且下端則與第1電容用不純物擴散範圍68加以連接之第1電容接觸塞46-1，和埋入第2電容接觸孔45-2，且與第2電容用不純物擴散範圍78加以連接之第2電容接觸塞46-2。 Then, a well-known method includes forming a first capacitor contact plug 46-1 in which the first capacitor contact hole 45-1 is buried, and a lower end is connected to the first capacitor impurity diffusion range 68, and embedding the second capacitor. The contact hole 45-2 is in contact with the second capacitor contact plug 46-2 connected to the second capacitor impurity diffusion range 78.
此時，第1及第2電容接觸塞46-1，46-2係其上面則呈對於第2層間絕緣膜44之上面而言成為拉平地形成。 At this time, the first and second capacitor contact plugs 46-1 and 46-2 are formed on the upper surface of the second interlayer insulating film 44 so as to be flattened.
接著，在圖14所示之工程中，經由周知的手法，於圖13所示之構造體上，形成停止膜48。停止膜48係例如，由將矽氮化膜(SiN膜)成膜而形成。 Next, in the process shown in Fig. 14, the stopper film 48 is formed on the structure shown in Fig. 13 by a well-known technique. The stop film 48 is formed, for example, by forming a tantalum nitride film (SiN film).
接著，經由周知的手法，於停止膜48上形成第3層間絕緣膜49。第3層間絕緣膜49係例如，由將矽氧化膜(SiO2膜)成膜而形成。 Next, a third interlayer insulating film 49 is formed on the stopper film 48 by a well-known method. The third interlayer insulating film 49 is formed, for example, by forming a tantalum oxide film (SiO 2 film).
接著，經由光微影技術及乾蝕刻技術，由除去位置在第1電容接觸塞46-1上，及第2電容接觸塞46-2上之停止膜48及第3層間絕緣膜49者，形成露出第1電容接觸塞46-1之上面，或第2電容接觸塞46-2之上面的缸孔51。 Then, the photo-lithography technique and the dry etching technique are used to remove the stop film 48 and the third interlayer insulating film 49 on the first capacitor contact plug 46-1 and the second capacitor contact plug 46-2. The upper surface of the first capacitor contact plug 46-1 or the cylinder hole 51 of the upper surface of the second capacitor contact plug 46-2 is exposed.
接著，經由周知的手法，形成被覆缸孔51之內面的下部電極84。經由此，加以配置有作為王冠形狀之下部電極84於第1及第2電容接觸塞46-1，46-2上。 Next, the lower electrode 84 covering the inner surface of the cylinder bore 51 is formed by a well-known technique. Thereby, the lower electrode 84 as the crown shape is placed on the first and second capacitor contact plugs 46-1, 46-2.
接著，經由周知的手法，形成連續被覆複數之下部電極84內面，及第3層間絕緣膜49上面之電容絕緣膜85。 Next, the inner surface of the lower electrode 84 and the capacitor insulating film 85 on the upper surface of the third interlayer insulating film 49 are formed by a known method.
接著，藉由電容絕緣膜85，形成埋入複數之下部電極84，且具有加以配置於較電容絕緣膜85為上方之平坦的上面之上部電極86。 Then, a plurality of buried lower electrodes 84 are formed by the capacitor insulating film 85, and a flat upper surface upper electrode 86 disposed above the relatively capacitive insulating film 85 is formed.
經由此，對於複數之第1及第2之第1電容接觸塞46-1，46-2而言各形成有1個電容器53(下部電極84，電容絕緣膜85，及上部電極86所成之電容器)。 Thus, for each of the plurality of first and second capacitive contact plugs 46-1 and 46-2, one capacitor 53 (the lower electrode 84, the capacitor insulating film 85, and the upper electrode 86) is formed. Capacitor).
另外，由形成複數之電容器53者，對於1個活性範圍19係形成有2個單元(具體而言，第1單元電晶體25與電容器53所成之單元，和第2單元電晶體27與電容器53所成之單元)。 Further, in the case where a plurality of capacitors 53 are formed, two units are formed for one active range 19 (specifically, a unit formed by the first unit transistor 25 and the capacitor 53, and a second unit transistor 27 and a capacitor) 53 units of the unit).
接著，經由周知的手法，形成被覆上部電極膜86之上面的第4層間絕緣膜55(例如，矽氧化膜(SiO2膜))。 Next, a fourth interlayer insulating film 55 (for example, a tantalum oxide film (SiO 2 film)) covering the upper surface of the upper electrode film 86 is formed by a well-known method.
然而，雖未圖示，但亦可設置貫通第4層間絕緣膜55，下端則與上部電極86加以連接的貫孔。另外，於第4層間絕緣膜55上，亦可設置與該貫孔的上端加以連接之未圖示的配線。 However, although not shown, a through hole penetrating the fourth interlayer insulating film 55 and connecting the lower end to the upper electrode 86 may be provided. Further, a wiring (not shown) connected to the upper end of the through hole may be provided on the fourth interlayer insulating film 55.
之後，由形成保護膜57於第4層間絕緣膜55 上者，加以製造第1實施形態之半導體裝置10之記憶體單元部11。 Thereafter, a protective film 57 is formed on the fourth interlayer insulating film 55. In the above, the memory cell unit 11 of the semiconductor device 10 of the first embodiment is manufactured.
圖15係經由等角圖法，圖示第2實施形態之半導體裝置之記憶體單元部之主要部的等角投影圖。圖16係擴大由圖15所示之範圍B所圍繞之記憶體單元部的剖面圖。 Fig. 15 is an isometric view showing a main portion of a memory cell unit of the semiconductor device of the second embodiment, via an isometric method. Fig. 16 is a cross-sectional view showing the expansion of the memory unit portion surrounded by the range B shown in Fig. 15.
在圖15及圖16中，作為第2實施形態之半導體裝置110的一例，舉例圖示DRAM。在圖15及圖16中，對於與第1實施形態之半導體裝置10同一構成部分係附上同一符號。 In FIGS. 15 and 16, as an example of the semiconductor device 110 of the second embodiment, a DRAM is illustrated. In FIGS. 15 and 16, the same components as those of the semiconductor device 10 of the first embodiment are denoted by the same reference numerals.
對於參照圖15及圖16，第2實施形態之半導體裝置110係取代於構成第1實施形態之半導體裝置10之第1溝21，第2溝22，第1單元電晶體25，及第2單元電晶體27，而具有第1溝113，第2溝114，第1單元電晶體116，及第2單元電晶體117以外係與半導體裝置10同樣地加以構成。 Referring to FIGS. 15 and 16, the semiconductor device 110 of the second embodiment is replaced by the first trench 21, the second trench 22, the first cell transistor 25, and the second cell constituting the semiconductor device 10 of the first embodiment. The transistor 27 is configured similarly to the semiconductor device 10 except for the first trench 113, the second trench 114, the first unit transistor 116, and the second unit transistor 117.
第1溝113係底面113a則具有平坦的部分，與***的部分以外係作為與在第1實施形態所說明之第1溝21同樣之構成。 The first groove 113 has a flat portion on the bottom surface 113a, and has the same configuration as the first groove 21 described in the first embodiment except for the raised portion.
第2溝114係底面114a則具有平坦的部分，與***的部分以外係作為與在第1實施形態所說明之第2溝22同樣之構成。 The second groove 114 has a flat portion on the bottom surface 114a, and has the same configuration as the second groove 22 described in the first embodiment except for the raised portion.
第1單元電晶體116係取代於構成在第1實施形態所說明之第1單元電晶體25之第1底部通道範圍66，而具有第1底部通道範圍121以外係作為與第1單元電晶體25同樣之構成。 The first unit transistor 116 is replaced by the first bottom channel range 66 constituting the first unit transistor 25 described in the first embodiment, and has the first bottom channel range 121 as the first unit transistor 25. The same composition.
第1底部通道範圍121係其配設位置與第2底部通道範圍122不同以外，係作為與圖16所示之第2底部通道範圍122同樣之構成。 The first bottom channel range 121 has the same configuration as the second bottom channel range 122 shown in FIG. 16 except that the arrangement position is different from the second bottom channel range 122.
也就是，第1底部通道範圍121係加以配置於第1溝121之底面121a與絕緣層13-2之間，具有平板狀通道範圍124，和突出通道範圍125。 That is, the first bottom channel range 121 is disposed between the bottom surface 121a of the first trench 121 and the insulating layer 13-2, and has a flat channel range 124 and a protruding channel range 125.
平板狀通道範圍124係具有平行於半導體基板主體13-1的一面13-1a之上面124c及下面124d。對於Y方向而言加以對向配置之平板狀通道範圍124的側面124a，124b係與第1元件分離範圍14接觸。另外，平板狀通道範圍124之上面124c係與第1閘極絕緣膜59-1接觸。 The flat channel range 124 has an upper surface 124c and a lower surface 124d which are parallel to one surface 13-1a of the semiconductor substrate main body 13-1. The side faces 124a, 124b of the flat channel region 124 that are opposed to each other in the Y direction are in contact with the first element separation range 14. Further, the upper surface 124c of the flat channel region 124 is in contact with the first gate insulating film 59-1.
平板狀通道範圍124之下面124d係與絕緣層13-2之一面13-2a接觸。 The lower surface 124d of the flat channel range 124 is in contact with one of the faces 13-2a of the insulating layer 13-2.
配置於X方向之平板狀通道範圍124之2個端部之中，一方的端部係與第1側壁部通道範圍63作為一體。另一方的端部係與第2側壁部通道範圍64作為一體。 One of the two end portions of the flat channel region 124 disposed in the X direction is integrated with the first side wall portion passage region 63. The other end portion is integral with the second side wall portion passage range 64.
作為上述構成之平板狀通道範圍124之厚度M5係例如，可作為25nm者。 The thickness M5 of the flat channel region 124 having the above configuration is, for example, 25 nm.
突出通道範圍125係從平板狀通道範圍124 之上面124c突出於其上方之通道範圍，與平板狀通道範圍124作為一體。 Outstanding channel range 125 is from flat channel range 124 The upper surface 124c protrudes from the channel area above it, and is integrated with the flat channel range 124.
突出通道範圍125係具有2個傾斜之側面125a，125b，且切斷面之形狀則作為三角形。 The protruding channel range 125 has two inclined sides 125a, 125b, and the shape of the cut surface is a triangle.
將平板狀通道範圍124之上面124c作為基準時之突出通道範圍125的突出量H1係例如，可作為25nm。 The amount of protrusion H1 of the protruding channel range 125 when the upper surface 124c of the flat channel region 124 is used as a reference is, for example, 25 nm.
第2單元電晶體117係取代於構成在第1實施形態所說明之第2單元電晶體27之第2底部通道範圍77，而具有第2底部通道範圍122以外係作為與第2單元電晶體27同樣之構成。 The second unit transistor 117 is replaced with the second bottom channel range 77 constituting the second unit transistor 27 described in the first embodiment, and has the second bottom channel range 122 as the second unit transistor 27. The same composition.
第2底部通道範圍122係加以配置於第2溝122之底面122a與絕緣層13-2之間，且X方向的端部則與第2側壁部通道範圍64及第3側壁部通道範圍76作為一體以外，係與先前說明之第1底部通道範圍121同樣地加以構成。 The second bottom channel range 122 is disposed between the bottom surface 122a of the second groove 122 and the insulating layer 13-2, and the end portion in the X direction and the second side wall portion channel range 64 and the third side wall portion channel range 76 are The integration is the same as the first bottom channel range 121 described above.
也就是，第2底部通道範圍122係作為具有平板狀通道範圍124與突出通道範圍125之構成。 That is, the second bottom channel range 122 is configured to have a flat channel range 124 and a protruding channel range 125.
作為上述構成之第2實施形態之半導體裝置110係可得到與第1實施形態之半導體裝置10同樣的效果者。 The semiconductor device 110 of the second embodiment having the above configuration can obtain the same effects as those of the semiconductor device 10 of the first embodiment.
另外，成為在維持第1及第2底部通道範圍121，122之完全空乏化之後，可較在第1實施形態所說明之第1及第2底部通道66，77增加剖面積者。隨之，可謀求第1及第2單元電晶體116，117之動作時的Ion之增大 與S特性的提升者。 Further, after maintaining the complete depletion of the first and second bottom passage regions 121, 122, the cross-sectional area can be increased as compared with the first and second bottom passages 66, 77 described in the first embodiment. Accordingly, an increase in Ion during operation of the first and second unit transistors 116, 117 can be achieved. Promoter with S characteristics.
然而，上述之「S特性」係指次臨界電壓擺動係數(S因數)之業界通稱，意味著對於使汲極電流值1位數變化必要之閘極電壓。隨之，此閘極電壓越小越可有效果地達成電晶體之開啟/關閉控制者，而貢獻於高速動作化及低消耗電力化。 However, the above-mentioned "S characteristic" refers to the industry-wide term for the sub-threshold voltage swing coefficient (S factor), and means the gate voltage necessary for changing the value of the drain current value by one digit. As a result, the smaller the gate voltage, the more effective the opening/closing control of the transistor is, and the higher the speed of operation and the lower the power consumption.
圖17係擴大有關本發明之第2實施形態的變形例之半導體裝置之記憶體單元部之中，與第2實施形態之半導體裝置不同之部分的剖面圖。在圖17中，對於與圖16所示之構造體同一構成部分係附上同一符號。 Fig. 17 is a cross-sectional view showing a portion of a memory cell unit of a semiconductor device according to a modification of the second embodiment of the present invention, which is different from the semiconductor device of the second embodiment. In Fig. 17, the same components as those of the structure shown in Fig. 16 are denoted by the same reference numerals.
在此，參照圖17，對於有關第2實施形態之變形例的半導體裝置130的記憶體單元部131之主要部加以說明。 Here, the main part of the memory cell unit 131 of the semiconductor device 130 according to the modification of the second embodiment will be described with reference to FIG.
對於參照圖17，平板狀通道範圍124之側面124a，124b則由第1閘極絕緣膜59-1(對於圖17係未圖示)或第2閘極絕緣膜59-2加以被覆。藉由第1閘極絕緣膜59-1或第2閘極絕緣膜59-2，平板狀通道範圍124之側面124a，124b則與第1閘極電極61(對於圖17係未圖示)或第2閘極電極74對向。此等構成以外係有關第2實施形態之變形例之半導體裝置130係與第2實施形態之半導體裝置110同樣地加以構成。 Referring to Fig. 17, the side faces 124a, 124b of the flat channel region 124 are covered by the first gate insulating film 59-1 (not shown in Fig. 17) or the second gate insulating film 59-2. By the first gate insulating film 59-1 or the second gate insulating film 59-2, the side faces 124a and 124b of the flat channel region 124 are the same as the first gate electrode 61 (not shown in FIG. 17) or The second gate electrode 74 is opposed to each other. The semiconductor device 130 according to the modification of the second embodiment is configured in the same manner as the semiconductor device 110 of the second embodiment.
具有上述鞍狀翼片構造之半導體裝置130係可得到與第1實施形態之半導體裝置10同樣的效果者。更且，半導體裝置130係成為在維持第1及第2底部通道 範圍121，122之完全空乏化之後，可較在第1實施形態所說明之第1及第2底部通道66，77增加剖面積者。隨之，半導體裝置130係可謀求第1及第2單元電晶體116，117之動作時的Ion之增大與S特性的提升者。 The semiconductor device 130 having the above-described saddle-shaped fin structure can obtain the same effects as those of the semiconductor device 10 of the first embodiment. Furthermore, the semiconductor device 130 is configured to maintain the first and second bottom channels. After the complete depletion of the ranges 121, 122, the cross-sectional area can be increased as compared with the first and second bottom passages 66, 77 described in the first embodiment. Accordingly, the semiconductor device 130 can improve the Ion and the S characteristic when the first and second unit transistors 116 and 117 are operated.
圖18及圖19係顯示本發明之第2實施形態之半導體裝置之工程的剖面圖。在圖18及圖19中，對於與圖15及圖16所示之構造體同一構成部分係附上同一符號。 18 and 19 are cross-sectional views showing the construction of a semiconductor device according to a second embodiment of the present invention. In FIGS. 18 and 19, the same components as those of the structures shown in FIGS. 15 and 16 are denoted by the same reference numerals.
接著，主要參照圖18及圖19，對於第2實施形態之半導體裝置110之記憶體單元部111的製造方法加以說明。 Next, a method of manufacturing the memory cell unit 111 of the semiconductor device 110 of the second embodiment will be described mainly with reference to FIGS. 18 and 19.
首先，由依序進行在第1實施形態所說明之圖8所示之工程，和圖9A及圖9B所示之工程者，形成圖9A及圖9B所示之構造體。 First, the construction shown in Fig. 8 described in the first embodiment and the engineer shown in Figs. 9A and 9B are sequentially formed to form the structure shown in Figs. 9A and 9B.
接著，在第1實施形態所說明之圖10所示之工程之中，進行形成具有第1及第2開口溝29A，29B之第1層間絕緣膜29的工程。 Next, in the process shown in FIG. 10 described in the first embodiment, the first interlayer insulating film 29 having the first and second opening grooves 29A and 29B is formed.
接著，在圖18所示之工程中，經由使用較半導體層13-3，第1元件分離範圍14之蝕刻選擇比變大之蝕刻條件(例如，選擇比為3~10程度之蝕刻條件)的向異性乾蝕刻，藉由具有第1及第2開口溝29A，29B之第1層間絕緣膜29，而蝕刻半導體層13-3及第1元件分離範圍14。 Next, in the process shown in FIG. 18, by using the semiconductor layer 13-3, the etching selectivity of the first element isolation range 14 is increased (for example, the etching ratio is about 3 to 10). The opposite layer is dry-etched, and the semiconductor layer 13-3 and the first element isolation region 14 are etched by the first interlayer insulating film 29 having the first and second opening grooves 29A and 29B.
此時，由使用較半導體層13-3，第1元件分 離範圍14之蝕刻選擇比為大之蝕刻條件者，第1元件分離範圍14則較半導體層13-3加以快速蝕刻。 At this time, by using the semiconductor layer 13-3, the first component is divided into When the etching selection ratio of the range 14 is a large etching condition, the first element isolation range 14 is rapidly etched compared to the semiconductor layer 13-3.
經由此，在蝕刻之後，第1元件分離範圍14之上面係加以配置於較半導體層13-3之上面為下方之同時，於自第1元件分離範圍14隔離之半導體層13-3之中央部，形成有作為突出於上方之山形狀的突出部。 Thus, after the etching, the upper surface of the first element isolation range 14 is disposed below the upper surface of the semiconductor layer 13-3, and is at the center of the semiconductor layer 13-3 isolated from the first element isolation range 14. A protrusion is formed as a mountain shape that protrudes above.
然而，對於圖18係雖未圖示，但對應於第2溝114之形成範圍的部分之第1元件分離範圍14及半導體層13-3係加以蝕刻為與圖18所示之第1元件分離範圍14及半導體層13-3同樣之形狀。 However, although not shown in FIG. 18, the first element isolation range 14 and the semiconductor layer 13-3 corresponding to the formation range of the second groove 114 are etched to be separated from the first element shown in FIG. The range 14 and the semiconductor layer 13-3 have the same shape.
接著，在圖19所示之工程中，在經由使用向異性高，且較第1元件分離範圍14，半導體層13-3之選擇比為大之蝕刻條件(例如，選擇比為3~10程度)之向異性蝕刻，使上述突出部之形狀殘存於半導體層13-3之上端的狀態，蝕刻位置在第1及第2開口溝29A，29B(對於圖19係未圖示)之下方的半導體層13-3及第1元件分離範圍14。經由此，一括形成平板狀通道範圍124及突出通道範圍125所成之第1及第2底部通道範圍121，122(對於圖19係未圖示第2底部通道範圍122)。 Next, in the process shown in FIG. 19, the selection ratio of the semiconductor layer 13-3 is large and the etching ratio is larger than the first element isolation range 14 (for example, the selection ratio is 3 to 10). The anisotropic etching is performed such that the shape of the protruding portion remains in the upper end of the semiconductor layer 13-3, and the etching position is in the semiconductor below the first and second opening grooves 29A and 29B (not shown in FIG. 19). Layer 13-3 and the first element are separated by a range 14. Thus, the first and second bottom channel ranges 121, 122 formed by the flat channel range 124 and the protruding channel range 125 are formed (the second bottom channel range 122 is not shown in FIG. 19).
此時，將蝕刻後之第1元件分離範圍14之上面作為基準時之突出通道範圍125的頂部高度H1呈成為50nm以下地，進行上述向異性蝕刻為佳。 At this time, it is preferable to perform the anisotropic etching by setting the top height H1 of the protruding channel range 125 when the upper surface of the first element isolation range 14 after etching is used as a reference to 50 nm or less.
之後，由進行與在第1實施形態所說明之圖11~圖14所示之工程同樣的處理者，加以製造圖15所示 之第2實施形態之半導體裝置110之記憶體單元部111。 Thereafter, the same processing as that shown in FIGS. 11 to 14 described in the first embodiment is performed, and the manufacturing shown in FIG. 15 is performed. The memory cell unit 111 of the semiconductor device 110 of the second embodiment.
圖20係經由等角圖法，圖示第3實施形態之半導體裝置之記憶體單元部之主要部的等角投影圖。圖21係擴大由圖20所示之範圍C所圍繞之記憶體單元部的剖面圖。 Fig. 20 is an isometric view showing a main portion of a memory cell unit of the semiconductor device of the third embodiment, via an isometric method. Fig. 21 is a cross-sectional view showing the expansion of the memory unit portion surrounded by the range C shown in Fig. 20.
在圖20及圖21中，作為第3實施形態之半導體裝置140的一例，舉例圖示DRAM。在圖20及圖21中，對於與先前說明之第1及第2實施形態之半導體裝置10，110同一構成部分係附上同一符號。 In FIGS. 20 and 21, a DRAM is exemplified as an example of the semiconductor device 140 of the third embodiment. In FIGS. 20 and 21, the same components as those of the semiconductor devices 10 and 110 of the first and second embodiments described above are denoted by the same reference numerals.
對於參照圖20及圖21，第3實施形態之半導體裝置140係取代於構成第1實施形態之半導體裝置10之第1溝21，第2溝22，第1單元電晶體25，及第2單元電晶體27，而具有第1溝143，第2溝144，第1單元電晶體146，及第2單元電晶體147以外係與半導體裝置10同樣地加以構成。 Referring to FIGS. 20 and 21, the semiconductor device 140 of the third embodiment is replaced by the first trench 21, the second trench 22, the first cell transistor 25, and the second cell constituting the semiconductor device 10 of the first embodiment. The transistor 27 is configured similarly to the semiconductor device 10 except for the first trench 143, the second trench 144, the first unit transistor 146, and the second unit transistor 147.
第1溝143係底面143a則具有平坦的部分，與***的部分，且使絕緣層13-2之一面13-2a之一部分露出以外係作為與在第1實施形態所說明之第1溝21同樣之構成。 The first groove 143 has a flat portion on the bottom surface 143a, and the portion of the first groove 143a is formed in the same manner as the first groove 21 described in the first embodiment, except that one of the surfaces 13-2a of the insulating layer 13-2 is exposed. The composition.
第2溝144係底面144a則具有平坦的部分，與***的部分，且使絕緣層13-2之一面13-2a之一部分露出以外係作為與在第1實施形態所說明之第2溝22同樣之構 成。 The bottom surface 144a of the second groove 144 has a flat portion, and the portion of the raised portion 13-2 is exposed to the same portion as the second groove 22 described in the first embodiment. Structure to make.
第1單元電晶體146係取代於構成在第1實施形態所說明之第1單元電晶體25之第1底部通道範圍66，而具有第1底部通道範圍151以外係作為與第1單元電晶體25同樣之構成。 The first unit transistor 146 is replaced with the first bottom channel range 66 constituting the first unit transistor 25 described in the first embodiment, and has the first bottom channel range 151 as the first unit transistor 25. The same composition.
第1底部通道範圍151係其配設位置與第2底部通道範圍152不同以外，係作為與圖21所示之第2底部通道範圍152同樣之構成。 The first bottom channel range 151 has the same configuration as the second bottom channel range 152 shown in FIG. 21 except that the arrangement position is different from the second bottom channel range 152.
也就是，第1底部通道範圍151係作為與具有在第2實施形態所說明之2個傾斜之側面125a，125b，且切斷面之形狀作為三角形之突出通道範圍125同樣之構成。 That is, the first bottom passage region 151 has the same configuration as the two-inclined side faces 125a and 125b described in the second embodiment, and the shape of the cut surface is the same as the triangular projecting passage range 125.
將絕緣層13-2之一面13-2a作為基準時之第1底部通道範圍151之高度H2係例如，可在25nm以上50nm以下的範圍內做適宜選擇者。 The height H2 of the first bottom channel range 151 when one surface 13-2a of the insulating layer 13-2 is used as a reference can be suitably selected, for example, in the range of 25 nm or more and 50 nm or less.
第2單元電晶體147係取代於構成在第1實施形態所說明之第2單元電晶體27之第2底部通道範圍77，而具有第2底部通道範圍152以外係作為與第2單元電晶體27同樣之構成。 The second unit transistor 147 is replaced by the second bottom channel range 77 constituting the second unit transistor 27 described in the first embodiment, and has the second bottom channel range 152 as the second unit transistor 27. The same composition.
第2底部通道範圍152係作為與先前說明之第1底部通道範圍151同樣的形狀(參照圖21)。 The second bottom channel range 152 has the same shape as the first bottom channel range 151 described above (see FIG. 21).
第3實施形態之半導體裝置係具有：第1底部通道範圍151，和第2底部通道範圍152。第1底部通道範圍151係具有2個傾斜之側面125a，125b，將切斷面之形狀作為三角形，與第1及第2側壁部通道範圍 63，64作為一體。第2底部通道範圍152係具有2個傾斜之側面125a，125b，將切斷面之形狀作為三角形，與第2及第3側壁部通道範圍64，76作為一體。如根據第3實施形態之半導體裝置，成為可較在第1實施形態之半導體裝置10所說明之第1及第2底部通道範圍66，77的剖面積，縮小第1及第2底部通道範圍151，152之剖面積者。隨之，第3實施形態之半導體裝置係與半導體裝置10做比較，可更有效果地抑制干擾不良。 The semiconductor device of the third embodiment has a first bottom channel range 151 and a second bottom channel range 152. The first bottom channel range 151 has two inclined side faces 125a, 125b, and the shape of the cut surface is a triangle, and the first and second side wall passage ranges 63, 64 as one. The second bottom channel range 152 has two inclined side faces 125a, 125b, and the shape of the cut surface is a triangle, and is integrated with the second and third side wall passage ranges 64, 76. According to the semiconductor device of the third embodiment, the first and second bottom channel ranges 151 can be reduced as compared with the first and second bottom channel ranges 66, 77 described in the semiconductor device 10 of the first embodiment. , 152 cross-sectional area. As a result, the semiconductor device of the third embodiment can suppress the interference failure more effectively than the semiconductor device 10.
圖22係顯示本發明之第3實施形態的半導體裝置之工程的剖面圖。在圖22中，對於與圖20及圖21所示之構造體同一構成部分係附上同一符號。 Fig. 22 is a cross-sectional view showing the construction of a semiconductor device according to a third embodiment of the present invention. In FIG. 22, the same components as those of the structures shown in FIGS. 20 and 21 are denoted by the same reference numerals.
接著，主要參照圖22，對於第3實施形態之半導體裝置140之記憶體單元部141的製造方法加以說明。 Next, a method of manufacturing the memory cell unit 141 of the semiconductor device 140 of the third embodiment will be described mainly with reference to FIG.
首先，由依序進行在第1實施形態所說明之圖8所示之工程，和圖9A及圖9B所示之工程者，形成圖9A及圖9B所示之構造體。 First, the construction shown in Fig. 8 described in the first embodiment and the engineer shown in Figs. 9A and 9B are sequentially formed to form the structure shown in Figs. 9A and 9B.
接著，在第1實施形態所說明之圖10所示之工程之中，進行形成具有第1及第2開口溝29A，29B之第1層間絕緣膜29的工程。 Next, in the process shown in FIG. 10 described in the first embodiment, the first interlayer insulating film 29 having the first and second opening grooves 29A and 29B is formed.
接著，由進行與在第2實施形態所說明之圖18所示之工程同樣的處理者，形成圖18所示之構造體。 Next, the structure shown in Fig. 18 is formed by the same processor as the one shown in Fig. 18 described in the second embodiment.
接著，在圖22所示之工程中，經由使用在第2實施形態之圖19所示之工程所說明之蝕刻條件之向異 性乾蝕刻，絕緣層13-2之上面13-2a至露出為止進行蝕刻處理。 Next, in the process shown in FIG. 22, the divergence of the etching conditions described in the construction shown in FIG. 19 of the second embodiment is used. The dry etching is performed until the upper surface 13-2a of the insulating layer 13-2 is exposed.
經由此，一括形成有具有2個傾斜之側面125a，125b，切斷面之形狀作為三角形之第1底部通道範圍151，和具有2個傾斜之側面125a，125b，切斷面之形狀作為三角形之第2底部通道範圍152(對於圖22係未圖示)。 Thus, a side surface 125a, 125b having two inclined sides is formed, and the shape of the cut surface is a first bottom passage range 151 of a triangle, and two inclined sides 125a, 125b are formed, and the shape of the cut surface is a triangle. The second bottom channel range 152 (not shown in Fig. 22).
之後，由進行與在第1實施形態所說明之圖11~圖14所示之工程同樣的處理者，加以製造圖20所示之第3實施形態之半導體裝置140之記憶體單元部141。 Then, the memory unit unit 141 of the semiconductor device 140 of the third embodiment shown in FIG. 20 is manufactured by the same processor as the one shown in FIG. 11 to FIG. 14 described in the first embodiment.
以上，對於本發明之理想的實施形態已做過詳述，但本發明係並不限定於有關之特定的實施形態，而在記載於申請專利範圍內之本發明的內容範圍內，可做種種的變形．變更。 The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to the specific embodiments described above, and various modifications can be made within the scope of the invention as described in the claims. Deformation. change.
本發明係可適用於半導體裝置。 The present invention is applicable to a semiconductor device.
13a‧‧‧主面 13a‧‧‧Main face
13-2‧‧‧絕緣層 13-2‧‧‧Insulation
13-2a‧‧‧一面 13-2a‧‧‧ side
13-3‧‧‧半導體層 13-3‧‧‧Semiconductor layer
17‧‧‧第2元件分離範圍 17‧‧‧Second component separation range
17-1‧‧‧第2元件分離用溝 17-1‧‧‧Separation of the second component separation trench
17-2‧‧‧第2元件分離用絕緣膜 17-2‧‧‧Insulation film for second component separation
19‧‧‧活性範圍 19‧‧‧Active range
66c，68a，71a，77c，78a‧‧‧上面 66c, 68a, 71a, 77c, 78a‧‧‧ above
21‧‧‧第1溝 21‧‧‧1st ditch
21a，22a‧‧‧底面 21a, 22a‧‧‧ bottom
21b，21c，22b，22c‧‧‧側面 21b, 21c, 22b, 22c‧‧‧ side
22‧‧‧第2溝 22‧‧‧2nd ditch
25‧‧‧第1單元電晶體 25‧‧‧1st unit transistor
27‧‧‧第2單元電晶體 27‧‧‧2nd unit transistor
29‧‧‧第1層間絕緣膜 29‧‧‧1st interlayer insulating film
32‧‧‧埋入絕緣膜 32‧‧‧Insert insulating film
33‧‧‧位元線接觸開口部 33‧‧‧ bit line contact opening
35‧‧‧位元線接觸塞 35‧‧‧ bit line contact plug
46-1‧‧‧第1電容接觸塞 46-1‧‧‧1st capacitive contact plug
46-2‧‧‧第2電容接觸塞 46-2‧‧‧2nd capacitive contact plug
59-1‧‧‧第1閘極絕緣膜 59-1‧‧‧1st gate insulating film
59-2‧‧‧第2閘極絕緣膜 59-2‧‧‧2nd gate insulating film
61‧‧‧第1閘極電極 61‧‧‧1st gate electrode
63‧‧‧第1側壁部通道範圍 63‧‧‧1st side wall passage range
64‧‧‧第2側壁部通道範圍 64‧‧‧2nd side wall channel range
66‧‧‧第1底部通道範圍 66‧‧‧1st bottom channel range
66A，66B，77A，77B‧‧‧端部 66A, 66B, 77A, 77B‧‧‧ end
66d，77d‧‧‧下面 66d, 77d‧‧‧ below
68‧‧‧第1電容用不純物擴散範圍 68‧‧‧The first capacitor uses impurity diffusion range
71‧‧‧位元線用不純物擴散範圍 71‧‧‧ bit line diffusion range of impurities
74‧‧‧第2閘極電極 74‧‧‧2nd gate electrode
76‧‧‧第3側壁部通道範圍 76‧‧‧3rd side wall passage range
77‧‧‧第2底部通道範圍 77‧‧‧2nd bottom channel range
78‧‧‧第2電容用不純物擴散範圍 78‧‧‧The second capacitor uses impurity diffusion range
M1，M2，M3‧‧‧厚度 M1, M2, M3‧‧‧ thickness
Claims (21)
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI560853B (en) * | 2015-09-15 | 2016-12-01 | Inotera Memories Inc | Cell contact structure |
| TWI771129B (en) * | 2021-08-02 | 2022-07-11 | 南亞科技股份有限公司 | Memory structure and method for preparing the same |
| TWI803372B (en) * | 2022-05-11 | 2023-05-21 | 南亞科技股份有限公司 | Method for fabricating a memory device having protruding channel structure |
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| JPH0461157A (en) * | 1990-06-22 | 1992-02-27 | Sony Corp | Manufacture of semiconductor memory |
| JP2007005568A (en) * | 2005-06-23 | 2007-01-11 | Toshiba Corp | Semiconductor device |
| JP2011040422A (en) * | 2009-08-06 | 2011-02-24 | Elpida Memory Inc | Semiconductor substrate, semiconductor device and method of manufacturing the semiconductor device |
| JP5507287B2 (en) * | 2010-02-22 | 2014-05-28 | ピーエスフォー ルクスコ エスエイアールエル | Semiconductor device and manufacturing method thereof |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI560853B (en) * | 2015-09-15 | 2016-12-01 | Inotera Memories Inc | Cell contact structure |
| CN106549018A (en) * | 2015-09-15 | 2017-03-29 | 美光科技公司 | Cell contact structure |
| CN106549018B (en) * | 2015-09-15 | 2020-04-07 | 美光科技公司 | Cell contact structure |
| TWI771129B (en) * | 2021-08-02 | 2022-07-11 | 南亞科技股份有限公司 | Memory structure and method for preparing the same |
| TWI803372B (en) * | 2022-05-11 | 2023-05-21 | 南亞科技股份有限公司 | Method for fabricating a memory device having protruding channel structure |
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