TW201429132A - System controller, signal generator and method for protecting power converter and method for protecting signal of power converter - Google Patents

System controller, signal generator and method for protecting power converter and method for protecting signal of power converter Download PDF

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TW201429132A
TW201429132A TW102116552A TW102116552A TW201429132A TW 201429132 A TW201429132 A TW 201429132A TW 102116552 A TW102116552 A TW 102116552A TW 102116552 A TW102116552 A TW 102116552A TW 201429132 A TW201429132 A TW 201429132A
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signal
time
switch
threshold
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TWI523381B (en
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Chao Yao
yun-chao Zhang
Yuan Lin
Zi-Qiang Sun
lie-yi Fang
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On Bright Electronics Shanghai
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Abstract

The present invention discloses a system and a method for protecting a power converter. An exemplary system controller for protecting a power converter comprises a signal generator, a comparator, and modulation and driving components. The signal generator is configured for generating a threshold signal. The comparator is configured for receiving the threshold signal and a current sensing signal, and generating a comparison signal based on at least information associated with the threshold signal and the current sensing signal. The current sensing signal indicates a magnitude of a primary current flowing through a primary winding of a power converter. The modulation and driving components are coupled to the signal generator.

Description

用於保護電源轉換器的系統控制器、信號生成器和方法及用於保護電源轉換器的信號的方法 System controller, signal generator and method for protecting a power converter and method for protecting a signal of a power converter

本發明涉及積體電路。更具體地，本發明提供了對於過流保護(Over-Current Protection,OCP)和過功率保護(Over-Power Protection,OPP)的控制系統和方法。僅僅作為示例，本發明已應用於電源轉換器。但是將認識到，本發明具有更廣泛的應用範圍。 The present invention relates to an integrated circuit. More specifically, the present invention provides control systems and methods for Over-Current Protection (OCP) and Over-Power Protection (OPP). Merely by way of example, the invention has been applied to power converters. However, it will be appreciated that the invention has a broader range of applications.

電源轉換器被廣泛用於諸如可攜式裝置之類的消費電子設備。電源轉換器可以將電力從一種形式轉換為另一種形式。作為一個示例，將電力從交流(Alternating Current,AC)變換為直流(Direct Current,DC)，從DC變換為AC，從AC變換為AC，或者從DC變換為DC。另外，電源轉換器可將電力從一種電壓電平轉換為另一電壓電平。 Power converters are widely used in consumer electronic devices such as portable devices. A power converter can convert power from one form to another. As an example, power is converted from alternating current (AC) to direct current (DC), from DC to AC, from AC to AC, or from DC to DC. In addition, the power converter can convert power from one voltage level to another.

電源轉換器包括線性轉換器和開關模式轉換器。開關模式轉換器通常使用脈寬調製(Pulse Width Modulation,PWM)機制或脈衝頻率調製(Pulse Frequency Modulation,PFM)機制。這些機制常常是利用包含各種保護元件的開關模式控制器來實現的。這些元件可以提供過壓保護、過溫度保護、過流保護(OCP)和過功率(OPP)保護。這些保護通常可以防止電源轉換器及相連電路遭受永久損壞。 The power converter includes a linear converter and a switch mode converter. Switch mode converters typically use a Pulse Width Modulation (PWM) mechanism or a Pulse Frequency Modulation (PFM) mechanism. These mechanisms are often implemented using switch mode controllers that include various protection components. These components provide overvoltage protection, overtemperature protection, overcurrent protection (OCP), and overpower (OPP) protection. These protections typically protect the power converter and associated circuitry from permanent damage.

例如，電源轉換器包括開關以及與開關串聯的變壓器繞組。流經該開關和變壓器繞組的電流可能受到OCP系統的限制。如果OCP系統無效，則由於開關時的過大電流和電壓應力或者由於操作期間的熱耗散，電流可能達到即將損壞該開關的水準。例如，當輸出短路或超載發生時，可能達到該電流水準。因此，在許多離線反激式轉換器中，由於過大的電壓和電流應力，變壓器次級側上的整流器元件經歷永久損壞。因此，有效的OCP系統對於可靠開關模式轉換器是重要的。 For example, a power converter includes a switch and a transformer winding in series with the switch. The current flowing through the switch and transformer windings may be limited by the OCP system. If the OCP system is ineffective, the current may reach the level that is about to damage the switch due to excessive current and voltage stress during switching or due to heat dissipation during operation. For example, when an output short circuit or overload occurs, the current level may be reached. Therefore, in many off-line flyback converters, the rectifier elements on the secondary side of the transformer experience permanent damage due to excessive voltage and current stresses. Therefore, an effective OCP system is important for a reliable switch mode converter.

第1圖是具有過流保護的簡化傳統開關模式轉換器。開關模 式轉換器100包括OCP比較器110、PWM控制器元件120、柵極驅動器130、開關140、電阻器150,152,154和156、以及初級繞組160。OCP比較器110、PWM控制器元件120和柵極驅動器130是用於PWM控制的晶片180的多個部分。 Figure 1 is a simplified conventional switch mode converter with overcurrent protection. Switching mode The converter 100 includes an OCP comparator 110, a PWM controller component 120, a gate driver 130, a switch 140, resistors 150, 152, 154 and 156, and a primary winding 160. OCP comparator 110, PWM controller component 120, and gate driver 130 are portions of wafer 180 for PWM control.

例如，PWM控制器元件120生成PWM信號122，該PWM 信號122由柵極驅動器130接收。在又一示例中，OCP比較器110接收並比較過流閾值信號112(例如，Vth_oc)和電流感測信號114(例如，VCS)，並且將過流控制信號116發送給PWM控制器元件120。當初級繞組的電流大於限制水準時，PWM控制器元件120關斷開關140並且關閉開關模式轉換器100。 For example, PWM controller component 120 generates a PWM signal 122 that is received by gate driver 130. In yet another example, OCP comparator 110 receives and compares overcurrent threshold signal 112 (eg, V th — oc ) and current sense signal 114 (eg, V CS ), and transmits overcurrent control signal 116 to the PWM controller component. 120. When the current of the primary winding is greater than the limit level, the PWM controller component 120 turns off the switch 140 and turns off the switch mode converter 100.

對於開關模式轉換器，常將逐週期或逐脈衝控制機制用於 OCP。例如，逐週期控制方案限制由開關模式轉換器傳遞的最大電流並且因此限制最大功率。對最大功率的這種限制可以保護電源轉換器不經歷熱耗散。一些傳統的OCP系統使用基於線路輸入電壓的可調節OCP閾值，但是，針對比較寬的輸入電壓範圍而言，為保持最大輸出功率恒定，最大電流並非是恒定的。其它傳統OCP系統使用附加電阻器152和154，附加電阻器152和154位於晶片180外面並被***在Vin與電阻器150之間，如第1圖所示。但是，電阻器152消耗巨大功率，通常無法滿足低待機功率的嚴格要求。例如，2 MΩ的電阻器152在264伏特的輸入AC電壓下可消耗約70 mW。 For switch mode converters, cycle-by-cycle or pulse-by-pulse control mechanisms are often used for OCP. For example, a cycle-by-cycle control scheme limits the maximum current delivered by the switch mode converter and thus limits the maximum power. This limitation on maximum power protects the power converter from thermal dissipation. Some conventional OCP systems use an adjustable OCP threshold based on the line input voltage, but for a relatively wide input voltage range, to keep the maximum output power constant, the maximum current is not constant. Other conventional systems use additional OCP resistors 152 and 154, and additional resistor 152 and 154 located outside the wafer 180 is interposed between V in and the resistor 150, as shown in Figure 1. However, the resistor 152 consumes a large amount of power and usually cannot meet the strict requirements of low standby power. For example, a 2 MΩ resistor 152 can consume approximately 70 mW at an input AC voltage of 264 volts.

如第1圖所示，電流限制被表達如下： 其中，ILimit表示電流限制。例如，電流限制是觸發過流保護的電流閾值。另外，Vin是節點190處的整流後電容上的電壓(bulk voltage)(例如，與電網輸入電壓VAC相關聯)，並且Vth_oc是OCP比較器110的輸入過流閾值信號112處的電壓電平。Rs是電阻器150的電阻，並且Lp是初級繞組160的電感。此外，ton表示每個週期中開關140的導通時間。因此，儲存在初級繞組160中的最大能量ε為 其中，T表示時鐘週期，並且P表示最大功率。因此，最大功率P可被表達如下： As shown in Figure 1, the current limit is expressed as follows: Where I Limit represents the current limit. For example, the current limit is the current threshold that triggers overcurrent protection. Additionally, V in is the bulk voltage at the rectified capacitor at node 190 (eg, associated with grid input voltage VAC), and V th — oc is the voltage at input overcurrent threshold signal 112 of OCP comparator 110 level. R s is the resistance of the resistor 150 and L p is the inductance of the primary winding 160. Further, t on represents the on- time of the switch 140 in each cycle. Therefore, the maximum energy ε stored in the primary winding 160 is Where T represents the clock period and P represents the maximum power. Therefore, the maximum power P can be expressed as follows:

因此，可以通過控制電流限制ILimit來限制功率。但是式3並未考慮到“輸出延遲”，其包括通過電流感測路徑到開關140的傳播延遲。例如，該傳播延遲包括通過OCP比較器110、PWM控制器元件120、柵極驅動器130的傳播延遲以及關斷開關140的回應延遲。在“輸出延遲”期間，開關140保持導通，並且通過開關140的輸入電流保持傾斜上升，儘管電流已經達到OCP比較器110的閾值水準。由於“輸出延遲”引起的額外電流斜升幅度△I與整流後電容上的電壓Vin成比例，如下： 其中，Tdelay表示“輸出延遲”。 Therefore, the power can be limited by controlling the current limit I Limit . However, Equation 3 does not take into account the "output delay", which includes the propagation delay through the current sensing path to the switch 140. For example, the propagation delay includes a propagation delay through the OCP comparator 110, the PWM controller component 120, the gate driver 130, and a response delay of the shutdown switch 140. During the "output delay", the switch 140 remains on and the input current through the switch 140 remains ramped up, although the current has reached the threshold level of the OCP comparator 110. The extra current ramp-up amplitude Δ I due to the “output delay” is proportional to the voltage V in on the rectified capacitor, as follows: Where T delay means "output delay".

第2圖是示出額外電流斜升幅度與整流後電容上的電壓之間的傳統關係的簡化圖式。如第2圖所示，與較高的Vin相對應的實際最大電流IPEAK1大於較低的Vin相對應的實際最大電流IPEAK2。因此，實際最大功率在整流後電容上的電壓的寬範圍中不是恒定的。因此，實際最大功率表達如下： Figure 2 is a simplified diagram showing the conventional relationship between the magnitude of the extra current ramp and the voltage across the rectified capacitor. As shown in FIG. 2, the actual maximum current I PEAK1 corresponding to the higher V in is greater than the actual maximum current I PEAK2 corresponding to the lower V in . Therefore, the actual maximum power is not constant over a wide range of voltages across the rectified capacitor. Therefore, the actual maximum power is expressed as follows:

例如，Tdelay取決於內部延遲、柵極電荷以及與柵極驅動器130有關的電路。在另一示例中，對於預定的開關模式轉換器100，Tdelay是恒定的，因此實際最大功率取決於整流後電容上的電壓。為了補償實際最大功率的變化，用於過流保護的閾值應當基於整流後電容上的電壓及輸出延遲被調節。 For example, Tdelay depends on internal delay, gate charge, and circuitry associated with gate driver 130. In another example, for a predetermined switch mode converter 100, Tdelay is constant, so the actual maximum power is dependent on the voltage across the rectified capacitor. In order to compensate for the actual maximum power variation, the threshold for overcurrent protection should be adjusted based on the voltage on the rectified capacitor and the output delay.

第3圖是示出電流閾值與整流後電容上的電壓之間的傳統關係的簡化圖式。整流後電容上的電壓Vin2低於整流後電容上的電壓Vin1，並且針對Vin2的電流閾值Ith_oc_vin2大於針對Vin1的Ith_oc_vin1，如第3圖所示。在電流閾值處，過流保護被觸發。所得到的針對較高Vin的最大電流IPEAK1與所得到的針對較低Vin的最大電流IPEAK2相同。 Figure 3 is a simplified diagram showing the conventional relationship between the current threshold and the voltage across the rectified capacitor. After the rectified voltage V in2 is lower than the capacitor voltage across the capacitor V in1 rectifier, and greater than I th_oc_vin1 for V in1 for current threshold I th_oc_vin2 V in2, as shown in Fig. 3. At the current threshold, overcurrent protection is triggered. The resulting maximum current I PEAK1 for the higher V in is the same as the resulting maximum current I PEAK2 for the lower V in .

例如，該電流閾值與整流後電容上的電壓具有如下關係： 其中，Ith_oc是電流閾值，Vin是整流後電容上的電壓，Lp是初級繞組的電感，並且Tdelay是“輸出延遲”。另外，Ith_oc(Vin1)是針對整流後電容上的電壓Vin1預先確定的電流閾值。例如，Vin1是最小整流後電容上的電壓。在另一示例中，流經開關和初級繞組的電流被感測。如果感測到的電流達到Ith_oc，則PWM控制器元件發送信號以關斷開關。在“輸出延遲”之後，開關關斷。 For example, the current threshold has the following relationship with the voltage across the rectified capacitor: Where I th — oc is the current threshold, V in is the voltage across the rectified capacitor, L p is the inductance of the primary winding, and T delay is the “output delay”. In addition, I th — oc (V in1 ) is a current threshold predetermined for the voltage V in1 on the rectified capacitor. For example, V in1 is the voltage across the minimum rectified capacitance. In another example, the current flowing through the switch and the primary winding is sensed. If the sensed current reaches Ith_oc , the PWM controller component sends a signal to turn off the switch. After the "output delay", the switch is turned off.

在式6中，第二項表示補償“輸出延遲”的影響的 閾值偏移。第4圖是示出閾值偏移與整流後電容上的電壓之間的傳統關係 的簡化圖式。如第4圖所示，項是取決於“輸出延遲”和初級繞組的電感 的斜率。如第4圖所示，電流閾值隨著整流後電容上的電壓的增大而減小。 In Equation 6, the second term Represents the threshold offset that compensates for the effects of the "output delay." Figure 4 is a simplified diagram showing the conventional relationship between the threshold offset and the voltage across the rectified capacitor. As shown in Figure 4, the item It is dependent on the "output delay" and the slope of the inductance of the primary winding. As shown in Figure 4, the current threshold decreases as the voltage across the rectified capacitor increases.

有至少兩種傳統方法用來將電流閾值實現為根據第4圖的整流後電容上的電壓的函數。在一個示例中，整流後電容上的電壓被感測以生成與整流後電容上的電壓成比例的偏移DC電壓，以補償如式6所示的“輸出延遲”的影響。 There are at least two conventional methods for implementing the current threshold as a function of the voltage across the rectified capacitor of Figure 4. In one example, the voltage on the rectified capacitor is sensed to generate an offset DC voltage that is proportional to the voltage on the rectified capacitor to compensate for the effects of "output delay" as shown in Equation 6.

在另一示例中，基於PWM信號的最大寬度來感測整流後電容上的電壓。PWM信號被應用於與電源轉換器的初級繞組串聯的開關的柵極。第5圖是示出PWM信號最大寬度與整流後電容上的電壓之間的傳統關係的簡化圖式。如第5圖所示，最大電流相對於整流後電容上的電壓是恒定的，並且PWM信號的最大寬度隨著整流後電容上的電壓而變化。最大電流IPEAK1等於最大電流IPEAK2。最大電流IPEAK1對應於較高的整流後電容上的電壓和PWM信號510，並且最大電流IPEAK2對應於較低的整流後電容上的電壓和PWM信號520。如第5圖所示，PWM信號510的最大寬度對於較高的整流後電容上的電壓來說較窄，並且PWM信號520的最大寬度對於較低整流後電容上的電壓來說較寬。如果最大電流相對於整流後電容上的電壓是恒定的，則整流後電容上的電壓用PWM信號的最大寬度來表示。因此，PWM信號的最大寬度可被用來確定閾值偏移以補償如式6所示的“輸出延遲”的影響。 In another example, the voltage across the rectified capacitor is sensed based on the maximum width of the PWM signal. The PWM signal is applied to the gate of a switch in series with the primary winding of the power converter. Figure 5 is a simplified diagram showing the conventional relationship between the maximum width of the PWM signal and the voltage across the rectified capacitor. As shown in Figure 5, the maximum current is constant relative to the voltage across the rectified capacitor, and the maximum width of the PWM signal varies with the voltage across the rectified capacitor. The maximum current I PEAK1 is equal to the maximum current I PEAK2 . The maximum current I PEAK1 corresponds to the voltage on the higher rectified capacitor and the PWM signal 510, and the maximum current I PEAK2 corresponds to the voltage on the lower rectified capacitor and the PWM signal 520. As shown in FIG. 5, the maximum width of the PWM signal 510 is narrower for the higher voltage on the rectified capacitor, and the maximum width of the PWM signal 520 is wider for the voltage on the lower rectified capacitor. If the maximum current is constant relative to the voltage across the rectified capacitor, the voltage across the rectified capacitor is represented by the maximum width of the PWM signal. Therefore, the maximum width of the PWM signal can be used to determine the threshold offset to compensate for the effects of the "output delay" as shown in Equation 6.

根據第5圖，可以通過生成電流閾值Ith_oc來實現補償，該 電流閾值Ith_oc是PWM信號的最大寬度的函數。例如，對於PWM信號510，電流閾值等於Ith_oc_1，並且對於PWM信號520，電流閾值等於Ith_oc_2。在另一示例中，相對於最大寬度的Ith_oc的斜率被合適地選擇以補償如式6所示的“輸出延遲”的影響。所選斜率與用於PWM控制的晶片之外的電源轉換器元件有關。外部元件可以包括初級繞組、電流感測電阻器和功率MOSFET。 According to FIG. 5, the compensation may be achieved by generating a current threshold I th_oc, the current threshold I th_oc is a function of the maximum width of the PWM signal. For example, for PWM signal 510, the current threshold is equal to Ith_oc_1 , and for PWM signal 520, the current threshold is equal to Ith_oc_2 . In another example, the slope of Ith_oc relative to the maximum width is suitably selected to compensate for the effects of "output delay" as shown in Equation 6. The selected slope is related to the power converter components outside the wafer for PWM control. The external components can include a primary winding, a current sensing resistor, and a power MOSFET.

另外，為了獲得高效率，電源轉換器通常在低的整流後電容上的電壓時在CCM模式中工作，在高的整流後電容上的電壓時在DCM模式中工作。第6圖示出了CCM模式和DCM模式中的初級繞組的簡化傳統電流曲線。這些電流曲線描述了作為時間的函數的電流大小。如第6A圖所示，初級繞組的電流在DCM模式中在每個週期在一脈衝寬度內從I_L增大到電流限制I_p1。例如，I_L等於零。在每個週期傳遞到負載的能量為 In addition, in order to achieve high efficiency, the power converter typically operates in CCM mode at low voltages on the rectified capacitor and in DCM mode at high voltages on the rectified capacitor. Figure 6 shows a simplified conventional current curve for the primary winding in CCM mode and DCM mode. These current curves describe the magnitude of the current as a function of time. As shown in Fig. 6A, the current of the primary winding increases from I_L to current limit I_p1 in one pulse period in DCM mode. For example, I_L is equal to zero. The energy delivered to the load in each cycle is

相比之下，如第6B圖所示，初級繞組的電流在CCM模式中在每個週期在一脈衝寬度內從I_i2增大到電流限制I_p2。例如，I_i2大於零。在每個週期傳遞到負載的能量為 其中，比率可隨著整流後電容上的電壓變化。例如，該比率隨著整流後電容上的電壓的減小而增大。如式7和式8所描述的，如果兩個電流限制I_p1和I_p2相等，則在每個週期中，在DCM模式中傳遞到負載的能量的量高於在CCM模式中傳遞到負載的能量的量。 In contrast, as shown in FIG. 6B, the current of the primary winding increases from I_i2 to the current limit I_p2 in a pulse width in each cycle in the CCM mode. For example, I_i2 is greater than zero. The energy delivered to the load in each cycle is Where the ratio It can vary with the voltage across the rectified capacitor. For example, the ratio increases as the voltage across the rectified capacitor decreases. As described in Equations 7 and 8, if the two current limits I_p1 and I_p2 are equal, then in each cycle, the amount of energy delivered to the load in the DCM mode is higher than the energy delivered to the load in the CCM mode. the amount.

第7圖示出了作為整流後電容上的電壓的傳統函數的在每個週期中傳遞到負載的最大能量的簡化圖式。作為整流後電容上的電壓的函數，等於I_p1或I_p2的電流限制被調節以補償如第4圖所示的“輸出延遲”，但是式7和式8之間的差異未被考慮在內。此外，第7圖似乎並未考慮到比率的變化。因此，最大能量在整流後電容上的電壓的整個範圍中不是恒定的。例如，如曲線1300所示，雖然在DCM模式中最大能量似乎基本上恒定，但是在CCM模式中最大能量隨著整流後電容上的電壓的減小而急劇減小。 Figure 7 shows a simplified diagram of the maximum energy delivered to the load in each cycle as a traditional function of the voltage across the rectified capacitor. As a function of the voltage across the rectified capacitor, the current limit equal to I_p1 or I_p2 is adjusted to compensate for the "output delay" as shown in Figure 4, but the difference between Equations 7 and 8 is not taken into account. In addition, Figure 7 does not seem to take into account the ratio. The change. Therefore, the maximum energy is not constant over the entire range of voltages across the rectified capacitor. For example, as shown by curve 1300, although the maximum energy appears to be substantially constant in the DCM mode, the maximum energy in the CCM mode decreases sharply as the voltage across the rectified capacitance decreases.

為了提高CCM模式和DCM模式中最大能量的一致性，可以在不同模式中使用於電流閾值或相應的電壓閾值的補償斜率不同。具體地，如式7和式8所示，CCM模式中的補償斜率在大小上大於DCM模式中的補償斜率。 In order to increase the consistency of the maximum energy in the CCM mode and the DCM mode, the compensation slopes used for the current threshold or the corresponding voltage threshold may be different in different modes. Specifically, as shown in Equations 7 and 8, the compensation slope in the CCM mode is larger in magnitude than the compensation slope in the DCM mode.

但是，電源轉換器的最大能量可能也受系統的其它特性的影響。因此，改善用於過流保護和過功率保護的技術變得非常重要。 However, the maximum energy of the power converter may also be affected by other characteristics of the system. Therefore, it is very important to improve the technology for overcurrent protection and overpower protection.

本發明涉及積體電路。更具體地，本發明提供了對於過流保護和過功率保護的控制系統和方法。僅僅作為示例，本發明已應用於電源轉換器。但是將認識到，本發明具有更廣泛的應用範圍。 The present invention relates to an integrated circuit. More specifically, the present invention provides control systems and methods for overcurrent protection and overpower protection. Merely by way of example, the invention has been applied to power converters. However, it will be appreciated that the invention has a broader range of applications.

根據一實施例，一種用於保護電源轉換器的系統控制器包括信號生成器、比較器以及調製和驅動元件。信號生成器被配置為生成閾值信號。比較器，被配置為接收所述閾值信號以及電流感測信號，並且至少基於與所述閾值信號和所述電流感測信號相關聯的資訊生成比較信號，所述電流感測信號指示流經電源轉換器的初級繞組的初級電流的大小。調製和驅動元件被耦合到所述信號生成器並被配置為至少接收所述比較信號，至少基於與所述比較信號相關聯的資訊生成驅動信號，並且向開關輸出所述驅動信號以影響所述初級電流，所述驅動信號與一個或多個第一開關時程以及在所述一個或多個第一開關時程之後的第二開關時程相關聯，所述一個或多個第一開關時程對應於一個或多個第一占空比。所述信號生成器還被配置為，在所述第二開關時程中，至少基於與所述一個或多個第一占空比相關聯的資訊確定第一閾值信號值；以及生成與所確定的第一閾值信號值相等的所述閾值信號，所述閾值信號在所述第二開關時程中作為時間的函數在大小上是恒定的。 According to an embodiment, a system controller for protecting a power converter includes a signal generator, a comparator, and a modulation and drive component. The signal generator is configured to generate a threshold signal. a comparator configured to receive the threshold signal and a current sense signal and generate a comparison signal based on at least information associated with the threshold signal and the current sense signal, the current sense signal indicating flow through a power source The magnitude of the primary current of the primary winding of the converter. A modulation and drive element is coupled to the signal generator and configured to receive at least the comparison signal, generate a drive signal based on at least information associated with the comparison signal, and output the drive signal to a switch to affect the Primary current, the drive signal being associated with one or more first switch time periods and a second switch time history after the one or more first switch time periods, the one or more first switch times The process corresponds to one or more first duty cycles. The signal generator is further configured to determine a first threshold signal value based on at least information associated with the one or more first duty cycles in the second switching time course; and generating and determining The threshold signal is equal to the first threshold signal value, the threshold signal being constant in magnitude as a function of time in the second switching time course.

根據另一實施例，一種用於保護電源轉換器的系統控制器包括：信號生成器、比較器以及調製和驅動元件。信號生成器被配置為生成閾值信號。比較器被配置為接收所述閾值信號以及電流感測信號，並且至少基於與所述閾值信號和所述電流感測信號相關聯的資訊生成比較信號，所述電流感測信號指示流經電源轉換器的初級繞組的初級電流的大小。調 製和驅動元件，被耦合到所述信號生成器並被配置為至少接收所述比較信號，至少基於與所述比較信號相關聯的資訊生成驅動信號，並且向開關輸出所述驅動信號以影響所述初級電流，所述驅動信號與一個或多個第一開關時程以及在所述一個或多個第一開關時程之後的第二開關時程相關聯，所述一個或多個第一開關時程對應於一個或多個第一占空比，所述第二開關時程包括導通時間和關斷時間。所述信號生成器還被配置為，在所述第二開關時程中，至少基於與所述一個或多個第一占空比相關聯的資訊確定第一閾值信號值；在所述導通時間的開始處將時間設為零；如果該時間滿足一個或多個第一預定條件，則生成與所確定的第一閾值信號值相等的所述閾值信號，以使得所述閾值信號作為時間的函數在大小上是恒定的；以及如果該時間滿足一個或多個第二預定條件，則生成所述閾值信號以使得所述閾值信號的大小隨著時間的增長而減小。 In accordance with another embodiment, a system controller for protecting a power converter includes a signal generator, a comparator, and a modulation and drive component. The signal generator is configured to generate a threshold signal. A comparator is configured to receive the threshold signal and a current sense signal and generate a comparison signal based on at least information associated with the threshold signal and the current sense signal, the current sense signal indicating a flow through power conversion The primary current of the primary winding of the device. Tune And a driving component coupled to the signal generator and configured to receive at least the comparison signal, generate a drive signal based on at least information associated with the comparison signal, and output the drive signal to a switch to affect Primary current, the drive signal being associated with one or more first switch time periods and a second switch time history after the one or more first switch time periods, the one or more first switches The time history corresponds to one or more first duty cycles, and the second switch time history includes an on time and an off time. The signal generator is further configured to determine a first threshold signal value based on at least information associated with the one or more first duty cycles in the second switching time course; The time is set to zero at the beginning; if the time satisfies one or more first predetermined conditions, the threshold signal equal to the determined first threshold signal value is generated such that the threshold signal is a function of time The size is constant; and if the time satisfies one or more second predetermined conditions, the threshold signal is generated such that the magnitude of the threshold signal decreases over time.

根據又一實施例，一種用於保護電源轉換器的系統控制器包括：信號生成器、比較器以及調製和驅動元件。信號生成器被配置為生成閾值信號。比較器被配置為接收所述閾值信號以及電流感測信號，並且至少基於與所述閾值信號和所述電流感測信號相關聯的資訊生成比較信號，所述電流感測信號指示流經電源轉換器的初級繞組的初級電流的大小。調製和驅動元件，被耦合到所述信號生成器並被配置為至少接收所述比較信號，至少基於與所述比較信號相關聯的資訊生成驅動信號，並且向開關輸出所述驅動信號以影響所述初級電流，所述驅動信號與一個或多個第一開關時程以及在所述一個或多個第一開關時程之後的第二開關時程相關聯，所述一個或多個第一開關時程對應於一個或多個第一占空比，所述第二開關時程包括導通時間和關斷時間。所述信號生成器還被配置為，在所述第二開關時程中，至少基於與所述一個或多個第一占空比相關聯的資訊確定第一閾值信號值；在所述導通時間的開始處將時間設為零；以及如果該時間滿足一個或多個第一預定條件，則生成所述閾值信號以使得所述閾值信號的大小隨著時間的增長從所確定的第一閾值信號值減小。 In accordance with yet another embodiment, a system controller for protecting a power converter includes a signal generator, a comparator, and a modulation and drive component. The signal generator is configured to generate a threshold signal. A comparator is configured to receive the threshold signal and a current sense signal and generate a comparison signal based on at least information associated with the threshold signal and the current sense signal, the current sense signal indicating a flow through power conversion The primary current of the primary winding of the device. a modulation and drive component coupled to the signal generator and configured to receive at least the comparison signal, generate a drive signal based on at least information associated with the comparison signal, and output the drive signal to a switch to affect Primary current, the drive signal being associated with one or more first switch time periods and a second switch time history after the one or more first switch time periods, the one or more first switches The time history corresponds to one or more first duty cycles, and the second switch time history includes an on time and an off time. The signal generator is further configured to determine a first threshold signal value based on at least information associated with the one or more first duty cycles in the second switching time course; Setting the time to zero; and if the time satisfies one or more first predetermined conditions, generating the threshold signal such that the magnitude of the threshold signal increases from time from the determined first threshold signal The value is reduced.

根據又一實施例，一種用於保護電源轉換器的系統控制器包括：信號生成器、比較器以及調製和驅動元件。信號生成器被配置為生成 閾值信號。比較器被配置為接收所述閾值信號以及電流感測信號，並且至少基於與所述閾值信號和所述電流感測信號相關聯的資訊生成比較信號，所述電流感測信號指示流經電源轉換器的初級繞組的初級電流的大小。調製和驅動元件，被耦合到所述信號生成器並被配置為至少接收所述比較信號，至少基於與所述比較信號相關聯的資訊生成驅動信號，並且向開關輸出所述驅動信號以影響所述初級電流，所述驅動信號與多個開關時程相關聯，所述多個開關時程的每個包括導通時間和關斷時間。所述信號生成器還被配置為，在所述多個開關時程之中，在所述導通時間的開始處將時間設為零；如果該時間滿足一個或多個第一預定條件，則生成所述閾值信號，以使得所述閾值信號的大小隨著時間的增長而增大；以及如果該時間滿足一個或多個第二預定條件，則生成所述閾值信號以使得所述閾值信號的大小隨著時間的增長而減小。 In accordance with yet another embodiment, a system controller for protecting a power converter includes a signal generator, a comparator, and a modulation and drive component. Signal generator is configured to generate Threshold signal. A comparator is configured to receive the threshold signal and a current sense signal and generate a comparison signal based on at least information associated with the threshold signal and the current sense signal, the current sense signal indicating a flow through power conversion The primary current of the primary winding of the device. a modulation and drive component coupled to the signal generator and configured to receive at least the comparison signal, generate a drive signal based on at least information associated with the comparison signal, and output the drive signal to a switch to affect The primary current is associated with a plurality of switching time courses, each of the plurality of switching time periods including an on time and an off time. The signal generator is further configured to, in the plurality of switch schedules, set a time to zero at the beginning of the on time; if the time satisfies one or more first predetermined conditions, generate the a threshold signal such that the magnitude of the threshold signal increases over time; and if the time satisfies one or more second predetermined conditions, the threshold signal is generated such that the magnitude of the threshold signal follows The time increases and decreases.

根據又一實施例，一種用於保護電源轉換器的信號生成器包括：調製和驅動元件、斜坡信號生成器、採樣信號生成器以及採樣和保持組件。調製和驅動元件被配置為生成調製信號以向開關輸出驅動信號從而影響流經電源轉換器的初級繞組的初級電流。斜坡信號生成器被配置為接收所述調製信號並且至少基於與所述調製信號相關聯的資訊生成斜坡信號。採樣信號生成器被配置為接收所述調製信號並且回應於所述調製信號的下降沿而生成包含脈衝的採樣信號。採樣和保持元件被配置為接收所述採樣信號和所述斜坡信號，並且輸出與所述採樣信號的所述脈衝相應的、與所述斜坡信號的大小相關聯的採樣和保持信號。 In accordance with yet another embodiment, a signal generator for protecting a power converter includes a modulation and drive component, a ramp signal generator, a sampled signal generator, and a sample and hold component. The modulation and drive elements are configured to generate a modulated signal to output a drive signal to the switch to affect a primary current flowing through the primary winding of the power converter. A ramp signal generator is configured to receive the modulated signal and generate a ramp signal based on at least information associated with the modulated signal. A sampled signal generator is configured to receive the modulated signal and generate a sampled signal comprising a pulse in response to a falling edge of the modulated signal. A sample and hold element is configured to receive the sampled signal and the ramp signal and output a sample and hold signal associated with the pulse of the sampled signal and associated with a magnitude of the ramp signal.

根據又一實施例，一種用於保護電源轉換器的信號生成器包括：調製和驅動元件、斜坡信號生成器、採樣和保持元件、濾波器信號生成器以及低通濾波器。調製和驅動元件被配置為生成調製信號以向開關輸出驅動信號從而影響流經電源轉換器的初級繞組的初級電流。斜坡信號生成器被配置為接收所述調製信號並且至少基於與所述調製信號相關聯的資訊生成斜坡信號。採樣和保持元件被配置為接收所述斜坡信號和所述調製信號，並且回應於所述調製信號輸出與所述斜坡信號的大小相關聯的採樣和保持信號。濾波器信號生成器被配置為接收所述調製信號並且至少基於 與所述調製信號相關聯的資訊生成濾波器信號。低通濾波器被配置為接收所述濾波器信號和所述採樣和保持信號並且回應於所述濾波器信號，至少基於與所述採樣和保持信號相關聯的資訊生成第一信號。 In accordance with yet another embodiment, a signal generator for protecting a power converter includes a modulation and drive component, a ramp signal generator, a sample and hold component, a filter signal generator, and a low pass filter. The modulation and drive elements are configured to generate a modulated signal to output a drive signal to the switch to affect a primary current flowing through the primary winding of the power converter. A ramp signal generator is configured to receive the modulated signal and generate a ramp signal based on at least information associated with the modulated signal. A sample and hold element is configured to receive the ramp signal and the modulation signal and output a sample and hold signal associated with a magnitude of the ramp signal in response to the modulation signal. A filter signal generator is configured to receive the modulated signal and based at least on Information associated with the modulated signal generates a filter signal. A low pass filter is configured to receive the filter signal and the sample and hold signal and to generate a first signal based on at least information associated with the sample and hold signal in response to the filter signal.

在一個實施例中，一種用於保護電源轉換器的方法包括：生成閾值信號；接收所述閾值信號以及電流感測信號，所述電流感測信號指示流經電源轉換器的初級繞組的初級電流的大小；以及至少基於與所述閾值信號和所述電流感測信號相關聯的資訊生成比較信號。另外，該方法包括：至少接收所述比較信號；至少基於與所述比較信號相關聯的資訊生成驅動信號，所述驅動信號與一個或多個第一開關時程以及在所述一個或多個第一開關時程之後的第二開關時程相關聯，所述一個或多個第一開關時程對應於一個或多個第一占空比；以及向開關輸出所述驅動信號以影響所述初級電流。用於生成閾值信號的處理包括：在所述第二開關時程中，至少基於與所述一個或多個占空比相關聯的資訊確定閾值信號值；以及生成與所確定的閾值信號值相等的所述閾值信號，所述閾值信號在所述第二開關時程中作為時間的函數在大小上是恒定的。 In one embodiment, a method for protecting a power converter includes: generating a threshold signal; receiving the threshold signal and a current sense signal indicative of a primary current flowing through a primary winding of a power converter a size; and generating a comparison signal based at least on information associated with the threshold signal and the current sense signal. Additionally, the method includes: receiving at least the comparison signal; generating a drive signal based on at least information associated with the comparison signal, the drive signal and one or more first switch schedules and in the one or more Associated with a second switching time history after the first switching time period, the one or more first switching time periods corresponding to one or more first duty cycles; and outputting the driving signal to the switch to affect the Primary current. The process for generating a threshold signal includes determining, in the second switching time history, a threshold signal value based on at least information associated with the one or more duty cycles; and generating a value equal to the determined threshold signal value The threshold signal is constant in magnitude as a function of time in the second switching time course.

在另一實施例中，一種用於保護電源轉換器的方法包括：生成閾值信號；接收所述閾值信號以及電流感測信號，所述電流感測信號指示流經電源轉換器的初級繞組的初級電流的大小；以及至少基於與所述閾值信號和所述電流感測信號相關聯的資訊生成比較信號。該方法還包括：至少接收所述比較信號；至少基於與所述比較信號相關聯的資訊生成驅動信號，所述驅動信號與一個或多個第一開關時程以及在所述一個或多個第一開關時程之後的第二開關時程相關聯，所述一個或多個第一開關時程對應於一個或多個第一占空比，所述第二開關時程包括導通時間和關斷時間；以及向開關輸出所述驅動信號以影響所述初級電流。用於生成閾值信號的處理包括：在所述第二開關時程中，至少基於與所述一個或多個占空比相關聯的資訊確定閾值信號值；在所述導通時間的開始處將時間設為零；如果該時間滿足一個或多個第一預定條件，則生成與所確定的閾值信號值相等的所述閾值信號，以使得所述閾值信號作為時間的函數在大小上是恒定的；以及如果該時間滿足一個或多個第二預定條件，則生成所述閾 值信號以使得所述閾值信號的大小隨著時間的增長而減小。 In another embodiment, a method for protecting a power converter includes: generating a threshold signal; receiving the threshold signal and a current sense signal indicative of a primary flowing through a primary winding of a power converter a magnitude of the current; and generating a comparison signal based at least on information associated with the threshold signal and the current sense signal. The method also includes receiving at least the comparison signal, generating a drive signal based on at least information associated with the comparison signal, the drive signal and one or more first switch schedules and in the one or more Associated with a second switching time history after a switching time period, the one or more first switching time periods corresponding to one or more first duty cycles, the second switching time history including an on time and a turn-off And outputting the drive signal to the switch to affect the primary current. The process for generating a threshold signal includes determining a threshold signal value based on at least information associated with the one or more duty cycles in the second switching time course; time at a beginning of the on time Set to zero; if the time satisfies one or more first predetermined conditions, generating the threshold signal equal to the determined threshold signal value such that the threshold signal is constant in magnitude as a function of time; And generating the threshold if the time satisfies one or more second predetermined conditions The value signal is such that the magnitude of the threshold signal decreases over time.

在又一實施例中，一種用於保護電源轉換器的方法包括：生成閾值信號；接收所述閾值信號以及電流感測信號，所述電流感測信號指示流經電源轉換器的初級繞組的初級電流的大小；以及至少基於與所述閾值信號和所述電流感測信號相關聯的資訊生成比較信號。該方法還包括：至少接收所述比較信號；至少基於與所述比較信號相關聯的資訊生成驅動信號，所述驅動信號與一個或多個第一開關時程以及在所述一個或多個第一開關時程之後的第二開關時程相關聯，所述一個或多個第一開關時程對應於一個或多個第一占空比，所述第二開關時程包括導通時間和關斷時間；以及向開關輸出所述驅動信號以影響所述初級電流。用於生成閾值信號的處理包括：在所述第二開關時程中，至少基於與所述一個或多個占空比相關聯的資訊確定閾值信號值；在所述導通時間的開始處將時間設為零；以及如果該時間滿足一個或多個預定條件，則生成所述閾值信號以使得所述閾值信號的大小隨著時間的增長從所確定的閾值信號值減小。 In yet another embodiment, a method for protecting a power converter includes: generating a threshold signal; receiving the threshold signal and a current sense signal, the current sense signal indicating a primary flowing through a primary winding of the power converter a magnitude of the current; and generating a comparison signal based at least on information associated with the threshold signal and the current sense signal. The method also includes receiving at least the comparison signal, generating a drive signal based on at least information associated with the comparison signal, the drive signal and one or more first switch schedules and in the one or more Associated with a second switching time history after a switching time period, the one or more first switching time periods corresponding to one or more first duty cycles, the second switching time history including an on time and a turn-off And outputting the drive signal to the switch to affect the primary current. The process for generating a threshold signal includes determining a threshold signal value based on at least information associated with the one or more duty cycles in the second switching time course; time at a beginning of the on time Set to zero; and if the time satisfies one or more predetermined conditions, the threshold signal is generated such that the magnitude of the threshold signal decreases from the determined threshold signal value over time.

在又一實施例中，一種用於保護電源轉換器的方法包括：生成閾值信號；接收所述閾值信號以及電流感測信號，所述電流感測信號指示流經電源轉換器的初級繞組的初級電流的大小；以及至少基於與所述閾值信號和所述電流感測信號相關聯的資訊生成比較信號。該方法還包括：至少所述比較信號相關聯的資訊生成驅動信號，所述驅動信號與多個開關時程相關聯，所述多個開關時程的每個包括導通時間和關斷時間；以及向開關輸出所述驅動信號以影響所述初級電流。用於生成閾值信號的處理包括：在所述多個開關時程之中，在所述導通時間的開始處將時間設為零；如果該時間滿足一個或多個第一預定條件，則生成所述閾值信號，以使得所述閾值信號的大小隨著時間的增長而增大；以及如果該時間滿足一個或多個第二預定條件，則生成所述閾值信號以使得所述閾值信號的大小隨著時間的增長而減小。 In yet another embodiment, a method for protecting a power converter includes: generating a threshold signal; receiving the threshold signal and a current sense signal, the current sense signal indicating a primary flowing through a primary winding of the power converter a magnitude of the current; and generating a comparison signal based at least on information associated with the threshold signal and the current sense signal. The method also includes generating, at least at least information associated with the comparison signal, a drive signal, the drive signal being associated with a plurality of switch time periods, each of the plurality of switch time periods including an on time and an off time; The drive signal is output to a switch to affect the primary current. The processing for generating the threshold signal includes: setting the time to zero at the beginning of the on time among the plurality of switch schedules; generating the threshold if the time satisfies one or more first predetermined conditions Signaling such that the magnitude of the threshold signal increases over time; and if the time satisfies one or more second predetermined conditions, generating the threshold signal such that the magnitude of the threshold signal is over time The growth is decreasing.

在又一實施例中，一種用於生成用於保護電源轉換器的信號的方法包括生成調製信號以向開關輸出驅動信號從而影響流經電源轉換器的初級繞組的初級電流；接收所述調製信號；以及處理與所述調製信號相 關聯的資訊。該方法還包括：至少基於與所述調製信號相關聯的資訊生成斜坡信號；回應於所述調製信號的下降沿而生成包含脈衝的採樣信號；接收所述採樣信號和所述斜坡信號；以及輸出與所述採樣信號的所述脈衝相應的、與所述斜坡信號的大小相關聯的採樣和保持信號。 In yet another embodiment, a method for generating a signal for protecting a power converter includes generating a modulated signal to output a drive signal to a switch to affect a primary current flowing through a primary winding of the power converter; receiving the modulated signal And processing the modulated signal Associated information. The method also includes generating a ramp signal based on at least information associated with the modulated signal; generating a sampled signal comprising the pulse in response to a falling edge of the modulated signal; receiving the sampled signal and the ramp signal; and outputting A sample and hold signal associated with the pulse of the sampled signal and associated with the magnitude of the ramp signal.

在又一實施例中，一種用於生成用於保護電源轉換器的信號的方法包括：生成調製信號以向開關輸出驅動信號從而影響流經電源轉換器的初級繞組的初級電流；接收所述調製信號；以及處理與所述調製信號相關聯的資訊。該方法還包括：至少基於與所述調製信號相關聯的資訊生成斜坡信號；至少基於與所述調製信號相關聯的資訊生成濾波器信號；以及接收所述斜坡信號和所述調製信號。另外，該方法包括：回應於所述調製信號輸出與所述斜坡信號的大小相關聯的採樣和保持信號；接收所述濾波器信號以及所述採樣和保持信號；以及回應於所述濾波器信號，至少基於與所述採樣和保持信號相關聯的資訊生成第一信號。 In yet another embodiment, a method for generating a signal for protecting a power converter includes generating a modulated signal to output a drive signal to a switch to affect a primary current flowing through a primary winding of the power converter; receiving the modulation a signal; and processing information associated with the modulated signal. The method also includes generating a ramp signal based on at least information associated with the modulated signal; generating a filter signal based on at least information associated with the modulated signal; and receiving the ramp signal and the modulated signal. Additionally, the method includes: outputting a sample and hold signal associated with a magnitude of the ramp signal in response to the modulation signal; receiving the filter signal and the sample and hold signal; and responsive to the filter signal Generating a first signal based at least on information associated with the sample and hold signal.

取決於實施例，可以獲得一個或多個益處。參考下面的詳細描述和附圖可以全面地理解本發明的這些益處以及各個另外的目的、特徵和優點。 One or more benefits may be obtained depending on the embodiment. These and other additional objects, features and advantages of the present invention will be fully understood from the description and appended claims.

100‧‧‧開關模式轉換器 100‧‧‧Switch mode converter

110,2510‧‧‧過流保護(OCP)比較器 110,2510‧‧‧Overcurrent protection (OCP) comparator

112,2512‧‧‧過流閾值信號 112, 2512‧‧‧Overcurrent threshold signal

114,2514‧‧‧電流感測信號 114,2514‧‧‧ Current sensing signal

116,2516‧‧‧過流控制信號 116,2516‧‧‧Overcurrent control signal

122,510,520,2522‧‧‧PWM信號 122,510,520,2522‧‧‧PWM signal

120,2520‧‧‧PWM控制器元件 120,2520‧‧‧PWM controller components

130,2530‧‧‧柵極驅動器 130,2530‧‧‧gate driver

140,1804,1812,1820,1932,1934,2540,2604,2612,2620,2654,2932,2934‧‧‧開關 140,1804,1812,1820,1932,1934,2540,2604,2612,2620,2654,2932,2934‧‧

150,152,154,156,1822,2550,2552,2554,2556‧‧‧電阻器 150,152,154,156,1822,2550,2552,2554,2556‧‧‧Resistors

160,2560‧‧‧初級繞組 160,2560‧‧‧Primary winding

180,2580‧‧‧晶片 180, 2580‧‧‧ wafer

190,2590‧‧‧節點 190, 2590‧‧‧ nodes

1300,2810,2820,2830,2840,2910,2920,2930,2940,3010,3020‧‧‧曲線 1300, 2810, 2820, 2830, 2840, 2910, 2920, 2930, 2940, 3010, 3020‧ ‧ curves

1202,1204,1206,1208,1210,1312,1314,1316,1318,1320,1322,1324,1326,1402,1404,1406,1408,1410,1412,1414,1416,1502,1504,1506,1508,1510,1512,1514,1516,1700,1702,1704,1706,1708,2000,2002,2004,2006,2008,2200,2202,2204,2206,2208,2210,2400,2402,2404,2406,2408‧‧‧波形 1202, 1204, 1206, 1208, 1210, 1312, 1314, 1316, 1318, 1320, 1322, 1324, 1326, 1402, 1404, 1406, 1408, 1410, 1412, 1414, 1416, 1502, 1504, 1506, 1508, 1510, 1512, 1514, 1516, 1700, 1702, 1704, 1706, 1708, 2000, 2002, 2004, 2006, 2008, 2200, 2202, 2204, 2206, 2208, 2210, 2400, 2402, 2404, 2406, 2408 ‧‧ Waveform

1601,1901,2801,2901‧‧‧信號處理元件 1601,1901,2801,2901‧‧‧Signal Processing Components

1602,1902,2102,2302‧‧‧採樣信號生成器 1602, 1902, 2102, 2302‧‧‧Sampling signal generator

1604,1904,2104,2304,2804,2904‧‧‧信號生成器 1604, 1904, 2104, 2304, 2804, 2904‧‧‧Signal Generator

1606,1906,2106,2306,2806,2906‧‧‧採樣和保持元件 1606, 1906, 2106, 2306, 2806, 2906‧‧‧Sampling and holding components

1608,1908,2808,2908‧‧‧低通濾波器 1608, 1908, 2808, 2908‧‧‧ low pass filter

1614,1914,2114,2314,2814,2914‧‧‧斜坡信號 1614,1914,2114,2314,2814,2914‧‧‧Ramp signal

1616,1916,2116,2316‧‧‧採樣信號 1616, 1916, 2116, 2316‧‧‧Sampling signals

1618,1826,1832,1836,1838,1918,2582,2626,2632,2636,2638,2818,2918‧‧‧信號 1618, 1826, 1832, 1836, 1838, 1918, 2582, 2626, 2632, 2636, 2638, 2818, 2918‧‧ signals

1710,1712,1714,1716,1718,1720,1722,1724,2010,2012,2014,2016,2018,2024,2026,2028,2030,2032,2212,2214,2216,2218,2220,2222,2224,2412,2414,2416,2418,2420,2422,2422,2424‧‧‧大小 1710,1712,1714,1716,1718,1720,1722,1724,2010,2012,2014,2016,2018,2024,2026,2028,2030,2032,2212,2214,2216,2218,2220,2222,2224, 2412, 2414, 2416, 2418, 2420, 2422, 2422, 2424‧‧‧ size

1802,2602‧‧‧電流源 1802, 2602‧‧‧ current source

1806,1814,2606,2614‧‧‧及閘 1806, 1814, 2606, 2614‧‧ and gates

1808,1816,2608,2616‧‧‧比較器 1808, 1816, 2608, 2616‧‧‧ comparator

1810,1824,2610,2624,2656‧‧‧電容器 1810, 1824, 2610, 2624, 2656‧‧ ‧ capacitor

1828,2572,2628‧‧‧電流 1828, 2572, 2628‧‧‧ Current

1818,2618‧‧‧運算放大器 1818,2618‧‧‧Operational Amplifier

1830,1834,2630,2634‧‧‧參考信號 1830, 1834, 2630, 2634‧‧‧ reference signals

1840,2640‧‧‧放電信號 1840, 2640‧‧‧discharge signal

1926,2126,2926‧‧‧占空比檢測器 1926, 2126, 2926‧‧‧ Duty cycle detector

1928,2928‧‧‧計數器元件 1928, 2928‧‧‧ counter components

1930,2650,2930‧‧‧反閘 1930, 2650, 2930‧‧ ‧ reverse gate

1936,2936‧‧‧補償元件 1936, 2936‧‧‧Compensation components

1938,2938‧‧‧採樣使能信號 1938, 2938‧‧‧Sampling enable signal

1940,2940‧‧‧採樣禁止信號 1940, 2940‧‧‧Sampling prohibited signal

2108,2308‧‧‧負斜坡信號生成器 2108, 2308‧‧‧ Negative ramp signal generator

2130‧‧‧控制信號 2130‧‧‧Control signal

3110,3120,3122‧‧‧脈衝 3110, 3120, 3122‧‧ ‧ pulse

2500‧‧‧電源轉換器 2500‧‧‧Power Converter

2570‧‧‧過流閾值信號生成器 2570‧‧‧Overcurrent threshold signal generator

2584‧‧‧柵極驅動信號 2584‧‧‧Gate drive signal

2592‧‧‧電壓Vin 2592‧‧‧V Voltage V in

2594‧‧‧前沿消隱(LEB)元件 2594‧‧‧Leading edge blanking (LEB) components

2599‧‧‧VAC信號 2599‧‧‧VAC signal

2802,2902‧‧‧濾波器信號生成器 2802, 2902‧‧‧ Filter Signal Generator

2816,2916‧‧‧濾波器信號 2816,2916‧‧‧Filter signal

第1圖是具有過流保護的簡化傳統開關模式轉換器。 Figure 1 is a simplified conventional switch mode converter with overcurrent protection.

第2圖是示出額外電流斜升幅度與整流後電容上的電壓之間的傳統關係的簡化圖式。 Figure 2 is a simplified diagram showing the conventional relationship between the magnitude of the extra current ramp and the voltage across the rectified capacitor.

第3圖是示出電流閾值與整流後電容上的電壓之間的傳統關係的簡化圖式。 Figure 3 is a simplified diagram showing the conventional relationship between the current threshold and the voltage across the rectified capacitor.

第4圖是示出閾值偏移與整流後電容上的電壓之間的傳統關係的簡化圖式。 Figure 4 is a simplified diagram showing the conventional relationship between the threshold offset and the voltage across the rectified capacitor.

第5圖是示出PWM信號最大寬度與整流後電容上的電壓之間的傳統關係的簡化圖式。 Figure 5 is a simplified diagram showing the conventional relationship between the maximum width of the PWM signal and the voltage across the rectified capacitor.

第6圖示出了CCM模式和DCM模式中的初級繞組的簡化傳統電流 曲線。 Figure 6 shows a simplified conventional current for the primary winding in CCM mode and DCM mode. curve.

第7圖示出了作為整流後電容上的電壓的傳統函數的在每個週期中傳遞到負載的最大能量的簡化圖式。 Figure 7 shows a simplified diagram of the maximum energy delivered to the load in each cycle as a traditional function of the voltage across the rectified capacitor.

第8圖和第9圖是在CCM模式中與不同整流後電容上的電壓相對應的開關模式轉換器的簡化時序圖。 Figures 8 and 9 are simplified timing diagrams of a switch mode converter corresponding to voltages on different rectified capacitors in CCM mode.

第10圖是示出對於傳統的開關模式轉換器，整流後電容上的電壓Vin的改變對電流感測信號的影響的簡化圖式。 FIG 10 is a diagram for illustrating a conventional switch-mode converter, the influence of voltage V in the capacitance change of the current-sensing signal is rectified to simplify the drawing.

第11圖是示出對電流感測信號的電壓脈衝進行校正的簡化圖式。 Figure 11 is a simplified diagram showing the correction of the voltage pulses of the current sense signal.

第12圖是根據本發明一個實施例的具有過流保護的簡化電源轉換器。 Figure 12 is a simplified power converter with overcurrent protection in accordance with one embodiment of the present invention.

第13A圖是示出根據本發明一個實施例的作為時間的函數的如第12圖所示的過流閾值信號的簡化圖式。 Figure 13A is a simplified diagram showing the overcurrent threshold signal as shown in Fig. 12 as a function of time, in accordance with one embodiment of the present invention.

第13B圖是示出根據本發明一個實施例的在整流後電容上的電壓的不同值下作為時間的函數的如第12圖所示的電流感測信號的簡化圖式。 Figure 13B is a simplified diagram of the current sense signal as shown in Figure 12 as a function of time at different values of voltage across the rectified capacitor, in accordance with one embodiment of the present invention.

第14A圖是示出根據本發明一個實施例的具有過流保護的如第12圖所示的電源轉換器的某些元件的簡化圖式。 Figure 14A is a simplified diagram showing certain elements of a power converter as shown in Figure 12 with overcurrent protection in accordance with one embodiment of the present invention.

第14B圖是根據本發明一個實施例的如第14A圖所示的電源轉換器的簡化時序圖。 Figure 14B is a simplified timing diagram of the power converter as shown in Figure 14A, in accordance with one embodiment of the present invention.

第14C圖是示出根據本發明一個實施例的如第14A圖所示的電源轉換器的某些元件的簡化圖式。 Figure 14C is a simplified diagram showing certain elements of the power converter as shown in Figure 14A, in accordance with one embodiment of the present invention.

第15A圖是示出根據本發明另一實施例的具有過流保護的如第12圖所示的電源轉換器的某些元件的簡化圖式。 Figure 15A is a simplified diagram showing certain elements of a power converter as shown in Figure 12 with overcurrent protection in accordance with another embodiment of the present invention.

第15B圖是示出根據本發明另一實施例的如第15A圖所示的電源轉換器的某些元件的簡化圖式。 Figure 15B is a simplified diagram showing certain elements of the power converter as shown in Figure 15A in accordance with another embodiment of the present invention.

第16A圖是示出根據本發明另一實施例的具有過流保護的如第12圖所示的電源轉換器的某些元件的簡化圖式。 Figure 16A is a simplified diagram showing certain elements of a power converter as shown in Figure 12 with overcurrent protection in accordance with another embodiment of the present invention.

第16B圖是根據本發明另一實施例的如第16A圖所示的電源轉換器的簡化時序圖。 Figure 16B is a simplified timing diagram of the power converter as shown in Figure 16A, in accordance with another embodiment of the present invention.

第17圖是示出根據本發明又一實施例的具有過流保護的如第12圖所示的電源轉換器的某些元件的簡化圖式。 Figure 17 is a simplified diagram showing certain elements of a power converter as shown in Figure 12 with overcurrent protection in accordance with yet another embodiment of the present invention.

第18A圖是示出根據本發明又一實施例的作為時間的函數的如第12圖所示的過流閾值信號的簡化圖式。 Figure 18A is a simplified diagram showing an overcurrent threshold signal as shown in Fig. 12 as a function of time in accordance with yet another embodiment of the present invention.

第18B圖是示出根據本發明又一實施例的在整流後電容上的電壓的不同值下作為時間的函數的如第12圖所示的電流感測信號的簡化圖式。 Figure 18B is a simplified diagram of the current sense signal as shown in Figure 12 as a function of time at different values of voltage across the rectified capacitor, in accordance with yet another embodiment of the present invention.

第19A圖是示出根據本發明又一實施例的具有過流保護的如第12圖所示的電源轉換器的某些元件的簡化圖式。 Figure 19A is a simplified diagram showing certain elements of a power converter as shown in Figure 12 with overcurrent protection in accordance with yet another embodiment of the present invention.

第19B圖是根據本發明又一實施例的如第19A圖所示的電源轉換器的簡化時序圖。 Figure 19B is a simplified timing diagram of the power converter as shown in Figure 19A in accordance with yet another embodiment of the present invention.

第20A圖是示出根據本發明又一實施例的作為時間的函數的如第12圖所示的過流閾值信號的簡化圖式。 Figure 20A is a simplified diagram showing the overcurrent threshold signal as shown in Fig. 12 as a function of time in accordance with yet another embodiment of the present invention.

第20B圖是示出根據本發明又一實施例的在整流後電容上的電壓的不同值下作為時間的函數的如第12圖所示的電流感測信號的簡化圖式。 Figure 20B is a simplified diagram of the current sense signal as shown in Figure 12 as a function of time at different values of voltage across the rectified capacitor, in accordance with yet another embodiment of the present invention.

第21A圖是示出根據本發明又一實施例的具有過流保護的如第12圖所示的電源轉換器的某些元件的簡化圖式。 Figure 21A is a simplified diagram showing certain elements of a power converter as shown in Figure 12 with overcurrent protection in accordance with yet another embodiment of the present invention.

第21B圖是根據本發明又一實施例的如第21A圖所示的電源轉換器的簡化時序圖。 Figure 21B is a simplified timing diagram of the power converter as shown in Figure 21A in accordance with yet another embodiment of the present invention.

第22A圖是示出根據本發明又一實施例的作為時間的函數的如第12圖所示的過流閾值信號的簡化圖式。 Figure 22A is a simplified diagram showing the overcurrent threshold signal as shown in Fig. 12 as a function of time in accordance with yet another embodiment of the present invention.

第22B圖是示出根據本發明又一實施例的在整流後電容上的電壓的不同值下作為時間的函數的如第12圖所示的電流感測信號的簡化圖式。 Figure 22B is a simplified diagram of the current sense signal as shown in Figure 12 as a function of time at different values of voltage across the rectified capacitor, in accordance with yet another embodiment of the present invention.

本發明涉及積體電路。更具體地，本發明提供了對於過流保護和過功率保護的控制系統和方法。僅僅作為示例，本發明已應用於電源 轉換器。但是將認識到，本發明具有更廣泛的應用範圍。 The present invention relates to an integrated circuit. More specifically, the present invention provides control systems and methods for overcurrent protection and overpower protection. Merely by way of example, the invention has been applied to a power supply converter. However, it will be appreciated that the invention has a broader range of applications.

第8圖和第9圖是在CCM模式中與不同整流後電容上的電壓相對應的開關模式轉換器的簡化時序圖。例如，第8圖的整流後電容上的電壓高於第9圖的整流後電容上的電壓。 Figures 8 and 9 are simplified timing diagrams of a switch mode converter corresponding to voltages on different rectified capacitors in CCM mode. For example, the voltage on the rectified capacitor of Figure 8 is higher than the voltage on the rectified capacitor of Figure 9.

如第8圖所示，曲線2810,2820,2830和2840分別表示時鐘信號(例如，CLK)、PWM信號(例如，PWM)、過流閾值信號(例如，Vth_oc)和電流感測信號(例如，VCS)的時序圖。例如，時鐘信號與PWM信號同步。在另一示例中，PWM信號由PWM控制器元件生成。在又一示例中，過流閾值信號由OCP比較器接收，並且電流感測信號也由OCP比較器接收。如第8圖所示，曲線2830指示過流閾值信號在下限Vth_0與上限Vclamp之間改變，並且CCM模式中的時序圖的斜率高於DCM模式中的時序圖的斜率。 As shown in FIG. 8, curves 2810, 2820, 2830, and 2840 represent a clock signal (eg, CLK), a PWM signal (eg, PWM), an overcurrent threshold signal (eg, Vth_oc ), and a current sense signal (eg, , V CS ) timing diagram. For example, the clock signal is synchronized with the PWM signal. In another example, the PWM signal is generated by a PWM controller component. In yet another example, the overcurrent threshold signal is received by the OCP comparator and the current sense signal is also received by the OCP comparator. As shown in FIG. 8, a graph 2830 indicating the overcurrent threshold signal between the lower and upper limit of V th_0 V clamp change, and the slope of the timing chart CCM mode is higher than the slope of the timing chart in DCM mode.

類似地，如第9圖所示，曲線2910,2920,2930和2940分別表示時鐘信號(例如，CLK)、PWM信號(例如，PWM)、過流閾值信號(例如，Vth_oc)和電流感測信號(例如，VCS)的時序圖。例如，時鐘信號與PWM信號同步。在另一示例中，PWM信號由PWM控制器元件生成。在又一示例中，過流閾值信號由OCP比較器接收，並且電流感測信號也由OCP比較器接收。如第9圖所示，曲線2930指示過流閾值信號在下限Vth_0與上限Vclamp之間改變，並且CCM模式中的時序圖的斜率高於DCM模式中的時序圖的斜率。 Similarly, as shown in FIG. 9, curves 2910, 2920, 2930, and 2940 represent clock signals (eg, CLK), PWM signals (eg, PWM), overcurrent threshold signals (eg, Vth_oc ), and current sensing, respectively. Timing diagram of a signal (eg, V CS ). For example, the clock signal is synchronized with the PWM signal. In another example, the PWM signal is generated by a PWM controller component. In yet another example, the overcurrent threshold signal is received by the OCP comparator and the current sense signal is also received by the OCP comparator. As shown in Figure 9, a graph 2930 indicating the overcurrent threshold signal between the lower and upper limit of V th_0 V clamp change, and the slope of the timing chart CCM mode is higher than the slope of the timing chart in DCM mode.

參考第8圖和第9圖，本技術可以提高不同整流後電容上的電壓下CCM模式和DCM模式中的最大能量的一致性，但是本技術具有其自身的限制。 Referring to Figures 8 and 9, the present technique can improve the consistency of the maximum energy in the CCM mode and the DCM mode at different voltages on the rectified capacitor, but the technique has its own limitations.

如第1圖所示，節點190處的整流後電容上的電壓Vin通常不是完美的DC電壓。替代地，整流後電容上的電壓Vin通常隨著開關模式轉換器100的輸出負載以及VAC信號而改變。VAC信號是AC電壓信號，其隨著時間改變其大小。對於相同的VAC信號，整流後電容上的電壓Vin隨著開關模式轉換器100的輸出負載而改變。 As shown, node 190 rectified voltage V in across the capacitor is generally not a perfect view of the first DC voltage. Alternatively, the voltage V in on the rectified capacitor typically varies with the output load of the switch mode converter 100 and the VAC signal. The VAC signal is an AC voltage signal that changes its size over time. VAC for the same signal, the rectified voltage V in with the output load capacitance on the switch-mode converter 100 is changed.

第10圖是示出對於傳統的開關模式轉換器100，整流後電 容上的電壓Vin的改變對電流感測信號的影響的簡化圖式。曲線3010和3020分別表示整流後電容上的電壓Vin和電流感測信號的時序圖。 FIG 10 is a graph showing 100, the influence of voltage V in the capacitance change of the current-sensing signal is rectified simplified diagram of a conventional switch mode converter. Curves 3010 and 3020 represent a timing chart of the rectified voltage V in and the current sensing signal on the capacitor.

如第10圖所示，在區域A、B和C的每個中，電流感測信號中存在兩個電壓脈衝，一個電壓脈衝通常比另一個大。根據一實施例，對於一信號週期時間，信號的占空比是該信號處於邏輯高電平時的時間長度與該信號週期時間的長度之間的比率。在區域A中，PWM信號的占空比相對小，因此PWM信號的關斷時間對於充分退磁和能量到開關模式轉換器100的輸出端的有效傳送來說是足夠長的。然後，在下一PWM週期時間的開始處，電流感測信號的電壓值低於相應的電壓閾值Vth_0。因此，在此PWM週期時間中，初級繞組可以有效地儲存能量，並且所儲存的能量可以有效地傳送到開關模式轉換器100的輸出端。因此，在區域A中，由開關模式轉換器100實際傳遞的最大功率不受整流後電容上的電壓Vin改變的很大影響。 As shown in FIG. 10, in each of the regions A, B, and C, there are two voltage pulses in the current sensing signal, one voltage pulse being generally larger than the other. According to an embodiment, for a signal cycle time, the duty cycle of the signal is the ratio of the length of time the signal is at a logic high level to the length of the signal cycle time. In region A, the duty cycle of the PWM signal is relatively small, so the turn-off time of the PWM signal is sufficiently long for sufficient demagnetization and efficient transfer of energy to the output of switch mode converter 100. Then, at the beginning of the next PWM cycle time, the voltage value of the current sense signal is lower than the corresponding voltage threshold Vth_0 . Therefore, in this PWM cycle time, the primary winding can efficiently store energy, and the stored energy can be efficiently transferred to the output of the switch mode converter 100. Thus, in the area A, after the switch-mode converter 100 is not actually transmitted maximum power rectified voltage V in on capacitance change of a significant impact.

在區域B中，PWM信號的占空比相對大並且PWM信號的關斷時間對於充分退磁和能量到開關模式轉換器100的輸出端的有效傳送來說太短。然後，在下一PWM週期時間的開始處，電流感測信號的電壓值高於相應的電壓閾值Vth_0。因此，在此PWM週期時間中，開關140在接通之後立即被關斷，從而使得初級繞組不能夠有效地儲存能量，並且將開關頻率等效地降低了一半。因此，初級繞組的輸入功率也被減小一半，並且在區域B中由開關模式轉換器100實際傳遞的最大功率受到整流後電容上的電壓Vin改變的很大影響。 In region B, the duty cycle of the PWM signal is relatively large and the turn-off time of the PWM signal is too short for sufficient demagnetization and efficient transfer of energy to the output of switch mode converter 100. Then, at the beginning of the next PWM cycle time, the voltage value of the current sense signal is higher than the corresponding voltage threshold Vth_0 . Therefore, during this PWM cycle time, the switch 140 is turned off immediately after being turned on, so that the primary winding cannot efficiently store energy and the switching frequency is equivalently reduced by half. Accordingly, a primary winding of the input power is also reduced by half, and in the region B by a switch-mode converter 100 actual maximum power transfer is greatly affected on the rectified voltage V after the change in the capacitance.

類似地，在區域C中，PWM信號的占空比達到由用於PWM控制的晶片180設置的最大占空比。例如，最大占空比被設為80%。因此，PWM信號的關斷時間對於充分退磁和能量到開關模式轉換器100的輸出端的有效傳送來說太短。因此，在區域C中，由開關模式轉換器100實際傳遞的最大功率受到受整流後電容上的電壓Vin改變的很大影響。 Similarly, in region C, the duty cycle of the PWM signal reaches the maximum duty cycle set by the wafer 180 for PWM control. For example, the maximum duty cycle is set to 80%. Therefore, the turn-off time of the PWM signal is too short for sufficient demagnetization and efficient transfer of energy to the output of the switch mode converter 100. Thus, in the region C by a switch-mode converter 100 actually transmitted maximum power voltage V in is greatly affected by changes in the rectified on the capacitor.

如第10圖所示，區域A、B和C可以在VAC信號的不同的半個週期時間中重複出現。例如，TAC表示VAC信號的週期時間，對於220V/50Hz AC電壓，其等於20 ms，並且對於110V/60Hz AC電壓，其等於 16.67 ms。在另一示例中，與區域A相比，區域B和C對應於整流後電容上的電壓Vin較低。在又一示例中，在區域A、B和C中，整流後電容上的電壓Vin的改變對電流感測信號的影響可能不同。 As shown in Figure 10, regions A, B, and C can be repeated in different half cycle times of the VAC signal. For example, T AC represents the cycle time of the VAC signal, which is equal to 20 ms for a 220V/50 Hz AC voltage and 16.67 ms for a 110V/60 Hz AC voltage. In another example, regions B and C correspond to a lower voltage Vin in the rectified capacitor than region A. In yet another example, in the region A, B and C, the rectified voltage V in influence on the capacitance change of the electrical sense signal may be different.

如上面討論的，有效PWM開關頻率的減小是減小開關模式轉換器100實際遞送的最大功率的重要原因。因此，為了將實際最大功率恢復到預定的最大功率，校正較大電壓脈衝與較小電壓脈衝的組合是重要的。根據一個實施例，對較小電壓脈衝進行校正以使得在每個PWM週期時間中開關具有足夠的導通時間，以使得初級繞組能夠進行有效的能量儲存。 As discussed above, the reduction in the effective PWM switching frequency is an important reason for reducing the maximum power actually delivered by the switch mode converter 100. Therefore, in order to restore the actual maximum power to a predetermined maximum power, it is important to correct the combination of a larger voltage pulse and a smaller voltage pulse. According to one embodiment, the smaller voltage pulses are corrected such that the switches have sufficient on-time during each PWM cycle time to enable efficient energy storage of the primary windings.

第11圖是示出對電流感測信號的電壓脈衝進行校正的簡化圖式。根據一個實施例，如第11圖所示，如果在當前PWM週期時間(例如，與第11圖中的脈衝3110相對應的PWM週期時間)中PWM信號的占空比被確定為大於預定占空比閾值(例如，60%，則在下一PWM週期時間的開始處，電壓閾值被設為與下限Vth_0不同的另一閾值水準(例如，Vth_a)，以便將脈衝3120校正為變成脈衝3122。例如，閾值水準(例如，Vth_a)與上限Vclamp相同。在另一示例中，閾值水準(例如，Vth_a)大於下限Vth_0但小於上限Vclamp。 Figure 11 is a simplified diagram showing the correction of the voltage pulses of the current sense signal. According to an embodiment, as shown in FIG. 11, if the duty cycle of the PWM signal is determined to be greater than the predetermined duty in the current PWM cycle time (for example, the PWM cycle time corresponding to the pulse 3110 in FIG. 11) Above the threshold (eg, 60%, at the beginning of the next PWM cycle time, the voltage threshold is set to another threshold level (eg, Vth_a ) that is different from the lower limit Vth_0 to correct the pulse 3120 to become the pulse 3122. For example, a threshold level (e.g., V th_a) upper limit V clamp the same. in another example, the threshold level (e.g., V th_a) greater than the lower limit but less than V th_0 V clamp.

在另一示例中，這樣的校正可以修改PWM信號的占空比並且防止開關在導通之後立即關斷。在又一示例中，對電壓脈衝的這樣的校正使得開關模式轉換器的初級繞組有效地儲存並傳送能量。在又一示例中，對電壓脈衝的這樣的校正可以防止降低有效開關頻率並保持開關模式轉換器的最大功率。 In another example, such correction may modify the duty cycle of the PWM signal and prevent the switch from turning off immediately after conduction. In yet another example, such correction of the voltage pulse causes the primary winding of the switched mode converter to efficiently store and transfer energy. In yet another example, such correction of the voltage pulse can prevent the effective switching frequency from being lowered and the maximum power of the switching mode converter.

第12圖是根據本發明一個實施例的具有過流保護的簡化電源轉換器。該圖式僅僅是示例，其不應當不當地限制申請專利範圍的範圍。本領域技術人員將認識到許多變體、替換和修改。電源轉換器2500包括OCP比較器2510、PWM控制器元件2520、柵極驅動器2530、開關2540、電阻器2550,2552,2554和2556、過流閾值信號生成器2570、初級繞組2560以及前沿消隱(LEB)元件2594。OCP比較器2510、PWM控制器元件2520、柵極驅動器2530是用於PWM控制的晶片2580的部分。前沿消隱(LEB)組件2594在一些實施例中被省略。 Figure 12 is a simplified power converter with overcurrent protection in accordance with one embodiment of the present invention. The drawings are merely examples, which should not unduly limit the scope of the claimed scope. Those skilled in the art will recognize many variations, substitutions and modifications. Power converter 2500 includes OCP comparator 2510, PWM controller component 2520, gate driver 2530, switch 2540, resistors 2550, 2552, 2554, and 2556, overcurrent threshold signal generator 2570, primary winding 2560, and leading edge blanking ( LEB) element 2594. OCP comparator 2510, PWM controller component 2520, and gate driver 2530 are portions of wafer 2580 for PWM control. Leading edge blanking (LEB) component 2594 is omitted in some embodiments.

如第12圖所示，在一些實施例中，節點2590處的整流後電容上的電壓Vin 2592不是完美的DC電壓。例如，整流後電容上的電壓Vin隨著電源轉換器2500的輸出負載以及VAC信號2599而改變。在另一示例中，對於相同的VAC信號2599，整流後電容上的電壓Vin 2592隨著電源轉換器2500的輸出負載的改變而改變。 As shown in FIG. 12, in some embodiments, the voltage V in 2592 on the rectified capacitor at node 2590 is not a perfect DC voltage. For example, the rectified voltage V in with the output load capacitance and the power converter 2599 VAC signal 2500 is changed. In another example, for the same VAC signal 2599, the voltage V in 2592 on the rectified capacitor changes as the output load of the power converter 2500 changes.

根據一個實施例，PWM控制器元件2520生成PWM信號2522，其由柵極驅動器2530接收。在一實施例中，柵極驅動器2530作為回應，輸出柵極驅動信號2584給開關2540。在另一實施例中，過流閾值信號生成器2570接收信號2582並向OCP比較器2510輸出過流閾值信號2512(例如，Vth_oc)。例如，信號2582是PWM信號2522。在另一示例中，信號2582是柵極驅動信號2584。 According to one embodiment, PWM controller component 2520 generates a PWM signal 2522 that is received by gate driver 2530. In one embodiment, gate driver 2530, in response, outputs gate drive signal 2584 to switch 2540. In another embodiment, the overcurrent threshold signal generator 2570 receives the signal 2582 and outputs an overcurrent threshold signal 2512 (eg, Vth_oc ) to the OCP comparator 2510. For example, signal 2582 is PWM signal 2522. In another example, signal 2582 is gate drive signal 2584.

在又一示例中，根據某些實施例，過流閾值信號2512(例如，Vth_oc)在如下所述的第13A圖、第18A圖、第20A圖，和/或第22A圖中示出。在又一示例中，OCP比較器2510將過流閾值信號2512(例如，Vth_oc)與電流感測信號2514(例如，VCS)相比較，並且向PWM控制器元件2520發送過流控制信號2516。在又一示例中，當流經初級繞組的電流2572大於限制水準時，PWM控制器元件2520關斷開關2540並關閉電源轉換器2500。在又一示例中，電流感測信號2514(例如，VCS)被與指示電流2572的大小的電壓信號相關聯。 In yet another example, according to some embodiments, the overcurrent threshold signal 2512 (eg, Vth_oc ) is shown in FIG. 13A, FIG. 18A, FIG. 20A, and/or 22A. In yet another example, the OCP comparator 2510 compares the overcurrent threshold signal 2512 (eg, V th — oc ) with the current sense signal 2514 (eg, V CS ) and sends an overcurrent control signal 2516 to the PWM controller component 2520. . In yet another example, when current 2572 flowing through the primary winding is greater than the limit level, PWM controller component 2520 turns off switch 2540 and turns off power converter 2500. In yet another example, current sense signal 2514 (eg, V CS ) is associated with a voltage signal indicative of the magnitude of current 2572.

在一實施例中，PWM信號2522的開關時程包括導通時間和關斷時間，並且該開關時程的占空比等於導通時間與開關時程之比。例如，在導通時間期間，開關2540閉合(例如，接通)，並且在關斷時間期間，開關2540斷開(例如，關斷)。 In one embodiment, the switching time course of the PWM signal 2522 includes an on time and an off time, and the duty cycle of the switching time is equal to the ratio of the on time to the on time. For example, during the on time, switch 2540 is closed (eg, turned "on"), and during the off time, switch 2540 is open (eg, turned off).

在另一實施例中，過流閾值信號生成器2570生成作為開關時程內與導通時間相關的過流閾值信號2512(例如，Vth_oc)，從開關時程的導通時間的開始起來測量該時間。例如，在每個開關時程的導通時間的開始處，開關時程內的該時間被設為零。在又一示例中，過流閾值信號生成器2570接收PWM信號2522以檢測開關時程的導通時間的開始，並將該時間設為零，並且生成與導通時間相關的過流閾值信號2512(例如，Vth_oc)。 在又一示例中，過流閾值信號生成器2570還檢測每個開關時程中的導通時間。 In another embodiment, the overcurrent threshold signal generator 2570 generates an overcurrent threshold signal 2512 (eg, Vth_oc ) associated with the on time in the switch time period, which is measured from the beginning of the on time of the switch time course. . For example, at the beginning of the on-time of each switching time period, the time within the switching time period is set to zero. In yet another example, the overcurrent threshold signal generator 2570 receives the PWM signal 2522 to detect the beginning of the on time of the switch time period and sets the time to zero and generates an overcurrent threshold signal 2512 associated with the on time (eg, , V th_oc ). In yet another example, the overcurrent threshold signal generator 2570 also detects the on time in each switch time course.

根據本發明一些實施例，如第13A圖和第13B圖所示，自我調整補償方案可減少次諧波震盪，以便使最大輸出功率在整流後電容上的電壓的寬範圍中保持一致。 In accordance with some embodiments of the present invention, as shown in Figures 13A and 13B, the self-tuning compensation scheme can reduce subharmonic oscillations to maintain a uniform maximum output power over a wide range of voltages across the rectified capacitor.

第13A圖是示出根據本發明一實施例的作為開關時程內的時間的函數的過流閾值信號2512的簡化圖式。該圖式僅僅是示例，其不應當不當地限制申請專利範圍的範圍。本領域技術人員將認識到許多變體、替換和修改。 Figure 13A is a simplified diagram showing an overcurrent threshold signal 2512 as a function of time within a switch time course, in accordance with an embodiment of the present invention. The drawings are merely examples, which should not unduly limit the scope of the claimed scope. Those skilled in the art will recognize many variations, substitutions and modifications.

在一實施例中，波形1312表示作為開關時程T1內的時間的函數的過流閾值信號2512(例如，Vth_oc)，並且導通時間在開關時程T1的開始處被設為零。在另一實施例中，波形1314表示作為開關時程T2內的時間的函數的過流閾值信號2512(例如，Vth_oc)，並且導通時間在開關時程T2的開始處被設為零。在又一實施例中，波形1316表示作為開關時程T3內的時間的函數的過流閾值信號2512(例如，Vth_oc)，並且導通時間在開關時程T3的開始處被設為零。在又一實施例中，波形1318表示作為開關時程T4內的時間的函數的過流閾值信號2512(例如，Vth_oc)，並且導通時間在開關時程T4的開始處被設為零。 In one embodiment, the waveform 1312 denotes a switch overcurrent function of time in a course T threshold signal 2512 (e.g., V th_oc), and on-time course T at the beginning of 1 is set to zero when the switch. In another embodiment, the waveform 1314 represents as a function of time within a 2 course T switch overcurrent threshold signal 2512 (e.g., V th_oc), and the on-time when the switching path T at the beginning of 2 is set to zero . In yet another embodiment, the waveform 1316 represents as a function of time in 3 course T switch overcurrent threshold signal 2512 (e.g., V th_oc), and the on-time when the switching path T at the beginning of 3 is set to zero . In yet another embodiment, the waveform 1318 represents as a function of time in 4 course T switch overcurrent threshold signal 2512 (e.g., V th_oc), and the conduction time of the switch at the beginning of the process T 4 is set to zero .

例如，雖然開關時程T1,T2,T3和T4對應於不同的開關週期，然而它們的大小相等。在另一示例中，開關時程T1,T2,T3和T4的大小不相等，並且它們對應於不同的開關週期。在又一示例中，波形1312,1314,1316和1318分別對應於整流後電容上的電壓Vin1,Vin2,Vin3和Vin4。在另一示例中，過流閾值信號2512(例如，Vth_oc)與電源轉換器2500的電流閾值(Ith_oc)成比例。 For example, although the switching time periods T 1 , T 2 , T 3 , and T 4 correspond to different switching periods, they are equal in size. In another example, the switching time periods T 1 , T 2 , T 3 , and T 4 are not equal in magnitude, and they correspond to different switching periods. In yet another example, the waveform 1316, and 1318 respectively correspond to the rectified voltage across the capacitor V in1, V in2, V in3 and V in4. In another example, the overcurrent threshold signal 2512 (eg, Vth_oc ) is proportional to the current threshold ( Ith_oc ) of the power converter 2500.

根據一實施例，如第13A圖所示，對於特定的導通時間，過流閾值信號2512(例如，Vth_oc)在0(例如，導通時間的開始)與最大時間(例如，tmax)之間不隨著時間改變，如波形1312,1314,1316或1318所示。根據某些實施例，過流閾值信號2512(例如，Vth_oc)的值隨導通時間不同而不同，以補償“輸出延遲”的影響。例如，過流閾值信號2512的值 根據下式來確定：V th_oc (n+1)=(1-α)×V th_oc (n)+α×(V ocp_l +k ocp ×D(n)) (式9)其中，Vth_oc(n+1)表示在開關時程Tsw(n+1)內的隨導通時間變化的過流閾值信號2512的值，Vth_oc(n)表示在開關時程Tsw(n)內的隨導通時間變化的過流閾值信號2512的值，D(n)表示前一開關時程Tsw(n)的占空比，kocp是一個固定的常數，Vocp_l表示過流閾值信號2512的最小值，並且α表示係數(例如，α1)。在另一示例中，如果α=1，則過流閾值信號2512的大小根據下式確定：V th_oc (n+1)=V ocp_l +D(n)×k ocp (式10) According to an embodiment, as shown in FIG. 13A, for a particular on-time, the overcurrent threshold signal 2512 (eg, Vth_oc ) is between 0 (eg, the beginning of the on time) and the maximum time (eg, tmax ). Does not change over time, as shown by waveforms 1312, 1314, 1316 or 1318. According to some embodiments, the value of the overcurrent threshold signal 2512 (eg, Vth_oc ) varies with the on time to compensate for the effects of the "output delay." For example, the value of the overcurrent threshold signal 2512 is determined according to the following equation: V th_oc ( n +1) = (1 - α ) × V th_oc ( n ) + α × ( V ocp_l + k ocp × D ( n )) ( Equation 9) where V th — oc (n+1) represents the value of the overcurrent threshold signal 2512 as a function of the on-time during the switching time period T sw (n+1), and V th — oc (n) represents the switching time period T value on change over time guide overcurrent threshold signal 2512 within sw (n), when a switch before D (n) represents the path T sw (n) of the duty cycle, k ocp is a fixed constant, V ocp_l represents The minimum value of the overcurrent threshold signal 2512, and α represents the coefficient (eg, α 1). In another example, if α=1, the magnitude of the overcurrent threshold signal 2512 is determined according to the following equation: V th — oc ( n +1)= V ocp — l + D ( n ) × k ocp (Equation 10)

根據式9和式10，在一些實施例中，過流閾值信號2512的值在開關時程中的特定導通時間中受到一個或多個之前開關時程的占空比的影響。例如，一個或多個之前開關時程的占空比越大，該開關時程中的過流閾值信號2512的值就越大。在另一示例中，過流閾值信號2512(例如，Vth_oc(n+1))的值等於或大於過流閾值信號2512的最小值(例如，Vocp_l)，並且等於或小於過流閾值信號2512的最大值(例如，Vocp_h)。在又一示例中，kocp可被確定為在DCM模式下相對於時間的過流閾值信號的正斜率。在某些實施例中，可根據實際情況調節kocp。在又一示例中，在最大時間(例如，tmax)之後，電源轉換器2500執行關斷操作。 According to Equations 9 and 10, in some embodiments, the value of the overcurrent threshold signal 2512 is affected by the duty cycle of one or more previous switching time periods in a particular on time in the switching time period. For example, the greater the duty cycle of one or more previous switching time periods, the greater the value of the overcurrent threshold signal 2512 in the switching time course. In another example, the value of the overcurrent threshold signal 2512 (eg, V th — oc (n+1)) is equal to or greater than the minimum value of the overcurrent threshold signal 2512 (eg, Vocp — 1 ) and is equal to or less than the overcurrent threshold signal 2512 . The maximum value (for example, V ocp_h ). In yet another example, k ocp may be determined as the positive slope of the overcurrent threshold signal with respect to time in DCM mode. In some embodiments, k ocp can be adjusted according to actual conditions. In yet another example, after the maximum time (eg, t max ), the power converter 2500 performs a shutdown operation.

第13B圖是示出根據本發明一實施例的使用如第13A圖所示的作為開關時程內的時間的函數的過流閾值信號2512來確定導通時間的簡化圖式。該圖式僅僅是示例，其不應當不當地限制申請專利範圍的範圍。本領域技術人員將認識到許多變體、替換和修改。 Figure 13B is a simplified diagram showing the use of an overcurrent threshold signal 2512 as a function of time within the switch time history as shown in Figure 13A to determine the on time, in accordance with an embodiment of the present invention. The drawings are merely examples, which should not unduly limit the scope of the claimed scope. Those skilled in the art will recognize many variations, substitutions and modifications.

在一實施例中，波形1312表示作為開關時程T1內的時間的函數的過流閾值信號2512(例如，Vth_oc)，並且波形1320表示作為開關時程T1內的時間的函數的電流感測信號2514(例如，VCS)。在另一實施例中，波形1314表示作為開關時程T2內的時間的函數的過流閾值信號2512(例如，Vth_oc)，並且波形1322表示作為開關時程T2內的時間的函數的電流感測信號2514(例如，VCS)。 In one embodiment, the waveform 1312 shown as a function of time in a course T switch overcurrent threshold signal 2512 (e.g., V th_oc), and the waveform 1320 shown as a function of time in a course T switch current A sense signal 2514 (eg, V CS ). In another embodiment, the waveform 1314 denotes a overcurrent function of time in the 2 path T of the switching threshold signal 2512 (e.g., V th_oc), and the waveform 1322 represents as a function of time in the 2 path T when the switch Current sense signal 2514 (eg, V CS ).

在又一實施例中，波形1316表示作為開關時程T3內的時間 的函數的過流閾值信號2512(例如，Vth_oc)，並且波形1324表示作為開關時程T3內的時間的函數的電流感測信號2514(例如，VCS)。在另一實施例中，波形1318表示作為開關時程T4內的時間的函數的過流閾值信號2512(例如，Vth_oc)，並且波形1326表示作為開關時程T4內的時間的函數的電流感測信號2514(例如，VCS)。 In yet another embodiment, the waveform 1316 denotes a switch overcurrent function of time in 3 course T threshold signal 2512 (e.g., V th_oc), and the waveform 1324 represents as a function of time in the 3 path T when the switch Current sense signal 2514 (eg, V CS ). In another embodiment, the waveform 1318 denotes a switch overcurrent function of time in 4 course T threshold signal 2512 (e.g., V th_oc), and the waveform 1326 represents as a function of time in 4 course T when the switch Current sense signal 2514 (eg, V CS ).

波形1320,1322,1324和1326分別表示與整流後電容上的電壓Vin1,Vin2,Vin3和Vin4相對應的作為時間的函數的電流感測信號2514(例如，VCS)。例如，波形1320,1322,1324和1326所示的斜率分別是S1,S2,S3和S4。在另一示例中，電流感測信號2514(例如，VCS)與流經電源轉換器2500的初級繞組2560的電流2572成比例。 1320,1322,1324 and 1326 respectively represent waveforms of the rectified current sensing signal on the capacitor voltage V in1, V in2, V in3 and V in4 corresponding to 2514 as a function of time (e.g., V CS). For example, the slopes shown by waveforms 1320, 1322, 1324, and 1326 are S 1 , S 2 , S 3 , and S 4 , respectively . In another example, current sense signal 2514 (eg, V CS ) is proportional to current 2572 flowing through primary winding 2560 of power converter 2500.

根據一實施例，相對於特定的整流後電容上的電壓，電流感測信號2514(例如，VCS)隨著時間增大(例如，如波形1320,1322,1324和1326所示)。在一些實施例中，如第13B圖所示，電流感測信號2514(例如，VCS)相對於時間的斜率隨著整流後電容上的電壓增大。例如，Vin1>Vin2>Vin3>Vin4，並且相應地S1>S2>S3>S4。在另一示例中，當電流感測信號2514(例如，VCS)的大小超過過流閾值信號2512時(例如，如波形1320,1322,1324或1326所示)，過流保護被觸發。在又一示例中，在Tdelay(例如，“輸出延遲”)期間，電流感測信號2514(例如，VCS)的大小繼續增大。在又一示例中，在Tdelay的結束處，開關斷開(例如，關斷)，並且電流感測信號2514(例如，VCS)達到其最大大小。在一些實施例中，Tdelay的結束是在一開關時程期間開關2540的導通時間的結束。例如，對於整流後電容上的電壓Vin1，Tdelay的結束對應於時間tA，對於整流後電容上的電壓Vin2，Tdelay的結束對應於時間tB，對於整流後電容上的電壓Vin3，Tdelay的結束對應於時間tC，並且對於整流後電容上的電壓Vin4，Tdelay的結束對應於時間tD。在另一示例中，tA,tB,tC和tD分別表示開關時程T1,T2,T3和T4的導通時間的結束。 According to an embodiment, current sense signal 2514 (eg, V CS ) increases with time relative to a voltage on a particular rectified capacitor (eg, as shown by waveforms 1320, 1322, 1324, and 1326). In some embodiments, as shown in FIG. 13B, the slope of current sense signal 2514 (eg, V CS ) with respect to time increases with voltage on the rectified capacitor. For example, V in1> V in2> V in3> V in4, and accordingly the S 1> S 2> S 3 > S 4. In another example, when the magnitude of current sense signal 2514 (eg, V CS ) exceeds overcurrent threshold signal 2512 (eg, as shown by waveform 1320, 1322, 1324, or 1326), overcurrent protection is triggered. In yet another example, during Tdelay (eg, "output delay"), the magnitude of current sense signal 2514 (eg, VCS ) continues to increase. In yet another example, at the end of Tdelay , the switch is open (eg, turned off) and current sense signal 2514 (eg, VCS ) reaches its maximum size. In some embodiments, the end of Tdelay is the end of the on time of switch 2540 during a switching time period. For example, for the voltage V in1 on the rectified capacitor, the end of T delay corresponds to time t A , and for the voltage V in2 after rectification, the end of T delay corresponds to time t B , for voltage V on the rectified capacitor end IN3, T delay corresponds to the time t C, and for the rectified voltage V in4 capacitor, corresponding to the end of the time T delay t D. In another example, t A , t B , t C , and t D represent the end of the on-time of the switching time periods T 1 , T 2 , T 3 , and T 4 , respectively.

第14A圖是示出根據本發明一實施例的具有過流保護的電源轉換器2500的某些元件的簡化圖式。該圖式僅僅是示例，其不應當不當地限制申請專利範圍的範圍。本領域技術人員將認識到許多變體、替換和 修改。過流閾值信號生成器2570包括採樣信號生成器1602、信號生成器1604和信號處理元件1601。例如，信號處理元件1601包括採樣和保持元件1606和低通濾波器1608。在另一示例中，採樣和保持元件1606和低通濾波器1608共用一個或多個元件。在又一示例中，過流保護方案根據第13A圖和第13B圖來實現。 Figure 14A is a simplified diagram showing certain elements of a power converter 2500 with overcurrent protection in accordance with an embodiment of the present invention. The drawings are merely examples, which should not unduly limit the scope of the claimed scope. Those skilled in the art will recognize many variations, alternatives, and modify. The overcurrent threshold signal generator 2570 includes a sample signal generator 1602, a signal generator 1604, and a signal processing component 1601. For example, signal processing component 1601 includes a sample and hold component 1606 and a low pass filter 1608. In another example, sample and hold element 1606 and low pass filter 1608 share one or more elements. In yet another example, the overcurrent protection scheme is implemented in accordance with Figures 13A and 13B.

根據一實施例，在一開關時程期間，信號生成器1604接收信號2582(例如，PWM信號2522或柵極驅動信號2584)，並且基於信號2582在該開關時程中的占空比來生成斜坡信號1614。例如，採樣信號生成器1602接收信號2582，並且生成採樣信號1616。在另一示例中，採樣信號生成器1602在信號2582的下降沿時在採樣信號1616中輸出脈衝。在又一示例中，採樣和保持元件1606在採樣信號1616的脈衝期間對斜坡信號1614採樣，並且在該開關時程的其餘時間期間保持斜坡信號1614的大小(例如，在該脈衝的結束處)直到下一脈衝為止。在又一示例中，低通濾波器1608對採樣和保持元件1606生成的信號1618執行低通濾波，並且向OCP比較器2510輸出過流閾值信號2512。在又一示例中，OCP比較器2510還接收電流感測信號2514並且輸出過流控制信號2516。在又一示例中，過流閾值信號2512根據式9確定，其中，α與低通濾波器1608相關聯。 According to an embodiment, during a switching time period, signal generator 1604 receives signal 2582 (eg, PWM signal 2522 or gate drive signal 2584) and generates a ramp based on the duty cycle of signal 2582 in the switching time course. Signal 1614. For example, sample signal generator 1602 receives signal 2582 and generates sample signal 1616. In another example, the sampled signal generator 1602 outputs a pulse in the sampled signal 1616 at the falling edge of the signal 2582. In yet another example, the sample and hold element 1606 samples the ramp signal 1614 during the pulse of the sample signal 1616 and maintains the magnitude of the ramp signal 1614 during the remainder of the switch time period (eg, at the end of the pulse) Until the next pulse. In yet another example, low pass filter 1608 performs low pass filtering on signal 1618 generated by sample and hold element 1606 and over current threshold signal 2512 is output to OCP comparator 2510. In yet another example, the OCP comparator 2510 also receives the current sense signal 2514 and outputs an overcurrent control signal 2516. In yet another example, the overcurrent threshold signal 2512 is determined according to Equation 9, where a is associated with the low pass filter 1608.

在一實施例中，斜坡信號1614與傾斜上升過程和傾斜下降過程相關聯。例如，在傾斜上升過程期間，斜坡信號1614的大小從最小值增大到最大值，並且在傾斜下降過程期間，斜坡信號1614的大小從最大值減小到最小值。在另一示例中，傾斜上升過程和/或傾斜下降過程暫態地或者在一時間段期間發生。在另一實施例中，斜坡信號1614與傾斜上升過程、恒定過程和傾斜下降過程相關聯。例如，在傾斜上升過程期間，斜坡信號1614的大小從最小值增大到最大值；在恒定過程期間，斜坡信號1614保持為最大值；並且在傾斜下降過程期間，斜坡信號1614的大小從最大值減小到最小值。在另一示例中，傾斜上升過程、恒定過程和/或傾斜下降過程暫態地或者在一時間段期間發生。在又一實施例中，斜坡信號1614與傾斜上升過程、第一恒定過程、傾斜下降過程和第二恒定過程相關聯。例如，在傾斜上升過程期間，斜坡信號1614的大小從最小值增大到最大值；並且在 第一恒定過程期間，斜坡信號1614保持為最大值。在傾斜下降過程期間，斜坡信號1614的大小從最大值減小到最小值；並且在第二恒定過程期間，斜坡信號1614保持為最小值。傾斜上升過程、第一恒定過程、傾斜下降過程和/或第二恒定過程暫態地或者在一時間段期間發生。 In an embodiment, the ramp signal 1614 is associated with a ramp up process and a ramp down process. For example, during the ramp up process, the magnitude of the ramp signal 1614 increases from a minimum value to a maximum value, and during the ramp down process, the magnitude of the ramp signal 1614 decreases from a maximum value to a minimum value. In another example, the ramp up process and/or the ramp down process occur transiently or during a time period. In another embodiment, the ramp signal 1614 is associated with a ramp up process, a constant process, and a ramp down process. For example, during the ramp up process, the magnitude of the ramp signal 1614 increases from a minimum value to a maximum value; during a constant process, the ramp signal 1614 remains at a maximum value; and during the ramp down process, the magnitude of the ramp signal 1614 is from a maximum value Reduce to the minimum. In another example, the ramp up process, the constant process, and/or the ramp down process occur transiently or during a time period. In yet another embodiment, the ramp signal 1614 is associated with a ramp up process, a first constant process, a ramp down process, and a second constant process. For example, during the ramp up process, the magnitude of the ramp signal 1614 increases from a minimum value to a maximum value; During the first constant process, ramp signal 1614 remains at a maximum. During the ramp down process, the magnitude of ramp signal 1614 decreases from a maximum value to a minimum value; and during a second constant process, ramp signal 1614 remains at a minimum value. The ramp up process, the first constant process, the ramp down process, and/or the second constant process occur transiently or during a time period.

第14B圖是根據本發明一個實施例的包括如第14A圖所示的元件的電源轉換器2500的簡化時序圖。該圖式僅僅是示例，其不應當不當地限制申請專利範圍的範圍。本領域技術人員將認識到許多變體、替換和修改。波形1700表示作為時間的函數的信號2582，波形1702表示作為時間的函數的採樣信號1616，波形1704表示作為時間的函數的斜坡信號1614，波形1706表示作為時間的函數的過流閾值信號2512(例如，Vth_oc)，並且波形1708表示作為時間的函數的電流感測信號2514。 Figure 14B is a simplified timing diagram of a power converter 2500 including elements as shown in Figure 14A, in accordance with one embodiment of the present invention. The drawings are merely examples, which should not unduly limit the scope of the claimed scope. Those skilled in the art will recognize many variations, substitutions and modifications. Waveform 1700 represents signal 2582 as a function of time, waveform 1702 represents sampled signal 1616 as a function of time, waveform 1704 represents ramp signal 1614 as a function of time, and waveform 1706 represents overcurrent threshold signal 2512 as a function of time (eg, , V th — oc ), and waveform 1708 represents current sense signal 2514 as a function of time.

例如，波形1706表示作為時間的函數的過流閾值信號2512(例如，Vth_oc)其包括作為一開關時程Tswa內的時間的函數的過流閾值信號2512(例如，Vth_oc)、作為一開關時程Tswb內的時間的函數的過流閾值信號2512(例如，Vth_oc)以及作為一開關時程Tswc內的時間的函數的過流閾值信號2512(例如，Vth_oc)。在另一示例中，波形1708表示作為時間的函數的電流感測信號2514，其包括作為一開關時程Tswa內的時間的函數的電流感測信號2514、作為一開關時程Tswb內的時間的函數的電流感測信號2514以及作為一開關時程Tswc內的時間的函數的電流感測信號2514。例如，開關時程Tswa,Tswb和Tswc的大小相等，儘管它們對應於不同的開關週期。 For example, a waveform 1706 indicates as a function of time overcurrent threshold signal 2512 (e.g., V th_oc) comprising a function of time in the path T swa as a switch overcurrent threshold signal 2512 (e.g., V th_oc), as a when the switch overcurrent function of time in the path T swb threshold signal 2512 (e.g., V th_oc) and as a function of time in the path T swc when a switch overcurrent threshold signal 2512 (e.g., V th_oc). In another example, the waveform 1708 represents a function of time as a current sense signal 2514, which includes a current sense signal as a function of time when in the Cheng T swa a switch 2514, a switch as the time course of T swb current sensing signal as a function of time and as a function of time 2514 in the path T swc when a switch current sense signal 2514. For example, the switching time periods T swa , T swb , and T swc are equal in magnitude, although they correspond to different switching periods.

例如，如第14B圖所示，開關時程Tswa包括關斷時間Toffa和導通時間Tona，開關時程Tswb包括關斷時間Toffb和導通時間Tonb，並且開關時程Tswc包括關斷時間Toffc和導通時間Tonc。導通時間Tona開始於時間t2並結束於時間t3，關斷時間Toffa開始於時間t3並結束於時間t5，並且開關時程Tswa開始於時間t2並結束於時間t5。導通時間Tonb開始於時間t5並結束於時間t6，關斷時間Toffb開始於時間t6並結束於時間t8，並且開關時程Tswb開始於時間t5並結束於時間t8。導通時間Tonc開始於時間t8並結束於時間t9，關斷時間Toffc開始於時間t9並結束於時間t10，並且開關時程Tswc開始於時 間t8並結束於時間t10。在又一示例中，t2 t3 t4 t5 t6 t7 t8 t9 t10。 For example, as shown in FIG. 14B, the switching time period T swa includes an off time T offa and an on time T ona , and the switching time period T swb includes an off time T offb and an on time T onb , and the switching time period T swc includes T offc off-time and on-time T onc. Conduction time T ona begins at time t 2 and ends at time t 3, the off-time T offa begins at time t 3 and ends at time t 5, and the switch drive T swa begins at time t 2 and ends at time t 5 . The on-time T onb starts at time t 5 and ends at time t 6 , the off-time T offb starts at time t 6 and ends at time t 8 , and the switching time period T swb starts at time t 5 and ends at time t 8 . Conduction time T onc starts at time t 8 and ends at time t 9, the off-time T offc begins at time t 9 and ends at time t 10, and the switch drive T swc begins at time t 8 and ends at time t 10 . In yet another example, t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 .

根據一實施例，在導通時間Tona期間，信號2582保持為邏輯高電平(例如，如波形1700所示)。例如，斜坡信號1614從大小1710(例如，t2處)增大到大小1712(例如，t3處)，如波形1704所示。在另一示例中，過流閾值信號2512(例如，Vth_oc)在導通時間Tona期間保持為大小1714(例如，如波形1706所示)。在又一示例中，電流感測信號2514從大小1716(例如，t2處)增大，如波形1708所示。在一些實施例中，一旦電流感測信號2514超過大小1714(例如，t3處)，則過流保護被觸發。例如，OCP比較器2510將過流控制信號2516從邏輯高電平變為邏輯低電平。在另一示例中，然後，過流感測信號2514下降為大小1724(例如，t3處的0)並且在關斷時間Toffa期間保持為大小1724(例如，如波形1708所示)。 According to an embodiment, during the on time Tona , signal 2582 remains at a logic high level (eg, as shown by waveform 1700). For example, ramp signal 1614 increases from size 1710 (eg, at t 2 ) to size 1712 (eg, at t 3 ) as shown by waveform 1704. In another example, the overcurrent threshold signal 2512 (e.g., V th_oc) held during the on-time T ona is the size of 1714 (e.g., shown as waveform 1706). In yet another example, current sense signal 2514 increases from size 1716 (eg, at t 2 ) as shown by waveform 1708. In some embodiments, once current sense signal 2514 exceeds size 1714 (eg, at t 3 ), overcurrent protection is triggered. For example, OCP comparator 2510 changes overcurrent control signal 2516 from a logic high level to a logic low level. In another example, and then, through the sense signal 2514 falls to 1724 size (e.g., t at 30) and held during the off-time T offa size of 1724 (e.g., shown as waveform 1708).

根據另一實施例，在信號2582的下降沿處(例如，t3處)，在採樣信號1616中生成脈衝(例如，如波形1702所示)。例如，該脈衝開始於時間t3並結束於時間t4。在另一示例中，採樣和保持元件1606在該脈衝期間對斜坡信號1614採樣，並且作為回應，過流閾值信號2512(例如，Vth_oc)從大小1714(例如，t3處)變為大小1718(例如，t4處)，如波形1706所示。在又一示例中，信號1614在該脈衝期間保持為大小1712，並且在該脈衝的結束處(例如，t4處)下降為大小1710(例如，Vocp_l)，如波形1704所示。在又一示例中，在t4與t5之間的時間段期間，斜坡信號1614保持為大小1710(例如，Vocp_l)，如波形1704所示，並且過流閾值信號2512(例如，Vth_oc)保持為大小1718，如波形1706所示。 According to another embodiment, at a falling edge of the signal 2582 (e.g., t at 3), generates a pulse signal sampled in 1616 (e.g., shown as waveform 1702). For example, the pulse begins at time t 3 and ends at time t 4. In another example, the sample and hold element 16,061,614 samples during the ramp pulse signal, and in response, the overcurrent threshold signal 2512 (e.g., V th_oc) from the 1714 size (e.g., t at 3) becomes 1718 Size (eg, at t 4 ) as shown by waveform 1706. In yet another example, signal 1614 remains at size 1712 during the pulse and falls to a size 1710 (eg, V ocp — l ) at the end of the pulse (eg, at t 4 ), as shown by waveform 1704. In yet another example, during a time period between t 4 and t 5 , the ramp signal 1614 remains at a size 1710 (eg, V ocp — l ), as shown by waveform 1704, and an overcurrent threshold signal 2512 (eg, V th — oc ) remains at size 1718 as shown by waveform 1706.

根據又一實施例，在導通時間Tonb期間，信號2582保持為邏輯高電平(例如，如波形1700所示)。例如，斜坡信號1614從大小1710(例如，t5處)增大到大小1712(例如，t6處)，如波形1704所示。在另一示例中，過流閾值信號2512(例如，Vth_oc)在導通時間Tonb期間保持為大小1718(例如，如波形1706所示)。在又一示例中，電流感測信號2514從大小1720(例如，t5處)增大，如波形1708所示。在一些實施例中，一旦電流感測信號2514超過大小1718(例如，t6處)，則過流保護被觸發。例如，OCP比較器2510將過流控制信號2516從邏輯高電平變為邏輯低電平。 在另一示例中，然後，電流感測信號2514再次下降為大小1724(例如，t6處的0)並且在關斷時間Toffb期間保持為大小1724(例如，如波形1708所示)。 According to yet another embodiment, during the on time Tonb , signal 2582 remains at a logic high level (eg, as shown by waveform 1700). For example, ramp signal 1614 increases from size 1710 (eg, at t 5 ) to size 1712 (eg, at t 6 ) as shown by waveform 1704. In another example, the overcurrent threshold signal 2512 (eg, Vth_oc ) remains at a size 1718 during the on time Tond (eg, as shown by waveform 1706). In yet another example, current sense signal 2514 increases from size 1720 (eg, at t 5 ) as shown by waveform 1708. In some embodiments, once current sense signal 2514 exceeds size 1718 (eg, at t 6 ), overcurrent protection is triggered. For example, OCP comparator 2510 changes overcurrent control signal 2516 from a logic high level to a logic low level. In another example, then, the current sensing signal falls again to the size of 1724 2514 (e.g., 0 to t 6) and is held during the off-time T offb size of 1724 (e.g., shown as waveform 1708).

根據另一實施例，在信號2582的另一下降沿處(例如，t6處)，在採樣信號1616中生成另一脈衝(例如，如波形1702所示)。例如，該脈衝開始於時間t6並結束於時間t7。在另一示例中，採樣和保持元件1606在該脈衝期間對斜坡信號1614採樣，並且作為回應，過流閾值信號2512(例如，Vth_oc)從大小1718(例如，t6處)變為大小1722(例如，t7處)，如波形1706所示。在又一示例中，斜坡信號1614在該脈衝期間保持為大小1712，並且在該脈衝的結束處(例如，t7處)下降為大小1710(例如，Vocp_l)，如波形1704所示。在又一示例中，在t7與t8之間的時間段期間，斜坡信號1614保持為大小1720(例如，Vocp_l)，如波形1704所示。在又一示例中，在t7與t9之間的時間段期間，過流閾值信號2512(例如，Vth_oc)保持為大小1722，如波形1706所示。 According to another embodiment, another falling edge of the signal 2582 (e.g., t at 6), generates another pulse (e.g., shown as waveform 1702) in 1616 in the sampled signal. For example, the pulse begins at time t 6 and ends at time t 7 . In another example, the sample and hold element 16,061,614 samples during the ramp pulse signal, and in response, the overcurrent threshold signal 2512 (e.g., V th_oc) from the 1718 size (e.g., t at 6) becomes 1722 Size (eg, at t 7 ) as shown by waveform 1706. In yet another example, ramp signal 1614 remains at size 1712 during the pulse and falls to a size 1710 (eg, V ocp — l ) at the end of the pulse (eg, at t 7 ), as shown by waveform 1704. In yet another example, during a period between 7 and t 8 t, the ramp signal remains 1614 1720 size (e.g., V ocp_l), a waveform 1704 as shown. In yet another example, during a period between 7 and t 9 t, overcurrent threshold signal 2512 (e.g., V th_oc) maintaining the size 1722, the waveform 1706 as shown in FIG.

在某些實施例中，如上所述，對於特定的開關時程(例如，Tswc)，過流閾值信號2512(例如，Vth_oc)在導通時間期間(例如，從t7到t9的Tonc)保持為特定大小(例如，大小1722)，並且該特定大小(例如，大小1722)受到一個或多個之前開關時程(例如，Tona和Tonb)的占空比的影響。例如，過流閾值信號2512(例如，Vth_oc)的大小隨著開關時程而改變(例如，從開關時程Tswb中的大小1718變為隨後的開關時程Tswc中的大小1722)。在另一示例中，過流閾值信號2512(例如，Vth_oc)的大小1714,1718和1722可基於式9來確定。 In some embodiments, as described above, for a particular switching time period (eg, T swc ), an overcurrent threshold signal 2512 (eg, V th — oc ) during the on time (eg, T from t 7 to t 9 ) ONC) held to a specific size (e.g., size of 1722), and the specific size (e.g., size 1722) affected by the duty cycle prior to the switching of one or more processes (e.g., T ona and T ONB) of. For example, the overcurrent threshold signal 2512 (e.g., V th_oc) with the magnitude of the switch drive is changed (e.g., from a switch in the size of process T swb size at 1718 becomes T swc subsequent switching process in 1722). In another example, the magnitudes 1714, 1718, and 1722 of the overcurrent threshold signal 2512 (eg, Vth_oc ) may be determined based on Equation 9.

第14C圖是示出根據本發明一實施例的包括如第14A圖所示的元件的電源轉換器2500的某些元件的簡化圖式。該圖式僅僅是示例，其不應當不當地限制申請專利範圍的範圍。本領域技術人員將認識到許多變體、替換和修改。信號生成器1604包括電流源1802、開關1804和1812、及閘1806和1814、比較器1808和1816、電容器1810以及運算放大器1818。信號處理元件1601包括開關1820、電阻器1822和電容器1824。例如，採樣和保持元件1606包括開關1820和電容器1824。在另一示例中，低通濾 波器1608包括電阻器1822和電容器1824。 Figure 14C is a simplified diagram showing certain elements of a power converter 2500 including elements as shown in Figure 14A, in accordance with an embodiment of the present invention. The drawings are merely examples, which should not unduly limit the scope of the claimed scope. Those skilled in the art will recognize many variations, substitutions and modifications. Signal generator 1604 includes current source 1802, switches 1804 and 1812, and gates 1806 and 1814, comparators 1808 and 1816, capacitor 1810, and operational amplifier 1818. Signal processing component 1601 includes a switch 1820, a resistor 1822, and a capacitor 1824. For example, the sample and hold element 1606 includes a switch 1820 and a capacitor 1824. In another example, low pass filtering The waver 1608 includes a resistor 1822 and a capacitor 1824.

在一些實施例中，如第14C圖所示，及閘1806接收信號2582和來自比較器1808的信號1832，並且如果信號2582和信號1832兩者為邏輯高電平，則輸出邏輯高電平的信號1826。例如，開關1804(例如，S1)響應於為邏輯高電平的信號1826而閉合(例如，接通)。在另一示例中，從電流源1802流經開關1804的電流1828對電容器1810充電，並且作為回應，斜坡信號1614(例如，Vramp)的大小增大。在又一示例中，如果斜坡信號1614的大小超過參考信號1830(例如，Vocp_h)，則比較器1808輸出邏輯低電平的信號1832，並且及閘1806將信號1826改變為邏輯低電平以斷開(例如，關斷)開關1804從而停止對電容器1810充電。在又一示例中，當在採樣信號1616(例如，sample)中的一脈衝期間對斜坡信號1614採樣之後，及閘1814接收邏輯高電平的放電信號1840，並且如果來自比較器1816的信號1836為邏輯高電平，則輸出邏輯高電平的信號1838。在又一示例中，響應於信號1838為邏輯高電平，開關1812(例如，S2)閉合(例如，接通)以對電容器1810放電並且斜坡信號1614的大小減小。在又一示例中，如果斜坡信號1614的大小達到參考信號1834(例如，Vocp_l)，則比較器1816將信號1836變為邏輯低電平，並且作為響應，及閘1814將信號1838改變為邏輯低電平以斷開(例如，關斷)開關1812從而停止對電容器1810放電。在又一示例中，運算放大器1818作為緩衝器。 In some embodiments, as shown in FIG. 14C, AND gate 1806 receives signal 2582 and signal 1832 from comparator 1808, and outputs a logic high if both signal 2582 and signal 1832 are at a logic high level. Signal 1826. For example, switch 1804 (eg, S1) is closed (eg, turned "on" in response to signal 1826 that is a logic high level. In another example, current 1828 flowing from current source 1802 through switch 1804 charges capacitor 1810, and in response, the magnitude of ramp signal 1614 (eg, V ramp ) increases. In yet another example, if the magnitude of the ramp signal 1614 exceeds the reference signal 1830 (eg, V ocp — h ), the comparator 1808 outputs a signal 1832 of a logic low level, and the gate 1806 changes the signal 1826 to a logic low level. Switch 1804 is turned off (eg, turned off) to stop charging capacitor 1810. In yet another example, when the ramp signal 1614 is sampled during a pulse in the sampled signal 1616 (eg, sample), the AND gate 1814 receives a discharge signal 1840 of a logic high level, and if the signal 1836 from the comparator 1816 A logic high level outputs a signal 1838 of a logic high level. In yet another example, in response to signal 1838 being at a logic high level, switch 1812 (eg, S2) is closed (eg, turned "on") to discharge capacitor 1810 and the magnitude of ramp signal 1614 is reduced. In yet another example, if the magnitude of ramp signal 1614 reaches reference signal 1834 (eg, V ocp — l ), comparator 1816 changes signal 1836 to a logic low level, and in response, AND gate 1814 changes signal 1838 to logic. Low level turns off (eg, turns off) switch 1812 to stop discharging capacitor 1810. In yet another example, operational amplifier 1818 acts as a buffer.

根據一實施例，採樣信號生成器1602接收信號2582並且在信號2582的下降沿時在採樣信號1616中輸出脈衝。例如，開關1820(例如，S3)回應於該脈衝而閉合。在另一示例中，信號處理元件1601採樣和保持斜坡信號1614，並且執行低通濾波。在又一示例中，OCP比較器2510將過流閾值信號2512與電流感測信號2514相比較，並且輸出過流控制信號2516。在又一示例中，如果過流閾值信號2512的大小大於電流感測信號2514，則過流控制信號2516為邏輯高電平，並且如果電流感測信號2514的大小達到或超過過流閾值信號2512，則過流控制信號2516變為邏輯低電平以觸發過流保護。 According to an embodiment, the sampled signal generator 1602 receives the signal 2582 and outputs a pulse in the sampled signal 1616 at the falling edge of the signal 2582. For example, switch 1820 (eg, S3) closes in response to the pulse. In another example, signal processing component 1601 samples and holds ramp signal 1614 and performs low pass filtering. In yet another example, the OCP comparator 2510 compares the overcurrent threshold signal 2512 with the current sense signal 2514 and outputs an overcurrent control signal 2516. In yet another example, if the magnitude of the overcurrent threshold signal 2512 is greater than the current sense signal 2514, the overcurrent control signal 2516 is at a logic high level, and if the magnitude of the current sense signal 2514 reaches or exceeds the overcurrent threshold signal 2512 Then, the overcurrent control signal 2516 becomes a logic low level to trigger overcurrent protection.

參考式9，根據一些實施例，係數α被確定如下： (式11)其中，Rocp表示電阻器1822的電阻，Toneshot表示在採樣信號1616中生成的脈衝的脈寬，並且Cocp表示電容器1824的電容。例如，如果Rocp×Cocp>>Toneshot，則(式12) Referring to Equation 9, according to some embodiments, the coefficient α is determined as follows: (Equation 11) where R ocp represents the resistance of the resistor 1822, T oneshot represents the pulse width of the pulse generated in the sampling signal 1616, and C ocp represents the capacitance of the capacitor 1824. For example, if R ocp ×C ocp >>T oneshot , then (Equation 12)

第15A圖是示出根據本發明另一實施例的具有過流保護的電源轉換器2500的某些元件的簡化圖式。該圖式僅僅是示例，其不應當不當地限制申請專利範圍的範圍。本領域技術人員將認識到許多變體、替換和修改。過流閾值信號生成器2570包括濾波器信號生成器2802、信號生成器2804和信號處理元件2801。例如，信號處理元件2801包括採樣和保持元件2806和低通濾波器2808。在另一示例中，採樣和保持元件2806和低通濾波器2808共用一個或多個元件。在又一示例中，過流保護方案根據第13A圖和第13B圖來實現。在又一示例中，信號生成器2804與信號生成器1604相同。 Figure 15A is a simplified diagram showing certain elements of a power converter 2500 with overcurrent protection in accordance with another embodiment of the present invention. The drawings are merely examples, which should not unduly limit the scope of the claimed scope. Those skilled in the art will recognize many variations, substitutions and modifications. The overcurrent threshold signal generator 2570 includes a filter signal generator 2802, a signal generator 2804, and a signal processing component 2801. For example, signal processing component 2801 includes sample and hold component 2806 and low pass filter 2808. In another example, sample and hold element 2806 and low pass filter 2808 share one or more elements. In yet another example, the overcurrent protection scheme is implemented in accordance with Figures 13A and 13B. In yet another example, signal generator 2804 is the same as signal generator 1604.

根據一實施例，在一開關時程期間，信號生成器2804接收信號2582(例如，PWM信號2522或柵極驅動信號2584)，並且基於信號2582在該開關時程中的占空比來生成斜坡信號2814。例如，濾波器信號生成器2802接收信號2582，並且輸出濾波器信號2816到低通濾波器2808。在又一示例中，當信號2582為邏輯高電平時，採樣和保持元件2806對斜坡信號2814進行採樣和保持。在又一示例中，當信號2582變為邏輯低電平時，低通濾波器2808對採樣和保持元件2806生成的信號2818執行低通濾波，並且向OCP比較器2510輸出過流閾值信號2512。在又一示例中，OCP比較器2510還接收電流感測信號2514並且輸出過流控制信號2516。在又一示例中，過流閾值信號2512根據式9確定，其中，α與低通濾波器2808相關聯。 According to an embodiment, during a switching time period, signal generator 2804 receives signal 2582 (eg, PWM signal 2522 or gate drive signal 2584) and generates a ramp based on the duty cycle of signal 2582 in the switching time course. Signal 2814. For example, filter signal generator 2802 receives signal 2582 and outputs filter signal 2816 to low pass filter 2808. In yet another example, the sample and hold component 2806 samples and holds the ramp signal 2814 when the signal 2582 is at a logic high level. In yet another example, when signal 2582 becomes a logic low level, low pass filter 2808 performs low pass filtering on signal 2818 generated by sample and hold element 2806 and an overcurrent threshold signal 2512 is output to OCP comparator 2510. In yet another example, the OCP comparator 2510 also receives the current sense signal 2514 and outputs an overcurrent control signal 2516. In yet another example, the overcurrent threshold signal 2512 is determined according to Equation 9, where a is associated with the low pass filter 2808.

第15B圖是示出根據本發明另一實施例的包括如第15A圖所示的元件的電源轉換器2500的某些元件的簡化圖式。該圖式僅僅是示例，其不應當不當地限制申請專利範圍的範圍。本領域技術人員將認識到許多變體、替換和修改。信號生成器2804包括電流源2602、開關2604和 2612、及閘2606和2614、比較器2608和2616、電容器2610以及運算放大器2618。信號處理元件2801包括開關2620和2654以及電容器2624和2656。濾波器信號生成器2802包括反閘2650。例如，開關2620和電容器2656被包括在採樣和保持元件2806中。在另一示例中，電容器2656、開關2654和電容器2624被包括在低通濾波器2808中。在又一示例中，電流源2602、開關2604和2612、及閘2606和2614、比較器2608和2616、電容器2610、運算放大器2618和開關2620分別與電流源1802、開關1804和1812、及閘1806和1814、比較器1808和1816、電容器1810、運算放大器1818和開關1820相同。 Figure 15B is a simplified diagram showing certain elements of a power converter 2500 including elements as shown in Figure 15A, in accordance with another embodiment of the present invention. The drawings are merely examples, which should not unduly limit the scope of the claimed scope. Those skilled in the art will recognize many variations, substitutions and modifications. Signal generator 2804 includes current source 2602, switch 2604, and 2612, and gates 2606 and 2614, comparators 2608 and 2616, capacitor 2610, and operational amplifier 2618. Signal processing component 2801 includes switches 2620 and 2654 and capacitors 2624 and 2656. Filter signal generator 2802 includes a reverse gate 2650. For example, switch 2620 and capacitor 2656 are included in sample and hold element 2806. In another example, capacitor 2656, switch 2654, and capacitor 2624 are included in low pass filter 2808. In yet another example, current source 2602, switches 2604 and 2612, and gates 2606 and 2614, comparators 2608 and 2616, capacitor 2610, operational amplifier 2618, and switch 2620 are coupled to current source 1802, switches 1804 and 1812, and gate 1806, respectively. The same as 1814, comparators 1808 and 1816, capacitor 1810, operational amplifier 1818, and switch 1820.

在一些實施例中，如第15B圖所示，及閘2606接收信號2582和來自比較器2608的信號2632，並且如果信號2582和信號2632兩者為邏輯高電平，則輸出邏輯高電平的信號2626。例如，開關2604(例如，S1)響應於為邏輯高電平的信號2626而閉合(例如，接通)。在另一示例中，從電流源2602流經開關2604的電流2628對電容器2610充電，並且作為回應，斜坡信號2814(例如，Vramp)的大小增大。在又一示例中，如果斜坡信號2814的大小超過參考信號2630(例如，Vocp_h)，則比較器2608輸出邏輯低電平的信號2632，並且及閘2606將信號2626改變為邏輯低電平以斷開(例如，關斷)開關2604從而停止對電容器2610充電。在又一示例中，當斜坡信號2814被採樣之後，及閘2614接收邏輯高電平的放電信號2640，並且如果來自比較器2616的信號2636為邏輯高電平，則輸出邏輯高電平的信號2638。在又一示例中，響應於信號2638為邏輯高電平，開關2612(例如，S2)閉合(例如，接通)以對電容器2610放電並且斜坡信號2814的大小減小。在又一示例中，如果斜坡信號2814的大小達到參考信號2634(例如，Vocp_l)，則比較器2616將信號2636變為邏輯低電平，並且作為響應，及閘2614將信號2638改變為邏輯低電平以斷開(例如，關斷)開關2612從而停止對電容器2610放電。 In some embodiments, as shown in FIG. 15B, AND gate 2606 receives signal 2582 and signal 2632 from comparator 2608, and outputs a logic high if both signal 2582 and signal 2632 are at a logic high level. Signal 2626. For example, switch 2604 (eg, S1) is closed (eg, turned "on" in response to signal 2626 that is a logic high level. In another example, current 2628 flowing from current source 2602 through switch 2604 charges capacitor 2610, and in response, the magnitude of ramp signal 2814 (eg, V ramp ) increases. In yet another example, if the ramp signal exceeds the magnitude of the reference signal 2814 2630 (e.g., V ocp_h), the comparator 2608 outputs a logic low signal 2632, signal 2606 and AND gate 2626 changes to a logic low level Switch 2604 is turned off (eg, turned off) to stop charging capacitor 2610. In yet another example, after ramp signal 2814 is sampled, AND gate 2614 receives a high level discharge signal 2640, and if signal 2636 from comparator 2616 is at a logic high level, a logic high level signal is output. 2638. In yet another example, in response to signal 2638 being at a logic high level, switch 2612 (eg, S2) is closed (eg, turned "on") to discharge capacitor 2610 and the magnitude of ramp signal 2814 is reduced. In yet another example, if the magnitude of ramp signal 2814 reaches reference signal 2634 (eg, V ocp — l ), comparator 2616 changes signal 2636 to a logic low level, and in response, AND gate 2614 changes signal 2638 to logic. Low level turns off (eg, turns off) switch 2612 to stop discharging capacitor 2610.

根據一實施例，濾波器信號生成器2802接收信號2582並且輸出濾波器信號2816。例如，當信號2582為邏輯高電平時(例如，在導通時間期間)，開關2620回應於閉合(例如，接通)，並且開關2654回應於 濾波器信號2816斷開(例如，關斷)。在另一示例中，電容器2656回應於通過運算放大器2618的斜坡信號2814被充電。在又一示例中，當信號2582變為邏輯低電平時(例如，在信號2582的下降沿)，則開關2620斷開(例如，關斷)，並且開關2654回應於濾波器信號2816而閉合(例如，接通)。在又一示例中，斜坡信號2814的大小被儲存在電容器2656中並被傳送到電容器2624以生成過流閾值信號2512(例如，Vth_oc)。在又一示例中，當信號2582為邏輯低電平時，濾波器信號2816為邏輯高電平，並且當信號2582為邏輯高電平時，濾波器信號2816為邏輯低電平。 According to an embodiment, filter signal generator 2802 receives signal 2582 and outputs filter signal 2816. For example, when signal 2582 is at a logic high level (eg, during an on time), switch 2620 is responsive to closing (eg, on), and switch 2654 is responsive to filter signal 2816 being turned off (eg, turned off). In another example, capacitor 2656 is charged in response to ramp signal 2814 through operational amplifier 2618. In yet another example, when signal 2582 goes to a logic low level (eg, at the falling edge of signal 2582), switch 2620 is turned off (eg, turned off), and switch 2654 is closed in response to filter signal 2816 ( For example, turn on). In yet another example, the magnitude of ramp signal 2814 is stored in capacitor 2656 and passed to capacitor 2624 to generate an overcurrent threshold signal 2512 (eg, Vth_oc ). In yet another example, filter signal 2816 is a logic high level when signal 2582 is a logic low level and a logic low level when signal 2582 is a logic high level.

參考式9，根據一些實施例，係數α被確定如下： 其中，Csamp表示電容器2656的電容，並且Cocp表示電容器2624的電容。 Referring to Equation 9, according to some embodiments, the coefficient α is determined as follows: Where C samp represents the capacitance of capacitor 2656 and C ocp represents the capacitance of capacitor 2624.

第16A圖是示出根據本發明另一實施例的具有過流保護的電源轉換器2500的某些元件的簡化圖式。該圖式僅僅是示例，其不應當不當地限制申請專利範圍的範圍。本領域技術人員將認識到許多變體、替換和修改。過流閾值信號生成器2570包括採樣信號生成器1902、信號生成器1904、信號處理元件1901、占空比檢測器1926、計數器元件1928、反閘1930、開關1932和1934、以及補償元件1936。例如，信號處理元件1901包括採樣和保持元件1906和低通濾波器1908。例如，採樣和保持元件1906和低通濾波器1908共用一個或多個元件。在另一示例中，採樣信號生成器1902、信號生成器1904、採樣和保持元件1906以及低通濾波器1908分別與採樣信號生成器1602、信號生成器1604、採樣和保持元件1606以及低通濾波器1608相同。 Figure 16A is a simplified diagram showing certain elements of a power converter 2500 with overcurrent protection in accordance with another embodiment of the present invention. The drawings are merely examples, which should not unduly limit the scope of the claimed scope. Those skilled in the art will recognize many variations, substitutions and modifications. The overcurrent threshold signal generator 2570 includes a sample signal generator 1902, a signal generator 1904, a signal processing component 1901, a duty cycle detector 1926, a counter element 1928, a reverse gate 1930, switches 1932 and 1934, and a compensation component 1936. For example, signal processing component 1901 includes a sample and hold component 1906 and a low pass filter 1908. For example, sample and hold element 1906 and low pass filter 1908 share one or more elements. In another example, sample signal generator 1902, signal generator 1904, sample and hold element 1906, and low pass filter 1908 are coupled to sample signal generator 1602, signal generator 1604, sample and hold element 1606, and low pass filter, respectively. The device 1608 is the same.

根據一實施例，占空比檢測器1926接收信號2582並且判斷特定開關時程的信號2582的占空比是否大於占空比閾值。例如，如果占空比檢測器1926判定該特定開關時程的信號2582的占空比大於占空比閾值，則作為回應，計數器元件1928輸出邏輯低電平的採樣禁止信號1940，並且因此來自反閘1930的採樣使能信號1938為邏輯高電平，以使得開關1932閉合(例如，接通)並且開關1934斷開(例如，關斷)。在另一示例中，如果占空比檢測器1926判定該特定開關時程的信號2582的占空比小 於占空比閾值，則計數器元件1928檢測信號2582的占空比是否保持小於占空比閾值達預定數目的開關時程。在又一示例中，如果信號2582的占空比保持小於占空比閾值達預定數目的開關時程，則計數器元件1928輸出邏輯高電平的採樣禁止信號1940，並且因此採樣使能信號1938為邏輯低電平，以使得開關1932斷開(例如，關斷)並且開關1934閉合(例如，接通)。 According to an embodiment, the duty cycle detector 1926 receives the signal 2582 and determines if the duty cycle of the signal 2582 of the particular switching time period is greater than the duty cycle threshold. For example, if duty cycle detector 1926 determines that the duty cycle of signal 2582 for the particular switch time course is greater than the duty cycle threshold, then in response, counter component 1928 outputs a sample disable signal 1940 of a logic low level, and thus from the inverse The sample enable signal 1938 of the gate 1930 is at a logic high level such that the switch 1932 is closed (eg, turned "on" and the switch 1934 is turned "off" (eg, turned off). In another example, if duty cycle detector 1926 determines that the duty cycle of signal 2582 for the particular switch time period is small At the duty cycle threshold, counter element 1928 detects if the duty cycle of signal 2582 remains less than the duty cycle threshold for a predetermined number of switching time periods. In yet another example, if the duty cycle of signal 2582 remains less than the duty cycle threshold for a predetermined number of switch time periods, counter element 1928 outputs a sample disable signal 1940 of a logic high level, and thus sample enable signal 1938 is A logic low level causes switch 1932 to open (eg, turn off) and switch 1934 to close (eg, turn "on").

根據另一實施例，在一開關時程期間，信號生成器1904接收信號2582，並且基於信號2582在該開關時程中的占空比生成斜坡信號1914(例如，Vramp)。例如，採樣信號生成器1902接收信號2582，並且生成採樣信號1916。在另一示例中，採樣信號生成器1902在信號2582的下降沿時在採樣信號1916中輸出脈衝。在又一示例中，採樣和保持元件1906在採樣信號1916的脈衝期間對斜坡信號1914採樣，並且在該開關時程的其餘時間期間保持斜坡信號1914的大小(例如，在該脈衝的結束處)直到下一脈衝為止。在又一示例中，低通濾波器1908對採樣和保持元件1906生成的信號1918執行低通濾波，並且如果開關1932回應於採樣使能信號1938而閉合(例如，接通)，則輸出過流閾值信號2512(例如，Vth_oc)給OCP比較器2510。在又一示例中，作為時間的函數的過流閾值信號2512(例如，Vth_oc)的波形與如第14B圖所示的波形1706類似。在又一示例中，OCP比較器2510還接收電流感測信號2514並且輸出過流控制信號2516。 According to another embodiment, during a switching time period, signal generator 1904 receives signal 2582 and generates ramp signal 1914 (eg, V ramp ) based on the duty cycle of signal 2582 in the switching time period. For example, sample signal generator 1902 receives signal 2582 and generates sample signal 1916. In another example, the sampled signal generator 1902 outputs a pulse in the sampled signal 1916 at the falling edge of the signal 2582. In yet another example, the sample and hold element 1906 samples the ramp signal 1914 during the pulse of the sampled signal 1916 and maintains the magnitude of the ramp signal 1914 during the remainder of the switch time course (eg, at the end of the pulse) Until the next pulse. In yet another example, low pass filter 1908 performs low pass filtering on signal 1918 generated by sample and hold element 1906, and outputs over current if switch 1932 is closed (eg, turned "on") in response to sample enable signal 1938. Threshold signal 2512 (eg, Vth_oc ) is given to OCP comparator 2510. In yet another example, the waveform of the overcurrent threshold signal 2512 (eg, Vth_oc ) as a function of time is similar to the waveform 1706 as shown in FIG. 14B. In yet another example, the OCP comparator 2510 also receives the current sense signal 2514 and outputs an overcurrent control signal 2516.

根據又一實施例，補償元件1936接收信號2582，並且如果開關1934回應於採樣禁止信號1940而閉合(例如，接通)，則向OCP比較器2510輸出過流閾值信號2512(例如，Vth_oc)。例如，作為時間的函數的過流閾值信號2512(例如，Vth_oc)的波形在與補償元件1936相關聯的圖中示出。即，在一些實施例中，在0與最大時間(例如，tmax)之間，過流閾值信號2512(例如，Vth_oc)在最小值(例如，Vocp_l)與最大值(例如，Vocp_h)之間相對於時間以正斜率增大。 According to yet another embodiment, the compensation component 1936 receives the signal 2582 and, if the switch 1934 is closed (eg, turned "on" in response to the sample disable signal 1940, outputs an overcurrent threshold signal 2512 (eg, Vth_oc ) to the OCP comparator 2510. . For example, the waveform of the overcurrent threshold signal 2512 (eg, Vth_oc ) as a function of time is shown in the diagram associated with the compensation component 1936. That is, in some embodiments, between 0 and the maximum time (eg, tmax ), the overcurrent threshold signal 2512 (eg, Vth_oc ) is at a minimum (eg, Vocp_l ) and a maximum (eg, Vocp_h) ) increases with a positive slope with respect to time.

在一實施例中，斜坡信號1914與傾斜上升過程和傾斜下降過程相關聯。例如，在傾斜上升過程期間，斜坡信號1914的大小從最小值增大到最大值，並且在傾斜下降過程期間，斜坡信號1914的大小從最大值 減小到最小值。在另一示例中，傾斜上升過程和/或傾斜下降過程暫態地或者在一時間段期間發生。在另一實施例中，斜坡信號1914與傾斜上升過程、恒定過程和傾斜下降過程相關聯。例如，在傾斜上升過程期間，斜坡信號1914的大小從最小值增大到最大值；在恒定過程期間，斜坡信號1914保持為最大值；並且在傾斜下降過程期間，斜坡信號1914的大小從最大值減小到最小值。在另一示例中，傾斜上升過程、恒定過程和/或傾斜下降過程暫態地或者在一時間段期間發生。在又一實施例中，斜坡信號1914與傾斜上升過程、第一恒定過程、傾斜下降過程和第二恒定過程相關聯。例如，在傾斜上升過程期間，斜坡信號1914的大小從最小值增大到最大值；並且在第一恒定過程期間，斜坡信號1914保持為最大值。在傾斜下降過程期間，斜坡信號1914的大小從最大值減小到最小值；並且在第二恒定過程期間，斜坡信號1914保持為最小值。傾斜上升過程、第一恒定過程、傾斜下降過程和/或第二恒定過程暫態地或者在一時間段期間發生。 In an embodiment, the ramp signal 1914 is associated with a ramp up process and a ramp down process. For example, during the ramp up process, the magnitude of the ramp signal 1914 increases from a minimum value to a maximum value, and during the ramp down process, the magnitude of the ramp signal 1914 is from a maximum value. Reduce to the minimum. In another example, the ramp up process and/or the ramp down process occur transiently or during a time period. In another embodiment, the ramp signal 1914 is associated with a ramp up process, a constant process, and a ramp down process. For example, during the ramp up process, the magnitude of the ramp signal 1914 increases from a minimum value to a maximum value; during a constant process, the ramp signal 1914 remains at a maximum value; and during the ramp down process, the magnitude of the ramp signal 1914 is from a maximum value Reduce to the minimum. In another example, the ramp up process, the constant process, and/or the ramp down process occur transiently or during a time period. In yet another embodiment, the ramp signal 1914 is associated with a ramp up process, a first constant process, a ramp down process, and a second constant process. For example, during the ramp up process, the magnitude of the ramp signal 1914 increases from a minimum value to a maximum value; and during the first constant process, the ramp signal 1914 remains at a maximum value. During the ramp down process, the magnitude of the ramp signal 1914 decreases from a maximum value to a minimum value; and during the second constant process, the ramp signal 1914 remains at a minimum value. The ramp up process, the first constant process, the ramp down process, and/or the second constant process occur transiently or during a time period.

第16B圖是根據本發明另一實施例的包括如第16A圖所示的元件的電源轉換器2500的簡化時序圖。該圖式僅僅是示例，其不應當不當地限制申請專利範圍的範圍。本領域技術人員將認識到許多變體、替換和修改。波形2000表示作為時間的函數的信號2582，波形2002表示作為時間的函數的採樣信號1916，波形2004表示作為時間的函數的斜坡信號1914，波形2006表示作為時間的函數的過流閾值信號2512(例如，Vth_oc)，並且波形2008表示作為時間的函數的電流感測信號2514。 Figure 16B is a simplified timing diagram of a power converter 2500 including elements as shown in Figure 16A, in accordance with another embodiment of the present invention. The drawings are merely examples, which should not unduly limit the scope of the claimed scope. Those skilled in the art will recognize many variations, substitutions and modifications. Waveform 2000 represents signal 2582 as a function of time, waveform 2002 represents a sampled signal 1916 as a function of time, waveform 2004 represents a ramp signal 1914 as a function of time, and waveform 2006 represents an overcurrent threshold signal 2512 as a function of time (eg, , V th — oc ), and waveform 2008 represents current sense signal 2514 as a function of time.

例如，波形2006表示作為時間的函數的過流閾值信號2512(例如，Vth_oc)，其包括作為一開關時程Tswd內的時間的函數的過流閾值信號2512(例如，Vth_oc)以及作為一開關時程Tswe內的時間的函數的過流閾值信號2512(例如，Vth_oc)。在另一示例中，波形2008表示作為時間的函數的電流感測信號2514，其包括作為一開關時程Tswd內的時間的函數的電流感測信號2514以及作為一開關時程Tswe內的時間的函數的電流感測信號2514。 For example, a waveform 2006 indicates as a function of time overcurrent threshold signal 2512 (e.g., V th_oc), which comprises as a switch overcurrent function of time in the path T swd threshold signal 2512 (e.g., V th_oc) as well as when an overcurrent switching function of time in the threshold signal T swe drive 2512 (e.g., V th_oc). In another example, the waveform 2008 represents a function of time as a current sense signal 2514 that includes, as a function of time when in the Cheng T swd a switch current sense signal 2514 as an internal drive, and when a switch T swe Current sense signal 2514 as a function of time.

例如，如第16B圖所示，導通時間Tond開始於時間t10並結束於時間t11，關斷時間Toffd開始於時間t11並結束於時間t13，導通時間Tone 開始於時間t14並結束於時間t15，關斷時間Toffe開始於時間t15並結束於時間t17。在另一示例中，t10 t11 t12 t13 t14 t15 t16 t17 t18 t19。 For example, as shown in FIG. 16B, the on-time T ond starts at time t 10 and ends at time t 11 , the off-time T offd starts at time t 11 and ends at time t 13 , and the on-time T one starts at time t 14 and ending at time t 15 , the off time T offe starts at time t 15 and ends at time t 17 . In another example, t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 .

根據一實施例，最初，信號2582的占空比大於占空比閾值(例如，t10處)並且採樣使能信號1938為邏輯高電平以閉合(例如，接通)開關1932(例如，S2)。例如，在導通時間Tond期間，信號2582保持為邏輯高電平(例如，如波形2000所示)。在另一示例中，斜坡信號1914從大小2010(例如，t10處)增大到大小2012(例如，t11處)，如波形2004所示。在又一示例中，過流閾值信號2512(例如，Vth_oc)在導通時間Tond期間保持大小2014(例如，如波形2006所示)。在又一示例中，電流感測信號2514從大小2016(例如，t10處)增大，如波形2008所示。在一些實施例中，一旦電流感測信號2514超過大小2014(例如，t11處)，則過流保護被觸發。例如，OCP比較器2510將過流控制信號2516從邏輯高電平變為邏輯低電平。在另一示例中，然後，過流感測信號2514下降為大小2024(例如，t11處的0)並且在關斷時間Toffd期間保持為大小2024(例如，如波形2008所示)。 According to an embodiment, initially, the duty cycle of signal 2582 is greater than a duty cycle threshold (eg, at t 10 ) and sampling enable signal 1938 is at a logic high level to close (eg, turn on) switch 1932 (eg, S2) ). For example, during the on time Todd , signal 2582 remains at a logic high level (e.g., as shown by waveform 2000). In another example, ramp signal 1914 increases from size 2010 (eg, at t 10 ) to size 2012 (eg, at t 11 ) as shown by waveform 2004. In yet another example, the overcurrent threshold signal 2512 (e.g., V th_oc) holding size 2014 (e.g., shown as waveform 2006) during the on-time T ond. In yet another example, current sense signal 2514 increases from size 2016 (eg, at t 10 ) as shown by waveform 2008. In some embodiments, once the current sense signal 2514 exceeds the magnitude 2014 (eg, at t 11 ), overcurrent protection is triggered. For example, OCP comparator 2510 changes overcurrent control signal 2516 from a logic high level to a logic low level. In another example, the over- flux signal 2514 then falls to a size 2024 (eg, 0 at t 11 ) and remains at a size 2024 during the off-time T offd (eg, as shown by waveform 2008).

根據另一實施例，在信號2582的下降沿處(例如，t11處)，在採樣信號1916中生成脈衝(例如，如波形2002所示)。例如，該脈衝開始於時間t11並結束於時間t12。在另一示例中，採樣和保持元件1906在該脈衝期間對斜坡信號1914採樣，並且作為回應，過流閾值信號2512(例如，Vth_oc)從大小2014(例如，t11處)變為大小2018(例如，t12處)，如波形2006所示。在又一示例中，斜坡信號1914在該脈衝期間保持為大小2012，並且在該脈衝的結束處(例如，t12處)下降為大小2010(例如，Vocp_l)，如波形2004所示。在又一示例中，在t12與t13之間的時間段期間，斜坡信號1914保持為大小2010(例如，Vocp_l)，如波形2004所示，並且過流閾值信號2512(例如，Vth_oc)保持為大小2018，如波形2006所示。在另一示例中，過流閾值信號2512(例如，Vth_oc)的大小2014和2018可基於式9來確定。 According to another embodiment, at a falling edge of the signal 2582 (e.g., t 11 at), generates a pulse (e.g., shown as waveform 2002) in 1916 in the sampled signal. For example, the pulse begins at time t 11 and ends at time t 12 . In another example, the sample and hold element 19,061,914 samples during the ramp pulse signal, and in response, the overcurrent threshold signal 2512 (e.g., V th_oc) from the 2014 size (e.g., t 11 Office) becomes size 2018 (eg, at t 12 ) as shown by waveform 2006. In yet another example, ramp signal 1914 remains at size 2012 during the pulse and falls to size 2010 (eg, V ocp — l ) at the end of the pulse (eg, at t 12 ), as shown by waveform 2004. In yet another example, during a time period between t 12 and t 13 , ramp signal 1914 remains at size 2010 (eg, V ocp — l ), as shown by waveform 2004, and overcurrent threshold signal 2512 (eg, V th — oc ) remains at size 2018 as shown in waveform 2006. In another example, the magnitudes 2014 and 2018 of the overcurrent threshold signal 2512 (eg, Vth_oc ) may be determined based on Equation 9.

根據又一實施例，此後，信號2582的占空比變為小於占空比閾值(例如，t13處)。例如，如果信號2582的占空比保持小於占空比閾 值達預定數目的開關時程(例如，t13與t14之間)，則採樣使能信號1938變為邏輯低電平以斷開(例如，關斷)開關1932並且採樣禁止信號1940變為邏輯高電平以閉合(例如，接通)開關1934(例如，t14處)，以使得補償元件1936取代低通濾波器1908輸出過流閾值信號2512(例如，Vth_oc)。 According to yet another embodiment, thereafter, the signal 2582 becomes less than the duty ratio of the duty ratio threshold (e.g., t at 13). For example, if the duty cycle of signal 2582 remains less than the duty cycle threshold for a predetermined number of switching time periods (eg, between t 13 and t 14 ), then sample enable signal 1938 goes to a logic low level to turn off ( For example, the switch 1932 is turned off and the sample disable signal 1940 goes to a logic high level to close (eg, turn on) the switch 1934 (eg, at t 14 ) such that the compensation component 1936 replaces the low pass filter 1908 output overcurrent. Threshold signal 2512 (eg, Vth_oc ).

如第16B圖所示，在導通時間Tone期間，信號2582保持為邏輯高電平(例如，如波形2000所示)。例如，斜坡信號1914從大小2010(例如，t14處)增大到小於2012的某個值(例如，t15處)，如波形2004所示。在另一示例中，過流閾值信號2512(例如，Vth_oc)從大小2026(例如，t14處的Vocp_l)增大到大小2030(例如，t15處)，例如，如波形2006所示。在又一示例中，電流感測信號2514從大小2032(例如，t14處)增大，如波形2008所示。在一些實施例中，一旦電流感測信號2514超過大小2030(例如，t15處)，則過流保護被觸發。例如，OCP元件2510將過流控制信號2516從邏輯高電平變為邏輯低電平。在另一示例中，電流感測信號2514下降為大小2032(例如，t15處)並且在關斷時間Toffe期間保持為大小2032(例如，如波形2008所示)。在又一示例中，在關斷時間Toffe期間，過流閾值信號2512(例如，Vth_oc)繼續增大直到達到最大大小2028(例如，t16處的Vocp_h)為止，並且在下一導通時間之前保持為大小2028。在又一示例中，在下一開關時程期間，過流閾值信號2512(例如，Vth_oc)具有與導通時間Tone和關斷時間Toffe期間類似的波形(例如，如波形2006所示)。在一些實施例中，在t14與t18之間的時間段期間，當信號2582的占空比維持小於占空比閾值時，過流閾值信號2512(例如，Vth_oc)不由斜坡信號1914確定。 As shown in FIG. 16B, during the on time Tone , signal 2582 remains at a logic high level (eg, as shown by waveform 2000). For example, ramp signal 1914 increases from size 2010 (eg, at t 14 ) to a value less than 2012 (eg, at t 15 ), as shown by waveform 2004. In another example, the overcurrent threshold signal 2512 (eg, V th — oc ) increases from a size 2026 (eg, V ocp — l at t 14 ) to a size 2030 (eg, at t 15 ), eg, as shown in waveform 2006 . In yet another example, current sense signal 2514 increases from size 2032 (eg, at t 14 ) as shown by waveform 2008. In some embodiments, once current sense signal 2514 exceeds size 2030 (eg, at t 15 ), overcurrent protection is triggered. For example, OCP component 2510 changes overcurrent control signal 2516 from a logic high level to a logic low level. In another example, current sense signal 2514 falls to size 2032 (eg, at t 15 ) and remains at size 2032 during off time T offe (eg, as shown by waveform 2008). In yet another example, during the off time T offe , the overcurrent threshold signal 2512 (eg, V th — oc ) continues to increase until the maximum size 2028 is reached (eg, V ocp — h at t 16 ), and at the next on time Previously kept at size 2028. In still another example, during the next switch drive overcurrent threshold signal 2512 (e.g., V th_oc) having the conduction time T one and similar waveform during the off time T offe (e.g., as the waveform shown in 2006). In some embodiments, during a time period between t 14 and t 18 , the overcurrent threshold signal 2512 (eg, V th — oc ) is not determined by the ramp signal 1914 when the duty cycle of the signal 2582 remains less than the duty cycle threshold. .

根據又一實施例，此後，信號2582的占空比變為再次大於占空比閾值(例如，t18與t19之間)。例如，採樣使能信號1938變為邏輯高電平以閉合(例如，接通)開關1932並且採樣禁止信號1940變為邏輯低電平以斷開(例如，關斷)開關1934。在另一示例中，補償元件1936不再確定過流閾值信號2512(例如，Vth_oc)。在某些實施例中，取而代之的是，過流保護由信號生成器1904、採樣信號生成器1902、採樣和保持元件1906和/或低通濾波器1908執行，如上面討論的。 According to yet another embodiment, after the duty ratio of the signal 2582 becomes greater than the threshold value again, the duty cycle (e.g., t between 18 and t 19). For example, the sample enable signal 1938 goes to a logic high level to close (eg, turn on) the switch 1932 and the sample disable signal 1940 becomes a logic low to turn off (eg, turn off) the switch 1934. In another example, the compensation component 1936 no longer determines an overcurrent threshold signal 2512 (eg, Vth_oc ). In some embodiments, the overcurrent protection is instead performed by signal generator 1904, sample signal generator 1902, sample and hold element 1906, and/or low pass filter 1908, as discussed above.

第17圖是示出根據本發明又一實施例的具有過流保護的電 源轉換器2500的某些元件的簡化圖式。該圖示僅僅是示例，其不應當不當地限制申請專利範圍的範圍。本領域技術人員將認識到許多變體、替換和修改。過流閾值信號生成器2570包括濾波器信號生成器2902、信號生成器2904、信號處理元件2901、占空比檢測器2926、計數器元件2928、反閘2930、開關2932和2934、以及補償元件2936。信號處理元件2901包括採樣和保持元件2906和低通濾波器2908。例如，採樣和保持元件2906和低通濾波器2908共用一個或多個元件。 Figure 17 is a diagram showing electric power with overcurrent protection according to still another embodiment of the present invention. A simplified diagram of certain elements of source converter 2500. This illustration is merely an example and should not unduly limit the scope of the claimed scope. Those skilled in the art will recognize many variations, substitutions and modifications. The overcurrent threshold signal generator 2570 includes a filter signal generator 2902, a signal generator 2904, a signal processing component 2901, a duty cycle detector 2926, a counter element 2928, a reverse gate 2930, switches 2932 and 2934, and a compensation component 2936. Signal processing component 2901 includes a sample and hold component 2906 and a low pass filter 2908. For example, sample and hold element 2906 and low pass filter 2908 share one or more elements.

例如，濾波器信號生成器2902、信號生成器2904、採樣和保持元件2906以及低通濾波器2908分別與相同濾波器信號生成器2802、信號生成器2804、採樣和保持元件2806以及低通濾波器2808。在另一示例中，信號生成器2904、占空比檢測器2926、計數器元件2928、反閘2930、開關2932和2934、以及補償元件2936分別與信號生成器1904、占空比檢測器1926、計數器元件1928、反閘1930、開關1932和1934、以及補償元件1936相同。 For example, filter signal generator 2902, signal generator 2904, sample and hold element 2906, and low pass filter 2908 are identical to filter signal generator 2802, signal generator 2804, sample and hold element 2806, and low pass filter, respectively. 2808. In another example, signal generator 2904, duty cycle detector 2926, counter element 2928, inverse gate 2930, switches 2932 and 2934, and compensation component 2936, respectively, with signal generator 1904, duty cycle detector 1926, counter Element 1928, reverse gate 1930, switches 1932 and 1934, and compensation element 1936 are identical.

根據一實施例，占空比檢測器2926接收信號2582並且判斷特定開關時程的信號2582的占空比是否大於占空比閾值。例如，如果占空比檢測器2926判定該特定開關時程的信號2582的占空比大於占空比閾值，則作為回應，計數器元件2928輸出邏輯低電平的採樣禁止信號2940，並且因此來自反閘2930的採樣使能信號2938為邏輯高電平，以使得開關2932閉合(例如，接通)並且開關2934斷開(例如，關斷)。在另一示例中，如果占空比檢測器2926判定該特定開關時程的信號2582的占空比小於占空比閾值，則計數器元件2928檢測信號2582的占空比是否保持小於占空比閾值達預定數目的開關時程。在又一示例中，如果信號2582的占空比保持小於占空比閾值達預定數目的開關時程，則計數器元件2928輸出邏輯高電平的採樣禁止信號2940，並且因此採樣使能信號2938為邏輯低電平，以使得開關2932斷開(例如，關斷)並且開關2934閉合(例如，接通)。 According to an embodiment, duty cycle detector 2926 receives signal 2582 and determines if the duty cycle of signal 2582 for a particular switch time period is greater than a duty cycle threshold. For example, if duty cycle detector 2926 determines that the duty cycle of signal 2582 for the particular switch time course is greater than the duty cycle threshold, then in response, counter component 2928 outputs a sample disable signal 2940 of a logic low level, and thus from the inverse The sample enable signal 2938 of gate 2930 is at a logic high level such that switch 2932 is closed (eg, turned "on" and switch 2934 is turned "off" (eg, turned off). In another example, if duty cycle detector 2926 determines that the duty cycle of signal 2582 for the particular switch time course is less than the duty cycle threshold, then counter component 2928 detects if the duty cycle of signal 2582 remains less than the duty cycle threshold. A predetermined number of switching time courses. In yet another example, if the duty cycle of signal 2582 remains less than the duty cycle threshold for a predetermined number of switch time periods, counter element 2928 outputs a sample disable signal 2940 of a logic high level, and thus sample enable signal 2938 is The logic is low level such that switch 2932 is open (eg, turned off) and switch 2934 is closed (eg, turned "on").

根據另一實施例，在一開關時程期間，信號生成器2904接收信號2582，並且基於信號2582在該開關時程中的占空比生成斜坡信號 2914(例如，Vramp)。例如，濾波器信號生成器2902接收信號2582，並且向低通濾波器2908輸出濾波器信號2916。在另一示例中，當信號2582為邏輯高電平時，採樣和保持元件2906對斜坡信號2914採樣和保持。在又一示例中，當信號2582變為邏輯低電平時，低通濾波器2908對採樣和保持元件2906生成的信號2918(例如，Vsample)執行低通濾波，並且如果開關2932回應於採樣使能信號2938而閉合(例如，接通)，則輸出過流閾值信號2512(例如，Vth_oc)給OCP比較器2510。在又一示例中，OCP比較器2510還接收電流感測信號2514並且輸出過流控制信號2516。 According to another embodiment, during a switching time period, signal generator 2904 receives signal 2582 and generates ramp signal 2914 (eg, V ramp ) based on the duty cycle of signal 2582 in the switching time period. For example, filter signal generator 2902 receives signal 2582 and outputs filter signal 2916 to low pass filter 2908. In another example, when signal 2582 is at a logic high level, sample and hold element 2906 samples and holds ramp signal 2914. In yet another example, when signal 2582 becomes a logic low level, low pass filter 2908 performs low pass filtering on signal 2918 (eg, Vsample ) generated by sample and hold element 2906, and if switch 2932 is responsive to sampling The energy signal 2938 is closed (eg, turned "on"), and an overcurrent threshold signal 2512 (eg, Vth_oc ) is output to the OCP comparator 2510. In yet another example, the OCP comparator 2510 also receives the current sense signal 2514 and outputs an overcurrent control signal 2516.

根據又一實施例，補償元件2936接收信號2582，並且如果開關2934回應於採樣禁止信號2940而閉合(例如，接通)，則向OCP比較器2510輸出過流閾值信號2512(例如，Vth_oc)。例如，作為時間的函數的過流閾值信號2512(例如，Vth_oc)的波形在與補償元件2936相關聯的圖中示出。即，在一些實施例中，在0與最大時間(例如，tmax)之間，過流閾值信號2512(例如，Vth_oc)在最小值(例如，Vocp_l)與最大值(例如，Vocp_h)之間相對於時間以正斜率增大。 According to yet another embodiment, the compensation component 2936 receives the signal 2582 and, if the switch 2934 is closed (eg, turned "on" in response to the sample disable signal 2940, outputs an overcurrent threshold signal 2512 (eg, Vth_oc ) to the OCP comparator 2510. . For example, the waveform of the overcurrent threshold signal 2512 (eg, Vth_oc ) as a function of time is shown in the diagram associated with the compensation component 2936. That is, in some embodiments, between 0 and the maximum time (eg, tmax ), the overcurrent threshold signal 2512 (eg, Vth_oc ) is at a minimum (eg, Vocp_l ) and a maximum (eg, Vocp_h) ) increases with a positive slope with respect to time.

根據本發明一些實施例，負斜率補償可被引入過流閾值信號2512(例如，Vth_oc)，如第18A圖，第18B圖，第20A圖和第20B圖所示。 In accordance with some embodiments of the present invention, negative slope compensation may be introduced into overcurrent threshold signal 2512 (e.g., Vth_oc ) as shown in Fig. 18A, Fig. 18B, Fig. 20A and Fig. 20B.

第18A圖是示出根據本發明又一實施例的作為開關時程內的時間的函數的過流閾值信號2512的簡化圖式。該圖示僅僅是示例，其不應當不當地限制申請專利範圍的範圍。本領域技術人員將認識到許多變體、替換和修改。 Figure 18A is a simplified diagram showing an overcurrent threshold signal 2512 as a function of time within a switch time course, in accordance with yet another embodiment of the present invention. This illustration is merely an example and should not unduly limit the scope of the claimed scope. Those skilled in the art will recognize many variations, substitutions and modifications.

在一實施例中，波形1402表示在開關時程T5內作為時間的函數的過流閾值信號2512(例如，Vth_oc)，並且導通時間在開關時程T5的開始處被設為零。在另一實施例中，波形1404表示在開關時程T6內作為時間的函數的過流閾值信號2512(例如，Vth_oc)，並且導通時間在開關時程T6的開始處被設為零在又一實施例中，波形1406表示在開關時程T7內作為時間的函數的過流閾值信號2512(例如，Vth_oc)，並且導通時間在開關時程T7的開始處被設為零。在又一實施例中，波形1408表示在開關時程T8內作為時間的函數的過流閾值信號2512(例如，Vth_oc)，並且導通時間 在開關時程T8的開始處被設為零。例如，開關時程T5,T6,T7和T8的大小相等，儘管它們對應於不同的開關週期。在另一示例中，波形1402,1404,1406和1408分別對應於整流後電容上的電壓Vin5,Vin6,Vin7和Vin8。 In one embodiment, the waveform 1402 indicates when the switch is used as the overcurrent function of time threshold signal 2512 (e.g., V th_oc) course T 5, and the on-time when the switching path T at the beginning of 5 is set to zero. In another embodiment, the waveform 1404 when the switch 6 the course T as a function of time overcurrent threshold signal 2512 (e.g., V th_oc), and the conduction time of the switch at the beginning of the process T 6 is set to zero in yet another embodiment, the waveform 1406 when the switch as a function of time in the path T 7 overcurrent threshold signal 2512 (e.g., V th_oc), and the conduction time of the switch at the beginning of the process T 7 is set to zero . In yet another embodiment, a waveform 1408 indicates the switch as a function of time of 8 course T overcurrent threshold signal 2512 (e.g., V th_oc), and the conduction time of the switch at the beginning of the process T 8 is set to zero . For example, the switching time periods T 5 , T 6 , T 7 and T 8 are equal in magnitude, although they correspond to different switching periods. In another example, waveforms 1402, 1404, 1406, and 1408 correspond to voltages V in5 , V in6 , V in7 , and V in8 , respectively, on the rectified capacitor.

根據一實施例，如第18A圖所示，對於特定的導通時間，過流閾值信號2512(例如，Vth_oc)在0與一時間閾值(例如，th)之間不隨著時間改變，並且在該時間閾值(例如，th)與最大時間(例如，tmax)之間隨著時間改變，例如，如波形1402,1404,1406或1408所示。例如，時間閾值(例如，th)對應於占空比閾值(例如，Dh)。根據某些實施例，過流閾值信號2512(例如，Vth_oc)的值在不同的導通時間期間變化。例如，在0與該時間閾值(例如，th)之間的過流閾值信號2512的值根據式9和/或式10來確定。即，在一些實施例中，特定開關時程中的過流閾值信號2512的值受到一個或多個之前開關時程的占空比的影響。例如，一個或多個之前開關時程的占空比越大，該特定開關時程中的過流閾值信號2512的值就變得越大。在另一示例中，在0與該時間閾值(例如，th)之間，過流閾值信號2512的值等於或大於過流閾值信號2512的最小值(例如，Vocp_l)，並且等於或小於過流閾值信號2512的最大值(例如，Vocp_h)。在又一示例中，在該時間閾值(例如，th)之外，過流閾值信號2512的值等於或小於過流閾值信號2512的最大值(例如，Vocp_h)。在又一示例中，在該時間閾值(例如，th)之外，過流閾值信號2512的值等於或大於過流閾值信號2512的最小值(例如，Vocp_l)。 According to an embodiment, as the first 18A figure, for a particular on-time, the overcurrent threshold signal 2512 (e.g., V th_oc) does not change with time between a time threshold (e.g., t h) at 0, and The time threshold (eg, t h ) and the maximum time (eg, t max ) change over time, for example, as shown by waveforms 1402, 1404, 1406, or 1408. For example, a time threshold (eg, t h ) corresponds to a duty cycle threshold (eg, D h ). According to some embodiments, the value of the overcurrent threshold signal 2512 (eg, Vth_oc ) varies during different on-times. For example, the overcurrent threshold signal value 2512 between the time threshold (e.g., t h) 0 determined according to Formula 9 and / or Formula 10. That is, in some embodiments, the value of the overcurrent threshold signal 2512 in a particular switching time period is affected by the duty cycle of one or more previous switching time periods. For example, the greater the duty cycle of one or more previous switching time periods, the greater the value of the overcurrent threshold signal 2512 in that particular switching time period becomes. In another example, between 0 and the time threshold (eg, t h ), the value of the overcurrent threshold signal 2512 is equal to or greater than the minimum value of the overcurrent threshold signal 2512 (eg, Vocp_l) and is equal to or less than The maximum value of the flow threshold signal 2512 (eg, V ocp — h ). In yet another example, outside of the time threshold (eg, t h ), the value of the overcurrent threshold signal 2512 is equal to or less than the maximum value of the overcurrent threshold signal 2512 (eg, V ocp — h ). In yet another example, outside of the time threshold (eg, t h ), the value of the overcurrent threshold signal 2512 is equal to or greater than the minimum value of the overcurrent threshold signal 2512 (eg, Vocp — 1).

第18B圖是示出根據本發明又一實施例的使用如第18A圖所示作為開關時程內的時間的函數的過流閾值信號2512來確定導通時間的簡化圖式。該圖式僅僅是示例，其不應當不當地限制申請專利範圍的範圍。本領域技術人員將認識到許多變體、替換和修改。波形1410,1412,1414和1416分別表示與整流後電容上的電壓Vin5,Vin6,Vin7和Vin8相對應的、作為時間的函數的電流感測信號2514(例如，VCS)。例如，波形1410,1412,1414和1416中所示的斜率分別是S5,S6,S7和S8。 Figure 18B is a simplified diagram showing the determination of the on-time using an overcurrent threshold signal 2512 as a function of time within the switch time history as shown in Figure 18A, in accordance with yet another embodiment of the present invention. The drawings are merely examples, which should not unduly limit the scope of the claimed scope. Those skilled in the art will recognize many variations, substitutions and modifications. Waveforms 1410, 1412, 1414, and 1416 represent current sense signals 2514 (e.g., V CS ) as a function of time, corresponding to voltages V in5 , V in6 , V in7 , and V in8 on the rectified capacitor, respectively. For example, the slopes shown in waveforms 1410, 1412, 1414, and 1416 are S 5 , S 6 , S 7 , and S 8 , respectively .

根據一實施例，相對於特定的整流後電容上的電壓，電流感測信號2514(例如，VCS)隨著時間增大(例如，如波形1410,1412,1414和 1416所示)。在一些實施例中，如第18B圖所示，電流感測信號2514(例如，VCS)相對於時間的斜率隨著整流後電容上的電壓增大而增大。例如，Vin5>Vin6>Vin7>Vin8，並且相應地，S5>S6>S7>S8。在另一示例中，當電流感測信號2514(例如，VCS)的大小超過過流閾值信號2512時(例如，如波形1410,1412,1414或1416所示)，過流保護被觸發。在又一示例中，在Tdelay(例如，“輸出延遲”)期間，電流感測信號2514(例如，VCS)的大小繼續增大。在又一示例中，在Tdelay的結束處，開關被斷開(例如，關斷)，並且電流感測信號2514(例如，VCS)達到其最大大小。在一些實施例中，Tdelay的結束是在一開關時程內開關2540的導通時間的結束。例如，對於整流後電容上的電壓Vin5，Tdelay的結束對應於時間tE，對於整流後電容上的電壓Vin6，Tdelay的結束對應於時間tF，對於整流後電容上的電壓Vin7，Tdelay的結束對應於時間tG，並且對於整流後電容上的電壓Vin8，Tdelay的結束對應於時間tI。 According to an embodiment, current sense signal 2514 (eg, V CS ) increases with time relative to a voltage on a particular rectified capacitor (eg, as shown by waveforms 1410, 1412, 1414, and 1416). In some embodiments, as shown in FIG. 18B, the slope of current sense signal 2514 (eg, V CS ) with respect to time increases as the voltage across the rectified capacitor increases. For example, V in5 >V in6 >V in7 >V in8 , and correspondingly, S 5 >S 6 >S 7 >S 8 . In another example, when the magnitude of current sense signal 2514 (eg, V CS ) exceeds overcurrent threshold signal 2512 (eg, as shown by waveforms 1410, 1412, 1414, or 1416), overcurrent protection is triggered. In yet another example, during Tdelay (eg, "output delay"), the magnitude of current sense signal 2514 (eg, VCS ) continues to increase. In yet another example, at the end of Tdelay , the switch is turned off (eg, turned off) and current sense signal 2514 (eg, V CS ) reaches its maximum size. In some embodiments, the end of Tdelay is the end of the on time of switch 2540 during a switching time period. For example, for the voltage V in5 on the rectified capacitor, the end of T delay corresponds to time t E , for the voltage V in6 after rectification, the end of T delay corresponds to time t F , for voltage V on the rectified capacitor In7 , the end of T delay corresponds to time t G , and for the voltage V in8 on the rectified capacitor, the end of T delay corresponds to time t I .

第19A圖是示出根據本發明又一實施例的具有過流保護的電源轉換器2500的某些元件的簡化圖式。該圖式僅僅是示例，其不應當不當地限制申請專利範圍的範圍。本領域技術人員將認識到許多變體、替換和修改。過流閾值信號生成器2570包括採樣信號生成器2102、信號生成器2104、採樣和保持元件2106、負斜坡信號生成器2108以及占空比檢測器2126。例如，採樣信號生成器2102、信號生成器2104以及採樣和保持元件2106分別與採樣信號生成器1602、信號生成器1604以及採樣和保持元件1606相同。在另一示例中，過流保護方案根據第18A圖和第18B圖來實現。 Figure 19A is a simplified diagram showing certain elements of a power converter 2500 with overcurrent protection in accordance with yet another embodiment of the present invention. The drawings are merely examples, which should not unduly limit the scope of the claimed scope. Those skilled in the art will recognize many variations, substitutions and modifications. The overcurrent threshold signal generator 2570 includes a sample signal generator 2102, a signal generator 2104, a sample and hold element 2106, a negative ramp signal generator 2108, and a duty cycle detector 2126. For example, sample signal generator 2102, signal generator 2104, and sample and hold element 2106 are identical to sample signal generator 1602, signal generator 1604, and sample and hold element 1606, respectively. In another example, the overcurrent protection scheme is implemented in accordance with Figures 18A and 18B.

根據一實施例，在一開關時程期間，信號生成器2104接收信號2582(例如，PWM信號2522或柵極驅動信號2584)，並且基於信號2582在該開關時程中的占空比來生成斜坡信號2114。例如，採樣信號生成器2102接收信號2582，並且生成採樣信號2116。在另一示例中，採樣信號生成器2102在信號2582的下降沿時在採樣信號2116中輸出脈衝。在又一示例中，採樣和保持元件2106在採樣信號2116的脈衝期間對斜坡信號2114採樣，並且在該開關時程的其餘時間期間保持斜坡信號2114的大小(例如，在該脈衝的結束處)直到下一脈衝為止。在又一示例中，占空比檢測 器2126接收信號2582並且輸出指示信號2582的占空比的控制信號2130給負斜坡信號生成器2108。在又一示例中，負斜坡信號生成器2108向OCP比較器2510輸出過流閾值信號2512(例如，Vth_oc)。在又一示例中，OCP比較器2510還接收電流感測信號2514並且輸出過流控制信號2516。在又一示例中，當信號2582的占空比小於占空比閾值時，控制信號2130為邏輯低電平，並且當信號2582的占空比大於占空比閾值時，控制信號2130為邏輯高電平。在又一示例中，如果控制信號2130指示信號2582的占空比大於占空比閾值，則負斜坡信號生成器2108相對於時間向過流閾值信號2512(例如，Vth_oc)引入負斜率補償。 According to an embodiment, during a switching time period, signal generator 2104 receives signal 2582 (eg, PWM signal 2522 or gate drive signal 2584) and generates a ramp based on the duty cycle of signal 2582 in the switching time period. Signal 2114. For example, sample signal generator 2102 receives signal 2582 and generates sample signal 2116. In another example, the sampled signal generator 2102 outputs a pulse in the sampled signal 2116 at the falling edge of the signal 2582. In yet another example, the sample and hold element 2106 samples the ramp signal 2114 during the pulse of the sample signal 2116 and maintains the magnitude of the ramp signal 2114 during the remainder of the switch time period (eg, at the end of the pulse) Until the next pulse. In yet another example, the duty cycle detector 2126 receives the signal 2582 and outputs a control signal 2130 indicative of the duty cycle of the signal 2582 to the negative ramp signal generator 2108. In yet another example, the negative ramp signal generator 2108 outputs an overcurrent threshold signal 2512 (eg, Vth_oc ) to the OCP comparator 2510. In yet another example, the OCP comparator 2510 also receives the current sense signal 2514 and outputs an overcurrent control signal 2516. In yet another example, control signal 2130 is a logic low level when the duty cycle of signal 2582 is less than a duty cycle threshold, and control signal 2130 is a logic high when the duty cycle of signal 2582 is greater than a duty cycle threshold. Level. In yet another example, if the control signal 2130 indicates that the duty cycle of the signal 2582 is greater than the duty cycle threshold, the negative ramp signal generator 2108 introduces a negative slope compensation with respect to the time overcurrent threshold signal 2512 (eg, Vth_oc ).

在一實施例中，斜坡信號2114與傾斜上升過程和傾斜下降過程相關聯。例如，在傾斜上升過程期間，斜坡信號2114的大小從最小值增大到最大值，並且在傾斜下降過程期間，斜坡信號2114的大小從最大值減小到最小值。在另一示例中，傾斜上升過程和/或傾斜下降過程暫態地或者在一時間段期間發生。在另一實施例中，斜坡信號2114與傾斜上升過程、恒定過程和傾斜下降過程相關聯。例如，在傾斜上升過程期間，斜坡信號2114的大小從最小值增大到最大值；在恒定過程期間，斜坡信號2114保持為最大值；並且在傾斜下降過程期間，斜坡信號2114的大小從最大值減小到最小值。在另一示例中，傾斜上升過程、恒定過程和/或傾斜下降過程暫態地或者在一時間段期間發生。在又一實施例中，斜坡信號2114與傾斜上升過程、第一恒定過程、傾斜下降過程和第二恒定過程相關聯。例如，在傾斜上升過程期間，斜坡信號2114的大小從最小值增大到最大值；並且在第一恒定過程期間，斜坡信號2114保持為最大值。在傾斜下降過程期間，斜坡信號2114的大小從最大值減小到最小值；並且在第二恒定過程期間，斜坡信號2114保持為最小值。傾斜上升過程、第一恒定過程、傾斜下降過程和/或第二恒定過程暫態地或者在一時間段期間發生。 In an embodiment, the ramp signal 2114 is associated with a ramp up process and a ramp down process. For example, during the ramp up process, the magnitude of the ramp signal 2114 increases from a minimum value to a maximum value, and during the ramp down process, the magnitude of the ramp signal 2114 decreases from a maximum value to a minimum value. In another example, the ramp up process and/or the ramp down process occur transiently or during a time period. In another embodiment, the ramp signal 2114 is associated with a ramp up process, a constant process, and a ramp down process. For example, during the ramp up process, the magnitude of the ramp signal 2114 increases from a minimum value to a maximum value; during a constant process, the ramp signal 2114 remains at a maximum value; and during the ramp down process, the magnitude of the ramp signal 2114 is from a maximum value Reduce to the minimum. In another example, the ramp up process, the constant process, and/or the ramp down process occur transiently or during a time period. In yet another embodiment, the ramp signal 2114 is associated with a ramp up process, a first constant process, a ramp down process, and a second constant process. For example, during the ramp up process, the magnitude of the ramp signal 2114 increases from a minimum value to a maximum value; and during the first constant process, the ramp signal 2114 remains at a maximum value. During the ramp down process, the magnitude of the ramp signal 2114 decreases from a maximum value to a minimum value; and during the second constant process, the ramp signal 2114 remains at a minimum value. The ramp up process, the first constant process, the ramp down process, and/or the second constant process occur transiently or during a time period.

第19B圖是根據本發明又一實施例的包括如第19A圖所示的元件的電源轉換器2500的簡化時序圖。該圖式僅僅是示例，其不應當不當地限制申請專利範圍的範圍。本領域技術人員將認識到許多變體、替換和修改。波形2200表示作為時間的函數的信號2582，波形2202表示作為 時間的函數的採樣信號2116，並且波形2204表示作為時間的函數的斜坡信號2114。另外，波形2206表示作為時間的函數的過流閾值信號2512(例如，Vth_oc)，波形2208表示作為時間的函數的電流感測信號2514，並且波形2210表示作為時間的函數的控制信號2130。例如，如第19B圖所示，開關時程Tswf包括導通時間Tonf和關斷時間Tofff。導通時間Tonf開始於時間t20並結束於時間t22，關斷時間Tofff開始於時間t22並結束於時間t24。在另一示例中，t20 t21 t22 t23 t24。例如，波形2206表示作為時間的函數的過流閾值信號2512(例如，Vth_oc)，其包括作為開關時程Tswf內的時間的函數的過流閾值信號2512(例如，Vth_oc)以及作為開關時程Tswh內的時間的函數的過流閾值信號2512(例如，Vth_oc)。在另一示例中，波形2208表示作為時間的函數的電流感測信號2514，其包括作為開關時程Tswf內的時間的函數的電流感測信號2514以及作為開關時程Tswh內的時間的函數的電流感測信號2514。 Figure 19B is a simplified timing diagram of a power converter 2500 including elements as shown in Figure 19A, in accordance with yet another embodiment of the present invention. The drawings are merely examples, which should not unduly limit the scope of the claimed scope. Those skilled in the art will recognize many variations, substitutions and modifications. Waveform 2200 represents signal 2582 as a function of time, waveform 2202 represents sampled signal 2116 as a function of time, and waveform 2204 represents ramp signal 2114 as a function of time. Additionally, waveform 2206 represents an overcurrent threshold signal 2512 (eg, Vth_oc ) as a function of time, waveform 2208 represents current sense signal 2514 as a function of time, and waveform 2210 represents control signal 2130 as a function of time. For example, as shown, when the switch T swf process comprising on-time and off-time T onf as 19B, T offf. The on-time T onf starts at time t 20 and ends at time t 22 , and the off-time T offf starts at time t 22 and ends at time t 24 . In another example, t 20 t 21 t 22 t 23 t 24 . For example, a waveform 2206 indicates as a function of time overcurrent threshold signal 2512 (e.g., V th_oc), which includes a overcurrent threshold signal 2512 (e.g., V th_oc) function of time in the path T swf switch and a switch overcurrent function of time in the time course T swh threshold signal 2512 (e.g., V th_oc). In another example, the waveform 2208 represents the current sensing signal as a function of time 2514, which includes a current sense signal as a function of time in the path T swf 2514 as well as the time when the switch in the path of the switch T swh The current sense signal 2514 of the function.

根據一實施例，在導通時間Tonf期間，信號2582保持為邏輯高電平(例如，如波形2200所示)。例如，斜坡信號2114從大小2212(例如，t20處)增大到大小2214(例如，t22處)，如波形2204所示。在另一示例中，控制信號2130保持邏輯低電平(例如，在t20與t21之間)，並且然後變為指示信號2582的占空比達到占空比閾值的邏輯高電平(例如，在t21與t22之間)。在另一示例中，過流閾值信號2512(例如，Vth_oc)保持為大小2216(例如，在t21之前，如波形2206所示)，並且然後響應於控制信號2130變為邏輯高電平，過流閾值信號2512(例如，Vth_oc)從大小2216(例如，t21處)減小為大小2218(例如，t22處)，例如，如波形2206所示。在又一示例中，電流感測信號2514從大小2220(例如，t20處)增大，如波形2208所示。在一些實施例中，一旦電流感測信號2514超過大小2218(例如，t22處)，則過流保護被觸發。例如，OCP比較器2510將過流控制信號2516從邏輯高電平變為邏輯低電平。在另一示例中，然後，電流感測信號2514下降為大小2222(例如，t22處的0)並且在關斷時間Tofff期間保持為大小2222(例如，如波形2208所示)。 According to an embodiment, during the on time Tonf , signal 2582 remains at a logic high level (eg, as shown by waveform 2200). For example, the ramp signal increases from 2114 2212 size (e.g., t at 20) to the 2214 size (e.g., t 22), as shown in the waveform 2204. In another example, control signal 2130 remains at a logic low level (eg, between t 20 and t 21 ) and then becomes a logic high level indicating that the duty cycle of signal 2582 reaches a duty cycle threshold (eg, , between t 21 and t 22 ). In another example, the overcurrent threshold signal 2512 (eg, V th — oc ) remains at a size 2216 (eg, before t 21 , as shown by waveform 2206 ), and then becomes a logic high level in response to the control signal 2130, 2512 overcurrent threshold signal (e.g., V th_oc) from the 2216 size (e.g., t at 21) is reduced to the size of 2218 (e.g., t 22), e.g., 2206 as shown in the waveform. In yet another example, current sense signal 2514 increases from size 2220 (eg, at t 20 ) as shown by waveform 2208. In some embodiments, once current sense signal 2514 exceeds size 2218 (eg, at t 22 ), overcurrent protection is triggered. For example, OCP comparator 2510 changes overcurrent control signal 2516 from a logic high level to a logic low level. In another example, current sense signal 2514 then falls to size 2222 (eg, 0 at t 22 ) and remains at size 2222 during off time T offf (eg, as shown by waveform 2208).

根據另一實施例，在信號2582的下降沿處(例如，t22處)， 在採樣信號2116中生成脈衝(例如，如波形2202所示)。例如，該脈衝開始於時間t22並結束於時間t23。在另一示例中，採樣和保持元件2106在該脈衝期間對斜坡信號2114採樣，並且作為回應，過流閾值信號2512(例如，Vth_oc)從大小2218(例如，t22處)變為大小2224，如波形2206所示。在又一示例中，斜坡信號2114在該脈衝期間保持為大小2214，並且在該脈衝的結束處(例如，t23處)下降為大小2212(例如，Vocp_l)，如波形2204所示。在又一示例中，在t23與t24之間的時間段期間，斜坡信號2114保持為大小2212(例如，Vocp_l)，如波形2204所示，並且過流閾值信號2512(例如，Vth_oc)保持為大小2224，如波形2206所示。 According to another embodiment, at the falling edge of signal 2582 (eg, at t 22 ), a pulse is generated in sampled signal 2116 (eg, as shown by waveform 2202). For example, the pulse begins at time t 22 and ends at time t 23 . In another example, the sample and hold element 21,062,114 samples during the ramp pulse signal, and in response, the overcurrent threshold signal 2512 (e.g., V th_oc) from the 2218 size (e.g., t 22) becomes size 2224 As shown in waveform 2206. In yet another example, ramp signal 2114 remains at size 2214 during the pulse and falls to a size 2212 (eg, V ocp — l ) at the end of the pulse (eg, at t 23 ), as shown by waveform 2204. In yet another example, during a time period between t 23 and t 24 , ramp signal 2114 remains at size 2212 (eg, V ocp — l ), as shown by waveform 2204, and overcurrent threshold signal 2512 (eg, V th — oc ) remains at size 2224 as shown by waveform 2206.

第20A圖是示出根據本發明又一實施例的作為開關時程內的時間的函數的過流閾值信號2512的簡化圖式。該圖式僅僅是示例，其不應當不當地限制申請專利範圍的範圍。本領域技術人員將認識到許多變體、替換和修改。 20A is a simplified diagram showing an overcurrent threshold signal 2512 as a function of time within a switch time course, in accordance with yet another embodiment of the present invention. The drawings are merely examples, which should not unduly limit the scope of the claimed scope. Those skilled in the art will recognize many variations, substitutions and modifications.

在一實施例中，波形1502表示在開關時程T9內作為時間的函數的過流閾值信號2512(例如，Vth_oc)，並且導通時間在開關時程T9的開始處被設為零。在另一實施例中，波形1504表示在開關時程T10內作為時間的函數的過流閾值信號2512(例如，Vth_oc)，並且導通時間在開關時程T10的開始處被設為零。在又一實施例中，波形1506表示在開關時程T11內作為時間的函數的過流閾值信號2512(例如，Vth_oc)，並且導通時間在開關時程T11的開始處被設為零。在又一實施例中，波形1508表示在開關時程T12內作為時間的函數的過流閾值信號2512(例如，Vth_oc)，並且導通時間在開關時程T12的開始處被設為零。例如，開關時程T9,T10,T11和T12的大小相等，儘管它們對應於不同的開關週期。在另一示例中，波形1502,1504,1506和1508分別對應於整流後電容上的電壓Vin9,Vin10,Vin11和Vin12。 In one embodiment, the waveform 1502 indicates when the switch is used as the overcurrent function of time threshold signal 2512 (e.g., V th_oc) course T 9, and the conduction time of the switch at the beginning of the process T9 is set to zero. In another embodiment, the waveform 1504 represents the path T 10 as a function of time overcurrent threshold signal 2512 (e.g., V th_oc) when the switch and the on-time when the switching at the beginning of the process T 10 is set to zero . In yet another embodiment, a waveform 1506 indicates the path T 11 as a function of time overcurrent threshold signal 2512 (e.g., V th_oc) when the switch and the on-time when the switching at the beginning of the process T 11 is set to zero . In yet another embodiment, a waveform 1508 indicates the switch as a function of time in the process T 12 overcurrent threshold signal 2512 (e.g., V th_oc), and the conduction time of the switch at the beginning of the process T 12 is set to zero . For example, the switching time periods T 9 , T 10 , T 11 and T 12 are equal in magnitude, although they correspond to different switching periods. In another example, waveforms 1502 , 1504 , 1506 , and 1508 correspond to voltages V in9 , V in10 , V in11 , and V in12 , respectively, on the rectified capacitor.

根據一實施例，如第20A圖所示，過流閾值信號2512(例如，Vth_oc)的起始值(例如，0處)大於最小值(例如，Vocp_l)，並且等於或小於最大值(例如，Vocp_h)。例如，當過流閾值信號2512(例如，Vth_oc)大於最小值(例如，Vocp_l)並且小於最大值(例如，Vocp_h)時，過流閾值信號2512(例如，Vth_oc)相對於時間沿著負斜率改變(例如，如以 下波形所示：0與時間tJ之間的波形1502、0與時間tK之間的波形1504、時間tJ與最大時間tmax之間的波形1506，或者時間tM與最大時間tmax之間的波形1508)。在又一示例中，過流閾值信號2512(例如，Vth_oc)的起始值可根據式9和/或式10確定，如果從式9和/或式10計算的起始值在最小值(例如，Vocp_l)與最大值(例如，Vocp_h)之間的話。在又一示例中，如果基於式9和/或式10計算的起始值大於最大值(例如，Vocp_h)，則過流閾值信號2512(例如，Vth_oc)將開始於最大值(例如，Vocp_h)，例如如波形1506或波形1508所示。在又一示例中，tL tM tJ tK。 According to an embodiment, as shown in FIG. 20A, the start value (eg, 0) of the overcurrent threshold signal 2512 (eg, Vth_oc ) is greater than a minimum value (eg, Vocp_l) and is equal to or less than a maximum value (eg, , Vocp_h). For example, when the overcurrent threshold signal 2512 (eg, Vth_oc ) is greater than a minimum value (eg, Vocp_l ) and less than a maximum value (eg, Vocp_h ), the overcurrent threshold signal 2512 (eg, Vth_oc ) is relative to the time edge. negative slope change (e.g., as shown in the following waveforms: waveform between time t 0 and the time t J 1502,0 waveform between 1504 K, and the maximum time t J waveform 1506 between the time t max, or Waveform 1508) between time t M and maximum time t max . In yet another example, the starting value of the overcurrent threshold signal 2512 (eg, V th — oc ) may be determined according to Equation 9 and/or Equation 10 if the starting value calculated from Equation 9 and/or Equation 10 is at a minimum value ( For example, between V ocp_l ) and the maximum value (for example, V ocp_h ). In yet another example, if the starting value calculated based on Equation 9 and/or Equation 10 is greater than the maximum value (eg, V ocp — h ), the overcurrent threshold signal 2512 (eg, V th — oc ) will begin at the maximum value (eg, V ocp — h ), for example as shown by waveform 1506 or waveform 1508. In yet another example, t L t M t J t K .

第20B圖是示出根據本發明又一實施例的使用如第20A圖所示作為開關時程內的時間的函數的過流閾值信號2512來確定導通時間的簡化圖式。該圖式僅僅是示例，其不應當不當地限制申請專利範圍的範圍。本領域技術人員將認識到許多變體、替換和修改。波形1510,1512,1514和1516分別表示與整流後電容上的電壓Vin9,Vin10,Vin11和Vin12相對應的、作為時間的函數的電流感測信號2514(例如，VCS)。例如，波形1510,1512,1514和1516中所示的斜率分別是S9,S10,S11和S12。 Figure 20B is a simplified diagram showing the determination of the on-time using an overcurrent threshold signal 2512 as a function of time within the switch time history as shown in Figure 20A, in accordance with yet another embodiment of the present invention. The drawings are merely examples, which should not unduly limit the scope of the claimed scope. Those skilled in the art will recognize many variations, substitutions and modifications. Waveforms 1510, 1512, 1514, and 1516 represent current sense signals 2514 (e.g., V CS ) as a function of time, corresponding to voltages V in9 , V in10 , V in11 , and V in12 on the rectified capacitor, respectively. For example, as shown in the waveform slope 1510,1512,1514 and 1516 respectively S 9, S 10, S 11 and S 12.

根據一實施例，相對於特定的整流後電容上的電壓，電流感測信號2514(例如，VCS)隨著時間增大，如波形1510,1512,1514和1516所示。在一些實施例中，如第20B圖所示，電流感測信號2514(例如，VCS)相對於時間的斜率隨著整流後電容上的電壓增大。例如，Vin9>Vin10>Vin11>Vin12，並且相應地，S9>S10>S11>S12。在另一示例中，當電流感測信號2514(例如，VCS)的大小超過過流閾值信號2512時(例如，如波形1510,1512,1514或1516所示)，過流保護被觸發。在又一示例中，在Tdelay(例如，“輸出延遲”)期間，電流感測信號2514(例如，VCS)的大小繼續增大。在又一示例中，在Tdelay的結束處，開關被斷開(例如，關斷)，並且電流感測信號2514(例如，VCS)達到其最大大小。在一些實施例中，Tdelay的結束是在一開關時程期間開關2540的導通時間的結束。例如，對於整流後電容上的電壓Vin9，Tdelay的結束對應於時間tN，對於整流後電容上的電壓Vin10，Tdelay的結束對應於時間tO，對於整流後電容上的電壓Vin11，Tdelay的結束對應於時間tP，並且對於整流後電容上的電壓Vin12，Tdelay 的結束對應於時間tQ。 According to an embodiment, current sense signal 2514 (eg, V CS ) increases with time relative to a voltage on a particular rectified capacitor, as shown by waveforms 1510, 1512, 1514, and 1516. In some embodiments, as shown in FIG. 20B, the slope of current sense signal 2514 (eg, V CS ) with respect to time increases with voltage on the rectified capacitor. For example, V in9 >V in10 >V in11 >V in12 , and correspondingly, S 9 >S 10 >S 11 >S 12 . In another example, when the magnitude of current sense signal 2514 (eg, V CS ) exceeds overcurrent threshold signal 2512 (eg, as shown by waveforms 1510, 1512, 1514, or 1516), overcurrent protection is triggered. In yet another example, during Tdelay (eg, "output delay"), the magnitude of current sense signal 2514 (eg, VCS ) continues to increase. In yet another example, at the end of Tdelay , the switch is turned off (eg, turned off) and current sense signal 2514 (eg, V CS ) reaches its maximum size. In some embodiments, the end of Tdelay is the end of the on time of switch 2540 during a switching time period. For example, for the voltage V in9 on the rectified capacitor, the end of T delay corresponds to time t N . For the voltage V in10 on the rectified capacitor, the end of T delay corresponds to time t O , and the voltage V on the rectified capacitor IN11, T delay corresponding to the end time t P, and for the rectified voltage V in12 capacitor, corresponding to the end of the time T delay t Q.

第21A圖是示出根據本發明又一實施例的具有過流保護的電源轉換器2500的某些元件的簡化圖式。該圖式僅僅是示例，其不應當不當地限制申請專利範圍的範圍。本領域技術人員將認識到許多變體、替換和修改。過流閾值信號生成器2570包括採樣信號生成器2302、信號生成器2304、採樣和保持元件2306以及負斜坡信號生成器2308。 21A is a simplified diagram showing certain elements of a power converter 2500 with overcurrent protection in accordance with yet another embodiment of the present invention. The drawings are merely examples, which should not unduly limit the scope of the claimed scope. Those skilled in the art will recognize many variations, substitutions and modifications. The overcurrent threshold signal generator 2570 includes a sample signal generator 2302, a signal generator 2304, a sample and hold element 2306, and a negative ramp signal generator 2308.

例如，採樣信號生成器2302、信號生成器2304以及採樣和保持元件2306分別與採樣信號生成器1602、信號生成器1604以及採樣和保持元件1606相同。在另一示例中，採樣信號生成器2302、信號生成器2304、採樣和保持元件2306以及負斜坡信號生成器2308分別與採樣信號生成器2102、信號生成器2104、採樣和保持元件2106以及負斜坡信號生成器2108相同。在又一示例中，過流保護方案根據第20A圖和第20B圖來實現。 For example, sample signal generator 2302, signal generator 2304, and sample and hold element 2306 are identical to sample signal generator 1602, signal generator 1604, and sample and hold element 1606, respectively. In another example, sample signal generator 2302, signal generator 2304, sample and hold element 2306, and negative ramp signal generator 2308 are coupled to sample signal generator 2102, signal generator 2104, sample and hold element 2106, and negative ramp, respectively. Signal generator 2108 is identical. In yet another example, the overcurrent protection scheme is implemented in accordance with FIGS. 20A and 20B.

根據一實施例，在一開關時程期間，信號生成器2304接收信號2582(例如，PWM信號2522或柵極驅動信號2584)，並且基於信號2582在該開關時程中的占空比來生成斜坡信號2314。例如，採樣信號生成器2302接收信號2582，並且生成採樣信號2316。在另一示例中，採樣信號生成器2302在信號2582的下降沿時在採樣信號2316中輸出脈衝。在又一示例中，採樣和保持元件2306在採樣信號2316的脈衝期間對斜坡信號2314採樣，並且在該開關時程的其餘時間期間保持斜坡信號2314的大小(例如，該脈衝的結束處)直到下一脈衝為止。在又一示例中，負斜坡信號生成器2308向OCP比較器2510輸出過流閾值信號2512(例如，Vth_oc)。在又一示例中，OCP比較器2510還接收電流感測信號2514並且輸出過流控制信號2516。在又一示例中，負斜坡信號生成器2308相對於時間向過流閾值信號2512(例如，Vth_oc)引入負斜率補償。 According to an embodiment, during a switching time period, signal generator 2304 receives signal 2582 (eg, PWM signal 2522 or gate drive signal 2584) and generates a ramp based on the duty cycle of signal 2582 in the switching time course. Signal 2314. For example, sample signal generator 2302 receives signal 2582 and generates sample signal 2316. In another example, the sampled signal generator 2302 outputs a pulse in the sampled signal 2316 at the falling edge of the signal 2582. In yet another example, the sample and hold element 2306 samples the ramp signal 2314 during the pulse of the sample signal 2316 and maintains the magnitude of the ramp signal 2314 (eg, at the end of the pulse) during the remainder of the switch time period until Until the next pulse. In yet another example, the negative ramp signal generator 2308 outputs an overcurrent threshold signal 2512 (eg, Vth_oc ) to the OCP comparator 2510. In yet another example, the OCP comparator 2510 also receives the current sense signal 2514 and outputs an overcurrent control signal 2516. In yet another example, the negative ramp signal generator 2308 introduces a negative slope compensation with respect to the time overcurrent threshold signal 2512 (eg, Vth_oc ).

在一實施例中，斜坡信號2314與傾斜上升過程和傾斜下降過程相關聯。例如，在傾斜上升過程期間，斜坡信號2314的大小從最小值增大到最大值，並且在傾斜下降過程期間，斜坡信號2314的大小從最大值減小到最小值。在另一示例中，傾斜上升過程和/或傾斜下降過程暫態地或 者在一時間段期間發生。在另一實施例中，斜坡信號2314與傾斜上升過程、恒定過程和傾斜下降過程相關聯。例如，在傾斜上升過程期間，斜坡信號2314的大小從最小值增大到最大值；在恒定過程期間，斜坡信號2314保持為最大值；並且在傾斜下降過程期間，斜坡信號2314的大小從最大值減小到最小值。在另一示例中，傾斜上升過程、恒定過程和/或傾斜下降過程暫態地或者在一時間段期間發生。在又一實施例中，斜坡信號2314與傾斜上升過程、第一恒定過程、傾斜下降過程和第二恒定過程相關聯。例如，在傾斜上升過程期間，斜坡信號2314的大小從最小值增大到最大值；並且在第一恒定過程期間，斜坡信號2314保持為最大值。在傾斜下降過程期間，斜坡信號2314的大小從最大值減小到最小值；並且在第二恒定過程期間，斜坡信號2314保持為最小值。傾斜上升過程、第一恒定過程、傾斜下降過程和/或第二恒定過程暫態地或者在一時間段期間發生。 In an embodiment, the ramp signal 2314 is associated with a ramp up process and a ramp down process. For example, during the ramp up process, the magnitude of the ramp signal 2314 increases from a minimum value to a maximum value, and during the ramp down process, the magnitude of the ramp signal 2314 decreases from a maximum value to a minimum value. In another example, the ramp up process and/or the tilt down process are transiently or The person takes place during a period of time. In another embodiment, the ramp signal 2314 is associated with a ramp up process, a constant process, and a ramp down process. For example, during the ramp up process, the magnitude of the ramp signal 2314 increases from a minimum value to a maximum value; during a constant process, the ramp signal 2314 remains at a maximum value; and during the ramp down process, the magnitude of the ramp signal 2314 is from a maximum value Reduce to the minimum. In another example, the ramp up process, the constant process, and/or the ramp down process occur transiently or during a time period. In yet another embodiment, the ramp signal 2314 is associated with a ramp up process, a first constant process, a ramp down process, and a second constant process. For example, during the ramp up process, the magnitude of the ramp signal 2314 increases from a minimum value to a maximum value; and during the first constant process, the ramp signal 2314 remains at a maximum value. During the ramp down process, the magnitude of the ramp signal 2314 decreases from a maximum value to a minimum value; and during the second constant process, the ramp signal 2314 remains at a minimum value. The ramp up process, the first constant process, the ramp down process, and/or the second constant process occur transiently or during a time period.

第21B圖是根據本發明又一實施例的包括如第21A圖所示的元件的電源轉換器2500的簡化時序圖。該圖式僅僅是示例，其不應當不當地限制申請專利範圍的範圍。本領域技術人員將認識到許多變體、替換和修改。波形2400表示作為時間的函數的信號2582，波形2402表示作為時間的函數的採樣信號2316，並且波形2404表示作為時間的函數的斜坡信號2314。另外，波形2406表示作為時間的函數的過流閾值信號2512(例如，Vth_oc)，波形2408表示作為時間的函數的電流感測信號2514。例如，如第21B圖所示，開關時程Tswg包括導通時間Tong和關斷時間Toffg。導通時間Tong開始於時間t25並結束於時間t26，關斷時間Toffg開始於時間t26並結束於時間t28。在另一示例中，t25 t26 t27 t28。在又一示例中，波形2406表示作為時間的函數的過流閾值信號2512(例如，Vth_oc)，其包括作為開關時程Tswg內的時間的函數的過流閾值信號2512(例如，Vth_oc)以及作為開關時程Tswi內的時間的函數的過流閾值信號2512(例如，Vth_oc)。在另一示例中，波形2408表示作為時間的函數的電流感測信號2514，其包括作為開關時程Tswg內的時間的函數的電流感測信號2514以及作為開關時程Tswi內的時間的函數的電流感測信號2514。 Figure 21B is a simplified timing diagram of a power converter 2500 including elements as shown in Figure 21A in accordance with yet another embodiment of the present invention. The drawings are merely examples, which should not unduly limit the scope of the claimed scope. Those skilled in the art will recognize many variations, substitutions and modifications. Waveform 2400 represents signal 2582 as a function of time, waveform 2402 represents sampled signal 2316 as a function of time, and waveform 2404 represents ramp signal 2314 as a function of time. Additionally, waveform 2406 represents an overcurrent threshold signal 2512 (eg, Vth_oc ) as a function of time, and waveform 2408 represents current sense signal 2514 as a function of time. For example, as shown, when the switch T swg process comprising on-time and off-time T ong T offg 21B of FIG. The on time T ong begins at time t 25 and ends at time t 26 , and the off time T offg begins at time t 26 and ends at time t 28 . In another example, t 25 t 26 t 27 t 28 . In yet another example, a waveform 2406 indicates as a function of time overcurrent threshold signal 2512 (e.g., V th_oc), which includes a switch overcurrent function of time in the path T swg threshold signal 2512 (e.g., V th_oc ) and as a function of time in the process of the switch T swi overcurrent threshold signal 2512 (e.g., V th_oc). In another example, the waveform 2408 represents the current sensing signal as a function of time 2514, which includes a current sense signal as a function of time in the path T swg 2514 as well as the time when the switch is in the path of the switch T swi The current sense signal 2514 of the function.

根據一實施例，在導通時間Tong期間，信號2582保持為邏 輯高電平(例如，如波形2400所示)。例如，斜坡信號2314從大小2412(例如，t25處)增大到大小2414(例如，t26處)，如波形2404所示。在另一示例中，過流閾值信號2512(例如，Vth_oc)從大小2416(例如，t25處)減小為大小2418(例如，t26處)，如波形2406所示。即，在一些實施例中，在整個導通時間Tong中，負斜坡信號生成器2308將負斜率補償引入了過流閾值信號2512(例如，Vth_oc)。例如，電流感測信號2514從大小2420(例如，t25處)增大，如波形2408所示。在一些實施例中，一旦電流感測信號2514超過大小2418(例如，t26處)，則過流保護被觸發。例如，OCP比較器2510將過流控制信號2516從邏輯高電平變為邏輯低電平。在另一示例中，然後，電流感測信號2514下降為大小2422(例如，t26處的0)並且在關斷時間Toffg期間保持為大小2422(例如，如波形2408所示)。 According to one embodiment, during the on-time T ong, 2582 held at logic high signal (e.g., as shown in the waveform 2400). For example, ramp signal 2314 increases from size 2412 (eg, at t 25 ) to size 2414 (eg, at t 26 ) as shown by waveform 2404. In another example, the overcurrent threshold signal 2512 (e.g., V th_oc) from the 2416 size (e.g., t at 25) is reduced to the size of 2418 (e.g., t 26), as shown in the waveform 2406. That is, in some embodiments, the entire on-time T ong, the negative ramp signal generator 2308 introduces a negative slope compensation overcurrent threshold signal 2512 (e.g., V th_oc). For example, current sense signal 2514 increases from size 2420 (eg, at t 25 ) as shown by waveform 2408. In some embodiments, once current sense signal 2514 exceeds size 2418 (eg, at t 26 ), overcurrent protection is triggered. For example, OCP comparator 2510 changes overcurrent control signal 2516 from a logic high level to a logic low level. In another example, current sense signal 2514 then falls to size 2422 (eg, 0 at t 26 ) and remains at size 2422 during off time T offg (eg, as shown by waveform 2408).

根據另一實施例，在信號2582的下降沿處(例如，t26處)，在採樣信號2316中生成脈衝(例如，如波形2402所示)。例如，該脈衝開始於時間t26並結束於時間t27。在另一示例中，採樣和保持元件2306在該脈衝期間對斜坡信號2314採樣，並且作為回應，過流閾值信號2512(例如，Vth_oc)從大小2418(例如，t26處)變為大小2424，如波形2406所示。在又一示例中，斜坡信號2314在該脈衝期間保持為大小2414，並且在該脈衝的結束處(例如，t27處)下降為大小2412(例如，Vocp_l)，如波形2404所示。在又一示例中，在t27與t28之間的時間段期間，斜坡信號2314保持為大小2412(例如，Vocp_l)，如波形2404所示，並且過流閾值信號2512(例如，Vth_oc)保持為大小2424，如波形2406所示。 According to another embodiment, at a falling edge of the signal 2582 (e.g., t 26) generates a pulse (e.g., shown as waveform 2402) in 2316 in the sampled signal. For example, the pulse begins at time t 26 and ends at time t 27. In another example, the sample and hold element 23,062,314 samples during the ramp pulse signal, and in response, the overcurrent threshold signal 2512 (e.g., V th_oc) from the 2418 size (e.g., t 26) becomes size 2424 As shown in waveform 2406. In yet another example, ramp signal 2314 remains at size 2414 during the pulse and falls to a size 2412 (eg, V ocp — l ) at the end of the pulse (eg, at t 27 ), as shown by waveform 2404. In yet another example, during the time period between t 27 and t 28, the ramp signal remains 2314 2412 size (e.g., V ocp_l), as shown in the waveform 2404, and 2512 overcurrent threshold signal (e.g., V th_oc ) remains at size 2424 as shown by waveform 2406.

根據一些實施例，如第22A圖和第22B圖所示，當信號2582的占空比超過占空比閾值時，應用負斜率補償，以減少次諧波震盪，從而使最大輸出功率在整流後電容上的電壓的寬範圍中保持一致。 According to some embodiments, as shown in Figures 22A and 22B, when the duty cycle of signal 2582 exceeds the duty cycle threshold, negative slope compensation is applied to reduce subharmonic oscillations such that the maximum output power is rectified The wide range of voltages across the capacitors is consistent.

第22A圖是示出根據本發明又一實施例的作為開關時程內的時間的函數的過流閾值信號2512的簡化圖式。該圖式僅僅是示例，其不應當不當地限制申請專利範圍的範圍。本領域技術人員將認識到許多變體、替換和修改。波形1202表示在導通時間內作為時間的函數的過流閾值信號2512(例如，Vth_oc)，其中，該時間從導通時間的開始起被測量。 Figure 22A is a simplified diagram showing an overcurrent threshold signal 2512 as a function of time within a switch time course, in accordance with yet another embodiment of the present invention. The drawings are merely examples, which should not unduly limit the scope of the claimed scope. Those skilled in the art will recognize many variations, substitutions and modifications. Waveform 1202 represents an overcurrent threshold signal 2512 (e.g., Vth_oc ) as a function of time during the on time, wherein the time is measured from the beginning of the on time.

根據一個實施例，在0與時間閾值(例如，th)之間，過流閾值信號2512(例如，Vth_oc)相對於時間的正斜率適當地被選擇來補償“輸出延遲”的影響。例如，過流閾值信號2512(例如，Vth_oc)從最小值(例如，0處的Vocp_l)隨著時間增大到最大值(例如，時間閾值th處的Vocp_h)，如波形1202所示。在一些實施例中，在時間閾值th與最大時間(例如，tmax)之間，過流閾值信號2512(例如，Vth_oc)相對於時間的負斜率適當地被用來抑制次諧波震盪。例如，過流閾值信號2512(例如，Vth_oc)從最大值(例如，時間閾值th處的Vocp_h)下降為低的值(例如，最大時間tmax處的Vocp_m)，如波形1202所示。在又一示例中，Vocp_m<Vocp_h並且Vocp_1<Vocp_h。在又一示例中，Vocp_m小於、等於或大於Vocp_l。 According to one embodiment, between time threshold (e.g., t h), the overcurrent threshold signal 2512 (e.g., V th_oc) is selected impact to compensate for "output delay" is 0 with respect to positive slope time appropriately. For example, the overcurrent threshold signal 2512 (e.g., V th_oc) from a minimum value (e.g., V ocp_l 0 at) increases to a maximum with time (e.g., time threshold at t V ocp_h h), as shown by waveforms 1202 Show. In some embodiments, between the time threshold t h and the maximum time (eg, t max ), the negative slope of the overcurrent threshold signal 2512 (eg, V th — oc ) with respect to time is suitably used to suppress subharmonic oscillations. . For example, the overcurrent threshold signal 2512 (e.g., V th_oc) from the maximum value (e.g., time threshold t V ocp_h h at) falls to a low value (e.g., maximum time t V ocp_m max at), as waveform 1202 Show. In yet another example, V ocp_m <V ocp_h and V ocp_1 <V ocp_h . In yet another example, Vocp_m is less than, equal to, or greater than Vocp_l.

第22B圖是示出根據本發明又一實施例的使用如第22A圖所示作為開關時程內的時間的函數的過流閾值信號2512來確定導通時間的簡化圖式。該圖式僅僅是示例，其不應當不當地限制申請專利範圍的範圍。本領域技術人員將認識到許多變體、替換和修改。波形1204,1206,1208和1210分別表示與整流後電容上的電壓Vin13,Vin14,Vin15和Vin16相對應的、作為時間的函數的電流感測信號2514(例如，VCS)。例如，波形1204,1206,1208和1210中所示的斜率分別是S13,S14,S15和S16。 Figure 22B is a simplified diagram showing the determination of the on-time using an overcurrent threshold signal 2512 as a function of time within the switch time history as shown in Figure 22A, in accordance with yet another embodiment of the present invention. The drawings are merely examples, which should not unduly limit the scope of the claimed scope. Those skilled in the art will recognize many variations, substitutions and modifications. Waveforms 1204, 1206, 1208, and 1210 represent current sense signals 2514 (eg, V CS ) as a function of time, corresponding to voltages V in13 , V in14 , V in15 , and V in16 on the rectified capacitor, respectively. For example, the slopes shown in waveforms 1204, 1206, 1208, and 1210 are S 13 , S 14 , S 15 , and S 16 , respectively .

根據一實施例，相對於特定的整流後電容上的電壓，電流感測信號2514(例如，VCS)隨著時間增大，如波形1204,1206,1208和1210所示。在一些實施例中，如第22B圖所示，電流感測信號2514(例如，VCS)相對於時間的斜率隨著整流後電容上的電壓增大。例如，Vin13>Vin14>Vin15>Vin16，並且相應地，S13>S14>S15>S16。在另一示例中，當開關閉合(例如，接通)時，電流感測信號2514(例如，VCS)的大小隨著時間增大(例如，如波形1202,1204,1206或1208所示)。在又一示例中，當電流感測信號2514(例如，VCS)的大小超過過流閾值信號2512時(例如，如波形1202,1204,1206或1208所示)，過流保護被觸發。在又一示例中，在Tdelay(例如，“輸出延遲”)期間，電流感測信號2514(例如，VCS)的大小繼續增大。在一些實施例中，Tdelay的結束是在一開關時程期間開關2540的導通時間的結束。例如，對於整流後電容上的電壓Vin13,Vin14,Vin15和Vin16， Tdelay的結束分別對應於時間tR,tS,tT和tU。 According to an embodiment, current sense signal 2514 (eg, V CS ) increases with time relative to a voltage on a particular rectified capacitor, as shown by waveforms 1204, 1206, 1208, and 1210. In some embodiments, as shown in FIG. 22B, the slope of current sense signal 2514 (eg, V CS ) with respect to time increases with voltage on the rectified capacitor. For example, V in13 >V in14 >V in15 >V in16 , and correspondingly, S 13 >S 14 >S 15 >S 16 . In another example, when the switch is closed (eg, turned "on"), the magnitude of current sense signal 2514 (eg, V CS ) increases over time (eg, as shown by waveforms 1202, 1204, 1206, or 1208) . In yet another example, when the magnitude of the current sense signal 2514 (eg, V CS ) exceeds the overcurrent threshold signal 2512 (eg, as shown by waveforms 1202, 1204, 1206, or 1208), overcurrent protection is triggered. In yet another example, during Tdelay (eg, "output delay"), the magnitude of current sense signal 2514 (eg, VCS ) continues to increase. In some embodiments, the end of Tdelay is the end of the on time of switch 2540 during a switching time period. For example, for the voltages V in13 , V in14 , V in15 and V in16 on the rectified capacitor, the end of T delay corresponds to times t R , t S , t T and t U , respectively .

根據另一實施例，一種用於保護電源轉換器的系統控制器包括信號生成器、比較器以及調製和驅動元件。信號生成器被配置為生成閾值信號。比較器，被配置為接收所述閾值信號以及電流感測信號，並且至少基於與所述閾值信號和所述電流感測信號相關聯的資訊生成比較信號，所述電流感測信號指示流經電源轉換器的初級繞組的初級電流的大小。調製和驅動元件被耦合到所述信號生成器並被配置為至少接收所述比較信號，至少基於與所述比較信號相關聯的資訊生成驅動信號，並且向開關輸出所述驅動信號以影響所述初級電流，所述驅動信號與一個或多個第一開關時程以及在所述一個或多個第一開關時程之後的第二開關時程相關聯，所述一個或多個第一開關時程對應於一個或多個第一占空比。所述信號生成器還被配置為，在所述第二開關時程中，至少基於與所述一個或多個第一占空比相關聯的資訊確定第一閾值信號值；以及生成與所確定的第一閾值信號值相等的所述閾值信號，所述閾值信號在所述第二開關時程中作為時間的函數在大小上是恒定的。例如，該系統控制器至少根據第13A圖、第13B圖、第14A圖、第14B圖、第14C圖、第15A圖、第15B圖、第16A圖、第16B圖和/或第17圖來實現。 In accordance with another embodiment, a system controller for protecting a power converter includes a signal generator, a comparator, and a modulation and drive component. The signal generator is configured to generate a threshold signal. a comparator configured to receive the threshold signal and a current sense signal and generate a comparison signal based on at least information associated with the threshold signal and the current sense signal, the current sense signal indicating flow through a power source The magnitude of the primary current of the primary winding of the converter. A modulation and drive element is coupled to the signal generator and configured to receive at least the comparison signal, generate a drive signal based on at least information associated with the comparison signal, and output the drive signal to a switch to affect the Primary current, the drive signal being associated with one or more first switch time periods and a second switch time history after the one or more first switch time periods, the one or more first switch times The process corresponds to one or more first duty cycles. The signal generator is further configured to determine a first threshold signal value based on at least information associated with the one or more first duty cycles in the second switching time course; and generating and determining The threshold signal is equal to the first threshold signal value, the threshold signal being constant in magnitude as a function of time in the second switching time course. For example, the system controller is based at least on the 13A, 13B, 14A, 14B, 14C, 15A, 15B, 16A, 16B, and/or 17th achieve.

根據另一實施例，一種用於保護電源轉換器的系統控制器包括：信號生成器、比較器以及調製和驅動元件。信號生成器被配置為生成閾值信號。比較器被配置為接收所述閾值信號以及電流感測信號，並且至少基於與所述閾值信號和所述電流感測信號相關聯的資訊生成比較信號，所述電流感測信號指示流經電源轉換器的初級繞組的初級電流的大小。調製和驅動元件，被耦合到所述信號生成器並被配置為至少接收所述比較信號，至少基於與所述比較信號相關聯的資訊生成驅動信號，並且向開關輸出所述驅動信號以影響所述初級電流，所述驅動信號與一個或多個第一開關時程以及在所述一個或多個第一開關時程之後的第二開關時程相關聯，所述一個或多個第一開關時程對應於一個或多個第一占空比，所述第二開關時程包括導通時間和關斷時間。所述信號生成器還被配置為，在所述第二開關時程中，至少基於與所述一個或多個第一占空比相關聯的資訊確定 第一閾值信號值；在所述導通時間的開始處將時間設為零；如果該時間滿足一個或多個第一預定條件，則生成與所確定的第一閾值信號值相等的所述閾值信號，以使得所述閾值信號作為時間的函數在大小上是恒定的；以及如果該時間滿足一個或多個第二預定條件，則生成所述閾值信號以使得所述閾值信號的大小隨著時間的增長而減小。例如，該系統控制器至少根據第18A圖、第18B圖、第19A圖和/或第19B圖來實現。 In accordance with another embodiment, a system controller for protecting a power converter includes a signal generator, a comparator, and a modulation and drive component. The signal generator is configured to generate a threshold signal. A comparator is configured to receive the threshold signal and a current sense signal and generate a comparison signal based on at least information associated with the threshold signal and the current sense signal, the current sense signal indicating a flow through power conversion The primary current of the primary winding of the device. a modulation and drive component coupled to the signal generator and configured to receive at least the comparison signal, generate a drive signal based on at least information associated with the comparison signal, and output the drive signal to a switch to affect Primary current, the drive signal being associated with one or more first switch time periods and a second switch time history after the one or more first switch time periods, the one or more first switches The time history corresponds to one or more first duty cycles, and the second switch time history includes an on time and an off time. The signal generator is further configured to determine, based on at least information associated with the one or more first duty cycles, in the second switching time course a first threshold signal value; setting a time to zero at the beginning of the on time; generating the threshold signal equal to the determined first threshold signal value if the time satisfies one or more first predetermined conditions So that the threshold signal is constant in magnitude as a function of time; and if the time satisfies one or more second predetermined conditions, generating the threshold signal such that the magnitude of the threshold signal is over time Increase and decrease. For example, the system controller is implemented at least according to FIG. 18A, FIG. 18B, FIG. 19A, and/or FIG. 19B.

根據又一實施例，一種用於保護電源轉換器的系統控制器包括：信號生成器、比較器以及調製和驅動元件。信號生成器被配置為生成閾值信號。比較器被配置為接收所述閾值信號以及電流感測信號，並且至少基於與所述閾值信號和所述電流感測信號相關聯的資訊生成比較信號，所述電流感測信號指示流經電源轉換器的初級繞組的初級電流的大小。調製和驅動元件，被耦合到所述信號生成器並被配置為至少接收所述比較信號，至少基於與所述比較信號相關聯的資訊生成驅動信號，並且向開關輸出所述驅動信號以影響所述初級電流，所述驅動信號與一個或多個第一開關時程以及在所述一個或多個第一開關時程之後的第二開關時程相關聯，所述一個或多個第一開關時程對應於一個或多個第一占空比，所述第二開關時程包括導通時間和關斷時間。所述信號生成器還被配置為，在所述第二開關時程中，至少基於與所述一個或多個第一占空比相關聯的資訊確定第一閾值信號值；在所述導通時間的開始處將時間設為零；以及如果該時間滿足一個或多個第一預定條件，則生成所述閾值信號以使得所述閾值信號的大小隨著時間的增長從所確定的第一閾值信號值減小。例如，該系統控制器至少根據第20A圖、第20B圖、第21A圖和/或第21B圖來實現。 In accordance with yet another embodiment, a system controller for protecting a power converter includes a signal generator, a comparator, and a modulation and drive component. The signal generator is configured to generate a threshold signal. A comparator is configured to receive the threshold signal and a current sense signal and generate a comparison signal based on at least information associated with the threshold signal and the current sense signal, the current sense signal indicating a flow through power conversion The primary current of the primary winding of the device. a modulation and drive component coupled to the signal generator and configured to receive at least the comparison signal, generate a drive signal based on at least information associated with the comparison signal, and output the drive signal to a switch to affect Primary current, the drive signal being associated with one or more first switch time periods and a second switch time history after the one or more first switch time periods, the one or more first switches The time history corresponds to one or more first duty cycles, and the second switch time history includes an on time and an off time. The signal generator is further configured to determine a first threshold signal value based on at least information associated with the one or more first duty cycles in the second switching time course; Setting the time to zero; and if the time satisfies one or more first predetermined conditions, generating the threshold signal such that the magnitude of the threshold signal increases from time from the determined first threshold signal The value is reduced. For example, the system controller is implemented at least according to FIG. 20A, FIG. 20B, FIG. 21A, and/or FIG. 21B.

根據又一實施例，一種用於保護電源轉換器的系統控制器包括：信號生成器、比較器以及調製和驅動元件。信號生成器被配置為生成閾值信號。比較器被配置為接收所述閾值信號以及電流感測信號，並且至少基於與所述閾值信號和所述電流感測信號相關聯的資訊生成比較信號，所述電流感測信號指示流經電源轉換器的初級繞組的初級電流的大小。調製和驅動元件，被耦合到所述信號生成器並被配置為至少接收所述比較信號，至少基於與所述比較信號相關聯的資訊生成驅動信號，並且向開關輸 出所述驅動信號以影響所述初級電流，所述驅動信號與多個開關時程相關聯，所述多個開關時程的每個包括導通時間和關斷時間。所述信號生成器還被配置為，在所述多個開關時程的每個中，在所述導通時間的開始處將時間設為零；如果該時間滿足一個或多個第一預定條件，則生成所述閾值信號，以使得所述閾值信號的大小隨著時間的增長而增大；以及如果該時間滿足一個或多個第二預定條件，則生成所述閾值信號以使得所述閾值信號的大小隨著時間的增長而減小。例如，該系統控制器至少根據第22A圖和/或第22B圖來實現。 In accordance with yet another embodiment, a system controller for protecting a power converter includes a signal generator, a comparator, and a modulation and drive component. The signal generator is configured to generate a threshold signal. A comparator is configured to receive the threshold signal and a current sense signal and generate a comparison signal based on at least information associated with the threshold signal and the current sense signal, the current sense signal indicating a flow through power conversion The primary current of the primary winding of the device. a modulation and drive component coupled to the signal generator and configured to receive at least the comparison signal, generate a drive signal based on at least information associated with the comparison signal, and output to the switch The drive signal is derived to affect the primary current, the drive signal being associated with a plurality of switch time periods, each of the plurality of switch time periods including an on time and an off time. The signal generator is further configured to, in each of the plurality of switch time periods, set a time to zero at the beginning of the on time; if the time satisfies one or more first predetermined conditions, Generating the threshold signal such that the magnitude of the threshold signal increases over time; and if the time satisfies one or more second predetermined conditions, generating the threshold signal to cause the threshold signal The size decreases with time. For example, the system controller is implemented at least according to FIG. 22A and/or 22B.

根據又一實施例，一種用於保護電源轉換器的信號生成器包括：調製和驅動元件、斜坡信號生成器、採樣信號生成器以及採樣和保持元件。調製和驅動元件被配置為生成調製信號以向開關輸出驅動信號從而影響流經電源轉換器的初級繞組的初級電流。斜坡信號生成器被配置為接收所述調製信號並且至少基於與所述調製信號相關聯的資訊生成斜坡信號。採樣信號生成器被配置為接收所述調製信號並且回應於所述調製信號的下降沿而生成包含脈衝的採樣信號。採樣和保持元件被配置為接收所述採樣信號和所述斜坡信號，並且輸出與所述採樣信號的所述脈衝相應的、與所述斜坡信號的大小相關聯的採樣和保持信號。例如，該信號生成器至少根據第14A圖、第14C圖、第16A圖、第19A圖和/或第21A圖來實現。 In accordance with yet another embodiment, a signal generator for protecting a power converter includes a modulation and drive component, a ramp signal generator, a sampled signal generator, and a sample and hold component. The modulation and drive elements are configured to generate a modulated signal to output a drive signal to the switch to affect a primary current flowing through the primary winding of the power converter. A ramp signal generator is configured to receive the modulated signal and generate a ramp signal based on at least information associated with the modulated signal. A sampled signal generator is configured to receive the modulated signal and generate a sampled signal comprising a pulse in response to a falling edge of the modulated signal. A sample and hold element is configured to receive the sampled signal and the ramp signal and output a sample and hold signal associated with the pulse of the sampled signal and associated with a magnitude of the ramp signal. For example, the signal generator is implemented at least according to FIG. 14A, FIG. 14C, FIG. 16A, FIG. 19A, and/or FIG. 21A.

根據又一實施例，一種用於保護電源轉換器的信號生成器包括：調製和驅動元件、斜坡信號生成器、採樣和保持元件、濾波器信號生成器以及低通濾波器。調製和驅動元件被配置為生成調製信號以向開關輸出驅動信號從而影響流經電源轉換器的初級繞組的初級電流。斜坡信號生成器被配置為接收所述調製信號並且至少基於與所述調製信號相關聯的資訊生成斜坡信號。採樣和保持元件被配置為接收所述斜坡信號和所述調製信號，並且回應於所述調製信號輸出與所述斜坡信號的大小相關聯的採樣和保持信號。濾波器信號生成器被配置為接收所述調製信號並且至少基於與所述調製信號相關聯的資訊生成濾波器信號。低通濾波器被配置為接收所述濾波器信號和所述採樣和保持信號並且回應於所述濾波器信號，至少基於與所述採樣和保持信號相關聯的資訊生成第一信號。例如，該信號生 成器至少根據第15A圖、第15B圖和/或第17圖來實現。 In accordance with yet another embodiment, a signal generator for protecting a power converter includes a modulation and drive component, a ramp signal generator, a sample and hold component, a filter signal generator, and a low pass filter. The modulation and drive elements are configured to generate a modulated signal to output a drive signal to the switch to affect a primary current flowing through the primary winding of the power converter. A ramp signal generator is configured to receive the modulated signal and generate a ramp signal based on at least information associated with the modulated signal. A sample and hold element is configured to receive the ramp signal and the modulation signal and output a sample and hold signal associated with a magnitude of the ramp signal in response to the modulation signal. A filter signal generator is configured to receive the modulated signal and generate a filter signal based on at least information associated with the modulated signal. A low pass filter is configured to receive the filter signal and the sample and hold signal and to generate a first signal based on at least information associated with the sample and hold signal in response to the filter signal. For example, the signal is raw The implement is implemented at least according to Fig. 15A, Fig. 15B, and/or Fig. 17.

在一個實施例中，一種用於保護電源轉換器的方法包括：生成閾值信號；接收所述閾值信號以及電流感測信號，所述電流感測信號指示流經電源轉換器的初級繞組的初級電流的大小；以及至少基於與所述閾值信號和所述電流感測信號相關聯的資訊生成比較信號。另外，該方法包括：至少接收所述比較信號；至少基於與所述比較信號相關聯的資訊生成驅動信號，所述驅動信號與一個或多個第一開關時程以及在所述一個或多個第一開關時程之後的第二開關時程相關聯，所述一個或多個第一開關時程對應於一個或多個第一占空比；以及向開關輸出所述驅動信號以影響所述初級電流。用於生成閾值信號的處理包括：在所述第二開關時程中，至少基於與所述一個或多個占空比相關聯的資訊確定閾值信號值；以及生成與所確定的閾值信號值相等的所述閾值信號，所述閾值信號在所述第二開關時程中作為時間的函數在大小上是恒定的。例如，該方法至少根據第13A圖、第13B圖、第14A圖、第14B圖、第14C圖、第15A圖、第15B圖、第16A圖、第16B圖和/或第17圖來實現。 In one embodiment, a method for protecting a power converter includes: generating a threshold signal; receiving the threshold signal and a current sense signal indicative of a primary current flowing through a primary winding of a power converter a size; and generating a comparison signal based at least on information associated with the threshold signal and the current sense signal. Additionally, the method includes: receiving at least the comparison signal; generating a drive signal based on at least information associated with the comparison signal, the drive signal and one or more first switch schedules and in the one or more Associated with a second switching time history after the first switching time period, the one or more first switching time periods corresponding to one or more first duty cycles; and outputting the driving signal to the switch to affect the Primary current. The process for generating a threshold signal includes determining, in the second switching time history, a threshold signal value based on at least information associated with the one or more duty cycles; and generating a value equal to the determined threshold signal value The threshold signal is constant in magnitude as a function of time in the second switching time course. For example, the method is implemented at least in accordance with FIGS. 13A, 13B, 14A, 14B, 14C, 15A, 15B, 16A, 16B, and/or 17.

在另一實施例中，一種用於保護電源轉換器的方法包括：生成閾值信號；接收所述閾值信號以及電流感測信號，所述電流感測信號指示流經電源轉換器的初級繞組的初級電流的大小；以及至少基於與所述閾值信號和所述電流感測信號相關聯的資訊生成比較信號。該方法還包括：至少接收所述比較信號；至少基於與所述比較信號相關聯的資訊生成驅動信號，所述驅動信號與一個或多個第一開關時程以及在所述一個或多個第一開關時程之後的第二開關時程相關聯，所述一個或多個第一開關時程對應於一個或多個第一占空比，所述第二開關時程包括導通時間和關斷時間；以及向開關輸出所述驅動信號以影響所述初級電流。用於生成閾值信號的處理包括：在所述第二開關時程中，至少基於與所述一個或多個占空比相關聯的資訊確定閾值信號值；在所述導通時間的開始處將時間設為零；如果該時間滿足一個或多個第一預定條件，則生成與所確定的閾值信號值相等的所述閾值信號，以使得所述閾值信號作為時間的函數在大小上是恒定的；以及如果該時間滿足一個或多個第二預定條件，則生成所述閾 值信號以使得所述閾值信號的大小隨著時間的增長而減小。例如，該方法至少根據第18A圖、第18B圖、第19A圖和/或第19B圖來實現。 In another embodiment, a method for protecting a power converter includes: generating a threshold signal; receiving the threshold signal and a current sense signal indicative of a primary flowing through a primary winding of a power converter a magnitude of the current; and generating a comparison signal based at least on information associated with the threshold signal and the current sense signal. The method also includes receiving at least the comparison signal, generating a drive signal based on at least information associated with the comparison signal, the drive signal and one or more first switch schedules and in the one or more Associated with a second switching time history after a switching time period, the one or more first switching time periods corresponding to one or more first duty cycles, the second switching time history including an on time and a turn-off And outputting the drive signal to the switch to affect the primary current. The process for generating a threshold signal includes determining a threshold signal value based on at least information associated with the one or more duty cycles in the second switching time course; time at a beginning of the on time Set to zero; if the time satisfies one or more first predetermined conditions, generating the threshold signal equal to the determined threshold signal value such that the threshold signal is constant in magnitude as a function of time; And generating the threshold if the time satisfies one or more second predetermined conditions The value signal is such that the magnitude of the threshold signal decreases over time. For example, the method is implemented at least according to FIG. 18A, FIG. 18B, FIG. 19A, and/or 19B.

在又一實施例中，一種用於保護電源轉換器的方法包括：生成閾值信號；接收所述閾值信號以及電流感測信號，所述電流感測信號指示流經電源轉換器的初級繞組的初級電流的大小；以及至少基於與所述閾值信號和所述電流感測信號相關聯的資訊生成比較信號。該方法還包括：至少接收所述比較信號；至少基於與所述比較信號相關聯的資訊生成驅動信號，所述驅動信號與一個或多個第一開關時程以及在所述一個或多個第一開關時程之後的第二開關時程相關聯，所述一個或多個第一開關時程對應於一個或多個第一占空比，所述第二開關時程包括導通時間和關斷時間；以及向開關輸出所述驅動信號以影響所述初級電流。用於生成閾值信號的處理包括：在所述第二開關時程中，至少基於與所述一個或多個占空比相關聯的資訊確定閾值信號值；在所述導通時間的開始處將時間設為零；以及如果該時間滿足一個或多個預定條件，則生成所述閾值信號以使得所述閾值信號的大小隨著時間的增長從所確定的閾值信號值減小。例如，該方法至少根據第20A圖、第0B圖、第21A圖和/或第21B圖來實現。 In yet another embodiment, a method for protecting a power converter includes: generating a threshold signal; receiving the threshold signal and a current sense signal, the current sense signal indicating a primary flowing through a primary winding of the power converter a magnitude of the current; and generating a comparison signal based at least on information associated with the threshold signal and the current sense signal. The method also includes receiving at least the comparison signal, generating a drive signal based on at least information associated with the comparison signal, the drive signal and one or more first switch schedules and in the one or more Associated with a second switching time history after a switching time period, the one or more first switching time periods corresponding to one or more first duty cycles, the second switching time history including an on time and a turn-off And outputting the drive signal to the switch to affect the primary current. The process for generating a threshold signal includes determining a threshold signal value based on at least information associated with the one or more duty cycles in the second switching time course; time at a beginning of the on time Set to zero; and if the time satisfies one or more predetermined conditions, the threshold signal is generated such that the magnitude of the threshold signal decreases from the determined threshold signal value over time. For example, the method is implemented at least according to FIG. 20A, FIG. 0B, FIG. 21A, and/or FIG. 21B.

在又一實施例中，一種用於保護電源轉換器的方法包括：生成閾值信號；接收所述閾值信號以及電流感測信號，所述電流感測信號指示流經電源轉換器的初級繞組的初級電流的大小；以及至少基於與所述閾值信號和所述電流感測信號相關聯的資訊生成比較信號。該方法還包括：至少接收所述比較信號；至少基於與所述比較信號相關聯的資訊生成驅動信號，所述驅動信號與多個開關時程相關聯，所述多個開關時程的每個包括導通時間和關斷時間；以及向開關輸出所述驅動信號以影響所述初級電流。用於生成閾值信號的處理包括：在所述多個開關時程的每個中，在所述導通時間的開始處將時間設為零；如果該時間滿足一個或多個第一預定條件，則生成所述閾值信號，以使得所述閾值信號的大小隨著時間的增長而增大；以及如果該時間滿足一個或多個第二預定條件，則生成所述閾值信號以使得所述閾值信號的大小隨著時間的增長而減小。例如，該方法至少根據第22A圖和/或第22B圖來實現。 In yet another embodiment, a method for protecting a power converter includes: generating a threshold signal; receiving the threshold signal and a current sense signal, the current sense signal indicating a primary flowing through a primary winding of the power converter a magnitude of the current; and generating a comparison signal based at least on information associated with the threshold signal and the current sense signal. The method also includes receiving at least the comparison signal, generating a drive signal based on at least information associated with the comparison signal, the drive signal being associated with a plurality of switch schedules, each of the plurality of switch schedules An on time and an off time are included; and the drive signal is output to the switch to affect the primary current. The process for generating a threshold signal includes, in each of the plurality of switch time periods, setting a time to zero at the beginning of the on time; if the time satisfies one or more first predetermined conditions, Generating the threshold signal such that the magnitude of the threshold signal increases over time; and if the time satisfies one or more second predetermined conditions, generating the threshold signal to cause the threshold signal The size decreases with time. For example, the method is implemented at least according to FIG. 22A and/or 22B.

在又一實施例中，一種用於生成用於保護電源轉換器的信號的方法包括生成調製信號以向開關輸出驅動信號從而影響流經電源轉換器的初級繞組的初級電流；接收所述調製信號；以及處理與所述調製信號相關聯的資訊。該方法還包括：至少基於與所述調製信號相關聯的資訊生成斜坡信號；回應於所述調製信號的下降沿而生成包含脈衝的採樣信號；接收所述採樣信號和所述斜坡信號；以及輸出與所述採樣信號的所述脈衝相應的、與所述斜坡信號的大小相關聯的採樣和保持信號。例如，該方法至少根據第14A圖、第14C圖、第16A圖、第19A圖和/或第21A圖來實現。 In yet another embodiment, a method for generating a signal for protecting a power converter includes generating a modulated signal to output a drive signal to a switch to affect a primary current flowing through a primary winding of the power converter; receiving the modulated signal And processing information associated with the modulated signal. The method also includes generating a ramp signal based on at least information associated with the modulated signal; generating a sampled signal comprising the pulse in response to a falling edge of the modulated signal; receiving the sampled signal and the ramp signal; and outputting A sample and hold signal associated with the pulse of the sampled signal and associated with the magnitude of the ramp signal. For example, the method is implemented at least according to FIG. 14A, FIG. 14C, FIG. 16A, FIG. 19A, and/or 21A.

在又一實施例中，一種用於生成用於保護電源轉換器的信號的方法包括：生成調製信號以向開關輸出驅動信號從而影響流經電源轉換器的初級繞組的初級電流；接收所述調製信號；以及處理與所述調製信號相關聯的資訊。該方法還包括：至少基於與所述調製信號相關聯的資訊生成斜坡信號；至少基於與所述調製信號相關聯的資訊生成濾波器信號；以及接收所述斜坡信號和所述調製信號。另外，該方法包括：回應於所述調製信號輸出與所述斜坡信號的大小相關聯的採樣和保持信號；接收所述濾波器信號以及所述採樣和保持信號；以及回應於所述濾波器信號，至少基於與所述採樣和保持信號相關聯的資訊生成第一信號。例如，該方法至少根據第15A圖、第15B圖和/或第17圖來實現。 In yet another embodiment, a method for generating a signal for protecting a power converter includes generating a modulated signal to output a drive signal to a switch to affect a primary current flowing through a primary winding of the power converter; receiving the modulation a signal; and processing information associated with the modulated signal. The method also includes generating a ramp signal based on at least information associated with the modulated signal; generating a filter signal based on at least information associated with the modulated signal; and receiving the ramp signal and the modulated signal. Additionally, the method includes: outputting a sample and hold signal associated with a magnitude of the ramp signal in response to the modulation signal; receiving the filter signal and the sample and hold signal; and responsive to the filter signal Generating a first signal based at least on information associated with the sample and hold signal. For example, the method is implemented at least according to FIG. 15A, FIG. 15B, and/or FIG.

例如，本發明各個實施例中的一些或所有元件單獨地和/或與至少另一元件相組合地是利用一個或多個軟體元件、一個或多個硬體元件和/或軟體與硬體元件的一種或多種組合來實現的。在另一示例中，本發明各個實施例中的一些或所有元件單獨地和/或與至少另一元件相組合地在一個或多個電路中實現，例如在一個或多個類比電路和/或一個或多個數位電路中實現。在又一示例中，本發明的各個實施例和/或示例可以相組合。 For example, some or all of the elements of various embodiments of the invention, alone and/or in combination with at least one other element, utilize one or more of the software elements, one or more hardware elements, and/or software and hardware elements. One or more combinations are implemented. In another example, some or all of the elements of various embodiments of the invention are implemented in one or more circuits, alone and/or in combination with at least one other element, such as in one or more analog circuits and/or Implemented in one or more digital circuits. In yet another example, various embodiments and/or examples of the invention may be combined.

雖然已描述了本發明的具體實施例，然而本領域技術人員將明白，還存在於所述實施例等同的其它實施例。因此，將明白，本發明不受所示具體實施例的限制，而是僅由申請專利範圍的範圍來限定。 Although specific embodiments of the invention have been described, it will be apparent to those skilled in the art Therefore, it is to be understood that the invention is not limited by

2510‧‧‧過流保護(OCP)比較器 2510‧‧‧Overcurrent Protection (OCP) Comparator

2512‧‧‧過流閾值信號 2512‧‧‧Overcurrent threshold signal

2514‧‧‧電流感測信號 2514‧‧‧ Current sensing signal

2516‧‧‧過流控制信號 2516‧‧‧Overcurrent control signal

2522‧‧‧PWM信號 2522‧‧‧PWM signal

2520‧‧‧PWM控制器元件 2520‧‧‧PWM controller components

2530‧‧‧柵極驅動器 2530‧‧‧Gate Driver

2540‧‧‧開關 2540‧‧‧Switch

2550,2552,2554,2556‧‧‧電阻器 2550, 2552, 2554, 2556‧‧‧ resistors

2560‧‧‧初級繞組 2560‧‧‧Primary winding

2580‧‧‧晶片 2580‧‧‧ wafer

2590‧‧‧節點 2590‧‧‧ nodes

2582‧‧‧信號 2582‧‧‧ signal

2572‧‧‧電流 2572‧‧‧ Current

2500‧‧‧電源轉換器 2500‧‧‧Power Converter

2570‧‧‧過流閾值信號生成器 2570‧‧‧Overcurrent threshold signal generator

2584‧‧‧柵極驅動信號 2584‧‧‧Gate drive signal

2592‧‧‧電壓Vin 2592‧‧‧V Voltage V in

2594‧‧‧前沿消隱(LEB)元件 2594‧‧‧Leading edge blanking (LEB) components

2599‧‧‧VAC信號 2599‧‧‧VAC signal

Claims (67)

一種用於保護電源轉換器的系統控制器，該系統控制器包括：信號生成器，被配置為生成閾值信號；比較器，被配置為接收所述閾值信號以及電流感測信號，並且至少基於與所述閾值信號和所述電流感測信號相關聯的資訊生成比較信號，所述電流感測信號指示流經電源轉換器的初級繞組的初級電流的大小；以及調製和驅動元件，被耦合到所述信號生成器並被配置為至少接收所述比較信號，至少基於與所述比較信號相關聯的資訊生成驅動信號，並且向開關輸出所述驅動信號以影響所述初級電流，所述驅動信號與一個或多個第一開關時程以及在所述一個或多個第一開關時程之後的第二開關時程相關聯，所述一個或多個第一開關時程對應於一個或多個第一占空比；其中，所述信號生成器還被配置為，在所述第二開關時程中，至少基於與所述一個或多個第一占空比相關聯的資訊確定第一閾值信號值；以及生成與所確定的第一閾值信號值相等的所述閾值信號，所述閾值信號在所述第二開關時程中作為時間的函數在大小上是恒定的。 A system controller for protecting a power converter, the system controller comprising: a signal generator configured to generate a threshold signal; a comparator configured to receive the threshold signal and a current sensing signal, and based at least on The threshold signal and the information associated with the current sense signal generate a comparison signal indicative of a magnitude of a primary current flowing through a primary winding of the power converter; and a modulation and drive component coupled to the The signal generator is configured to receive at least the comparison signal, generate a drive signal based on at least information associated with the comparison signal, and output the drive signal to a switch to affect the primary current, the drive signal One or more first switch schedules associated with the second switch schedule after the one or more first switch schedules, the one or more first switch schedules corresponding to one or more a duty cycle; wherein the signal generator is further configured to, based on the one or more The duty cycle associated information determines a first threshold signal value; and generates the threshold signal equal to the determined first threshold signal value, the threshold signal being a function of time in the second switching time course The size is constant. 如申請專利範圍第1項所述之系統控制器，其中：所述驅動信號還與在所述一個或多個第一開關時程和所述第二開關時程之後的第三開關時程相關聯，所述第二開關時程對應於第二占空比；其中，所述信號生成器還被配置為，在所述第三開關時程中，至少基於與所述第二占空比相關聯的資訊確定第二閾值信號值；以及生成與所確定的第二閾值信號值相等的所述閾值信號，所述第二閾值信號在所述第三開關時程中作為時間的函數在大小上是恒定的。 The system controller of claim 1, wherein: the driving signal is further related to a third switching time period after the one or more first switching time periods and the second switching time period The second switch time period corresponds to a second duty cycle; wherein the signal generator is further configured to be based at least on the second duty cycle in the third switch time course The associated information determines a second threshold signal value; and generates the threshold signal equal to the determined second threshold signal value, the second threshold signal being in size as a function of time in the third switching time course It is constant. 如申請專利範圍第2項所述之系統控制器，其中，所述第二閾值信號值等於所述第一閾值信號值。 The system controller of claim 2, wherein the second threshold signal value is equal to the first threshold signal value. 如申請專利範圍第2項所述之系統控制器，其中，所述第二閾值信號值不同於所述第一閾值信號值。 The system controller of claim 2, wherein the second threshold signal value is different from the first threshold signal value. 一種用於保護電源轉換器的系統控制器，該系統控制器包括：信號生成器，被配置為生成閾值信號； 比較器，被配置為接收所述閾值信號以及電流感測信號，並且至少基於與所述閾值信號和所述電流感測信號相關聯的資訊生成比較信號，所述電流感測信號指示流經電源轉換器的初級繞組的初級電流的大小；以及調製和驅動元件，被耦合到所述信號生成器並被配置為至少接收所述比較信號，至少基於與所述比較信號相關聯的資訊生成驅動信號，並且向開關輸出所述驅動信號以影響所述初級電流，所述驅動信號與一個或多個第一開關時程以及在所述一個或多個第一開關時程之後的第二開關時程相關聯，所述一個或多個第一開關時程對應於一個或多個第一占空比，所述第二開關時程包括導通時間和關斷時間；其中，所述信號生成器還被配置為，在所述第二開關時程中，至少基於與所述一個或多個第一占空比相關聯的資訊確定第一閾值信號值；在所述導通時間的開始處將時間設為零；如果該時間滿足一個或多個第一預定條件，則生成與所確定的第一閾值信號值相等的所述閾值信號，以使得所述閾值信號作為時間的函數在大小上是恒定的；以及如果該時間滿足一個或多個第二預定條件，則生成所述閾值信號以使得所述閾值信號的大小隨著時間的增長而減小。 A system controller for protecting a power converter, the system controller comprising: a signal generator configured to generate a threshold signal; a comparator configured to receive the threshold signal and a current sense signal and generate a comparison signal based on at least information associated with the threshold signal and the current sense signal, the current sense signal indicating flow through a power source a magnitude of a primary current of a primary winding of the converter; and a modulation and drive component coupled to the signal generator and configured to receive at least the comparison signal, generating a drive signal based on at least information associated with the comparison signal And outputting the drive signal to a switch to affect the primary current, the drive signal and one or more first switch schedules and a second switch schedule after the one or more first switch schedules Correspondingly, the one or more first switch time periods correspond to one or more first duty cycles, and the second switch time history includes an on time and an off time; wherein the signal generator is further Configuring, in the second switching time course, determining a first threshold signal value based on at least information associated with the one or more first duty cycles; Setting the time to zero at the beginning of the time; if the time satisfies one or more first predetermined conditions, generating the threshold signal equal to the determined first threshold signal value such that the threshold signal is time The function is constant in size; and if the time satisfies one or more second predetermined conditions, the threshold signal is generated such that the magnitude of the threshold signal decreases over time. 如申請專利範圍第5項所述之系統控制器，其中，在所述第二開關時程中，如果該時間小於第一預定值，則該時間滿足一個或多個第一預定條件。 The system controller of claim 5, wherein in the second switching time period, if the time is less than the first predetermined value, the time satisfies one or more first predetermined conditions. 如申請專利範圍第5項所述之系統控制器，其中，在所述第二開關時程中，如果該時間大於所述第一預定值且小於第二預定值，則該時間滿足一個或多個第二預定條件。 The system controller of claim 5, wherein, in the second switching time period, if the time is greater than the first predetermined value and less than a second predetermined value, the time satisfies one or more Second predetermined condition. 如申請專利範圍第5項所述之系統控制器，其中，所述信號生成器還被配置為，在所述第二開關時程中，如果該時間滿足一個或多個第三預定條件，則生成與第二閾值信號值相等的所述閾值信號以使得所述閾值信號作為該時間的函數在大小上是恒定的，所述第二閾值信號值小於所述第一閾值信號值。 The system controller of claim 5, wherein the signal generator is further configured to, in the second switching time period, if the time satisfies one or more third predetermined conditions, The threshold signal equal to the second threshold signal value is generated such that the threshold signal is constant in magnitude as a function of the time, the second threshold signal value being less than the first threshold signal value. 如申請專利範圍第8項所述之系統控制器，其中，在所述第二開關時程中，如果該時間大於所述第二預定值，則該時間滿足一個或多個第三預定 條件。 The system controller of claim 8, wherein in the second switching time period, if the time is greater than the second predetermined value, the time satisfies one or more third predetermined condition. 如申請專利範圍第5項所述之系統控制器，其中：所述驅動信號還與在所述一個或多個第一開關時程和所述第二開關時程之後的第三開關時程相關聯，所述第二開關時程對應於第二占空比，所述第三開關時程包括第二導通時間和第二關斷時間；其中，所述信號生成器還被配置為，在所述第三開關時程中，至少基於與所述第二占空比相關聯的資訊確定第二閾值信號值；在所述第二導通時間的開始處將該時間設為零；如果該時間滿足所述一個或多個第一預定條件，則生成與所確定的第二閾值信號值相等的所述閾值信號，以使得所述第二閾值信號作為時間的函數在大小上是恒定的；以及如果該時間滿足所述一個或多個第二預定條件，則生成所述閾值信號，以使得所述閾值信號的大小隨著時間的增長而減小。 The system controller of claim 5, wherein: the driving signal is further related to a third switching time period after the one or more first switching time periods and the second switching time period The second switch time history corresponds to a second duty cycle, the third switch time history includes a second on time and a second off time; wherein the signal generator is further configured to Determining, in the third switching time history, a second threshold signal value based on at least information associated with the second duty cycle; setting the time to zero at the beginning of the second conduction time; if the time is satisfied The one or more first predetermined conditions, generating the threshold signal equal to the determined second threshold signal value such that the second threshold signal is constant in magnitude as a function of time; and if The time satisfies the one or more second predetermined conditions, and the threshold signal is generated such that the magnitude of the threshold signal decreases over time. 如申請專利範圍第10項所述之系統控制器，其中，所述第二閾值信號值等於所述第一閾值信號值。 The system controller of claim 10, wherein the second threshold signal value is equal to the first threshold signal value. 如申請專利範圍第10項所述之系統控制器，其中，所述第二閾值信號值不同於所述第一閾值信號值。 The system controller of claim 10, wherein the second threshold signal value is different from the first threshold signal value. 一種用於保護電源轉換器的系統控制器，該系統控制器包括：信號生成器，被配置為生成閾值信號；比較器，被配置為接收所述閾值信號以及電流感測信號，並且至少基於與所述閾值信號和所述電流感測信號相關聯的資訊生成比較信號，所述電流感測信號指示流經電源轉換器的初級繞組的初級電流的大小；以及調製和驅動元件，被耦合到所述信號生成器並被配置為至少接收所述比較信號，至少基於與所述比較信號相關聯的資訊生成驅動信號，並且向開關輸出所述驅動信號以影響所述初級電流，所述驅動信號與一個或多個第一開關時程以及在所述一個或多個第一開關時程之後的第二開關時程相關聯，所述一個或多個第一開關時程對應於一個或多個第一占空比，所述第二開關時程包括導通時間和關斷時間；其中，所述信號生成器還被配置為，在所述第二開關時程中，至少基於與所述一個或多個第一占空比相關聯的資訊確定第一閾 值信號值；在所述導通時間的開始處將時間設為零；以及如果該時間滿足一個或多個第一預定條件，則生成所述閾值信號以使得所述閾值信號的大小隨著時間的增長從所確定的第一閾值信號值減小。 A system controller for protecting a power converter, the system controller comprising: a signal generator configured to generate a threshold signal; a comparator configured to receive the threshold signal and a current sensing signal, and based at least on The threshold signal and the information associated with the current sense signal generate a comparison signal indicative of a magnitude of a primary current flowing through a primary winding of the power converter; and a modulation and drive component coupled to the The signal generator is configured to receive at least the comparison signal, generate a drive signal based on at least information associated with the comparison signal, and output the drive signal to a switch to affect the primary current, the drive signal One or more first switch schedules associated with the second switch schedule after the one or more first switch schedules, the one or more first switch schedules corresponding to one or more a duty cycle, the second switch time history including an on time and an off time; wherein the signal generator is further configured to be in the Switch process, a first threshold and determining based at least on the one or more information associated with a first duty cycle a value signal value; setting the time to zero at the beginning of the on time; and generating the threshold signal such that the magnitude of the threshold signal is over time if the time satisfies one or more first predetermined conditions The increase decreases from the determined first threshold signal value. 如申請專利範圍第13項所述之系統控制器，其中，在所述第二開關時程中，如果該時間小於第一預定值，則該時間滿足一個或多個第一預定條件。 The system controller of claim 13, wherein in the second switching time period, if the time is less than the first predetermined value, the time satisfies one or more first predetermined conditions. 如申請專利範圍第14項所述之系統控制器，其中，所述信號生成器還被配置為，在所述第二開關時程中，如果該時間滿足一個或多個第二預定條件，則生成與第二閾值信號值相等的所述閾值信號以使得所述閾值信號作為該時間的函數在大小上是恒定的，所述第二閾值信號值小於所述第一閾值信號值。 The system controller of claim 14, wherein the signal generator is further configured to, in the second switch time history, if the time satisfies one or more second predetermined conditions, The threshold signal equal to the second threshold signal value is generated such that the threshold signal is constant in magnitude as a function of the time, the second threshold signal value being less than the first threshold signal value. 如申請專利範圍第15項所述之系統控制器，其中，在所述第二開關時程中，如果該時間大於所述第一預定值，則該時間滿足一個或多個第二預定條件。 The system controller of claim 15, wherein in the second switching time period, if the time is greater than the first predetermined value, the time satisfies one or more second predetermined conditions. 如申請專利範圍第13項所述之系統控制器，其中：所述驅動信號還與在所述一個或多個第一開關時程和所述第二開關時程之後的第三開關時程相關聯，所述第二開關時程對應於第二占空比，所述第三開關時程包括第二導通時間和第二關斷時間；其中，所述信號生成器還被配置為，在所述第三開關時程中，至少基於與所述第二占空比相關聯的資訊確定第二閾值信號值；在所述第二導通時間的開始處將該時間設為零；以及如果該時間滿足所述一個或多個第一預定條件，則生成所述閾值信號以使得所述閾值信號的大小隨著時間的增長從所確定的第二閾值信號值減小。 The system controller of claim 13, wherein: the driving signal is further related to a third switching time period after the one or more first switching time periods and the second switching time period The second switch time history corresponds to a second duty cycle, the third switch time history includes a second on time and a second off time; wherein the signal generator is further configured to Determining, in the third switching time history, a second threshold signal value based on at least information associated with the second duty cycle; setting the time to zero at the beginning of the second conduction time; and if the time Satisfying the one or more first predetermined conditions, the threshold signal is generated such that the magnitude of the threshold signal decreases from the determined second threshold signal value over time. 如申請專利範圍第17項所述之系統控制器，其中，所述第二閾值信號值等於所述第一閾值信號值。 The system controller of claim 17, wherein the second threshold signal value is equal to the first threshold signal value. 如申請專利範圍第17項所述之系統控制器，其中，所述第二閾值信號值不同於所述第一閾值信號值。 The system controller of claim 17, wherein the second threshold signal value is different from the first threshold signal value. 一種用於保護電源轉換器的系統控制器，該系統控制器包括：信號生成器，被配置為生成閾值信號；比較器，被配置為接收所述閾值信號以及電流感測信號，並且至少基於與所述閾值信號和所述電流感測信號相關聯的資訊生成比較信號，所述電流感測信號指示流經電源轉換器的初級繞組的初級電流的大小；以及調製和驅動元件，被耦合到所述信號生成器並被配置為至少接收所述比較信號，至少基於與所述比較信號相關聯的資訊生成驅動信號，並且向開關輸出所述驅動信號以影響所述初級電流，所述驅動信號與多個開關時程相關聯，所述多個開關時程的每個包括導通時間和關斷時間；其中，所述信號生成器還被配置為，在所述多個開關時程之中，在所述導通時間的開始處將時間設為零；如果該時間滿足一個或多個第一預定條件，則生成所述閾值信號，以使得所述閾值信號的大小隨著時間的增長而增大；以及如果該時間滿足一個或多個第二預定條件，則生成所述閾值信號以使得所述閾值信號的大小隨著時間的增長而減小。 A system controller for protecting a power converter, the system controller comprising: a signal generator configured to generate a threshold signal; a comparator configured to receive the threshold signal and a current sensing signal, and based at least on The threshold signal and the information associated with the current sense signal generate a comparison signal indicative of a magnitude of a primary current flowing through a primary winding of the power converter; and a modulation and drive component coupled to the The signal generator is configured to receive at least the comparison signal, generate a drive signal based on at least information associated with the comparison signal, and output the drive signal to a switch to affect the primary current, the drive signal Associated with a plurality of switch time periods, each of the plurality of switch time periods including an on time and an off time; wherein the signal generator is further configured to be among the plurality of switch schedules The time is set to zero at the beginning of the on time; if the time satisfies one or more first predetermined conditions, the threshold signal is generated So that the magnitude of the threshold signal increases over time; and if the time satisfies one or more second predetermined conditions, generating the threshold signal such that the magnitude of the threshold signal increases over time And decrease. 如申請專利範圍第20項所述之系統控制器，其中，所述信號生成器還被配置為，在所述多個開關時程之中，如果該時間小於第一預定值且大於第二預定值，則生成所述閾值信號以使得所述閾值信號的大小隨著時間的增長而減小。 The system controller of claim 20, wherein the signal generator is further configured to, among the plurality of switch schedules, if the time is less than a first predetermined value and greater than a second predetermined value, The threshold signal is then generated such that the magnitude of the threshold signal decreases over time. 如申請專利範圍第21項所述之系統控制器，其中，所述信號生成器還被配置為，在所述多個開關時程之中，如果該時間小於所述第一預定值且大於所述第二預定值，則生成所述閾值信號以使得所述閾值信號的大小隨著時間的增長而線性地減小。 The system controller of claim 21, wherein the signal generator is further configured to, if the time is less than the first predetermined value and greater than the first one of the plurality of switch time courses The second predetermined value is then generated to cause the magnitude of the threshold signal to decrease linearly over time. 如申請專利範圍第21項所述之系統控制器，其中，所述信號生成器還被配置為，在所述多個開關時程之中，如果該時間小於所述第二預定值且大於第三預定值，則生成所述閾值信號以使得所述閾值信號的大小隨著時間的增長而增大。 The system controller of claim 21, wherein the signal generator is further configured to, among the plurality of switch schedules, if the time is less than the second predetermined value and greater than a third predetermined A value is generated to generate the threshold signal such that the magnitude of the threshold signal increases over time. 如申請專利範圍第23項所述之系統控制器，其中，所述信號生成器還被配置為，在所述多個開關時程之中，如果該時間小於所述第二預定值且大於所述第三預定值，則生成所述閾值信號以使得所述閾值信號的大小隨 著時間的增長而線性地增大。 The system controller of claim 23, wherein the signal generator is further configured to, if the time is less than the second predetermined value and greater than the first Three predetermined values, the threshold signal is generated such that the size of the threshold signal As time grows, it increases linearly. 如申請專利範圍第23項所述之系統控制器，其中，所述第三預定值等於零。 The system controller of claim 23, wherein the third predetermined value is equal to zero. 一種用於保護電源轉換器的信號生成器，該信號生成器包括：調製和驅動元件，被配置為生成調製信號以向開關輸出驅動信號從而影響流經電源轉換器的初級繞組的初級電流；斜坡信號生成器，被配置為接收所述調製信號並且至少基於與所述調製信號相關聯的資訊生成斜坡信號；採樣信號生成器，被配置為接收所述調製信號並且回應於所述調製信號的下降沿而生成包含脈衝的採樣信號；以及採樣和保持元件，被配置為接收所述採樣信號和所述斜坡信號，並且輸出與所述採樣信號的所述脈衝相應的、與所述斜坡信號的大小相關聯的採樣和保持信號。 A signal generator for protecting a power converter, the signal generator comprising: a modulation and drive component configured to generate a modulation signal to output a drive signal to the switch to affect a primary current flowing through a primary winding of the power converter; a signal generator configured to receive the modulated signal and generate a ramp signal based on at least information associated with the modulated signal; a sample signal generator configured to receive the modulated signal and responsive to a fall of the modulated signal Generating a sampling signal comprising a pulse; and a sample and hold element configured to receive the sampling signal and the ramp signal and output a magnitude corresponding to the pulse of the sampling signal and the ramp signal Associated sample and hold signals. 如申請專利範圍第26項所述之信號生成器，其中，所述調製信號是脈寬調製信號。 The signal generator of claim 26, wherein the modulated signal is a pulse width modulated signal. 如申請專利範圍第26項所述之信號生成器，其中，所述調製信號是所述驅動信號。 The signal generator of claim 26, wherein the modulation signal is the drive signal. 如申請專利範圍第26項所述之信號生成器，其中，所述調製信號不是所述驅動信號。 The signal generator of claim 26, wherein the modulation signal is not the drive signal. 如申請專利範圍第26項所述之信號生成器，其中，所述調製和驅動元件包括：調製元件，被配置為生成所述調製信號；以及柵極驅動元件，被配置為接收所述調製信號並且至少基於與所述調製信號相關聯的資訊輸出所述驅動信號。 The signal generator of claim 26, wherein the modulation and drive element comprises: a modulation element configured to generate the modulation signal; and a gate drive element configured to receive the modulation signal And outputting the drive signal based at least on information associated with the modulated signal. 如申請專利範圍第26項所述之信號生成器，其中，所述調製和驅動元件包括：調製元件，被配置為生成第一信號；以及柵極驅動元件，被配置為接收所述第一信號，至少基於與所述第一信號相關聯的資訊生成所述調製信號，並且輸出所述調製信號作為所述驅動信號。 The signal generator of claim 26, wherein the modulation and driving component comprises: a modulating component configured to generate a first signal; and a gate driving component configured to receive the first signal Generating the modulated signal based on at least information associated with the first signal and outputting the modulated signal as the drive signal. 如申請專利範圍第26項所述之信號生成器，還包括：比較器，被配置為接收與所述採樣和保持信號相關聯的閾值信號以及與所述初級電流相關聯的電流感測信號，並且至少基於與所述採樣和保持信號以及所述電流感測信號相關聯的資訊向所述調製和驅動元件輸出比較信號。 The signal generator of claim 26, further comprising: a comparator configured to receive a threshold signal associated with the sample and hold signal and a current sense signal associated with the primary current, And outputting a comparison signal to the modulation and drive element based at least on information associated with the sample and hold signal and the current sense signal. 如申請專利範圍第32項所述之信號生成器，還包括低通濾波器，被配置為接收所述採樣和保持信號並且至少基於與所述採樣和保持信號相關聯的資訊輸出所述閾值信號。 The signal generator of claim 32, further comprising a low pass filter configured to receive the sample and hold signal and output the threshold signal based on at least information associated with the sample and hold signal . 如申請專利範圍第33項所述之信號生成器，其中，所述採樣和保持元件和所述低通濾波器共用至少一個電容器。 The signal generator of claim 33, wherein the sample and hold element and the low pass filter share at least one capacitor. 如申請專利範圍第33項所述之信號生成器，其中，所述採樣和保持組件包括：第一開關，被配置為回應於所述採樣信號而閉合和斷開；以及第一電容器，被配置為當所述第一開關閉合時回應於所述斜坡信號被充電。 The signal generator of claim 33, wherein the sample and hold component comprises: a first switch configured to close and open in response to the sampling signal; and a first capacitor configured In response to the ramp signal being charged when the first switch is closed. 如申請專利範圍第35項所述之信號生成器，其中，所述低通濾波器包括：第一電阻器，包括第一電阻器端子和第二電阻器端子，所述第一電阻器端子被耦合到所述第一開關；以及第二電容器，被耦合到所述第二電阻器端子。 The signal generator of claim 35, wherein the low pass filter comprises: a first resistor comprising a first resistor terminal and a second resistor terminal, the first resistor terminal being Coupled to the first switch; and a second capacitor coupled to the second resistor terminal. 如申請專利範圍第32項所述之信號生成器，還包括：低通濾波器，被配置為接收所述採樣和保持信號並且至少基於與所述採樣和保持信號相關聯的資訊生成濾波器信號；占空比檢測和計數器元件，被配置為接收所述調製信號，檢測所述調製信號的占空比，並且至少基於與所述調製信號相關聯的資訊生成採樣使能信號，所述調製信號與一個或多個開關時程相關聯，所述一個或多個開關時程對應於一個或多個占空比；補償元件，被配置為接收所述調製信號並且至少基於與所述調製信號相關聯的資訊生成補償信號；第一開關，被耦合到所述補償元件；以及 第二開關，被耦合到所述低通濾波器；其中，所述占空比檢測和計數器元件還被配置為：如果與第一開關時程相對應的所述調製信號的第一占空比大於占空比閾值，則生成第一邏輯電平的所述採樣使能信號；以及如果與第二開關時程相對應的所述調製信號的第二占空比小於所述占空比閾值，則生成第二邏輯電平的所述採樣使能信號，所述第二開關時程為多個連續的開關時程；其中：所述第一開關被配置為，響應於所述第一邏輯電平的所述採樣使能信號而閉合，以輸出所述補償信號作為所述閾值信號；以及所述第二開關被配置為，響應於所述第二邏輯電平的所述採樣使能信號而閉合，以輸出所述濾波器信號作為所述閾值信號。 The signal generator of claim 32, further comprising: a low pass filter configured to receive the sample and hold signal and generate a filter signal based on at least information associated with the sample and hold signal a duty cycle detection and counter element configured to receive the modulated signal, detect a duty cycle of the modulated signal, and generate a sample enable signal based on at least information associated with the modulated signal, the modulated signal Associated with one or more switch time periods, the one or more switch time periods corresponding to one or more duty cycles; a compensation component configured to receive the modulation signal and based at least on the modulation signal The associated information generates a compensation signal; a first switch coupled to the compensation component; a second switch coupled to the low pass filter; wherein the duty cycle detection and counter element is further configured to: if the first duty cycle of the modulation signal corresponding to the first switch time course Generating the sampling enable signal of the first logic level when greater than the duty cycle threshold; and if the second duty cycle of the modulation signal corresponding to the second switching time period is less than the duty cycle threshold, Generating a sampling enable signal of a second logic level, wherein the second switching time period is a plurality of consecutive switching time courses; wherein: the first switch is configured to respond to the first logic power The sampling enable signal is closed to output the compensation signal as the threshold signal; and the second switch is configured to be responsive to the sampling enable signal of the second logic level Closing to output the filter signal as the threshold signal. 如申請專利範圍第37項所述之信號生成器，其中，所述占空比檢測和計數器元件包括：占空比檢測器，被配置為檢測所述調製信號的占空比；以及計數器元件，被配置為至少基於與所述調製信號相關聯的資訊生成所述採樣使能信號。 The signal generator of claim 37, wherein the duty cycle detecting and counter element comprises: a duty cycle detector configured to detect a duty cycle of the modulated signal; and a counter element, It is configured to generate the sample enable signal based on at least information associated with the modulated signal. 如申請專利範圍第37項所述之信號生成器，其中，所述補償元件還被配置為：至少基於與所述調製信號的第三占空比相關聯的資訊確定第一閾值信號值，所述第三占空比對應於第三開關時程，所述第三開關時程包括導通時間和關斷時間；在所述導通時間的開始處將時間設為零；以及如果該時間滿足一個或多個預定條件，則生成所述補償信號以使得所述補償信號的大小隨著時間的增長從所確定的第一閾值信號值增大。 The signal generator of claim 37, wherein the compensation component is further configured to: determine a first threshold signal value based on at least information associated with a third duty cycle of the modulation signal, The third duty ratio corresponds to a third switching time period, the third switching time period including an on time and an off time; setting the time to zero at the beginning of the on time; and if the time satisfies one or The plurality of predetermined conditions generate the compensation signal such that the magnitude of the compensation signal increases from the determined first threshold signal value over time. 如申請專利範圍第26項所述之信號生成器，其中，所述斜坡信號生成器包括電容器，該電容器被配置為回應於處於第一邏輯電平的所述調製信號而被充電並且輸出所述斜坡信號。 The signal generator of claim 26, wherein the ramp signal generator comprises a capacitor configured to be charged in response to the modulation signal at a first logic level and outputting the Ramp signal. 如申請專利範圍第40項所述之信號生成器，其中，所述斜坡信號生成器還包括： 第一比較器，被配置為接收所述斜坡信號和第一參考信號並且至少基於與所述斜坡信號和所述第一參考信號相關聯的資訊生成第一比較信號；以及第二比較器，被配置為接收所述斜坡信號和第二參考信號並且至少基於與所述斜坡信號和所述第二參考信號相關聯的資訊生成第二比較信號；其中，所述第一比較器還被配置為：如果所述斜坡信號的大小大於所述第一參考信號，則輸出第二邏輯電平的所述第一比較信號；如果所述斜坡信號的大小小於所述第一參考信號，則輸出第三邏輯電平的所述第一比較信號；其中，所述第二比較器還被配置為：如果所述斜坡信號的大小大於所述第二參考信號，則輸出第三邏輯電平的所述第二比較信號；如果所述斜坡信號的大小小於所述第二參考信號，則輸出第二邏輯電平的所述第二比較信號。 The signal generator of claim 40, wherein the ramp signal generator further comprises: a first comparator configured to receive the ramp signal and a first reference signal and generate a first comparison signal based on at least information associated with the ramp signal and the first reference signal; and a second comparator Configuring to receive the ramp signal and the second reference signal and generate a second comparison signal based on at least information associated with the ramp signal and the second reference signal; wherein the first comparator is further configured to: Outputting the first comparison signal of the second logic level if the magnitude of the ramp signal is greater than the first reference signal; outputting the third logic if the magnitude of the ramp signal is less than the first reference signal a first comparison signal of a level; wherein the second comparator is further configured to: output the second of the third logic level if the magnitude of the ramp signal is greater than the second reference signal Comparing the signal; if the magnitude of the ramp signal is less than the second reference signal, outputting the second comparison signal of the second logic level. 如申請專利範圍第41項所述之信號生成器，其中，所述斜坡信號生成器還包括：第一開關，被配置為回應於與所述調製信號和所述第一比較信號相關聯的第一開關信號而閉合和斷開，所述第一開關被耦合到所述電容器；第二開關，被配置為回應於與所述第二比較信號相關聯的第二開關信號而閉合和斷開，所述第二開關被耦合到所述電容器；其中，所述電容器還被配置為當所述第一開關閉合且所述第二開關斷開時被充電，並且當所述第一開關斷開且所述第二開關閉合時被放電。 The signal generator of claim 41, wherein the ramp signal generator further comprises: a first switch configured to respond to a first phase associated with the modulation signal and the first comparison signal a switch signal is closed and opened, the first switch is coupled to the capacitor; and a second switch is configured to close and open in response to a second switch signal associated with the second comparison signal, The second switch is coupled to the capacitor; wherein the capacitor is further configured to be charged when the first switch is closed and the second switch is open, and when the first switch is open and The second switch is discharged when it is closed. 如申請專利範圍第26項所述之信號生成器，還包括：閾值信號生成器，被配置為接收所述採樣和保持信號並且至少基於與所述採樣和保持信號相關聯的資訊生成閾值信號，所述調製信號與一個或多個第一開關時程以及在所述一個或多個第一開關時程之後的第二開關時程相關聯，所述一個或多個第一開關時程對應於一個或多個第一占空比，所述第二開關時程包括導通時間和關斷時間；其中，所述閾值信號生成器還被配置為： 至少基於與所述一個或多個第一占空比相關聯的資訊確定第一閾值信號值；在所述導通時間的開始處將時間設為零；以及如果該時間滿足一個或多個第一預定條件，則生成所述閾值信號以使得所述閾值信號的大小隨著時間的增長從所確定的第一閾值信號值減小。 The signal generator of claim 26, further comprising: a threshold signal generator configured to receive the sample and hold signal and generate a threshold signal based on at least information associated with the sample and hold signal, The modulation signal is associated with one or more first switch time periods and a second switch time history after the one or more first switch time periods, the one or more first switch time periods corresponding to One or more first duty cycles, the second switch time history including an on time and an off time; wherein the threshold signal generator is further configured to: Determining a first threshold signal value based at least on information associated with the one or more first duty cycles; setting a time to zero at the beginning of the on time; and if the time satisfies one or more first The predetermined condition is generated, the threshold signal is generated such that the magnitude of the threshold signal decreases from the determined first threshold signal value over time. 如申請專利範圍第26項所述之信號生成器，還包括：占空比檢測和信號生成器，被配置為接收所述調製信號和所述採樣和保持信號，並且至少基於與所述調製信號和所述採樣和保持信號相關聯的資訊生成閾值信號，所述調製信號與一個或多個第一開關時程以及在所述一個或多個第一開關時程之後的第二開關時程相關聯，所述一個或多個第一開關時程對應於一個或多個第一占空比，所述第二開關時程包括導通時間和關斷時間；其中，所述占空比檢測和信號生成器還被配置為，在所述第二開關時程中，至少基於與所述一個或多個第一占空比相關聯的資訊確定第一閾值信號值；在所述導通時間的開始處將時間設為零；如果該時間滿足一個或多個第一預定條件，則生成等於所確定的第一閾值信號值的所述閾值信號，以使得所述閾值信號作為時間的函數在大小上恒定；以及如果該時間滿足一個或多個第二預定條件，則生成所述閾值信號，以使得所述閾值信號的大小隨著時間的增長而減小。 The signal generator of claim 26, further comprising: a duty cycle detection and signal generator configured to receive the modulation signal and the sample and hold signal, and based at least on the modulation signal Generating a threshold signal with information associated with the sample and hold signal, the modulated signal being associated with one or more first switch time periods and a second switch time history after the one or more first switch time periods The one or more first switch time periods correspond to one or more first duty cycles, and the second switch time history includes an on time and an off time; wherein the duty cycle detection and signal The generator is further configured to determine a first threshold signal value based on at least information associated with the one or more first duty cycles in the second switching time course; at the beginning of the on time Setting the time to zero; if the time satisfies one or more first predetermined conditions, generating the threshold signal equal to the determined first threshold signal value such that the threshold signal is large as a function of time A constant; and if the second time or more satisfies a predetermined condition, generating a threshold signal, such that the size of the threshold signal decreases with increasing time. 如申請專利範圍第44項所述之信號生成器，其中，所述占空比檢測和信號生成器包括：占空比檢測器，被配置為接收所述調製信號並且至少基於與所述調製信號相關聯的資訊生成檢測信號；以及閾值信號生成器，被配置為接收所述檢測信號並且至少基於與所述檢測信號相關聯的資訊輸出所述閾值信號。 The signal generator of claim 44, wherein the duty cycle detection and signal generator comprises: a duty cycle detector configured to receive the modulation signal and based at least on the modulation signal The associated information generates a detection signal; and a threshold signal generator configured to receive the detection signal and output the threshold signal based on at least information associated with the detection signal. 一種用於保護電源轉換器的信號生成器，該信號生成器包括： 調製和驅動元件，被配置為生成調製信號以向開關輸出驅動信號從而影響流經電源轉換器的初級繞組的初級電流；斜坡信號生成器，被配置為接收所述調製信號並且至少基於與所述調製信號相關聯的資訊生成斜坡信號；採樣和保持元件，被配置為接收所述斜坡信號和所述調製信號，並且回應於所述調製信號輸出與所述斜坡信號的大小相關聯的採樣和保持信號；濾波器信號生成器，被配置為接收所述調製信號並且至少基於與所述調製信號相關聯的資訊生成濾波器信號；以及低通濾波器，被配置為接收所述濾波器信號和所述採樣和保持信號並且回應於所述濾波器信號，至少基於與所述採樣和保持信號相關聯的資訊生成第一信號。 A signal generator for protecting a power converter, the signal generator comprising: a modulation and drive component configured to generate a modulation signal to output a drive signal to the switch to affect a primary current flowing through a primary winding of the power converter; a ramp signal generator configured to receive the modulation signal and based at least on The information associated with the modulated signal generates a ramp signal; a sample and hold element configured to receive the ramp signal and the modulated signal, and in response to the modulated signal output sampling and holding associated with a magnitude of the ramp signal a signal; a filter signal generator configured to receive the modulated signal and generate a filter signal based at least on information associated with the modulated signal; and a low pass filter configured to receive the filter signal and The sample and hold signal is responsive to the filter signal and the first signal is generated based on at least information associated with the sample and hold signal. 如申請專利範圍第46項所述之信號生成器，其中，所述調製信號是所述驅動信號。 The signal generator of claim 46, wherein the modulation signal is the drive signal. 如申請專利範圍第46項所述之信號生成器，其中，所述調製信號不是所述驅動信號。 The signal generator of claim 46, wherein the modulation signal is not the drive signal. 如申請專利範圍第46項所述之信號生成器，其中，所述採樣和保持元件與所述低通濾波器共用至少一個電容器。 The signal generator of claim 46, wherein the sample and hold element shares at least one capacitor with the low pass filter. 如申請專利範圍第46項所述之信號生成器，其中，所述調製和驅動元件包括：調製元件，被配置為生成所述調製信號；以及柵極驅動元件，被配置為接收所述調製信號並且至少基於與所述調製信號相關聯的資訊輸出所述驅動信號。 The signal generator of claim 46, wherein the modulation and drive element comprises: a modulation element configured to generate the modulation signal; and a gate drive element configured to receive the modulation signal And outputting the drive signal based at least on information associated with the modulated signal. 如申請專利範圍第46項所述之信號生成器，還包括比較器，被配置為接收所述第一信號作為閾值信號以及與所述初級電流相關聯的電流感測信號，並且至少基於與所述採樣和保持信號以及所述電流感測信號相關聯的資訊向所述調製和驅動元件輸出比較信號。 The signal generator of claim 46, further comprising a comparator configured to receive the first signal as a threshold signal and a current sensing signal associated with the primary current, and based at least on The sample and hold signals and the information associated with the current sense signals output a comparison signal to the modulation and drive elements. 如申請專利範圍第46項所述之信號生成器，其中，所述採樣和保持組件包括：第一開關，被配置為回應於所述採樣信號而閉合和斷開；以及 第一電容器，被配置為當所述第一開關閉合時回應於所述斜坡信號而被充電。 The signal generator of claim 46, wherein the sample and hold component comprises: a first switch configured to close and open in response to the sampling signal; The first capacitor is configured to be charged in response to the ramp signal when the first switch is closed. 如申請專利範圍第52項所述之信號生成器，其中，所述低通濾波器包括：第二開關，被配置為回應於所述濾波器信號而閉合和斷開；以及第二電容器，被配置為當所述第二開關閉合時被充電。 The signal generator of claim 52, wherein the low pass filter comprises: a second switch configured to close and open in response to the filter signal; and a second capacitor It is configured to be charged when the second switch is closed. 如申請專利範圍第46項所述之信號生成器，其中，所述斜坡信號生成器包括電容器，該電容器被配置為回應於為第一邏輯電平的所述調製信號而被充電並且輸出所述斜坡信號。 The signal generator of claim 46, wherein the ramp signal generator comprises a capacitor configured to be charged in response to the modulation signal being a first logic level and outputting the Ramp signal. 如申請專利範圍第54項所述之信號生成器，其中，所述斜坡信號生成器還包括：第一比較器，被配置為接收所述斜坡信號和第一參考信號並且至少基於與所述斜坡信號和所述第一參考信號相關聯的資訊生成第一比較信號；以及第二比較器，被配置為接收所述斜坡信號和第二參考信號並且至少基於與所述斜坡信號和所述第二參考信號相關聯的資訊生成第二比較信號；其中，所述第一比較器還被配置為：如果所述斜坡信號的大小大於所述第一參考信號，則輸出第二邏輯電平的所述第一比較信號；如果所述斜坡信號的大小小於所述第一參考信號，則輸出第三邏輯電平的所述第一比較信號；其中，所述第二比較器還被配置為：如果所述斜坡信號的大小大於所述第二參考信號，則輸出所述第三邏輯電平的所述第二比較信號；並且如果所述斜坡信號的大小小於所述第二參考信號，則輸出所述第二邏輯電平的所述第二比較信號。 The signal generator of claim 54, wherein the ramp signal generator further comprises: a first comparator configured to receive the ramp signal and the first reference signal and based at least on the slope Generating a first comparison signal with information associated with the first reference signal; and a second comparator configured to receive the ramp signal and the second reference signal and based at least on the ramp signal and the second Generating a second comparison signal with information associated with the reference signal; wherein the first comparator is further configured to: output the second logic level if the magnitude of the ramp signal is greater than the first reference signal a first comparison signal; if the size of the ramp signal is smaller than the first reference signal, outputting the first comparison signal of a third logic level; wherein the second comparator is further configured to: if The magnitude of the ramp signal being greater than the second reference signal, outputting the second comparison signal of the third logic level; and if the magnitude of the ramp signal is less than Said second reference signal, outputting said second logic level of the second comparison signal. 如申請專利範圍第55項所述之信號生成器，其中，所述斜坡信號生成器還包括：第一開關，被配置為回應於與所述調製信號和所述第一比較信號相關聯的第一開關信號而閉合和斷開，所述第一開關被耦合到所述電容器； 第二開關，被配置為回應於與所述第二比較信號相關聯的第二開關信號而閉合和斷開，所述第二開關被耦合到所述電容器；其中，所述電容器被配置為當所述第一開關閉合且所述第二開關斷開時被充電，並且當所述第一開關斷開且所述第二開關閉合時被放電。 The signal generator of claim 55, wherein the ramp signal generator further comprises: a first switch configured to be responsive to a first associated with the modulated signal and the first comparison signal a switching signal to close and open, the first switch being coupled to the capacitor; a second switch configured to close and open in response to a second switching signal associated with the second comparison signal, the second switch being coupled to the capacitor; wherein the capacitor is configured to be The first switch is closed and the second switch is charged when it is off, and is discharged when the first switch is open and the second switch is closed. 如申請專利範圍第46項所述之信號生成器，其中，所述調製信號是脈寬調製信號。 The signal generator of claim 46, wherein the modulated signal is a pulse width modulated signal. 如申請專利範圍第46項所述之信號生成器，其中，所述調製和驅動元件包括：調製元件，被配置為生成所述調製信號；以及柵極驅動元件，被配置為接收所述調製信號並且至少基於與所述調製信號相關聯的資訊輸出所述驅動信號。 The signal generator of claim 46, wherein the modulation and drive element comprises: a modulation element configured to generate the modulation signal; and a gate drive element configured to receive the modulation signal And outputting the drive signal based at least on information associated with the modulated signal. 如申請專利範圍第46項所述之信號生成器，其中，所述調製和驅動元件包括：調製元件，被配置為生成第一信號；以及柵極驅動元件，被配置為接收所述第一信號，至少基於與所述第一信號相關聯的資訊生成所述調製信號，並且輸出所述調製信號作為所述驅動信號。 The signal generator of claim 46, wherein the modulation and driving component comprises: a modulating component configured to generate a first signal; and a gate driving component configured to receive the first signal Generating the modulated signal based on at least information associated with the first signal and outputting the modulated signal as the drive signal. 如申請專利範圍第46項所述之信號生成器，還包括：占空比檢測和計數器元件，被配置為接收所述調製信號，檢測所述調製信號的占空比，並且至少基於與所述調製信號相關聯的資訊生成採樣使能信號，所述調製信號與一個或多個開關時程相關聯，所述一個或多個開關時程對應於一個或多個占空比；補償元件，被配置為接收所述調製信號並且至少基於與所述調製信號相關聯的資訊生成補償信號；第一開關，被耦合到所述補償元件；以及第二開關，被耦合到所述低通濾波器；其中，所述占空比檢測和計數器元件還被配置為：如果與第一開關時程相對應的所述調製信號的第一占空比大於占空比閾值，則生成第一邏輯電平的所述採樣使能信號；以及如果與第二開關時程相對應的所述調製信號的第二占空比小於所 述占空比閾值，則生成第二邏輯電平的所述採樣使能信號，所述第二開關時程為多個連續的開關時程；其中：所述第一開關被配置為，響應於所述第一邏輯電平的所述採樣使能信號而閉合，以輸出所述補償信號作為所述閾值信號；以及所述第二開關被配置為，響應於所述第二邏輯電平的所述採樣使能信號而閉合，以輸出所述第一信號作為所述閾值信號。 The signal generator of claim 46, further comprising: a duty cycle detecting and counter element configured to receive the modulated signal, detect a duty cycle of the modulated signal, and based at least on The information associated with the modulated signal generates a sample enable signal, the modulated signal being associated with one or more switch time periods, the one or more switch time periods corresponding to one or more duty cycles; the compensation component being Configuring to receive the modulated signal and generate a compensation signal based at least on information associated with the modulated signal; a first switch coupled to the compensation element; and a second switch coupled to the low pass filter; Wherein the duty cycle detecting and counter element is further configured to generate a first logic level if a first duty cycle of the modulation signal corresponding to the first switch time course is greater than a duty cycle threshold The sampling enable signal; and if the second duty cycle of the modulation signal corresponding to the second switching time course is less than The duty cycle threshold is generated to generate the sampling enable signal of the second logic level, wherein the second switch time history is a plurality of consecutive switch time courses; wherein: the first switch is configured to respond to The sampling enable signal of the first logic level is closed to output the compensation signal as the threshold signal; and the second switch is configured to be responsive to the second logic level The sampling enable signal is closed to output the first signal as the threshold signal. 如申請專利範圍第60項所述之信號生成器，其中，所述占空比檢測和計數器元件包括：占空比檢測器，被配置為檢測所述調製信號的占空比；以及計數器元件，被配置為至少基於與所述調製信號相關聯的資訊生成所述採樣使能信號。 The signal generator of claim 60, wherein the duty cycle detecting and counter element comprises: a duty cycle detector configured to detect a duty cycle of the modulated signal; and a counter element, It is configured to generate the sample enable signal based on at least information associated with the modulated signal. 一種用於保護電源轉換器的方法，該方法包括：生成閾值信號；接收所述閾值信號以及電流感測信號，所述電流感測信號指示流經電源轉換器的初級繞組的初級電流的大小；至少基於與所述閾值信號和所述電流感測信號相關聯的資訊生成比較信號；至少接收所述比較信號；至少基於與所述比較信號相關聯的資訊生成驅動信號，所述驅動信號與一個或多個第一開關時程以及在所述一個或多個第一開關時程之後的第二開關時程相關聯，所述一個或多個第一開關時程對應於一個或多個第一占空比；以及向開關輸出所述驅動信號以影響所述初級電流；其中，用於生成閾值信號的處理包括：在所述第二開關時程中，至少基於與所述一個或多個占空比相關聯的資訊確定閾值信號值；以及生成與所確定的閾值信號值相等的所述閾值信號，所述閾值信號在所述第二開關時程中作為時間的函數在大小上是恒定的。 A method for protecting a power converter, the method comprising: generating a threshold signal; receiving the threshold signal and a current sensing signal, the current sensing signal indicating a magnitude of a primary current flowing through a primary winding of the power converter; Generating a comparison signal based on at least information associated with the threshold signal and the current sense signal; receiving at least the comparison signal; generating a drive signal based on at least information associated with the comparison signal, the drive signal Or a plurality of first switch schedules associated with the second switch schedule after the one or more first switch schedules, the one or more first switch schedules corresponding to one or more first a duty ratio; and outputting the drive signal to the switch to affect the primary current; wherein the processing for generating the threshold signal includes: in the second switch time history, based at least on the one or more The information associated with the space ratio determines a threshold signal value; and generates the threshold signal equal to the determined threshold signal value, the threshold signal being at the second Off time course is constant in magnitude as a function of time. 一種用於保護電源轉換器的方法，該方法包括： 生成閾值信號；接收所述閾值信號以及電流感測信號，所述電流感測信號指示流經電源轉換器的初級繞組的初級電流的大小；至少基於與所述閾值信號和所述電流感測信號相關聯的資訊生成比較信號；至少接收所述比較信號；至少基於與所述比較信號相關聯的資訊生成驅動信號，所述驅動信號與一個或多個第一開關時程以及在所述一個或多個第一開關時程之後的第二開關時程相關聯，所述一個或多個第一開關時程對應於一個或多個第一占空比，所述第二開關時程包括導通時間和關斷時間；以及向開關輸出所述驅動信號以影響所述初級電流；其中，用於生成閾值信號的處理包括：在所述第二開關時程中，至少基於與所述一個或多個占空比相關聯的資訊確定閾值信號值；在所述導通時間的開始處將時間設為零；如果該時間滿足一個或多個第一預定條件，則生成與所確定的閾值信號值相等的所述閾值信號，以使得所述閾值信號作為時間的函數在大小上是恒定的；以及如果該時間滿足一個或多個第二預定條件，則生成所述閾值信號以使得所述閾值信號的大小隨著時間的增長而減小。 A method for protecting a power converter, the method comprising: Generating a threshold signal; receiving the threshold signal and a current sensing signal, the current sensing signal indicating a magnitude of a primary current flowing through a primary winding of the power converter; based at least on the threshold signal and the current sensing signal Associated information generating a comparison signal; receiving at least the comparison signal; generating a drive signal based on at least information associated with the comparison signal, the drive signal being associated with one or more first switch schedules and at the one or Associated with a second switching time history after the plurality of first switching time periods, the one or more first switching time periods corresponding to one or more first duty cycles, the second switching time history including an on time And turning off the time; and outputting the drive signal to the switch to affect the primary current; wherein the processing for generating the threshold signal comprises: in the second switch time history, based at least on the one or more The duty cycle associated information determines a threshold signal value; the time is set to zero at the beginning of the on time; if the time satisfies one or more first predetermined conditions Generating the threshold signal equal to the determined threshold signal value such that the threshold signal is constant in magnitude as a function of time; and if the time satisfies one or more second predetermined conditions, generating The threshold signal is described such that the magnitude of the threshold signal decreases over time. 一種用於保護電源轉換器的方法，該方法包括：生成閾值信號；接收所述閾值信號以及電流感測信號，所述電流感測信號指示流經電源轉換器的初級繞組的初級電流的大小；至少基於與所述閾值信號和所述電流感測信號相關聯的資訊生成比較信號；至少接收所述比較信號；至少基於與所述比較信號相關聯的資訊生成驅動信號，所述驅動信號與一個或多個第一開關時程以及在所述一個或多個第一開關時程之後的第二開關時程相關聯，所述一個或多個第一開關時程對應於一個或多個第一 占空比，所述第二開關時程包括導通時間和關斷時間；以及向開關輸出所述驅動信號以影響所述初級電流；其中，用於生成閾值信號的處理包括：在所述第二開關時程中，至少基於與所述一個或多個占空比相關聯的資訊確定閾值信號值；在所述導通時間的開始處將時間設為零；以及如果該時間滿足一個或多個預定條件，則生成所述閾值信號以使得所述閾值信號的大小隨著時間的增長從所確定的閾值信號值減小。 A method for protecting a power converter, the method comprising: generating a threshold signal; receiving the threshold signal and a current sensing signal, the current sensing signal indicating a magnitude of a primary current flowing through a primary winding of the power converter; Generating a comparison signal based on at least information associated with the threshold signal and the current sense signal; receiving at least the comparison signal; generating a drive signal based on at least information associated with the comparison signal, the drive signal Or a plurality of first switch schedules associated with the second switch schedule after the one or more first switch schedules, the one or more first switch schedules corresponding to one or more first a duty cycle, the second switching time history including an on time and an off time; and outputting the driving signal to the switch to affect the primary current; wherein the processing for generating the threshold signal includes: at the second Determining, in a switch duration, a threshold signal value based at least on information associated with the one or more duty cycles; setting a time to zero at the beginning of the on time; and if the time satisfies one or more predetermined Condition, the threshold signal is generated such that the magnitude of the threshold signal decreases from the determined threshold signal value over time. 一種用於保護電源轉換器的方法，該方法包括：生成閾值信號；接收所述閾值信號以及電流感測信號，所述電流感測信號指示流經電源轉換器的初級繞組的初級電流的大小；至少基於與所述閾值信號和所述電流感測信號相關聯的資訊生成比較信號；至少接收所述比較信號；至少基於與所述比較信號相關聯的資訊生成驅動信號，所述驅動信號與多個開關時程相關聯，所述多個開關時程的每個包括導通時間和關斷時間；以及向開關輸出所述驅動信號以影響所述初級電流；其中，用於生成閾值信號的處理包括：在所述多個開關時程的每個中，在所述導通時間的開始處將時間設為零；如果該時間滿足一個或多個第一預定條件，則生成所述閾值信號，以使得所述閾值信號的大小隨著時間的增長而增大；以及如果該時間滿足一個或多個第二預定條件，則生成所述閾值信號以使得所述閾值信號的大小隨著時間的增長而減小。 A method for protecting a power converter, the method comprising: generating a threshold signal; receiving the threshold signal and a current sensing signal, the current sensing signal indicating a magnitude of a primary current flowing through a primary winding of the power converter; Generating a comparison signal based on at least information associated with the threshold signal and the current sense signal; receiving at least the comparison signal; generating a drive signal based on at least information associated with the comparison signal, the drive signal Associated with a switch time history, each of the plurality of switch time periods including an on time and an off time; and outputting the drive signal to the switch to affect the primary current; wherein the processing for generating the threshold signal includes : in each of the plurality of switch time periods, setting the time to zero at the beginning of the on time; if the time satisfies one or more first predetermined conditions, generating the threshold signal such that The magnitude of the threshold signal increases with time; and if the time satisfies one or more second predetermined conditions, then the Size threshold signal such that the threshold signal decreases with increasing time. 一種用於保護電源轉換器的信號的方法，該方法包括：生成調製信號以向開關輸出驅動信號從而影響流經電源轉換器的初級繞組的初級電流；接收所述調製信號；處理與所述調製信號相關聯的資訊； 至少基於與所述調製信號相關聯的資訊生成斜坡信號；回應於所述調製信號的下降沿而生成包含脈衝的採樣信號；接收所述採樣信號和所述斜坡信號；以及輸出與所述採樣信號的所述脈衝相應的、與所述斜坡信號的大小相關聯的採樣和保持信號。 A method for protecting a signal of a power converter, the method comprising: generating a modulated signal to output a drive signal to a switch to affect a primary current flowing through a primary winding of the power converter; receiving the modulated signal; processing and the modulating Information associated with the signal; Generating a ramp signal based on at least information associated with the modulated signal; generating a sampled signal comprising a pulse in response to a falling edge of the modulated signal; receiving the sampled signal and the ramped signal; and outputting the sampled signal The pulse and the sample and hold signals associated with the magnitude of the ramp signal. 一種用於保護電源轉換器的信號的方法，該方法包括：生成調製信號以向開關輸出驅動信號從而影響流經電源轉換器的初級繞組的初級電流；接收所述調製信號；處理與所述調製信號相關聯的資訊；至少基於與所述調製信號相關聯的資訊生成斜坡信號；至少基於與所述調製信號相關聯的資訊生成濾波器信號；接收所述斜坡信號和所述調製信號；回應於所述調製信號輸出與所述斜坡信號的大小相關聯的採樣和保持信號；接收所述濾波器信號以及所述採樣和保持信號；以及回應於所述濾波器信號，至少基於與所述採樣和保持信號相關聯的資訊生成第一信號。 A method for protecting a signal of a power converter, the method comprising: generating a modulated signal to output a drive signal to a switch to affect a primary current flowing through a primary winding of the power converter; receiving the modulated signal; processing and the modulating Information associated with the signal; generating a ramp signal based at least on information associated with the modulated signal; generating a filter signal based on at least information associated with the modulated signal; receiving the ramp signal and the modulated signal; The modulated signal outputs a sample and hold signal associated with a magnitude of the ramp signal; receiving the filter signal and the sample and hold signal; and responsive to the filter signal, based at least on the sample sum The information associated with the hold signal generates a first signal.
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