TW201426928A - 具有在封裝間之電絕緣材料之層疊封裝（ＰｏＰ） - Google Patents

具有在封裝間之電絕緣材料之層疊封裝（ＰｏＰ） Download PDF

Info

Publication number
TW201426928A
TW201426928A TW102134874A TW102134874A TW201426928A TW 201426928 A TW201426928 A TW 201426928A TW 102134874 A TW102134874 A TW 102134874A TW 102134874 A TW102134874 A TW 102134874A TW 201426928 A TW201426928 A TW 201426928A
Authority
TW
Taiwan
Prior art keywords
package
electrically insulating
insulating material
substrate
terminals
Prior art date
Application number
TW102134874A
Other languages
English (en)
Inventor
Jie-Hua Zhao
yi-zhang Yang
Jun Zhai
Chih-Ming Chung
Original Assignee
Apple Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Apple Inc filed Critical Apple Inc
Publication of TW201426928A publication Critical patent/TW201426928A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/37—Effects of the manufacturing process
    • H01L2924/37001—Yield
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P80/00—Climate change mitigation technologies for sector-wide applications
    • Y02P80/30—Reducing waste in manufacturing processes; Calculations of released waste quantities

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

本發明係關於一種層疊封裝，其包括耦接至頂部封裝之底部封裝。使用位於底部封裝之上表面與頂部封裝之下表面之間的電絕緣材料將該底部封裝之頂部上的端子耦接至該頂部封裝之底部上的端子。在加熱封裝的同時施加力以使該等封裝接合在一起之製程期間耦接底部封裝與頂部封裝。

Description

具有在封裝間之電絕緣材料之層疊封裝(PoP)
本發明係關於半導體封裝及封裝半導體器件之方法。更特定言之，本發明係關於在封裝間使用電絕緣材料之層疊封裝(package-on-package，PoP)及用以耦接該等封裝之熱壓接合。
隨著在半導體行業中持續需要較低成本、較高效能、增加之積體電路密度及增加之封裝密度，層疊封裝(「PoP」)技術已變得日益普及。隨著對愈來愈小之封裝的推動增加，晶粒與封裝之整合(例如「預堆疊」或系統單晶片(「system on a chip，SoC」)技術與記憶體技術之整合)可獲得較薄封裝。該預堆疊已成為薄及細間距之PoP封裝之關鍵組件。
薄及細間距之PoP封裝所產生之問題為當PoP封裝中之頂部封裝或底部封裝上之端子(例如球，諸如焊球)之間的間距減少時可能發生翹曲。在封裝中使用薄基板或無核心基板(coreless substrate)可能進一步增加PoP結構中之翹曲問題。由於所用材料之差異及/或該等材料之結構差異，PoP結構中之頂部封裝及底部封裝可具有不同翹曲行為。翹曲行為之差異可由引起封裝以不同速率膨脹/收縮之用於封裝之材料的特徵差異所造成。
頂部封裝與底部封裝之間的翹曲行為差異可引起耦接封裝之焊 接點(例如頂部封裝上之焊球與底部封裝上之平台墊(landing pad)之間的接點)的良率損失。由於對頂部封裝及底部封裝設置嚴格翹曲規範，因此大部分之PoP結構可能被丟棄(棄去)。棄去之PoP結構造成預堆疊良率較低、材料浪費及製造成本增加。
在某些實施例中，PoP封裝包括底部封裝及頂部封裝。底部封裝可包括基板，其具有至少部分覆蓋基板之上表面之囊封體。晶粒可耦接至基板之上表面。頂部封裝可包括基板，其具有至少部分覆蓋基板之上表面之囊封體。一或多個晶粒可耦接至基板之上表面且囊封於囊封體中。
當底部封裝耦接至頂部封裝時，底部封裝基板之頂部上的端子耦接(例如連接)至頂部封裝基板之底部上的端子。電絕緣材料位於底部封裝之上表面與頂部封裝之下表面之間。電絕緣材料藉由將封裝機械耦接或接合在一起而在底部封裝與頂部封裝之間提供加強，且抑制封裝之翹曲。
在某些實施例中，使用熱壓接合製程耦接底部封裝與頂部封裝。熱壓接合製程在加熱封裝的同時施加力以使封裝接合在一起。在熱壓接合製程期間，端子之材料(例如焊料)回流且在端子之間形成電連接且電絕緣材料固化。電絕緣材料固化使得在底部封裝之上表面與頂部封裝之下表面之間不存在氣隙。
100‧‧‧封裝/PoP封裝
102‧‧‧底部封裝
104‧‧‧頂部封裝
106‧‧‧基板
108‧‧‧囊封體
110‧‧‧晶粒
112‧‧‧端子
114‧‧‧端子
116‧‧‧端子
118‧‧‧基板
120‧‧‧囊封體
122‧‧‧晶粒
124‧‧‧焊線
126‧‧‧端子
128‧‧‧氣隙
150‧‧‧電絕緣材料
152‧‧‧箭頭
200‧‧‧PoP封裝/封裝
當結合隨附圖式時，藉由參考本發明之目前較佳但為說明性之實施例之以下詳細描述，將更充分地理解本發明之方法及裝置的特徵及優點，在該等圖式中：圖1A至圖1D描繪形成PoP封裝(「層疊封裝」)之製程流程之一項實例之步驟的剖面圖式。
圖2A至圖2D描繪形成PoP封裝之製程流程之一項實施例的剖面圖式。
雖然本發明容易發生各種修改及替代形式，但其特定實施例以舉例方式在圖式中展示且將在本文中詳細描述。該等圖式可能不按比例。應瞭解，該等圖式及其詳細描述不欲將本發明限於所揭示之特定形式，而與此對比，本發明欲涵蓋屬於如所附申請專利範圍所界定之本發明精神及範疇內的所有修改、等效物及替代物。
圖1A至圖1D描繪形成PoP封裝(「層疊封裝」)之製程流程之一項實例之步驟的剖面圖式。圖1A描繪底部封裝102之一項實施例的剖面圖式。底部封裝102包括基板106，其具有至少部分覆蓋基板之囊封體108。晶粒110可使用端子112(例如焊球)耦接(例如連接)至基板106且由囊封體108至少部分覆蓋。在一些實施例中，由囊封體108覆蓋晶粒110。在某些實施例中，晶粒110為處理器或邏輯晶粒，或晶粒110為系統單晶片(「SoC」)。晶粒110可為例如半導體晶片晶粒，諸如覆晶晶粒。
端子114可耦接至基板106之上(頂部)表面或在其上。端子114可為例如經焊料或錫(Sn)塗佈之平台墊。端子116(例如焊球)可耦接至基板106之下(底部)表面或在其上。端子116可用於將基板106及封裝100耦接至主板或印刷電路板(PCB)。
圖1B描繪使頂部封裝104朝向底部封裝102之一項實施例的剖面圖式。頂部封裝104包括基板118，其具有覆蓋基板之上(頂部)表面之囊封體120。在某些實施例中，一或多個晶粒122耦接至基板118且密封於囊封體120中。可使用例如一或多根焊線124將晶粒122耦接(例如連接)至基板118。晶粒122可為例如半導體晶片，諸如絲焊晶粒或覆晶晶粒。在某些實施例中，晶粒122為記憶體晶粒。
端子126耦接至基板106之下(底部)表面。端子126可為例如焊球。如圖1B中所示，當封裝接合在一起時，頂部封裝104上之端子126與底部封裝102上之相應端子114對準。
圖1C描繪藉由使端子114與端子126接觸將底部封裝102耦接至頂部封裝104之一項實施例的剖面圖式。在使端子126與端子114接觸之後，可向頂部封裝104及底部封裝102施加熱。可例如使用焊料回流烘箱施加熱(例如將封裝置放於焊料回流烘箱中並加熱)。可將封裝加熱至使端子114及端子126中之材料熔融(焊料回流)之溫度(例如焊料熔融溫度)。可在焊料回流製程期間在端子126與114之間施用焊接熔劑。通常，將封裝加熱至約220℃與約260℃之間的溫度(例如約240℃)。
所施加之熱使焊料熔融且蒸發焊接熔劑以形成PoP封裝100。隨後將PoP封裝100冷卻降溫至環境溫度。圖1D描繪在冷卻至環境溫度之後PoP封裝100之一項實施例的剖面圖式。PoP封裝100包括經端子114及端子126耦接之底部封裝102及頂部封裝104。為圖1D中所描繪之端子之間清晰起見，展示端子114與端子126之間的虛線。然而，端子114及端子126係由在熔融之後將實質上互混且在頂部封裝104與底部封裝102之間形成互混之接面的材料製成。
如圖1D中所示，PoP封裝100包括頂部封裝104與底部封裝102之間的氣隙128。如圖1D中所示，雖然在端子114及端子126中之材料熔融時頂部封裝104及底部封裝102向彼此更近地移動，但在封裝之間、尤其在頂部基板118與底部晶粒110之間仍保留有氣隙128。
如圖1A至圖1D中所示，底部封裝102及頂部封裝104可包括不同材料及/或不同結構。因此，底部封裝102及頂部封裝104可具有不同特徵(例如熱膨脹係數(「CTE」)及/或收縮率)。不同熱膨脹特徵可產生在使用PoP封裝期間底部封裝102及頂部封裝104中之不同翹曲行為。底部封裝102與頂部封裝104之間的此等翹曲行為差異可引起在預 堆疊(形成PoP)焊料回流製程期間相對焊接點之間的不連接(例如圖1D中之相應端子126與114之間的不連接)及/或鄰接焊接點之間的橋接(例如圖1D中之鄰接端子126或鄰接端子114之間的橋接)。此等問題可導致在預堆疊製程期間良率損失。
極端翹曲行為亦可隨時間推移而引起可靠性問題。舉例而言，在PoP封裝100之重複加熱/冷卻循環之後，114/126之連接焊接點可能失效。若基板106及/或基板118為相對較薄基板(例如厚度小於約400μm)及/或基板為無核心基板(例如僅由介電聚合物及微量銅製成之基板)，則底部封裝102及頂部封裝104中之翹曲問題可能增加。因此，對頂部封裝102及底部封裝104設置嚴格翹曲控制規範以避免PoP預堆疊之良率損失。除PoP之頂部封裝及底部封裝之嚴格翹曲規範以外，亦需要整體PoP封裝100(在PoP形成之後)之嚴格翹曲規範以確保PoP可焊接至主板或系統印刷電路板上。由於此等嚴格翹曲規範，因此可能棄去包括頂部封裝104、底部封裝102及PoP封裝100之許多封裝，此等封裝之棄去導致預堆疊及裝配良率較低及製造成本增加。
圖2A至圖2D描繪形成PoP封裝之製程流程之一項實施例的剖面圖式。圖2A描繪具有分配(沈積)至底部封裝之上表面上之電絕緣材料150之底部封裝102之一項實施例的剖面圖式。如上所述，底部封裝102可包括基板106，其具有至少部分覆蓋基板之囊封體108及使用端子112耦接至基板之晶粒110。端子114耦接至基板106之上(頂部)表面或在其上。端子114可為來自頂部封裝之端子的平台墊。舉例而言，端子114可為經焊料塗佈或經Sn塗佈之平台墊。
在一些實施例中，在材料150沈積於底部封裝之上表面上之前預加熱底部封裝102。舉例而言，可將底部封裝102預加熱至約150℃之溫度。在一些實施例中，在材料150沈積於底部封裝之上表面上之後加熱底部封裝102。
如圖2A中所示，電絕緣材料150實質上覆蓋底部封裝102上之端子114、晶粒110及囊封體108。材料150可為例如聚合物或環氧材料，諸如底部填充材料或不導電膏。舉例而言，材料150可為用於覆晶接合製程之底部填充材料，諸如快速固化底部填充材料或低剖面底部填充材料。通常，材料150為在用於端子114及端子126之材料之熔融溫度(例如焊料熔融溫度)下或低於熔融溫度下固化的電絕緣材料。
如圖2B中所示，在電絕緣材料150分配於底部封裝102上之後，使頂部封裝104朝向底部封裝。如上所述，頂部封裝104可包括基板118，其具有覆蓋基板之上(頂部)表面之囊封體120及一或多個耦接至基板且密封於囊封體中之晶粒122。端子126耦接至基板116之下(底部)表面。端子126可為例如焊球或銅(Cu)柱。
在一些實施例中，在頂部封裝104耦接至底部封裝102之前預加熱頂部封裝104。舉例而言，可將頂部封裝104預加熱至約150℃之溫度。在一些實施例中，在頂部封裝104耦接至底部封裝102之後預加熱頂部封裝104(例如一起預加熱該等封裝)。
如圖2B中所示，當封裝接合在一起時，頂部封裝104上之端子126與底部封裝102上之相應端子114對準。當頂部封裝104較接近底部封裝102時，電絕緣材料150分佈於頂部封裝與底部封裝之間的間隙中以及端子114及端子126周圍。在一些實施例中，在使封裝接合在一起之前，電絕緣材料150沈積於頂部封裝104之下表面上，而非(或另外)沈積於底部封裝102之上表面上。
圖2C描繪藉由使端子114與端子126接觸且使電絕緣材料150分佈於封裝間之間隙中將底部封裝102耦接至頂部封裝104之一項實施例的剖面圖式。在某些實施例中，在使端子126與端子114接觸之後，朝向底部封裝102施加力至頂部封裝104(如箭頭152所示)以使得該等封裝更近地接合在一起。亦可施加力至底部封裝104以使得該等封裝更近 地接合在一起(如箭頭152所示)。在一些實施例中，施加至底部封裝104之力用於平衡施加至頂部封裝102之力或對施加至頂部封裝102之力提供支撐。
當施加力以使封裝接合在一起時，可向底部封裝102及頂部封裝104兩者施加熱。在某些實施例中，實質上同時向封裝施加力及熱(例如在熱壓接合製程中施加力及熱以使封裝接合在一起)。施加之力與施加之熱的組合使電絕緣材料150分佈於封裝間之間隙中且使端子114及端子126中之材料回流(例如焊料回流)。當端子126為Cu柱時，作為焊料之端子114可在熱壓接合製程期間回流且與端子126形成電連接。
可使用諸如熱壓接合裝置(例如覆晶熱壓接合裝置)之裝置施加力及熱。覆晶熱壓接合裝置之一項實例為可購自Toray Engineering Co.,Ltd.(Tokyo,Japan)之FC3000覆晶接合機(Flip Chip Bonder)。在一些實施例中，用於熱壓接合之裝置亦可適用於在封裝之熱壓接合之前拾取頂部封裝104且將其置放至底部封裝102上(端子126與端子114對準)。
在某些實施例中，使封裝接合在一起所施加之力的量在約5 N(牛頓)與約500 N之間。在某些實施例中，在將封裝加熱至使端子114及/或端子126中之材料熔融之溫度(例如焊料熔融溫度)的同時施加力。在一些實施例中，將封裝加熱至高於約220℃、高於約240℃或高於約260℃之溫度。通常，將封裝加熱至恰高於端子114及端子126之材料之熔點的溫度。施加至封裝之力的量及封裝加熱溫度可視用於端子114及端子126之材料、電絕緣材料150之材料及/或用於底部封裝102或頂部封裝104之其他材料而變化。
在某些實施例中，當置放於底部封裝102及/或頂部封裝104上時，電絕緣材料150包括作為成分之焊接熔劑。因此，如上所述，在底部封裝102及頂部封裝104之熱壓接合期間，材料150可使焊料(例如端子114及/或端子126之材料)回流。材料150可在底部封裝102及頂部 封裝104之熱壓接合期間固化。在一些實施例中，對底部封裝102及頂部封裝104進行後固化加熱製程以充分固化電絕緣材料150。舉例而言，若熱壓接合製程未充分固化電絕緣材料150，則可進一步加熱底部封裝102及頂部封裝104以充分固化電絕緣材料。
在某些實施例中，底部封裝102及頂部封裝104之熱壓接合歷時約數秒(例如在約1秒與10秒之間)。當同時經受接合力(上文所述施加之力)且加熱至熔融溫度時，端子114及端子126中之材料可在數秒內回流(例如焊料回流)。材料150可在底部封裝102及頂部封裝104之熱壓接合期間快速固化(例如在數秒內)。材料150之快速固化及焊料回流所需之較短時間可使得使用熱壓接合製程之製程時間較短。底部封裝102及頂部封裝104之熱壓接合所需之時間可基於以下因素而變化：諸如(但不限於)端子114及/或端子126中之材料熔融所需之時間量及電絕緣材料150固化所需之時間量。底部封裝102及頂部封裝104之熱壓接合的較短製程時間提高對封裝進行預堆疊之產出量。
在熱壓接合步驟(或視情況選用之後固化製程)之後，使底部封裝102及頂部封裝104冷卻至環境溫度以形成PoP封裝(例如完成預堆疊製程)。圖2D描繪在冷卻底部封裝102及頂部封裝104之後在封裝間具有固化之電絕緣材料150之PoP封裝200之一項實施例的剖面圖式。PoP封裝200包括經端子114及端子126耦接之底部封裝102及頂部封裝104。為圖2D中所描繪之端子之間清晰起見，展示端子114與端子126之間的虛線。
在完成熱壓接合製程之後，端子116(例如焊球)可耦接至基板106之下(底部)表面或在其上。舉例而言，使用焊料回流加工可使PoP封裝200倒裝且將端子116耦接至基板106之底部表面。在熱壓接合之後將端子116置放於PoP封裝200上可向底部封裝102提供力或支撐(如圖2C中所示)以平衡熱壓接合製程期間頂部封裝102上之力。可在個別製 程(用於單個PoP封裝)中或在分批製程(在封裝基板帶材中具有多個PoP封裝)中將端子116耦接至基板106。端子116可用於將基板106及封裝200耦接至主板或系統印刷電路板(PCB)。在一些實施例中，使用不需要端子116作為焊球之平台柵格陣列(land grid array，LGA)製程將基板106耦接至主板或系統PCB。
如圖2D中所示，PoP封裝200包括在頂部封裝104與底部封裝102之間固化的電絕緣材料150。在熱壓接合製程期間，材料150流動且實質上填充底部封裝102之上表面與頂部封裝104之下表面之間的間隙。因此，在熱壓接合製程之後電絕緣材料150固化之後，電絕緣材料填充底部封裝102之上表面與頂部封裝104之下表面之間的間隙，使得在封裝之表面之間實質上無氣隙。在某些實施例中，電絕緣材料150將底部封裝102機械耦接或接合至頂部封裝104。
在某些實施例中，電絕緣材料150在底部封裝102與頂部封裝104之間提供加強且加強PoP封裝200。舉例而言，電絕緣材料150可藉由將底部封裝102與頂部封裝104機械耦接或接合在一起而加強該等封裝。由電絕緣材料150提供之加強使得PoP封裝200較堅固，且減少或消除在將PoP封裝焊接至主板或系統PCB上之回流期間發生翹曲。電絕緣材料150亦可改良PoP封裝200中之焊接點(例如圖2D中之端子114/126)的疲勞壽命。
由於在熱壓接合製程期間使用壓縮力，因此可在接合溫度下壓平底部封裝102及頂部封裝104。底部封裝102及頂部封裝104之此壓平可極大地放寬底部封裝與頂部封裝之翹曲規範。翹曲規範之放寬可減少棄去之頂部封裝及底部封裝之數目，增加預堆疊良率，且降低製造成本。另外，在形成PoP封裝200期間使用熱壓接合及電絕緣材料150(圖2D中所示)在環境溫度(室溫)下及在高於PoP封裝100(圖1D中所示)之溫度下在PoP封裝中提供較佳共面性。PoP封裝200中之較佳共面性 可減少將PoP封裝耦接至主板時的良率損失且在板級裝配下(例如在使多個封裝附接至主板時)提供較高良率。
在圖2A至圖2D中所描繪之形成PoP封裝200之製程流程中使用熱壓接合及電絕緣材料150亦消除對於使用回流烘箱進行焊料回流加工之需要。因為回流烘箱可為高成本設備，所以移除回流烘箱與其他PoP封裝相比可減少PoP封裝200之製造成本。
鑒於本說明書，本發明之各種態樣之進一步修改及替代性實施例將為熟習此項技術者顯而易知。因此，本說明書應理解為僅作為說明且僅為教示熟習此項技術者執行本發明之一般方式。應瞭解，本文中展示及描述之本發明形式應視為目前較佳之實施例。元件及材料可替代本文中說明及描述之元件及材料，部分且製程可顛倒，且可獨立地利用本發明之某些特徵，以上所有對於熟習此項技術者在具有本發明之本說明書之權益之後將顯而易知。在不脫離如以下申請專利範圍中所述之本發明精神及範疇的情況下，可對本文所述之元件作出改變。
102‧‧‧底部封裝
104‧‧‧頂部封裝
106‧‧‧基板
108‧‧‧囊封體
110‧‧‧晶粒
112‧‧‧端子
114‧‧‧端子
116‧‧‧端子
118‧‧‧基板
120‧‧‧囊封體
122‧‧‧晶粒
124‧‧‧焊線
126‧‧‧端子
150‧‧‧電絕緣材料
200‧‧‧PoP封裝/封裝

Claims (17)

  1. 一種半導體器件封裝總成，其包含：一頂部封裝，其包含在該頂部封裝之一下表面上之一或多個第一端子；一底部封裝，其包含在該底部封裝之一上表面上之一或多個第二端子，其中該等第二端子耦接至該頂部封裝上之相應第一端子；及一電絕緣材料，其位於該頂部封裝之該下表面與該底部封裝之該上表面之間；其中該頂部封裝與該底部封裝係使用一熱壓接合製程用該等封裝之間的該電絕緣材料耦接。
  2. 如請求項1之總成，其中該熱壓接合製程包含：在將該等封裝及該電絕緣材料加熱至一至少約220℃之溫度的同時施加力，以使該頂部封裝朝向該底部封裝。
  3. 如請求項1之總成，其中該電絕緣材料包含不導電膏或底部填充材料。
  4. 如請求項1之總成，其中該電絕緣材料實質上填充該底部封裝之該上表面與該頂部封裝之下表面之間的間隙。
  5. 如請求項1之總成，其中該電絕緣材料將該頂部封裝機械耦接至該底部封裝。
  6. 一種形成一層疊封裝總成之方法，其包含：提供一頂部封裝，在該頂部封裝之一下表面上具有一或多個第一端子；提供一底部封裝，在該底部封裝之一上表面上具有一或多個第二端子； 在該底部封裝之該上表面與該頂部封裝之該下表面之間提供一電絕緣材料；藉由使該等第一端子中之至少一些對準且耦接至相應第二端子而將該頂部封裝耦接至該底部封裝；及在將該等封裝及該電絕緣材料加熱至一至少約220℃之溫度的同時在一朝向該底部封裝之方向上向該頂部封裝提供一力。
  7. 如請求項6之方法，其進一步包含提供該電絕緣材料至該底部封裝之該上表面上。
  8. 如請求項6之方法，其進一步包含在耦接該等封裝之前將該頂部封裝及該底部封裝加熱至一至少約150℃之溫度。
  9. 如請求項6之方法，其中該電絕緣材料包含不導電膏或底部填充材料。
  10. 如請求項6之方法，其中該電絕緣材料在加熱至該至少約220℃之溫度之後固化。
  11. 如請求項6之方法，其中該頂部封裝包含一晶粒，其至少部分囊封於該底部封裝之該上表面上之一囊封體中。
  12. 如請求項6之方法，其進一步包含在將該等封裝及該電絕緣材料加熱至一至少約220℃之溫度的同時，藉由在該朝向該底部封裝之方向上向該頂部封裝提供該力，而用該電絕緣材料將該頂部封裝接合至該底部封裝。
  13. 一種半導體器件封裝總成，其包含：一第一基板，其具有至少部分覆蓋該第一基板之一上表面之一囊封體；一或多個第一端子，其耦接至該第一基板之該上表面；一晶粒，其耦接至該第一基板之該上表面，其中該晶粒至少部分囊封於該囊封體中； 一第二基板；一或多個第二端子，其耦接至該第二基板之一下表面；其中該第一基板上之該等第一端子中之至少一些耦接至該第二基板上之相應第二端子以耦接該等基板，在該等基板之間具有一間隙；及一電絕緣材料，其實質上填充該等基板之間的該間隙。
  14. 如請求項13之總成，其中該電絕緣材料至少部分覆蓋該囊封體之一上表面。
  15. 如請求項13之總成，其中在將該等基板及該電絕緣材料加熱至一至少約220℃之溫度的同時，藉由施加力以使該第一基板朝向該第二基板而用該等基板之間的該電絕緣材料，而將該第二基板之該下表面耦接至該第一基板之該上表面。
  16. 如請求項13之總成，其中該晶粒包含一處理器晶粒。
  17. 如請求項13之總成，其中該電絕緣材料將該第一基板接合至該第二基板。
TW102134874A 2012-09-26 2013-09-26 具有在封裝間之電絕緣材料之層疊封裝（ＰｏＰ） TW201426928A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/627,905 US8963311B2 (en) 2012-09-26 2012-09-26 PoP structure with electrically insulating material between packages

Publications (1)

Publication Number Publication Date
TW201426928A true TW201426928A (zh) 2014-07-01

Family

ID=49293924

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102134874A TW201426928A (zh) 2012-09-26 2013-09-26 具有在封裝間之電絕緣材料之層疊封裝（ＰｏＰ）

Country Status (3)

Country Link
US (2) US8963311B2 (zh)
TW (1) TW201426928A (zh)
WO (1) WO2014052273A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI692030B (zh) * 2015-11-17 2020-04-21 南韓商Ｎｅｐｅｓ股份有限公司 半導體封裝件及其製造方法

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9263377B2 (en) 2012-11-08 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. POP structures with dams encircling air gaps and methods for forming the same
US9202782B2 (en) * 2013-01-07 2015-12-01 Intel Corporation Embedded package in PCB build up
US9293404B2 (en) * 2013-01-23 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Pre-applying supporting materials between bonded package components
US9627325B2 (en) * 2013-03-06 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package alignment structure and method of forming same
US9576888B2 (en) * 2013-03-12 2017-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Package on-package joint structure with molding open bumps
KR102229202B1 (ko) * 2013-11-07 2021-03-17 삼성전자주식회사 트렌치 형태의 오프닝을 갖는 반도체 패키지 및 그 제조방법
US9368566B2 (en) * 2014-07-17 2016-06-14 Qualcomm Incorporated Package on package (PoP) integrated device comprising a capacitor in a substrate
US9484281B2 (en) * 2014-08-14 2016-11-01 Qualcomm Incorporated Systems and methods for thermal dissipation
US9478521B2 (en) * 2014-09-25 2016-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package Structure
KR102274742B1 (ko) * 2014-10-06 2021-07-07 삼성전자주식회사 패키지 온 패키지와 이를 포함하는 컴퓨팅 장치
US9875997B2 (en) * 2014-12-16 2018-01-23 Qualcomm Incorporated Low profile reinforced package-on-package semiconductor device
US9449953B1 (en) * 2015-10-08 2016-09-20 Inotera Memories, Inc. Package-on-package assembly and method for manufacturing the same
US10269720B2 (en) 2016-11-23 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out packaging
KR20190004964A (ko) * 2017-07-05 2019-01-15 삼성전자주식회사 반도체 패키지
US20200111765A1 (en) * 2018-10-09 2020-04-09 Medtronic, Inc. Electronic assembly and method of forming same
KR20210018577A (ko) 2019-08-05 2021-02-18 삼성전자주식회사 반도체 패키지 장치

Family Cites Families (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2833996B2 (ja) * 1994-05-25 1998-12-09 日本電気株式会社 フレキシブルフィルム及びこれを有する半導体装置
US6784023B2 (en) * 1996-05-20 2004-08-31 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US5766979A (en) * 1996-11-08 1998-06-16 W. L. Gore & Associates, Inc. Wafer level contact sheet and method of assembly
AU1040397A (en) * 1996-12-04 1998-06-29 Hitachi Limited Semiconductor device
US5861678A (en) * 1997-12-23 1999-01-19 Micron Technology, Inc. Method and system for attaching semiconductor dice to substrates
US6333209B1 (en) * 1999-04-29 2001-12-25 International Business Machines Corporation One step method for curing and joining BGA solder balls
US6555908B1 (en) * 2000-02-10 2003-04-29 Epic Technologies, Inc. Compliant, solderable input/output bump structures
JP2002289768A (ja) * 2000-07-17 2002-10-04 Rohm Co Ltd 半導体装置およびその製法
US6713880B2 (en) * 2001-02-07 2004-03-30 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for producing the same, and method for mounting semiconductor device
JP4045143B2 (ja) * 2002-02-18 2008-02-13 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド 配線膜間接続用部材の製造方法及び多層配線基板の製造方法
US20030170450A1 (en) 2002-03-05 2003-09-11 Stewart Steven L. Attachment of surface mount devices to printed circuit boards using a thermoplastic adhesive
US6798057B2 (en) * 2002-11-05 2004-09-28 Micron Technology, Inc. Thin stacked ball-grid array package
JP3912318B2 (ja) 2003-05-02 2007-05-09 セイコーエプソン株式会社 半導体装置の製造方法および電子デバイスの製造方法
US6919224B2 (en) * 2003-09-30 2005-07-19 Intel Corporation Modified chip attach process and apparatus
JP4204989B2 (ja) * 2004-01-30 2009-01-07 新光電気工業株式会社 半導体装置及びその製造方法
US7768795B2 (en) * 2004-09-08 2010-08-03 Panasonic Corporation Electronic circuit device, electronic device using the same, and method for manufacturing the same
US7528474B2 (en) 2005-05-31 2009-05-05 Stats Chippac Ltd. Stacked semiconductor package assembly having hollowed substrate
KR100609334B1 (ko) * 2005-06-13 2006-08-08 삼성전자주식회사 감광성 폴리머가 갭필된 적층 회로부재 및 그의 제조 방법
JP4556788B2 (ja) 2005-07-01 2010-10-06 パナソニック株式会社 多段電子部品の製造方法
JP2007281129A (ja) 2006-04-05 2007-10-25 Toshiba Corp 積層型半導体装置
US8581381B2 (en) * 2006-06-20 2013-11-12 Broadcom Corporation Integrated circuit (IC) package stacking and IC packages formed by same
US7700414B1 (en) * 2007-02-22 2010-04-20 Unisem (Mauritius) Holdings Limited Method of making flip-chip package with underfill
JP2009252916A (ja) 2008-04-04 2009-10-29 Nec Electronics Corp 多層配線基板、半導体パッケージ、および半導体パッケージの製造方法
JP5043743B2 (ja) 2008-04-18 2012-10-10 ラピスセミコンダクタ株式会社 半導体装置の製造方法
JP5366674B2 (ja) * 2008-06-27 2013-12-11 パナソニック株式会社 実装構造体および実装方法
US20100072600A1 (en) * 2008-09-22 2010-03-25 Texas Instrument Incorporated Fine-pitch oblong solder connections for stacking multi-chip packages
KR101198411B1 (ko) 2008-11-17 2012-11-07 삼성전기주식회사 패키지 온 패키지 기판
TWI499024B (zh) 2009-01-07 2015-09-01 Advanced Semiconductor Eng 堆疊式多封裝構造裝置、半導體封裝構造及其製造方法
JP5556072B2 (ja) 2009-01-07 2014-07-23 ソニー株式会社 半導体装置、その製造方法、ミリ波誘電体内伝送装置
JP2010272609A (ja) 2009-05-20 2010-12-02 Panasonic Corp 半導体装置及びその製造方法
KR101583354B1 (ko) 2009-06-01 2016-01-07 삼성전자주식회사 반도체 소자 패키지의 형성방법
US8034660B2 (en) * 2009-07-24 2011-10-11 Texas Instruments Incorporated PoP precursor with interposer for top package bond pad pitch compensation
TWI478257B (zh) 2009-08-06 2015-03-21 Htc Corp 封裝結構及封裝製程
US8035235B2 (en) 2009-09-15 2011-10-11 Stats Chippac Ltd. Integrated circuit packaging system with package-on-package and method of manufacture thereof
KR101624973B1 (ko) 2009-09-23 2016-05-30 삼성전자주식회사 패키지 온 패키지 타입의 반도체 패키지 및 그 제조방법
US8404518B2 (en) 2009-12-13 2013-03-26 Stats Chippac Ltd. Integrated circuit packaging system with package stacking and method of manufacture thereof
US8466567B2 (en) 2010-09-16 2013-06-18 Stats Chippac Ltd. Integrated circuit packaging system with stack interconnect and method of manufacture thereof
KR20120031697A (ko) 2010-09-27 2012-04-04 삼성전자주식회사 패키지 적층 구조 및 그 제조 방법
KR101711479B1 (ko) 2010-10-06 2017-03-03 삼성전자 주식회사 반도체 패키지 장치 및 그의 검사 시스템
KR101711045B1 (ko) 2010-12-02 2017-03-02 삼성전자 주식회사 적층 패키지 구조물
JP2012204631A (ja) * 2011-03-25 2012-10-22 Fujitsu Semiconductor Ltd 半導体装置、半導体装置の製造方法及び電子装置
US8409923B2 (en) 2011-06-15 2013-04-02 Stats Chippac Ltd. Integrated circuit packaging system with underfill and method of manufacture thereof
KR101867955B1 (ko) * 2012-04-13 2018-06-15 삼성전자주식회사 패키지 온 패키지 장치 및 이의 제조 방법
US8546932B1 (en) 2012-08-15 2013-10-01 Apple Inc. Thin substrate PoP structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI692030B (zh) * 2015-11-17 2020-04-21 南韓商Ｎｅｐｅｓ股份有限公司 半導體封裝件及其製造方法

Also Published As

Publication number Publication date
WO2014052273A1 (en) 2014-04-03
US20140084487A1 (en) 2014-03-27
US20150118795A1 (en) 2015-04-30
US8963311B2 (en) 2015-02-24
US9263426B2 (en) 2016-02-16

Similar Documents

Publication Publication Date Title
US9263426B2 (en) PoP structure with electrically insulating material between packages
US9312149B2 (en) Method for forming chip-on-wafer assembly
US8076232B2 (en) Semiconductor device and method of forming composite bump-on-lead interconnection
US8642393B1 (en) Package on package devices and methods of forming same
US8377745B2 (en) Method of forming a semiconductor device
US20150214207A1 (en) Chip stack, semiconductor devices having the same, and manufacturing methods for chip stack
US20110147945A1 (en) Semiconductor device capable of suppressing generation of cracks in semiconductor chip during manufacturing process
US10121774B2 (en) Method of manufacturing a semiconductor package
US20120077312A1 (en) Flip-chip bonding method to reduce voids in underfill material
US10867956B2 (en) Method of manufacturing a semiconductor device
TWI619223B (zh) 堆疊的半導體封裝以及其之製造方法
KR20120058118A (ko) 적층 패키지의 제조 방법, 및 이에 의하여 제조된 적층 패키지의 실장 방법
US9391031B2 (en) Method for manufacturing electronic device and electronic device
JP2012064991A (ja) フリップチップボンデッドパッケージ
US20150179597A1 (en) Semiconductor package and fabrication method thereof
TWI478257B (zh) 封裝結構及封裝製程
JP2006222470A (ja) 半導体装置および半導体装置の製造方法
KR101440342B1 (ko) 반도체 패키지 제조용 서포팅 장치 및 이를 이용한 반도체 패키지 제조 방법
JP2010135501A (ja) 半導体装置の製造方法
JP2004063524A (ja) 実装装置及びその実装方法若しくはプリント配線基板
KR101804568B1 (ko) 반도체 패키지 및 그 제조방법
KR101332857B1 (ko) 반도체 패키지 및 그 제조 방법
KR101002041B1 (ko) 칩 적층형 패키지 및 그 제조방법
JP4591715B2 (ja) 半導体装置の製造方法
JP2012174900A (ja) 半導体装置の製造方法