TW201405687A - Chip tray - Google Patents
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- TW201405687A TW201405687A TW101125698A TW101125698A TW201405687A TW 201405687 A TW201405687 A TW 201405687A TW 101125698 A TW101125698 A TW 101125698A TW 101125698 A TW101125698 A TW 101125698A TW 201405687 A TW201405687 A TW 201405687A
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Abstract
Description
本發明是有關於一種晶片承載盤，特別是一種可防止晶片滑出之晶片承載盤。
This invention relates to a wafer carrier disk, and more particularly to a wafer carrier disk that prevents wafers from slipping out.
請參閱第16圖，一種習知承載盤10具有複數個容置槽11，該些容置槽11係可供複數個晶片20或其他小型元件容置，當複數個容置有該些晶片20的承載盤10相互堆疊時，係可儲存或搬運該些晶片20，以進行下一個半導體製程，然由於環境溫度不同，使得該些承載盤10在不同環境溫度下，因溫度差異而產生翹曲，當該些承載盤10發生翹曲時，該相互堆疊的該些承載盤10之間的間距會隨著該些承載盤10翹曲而越來越大，因此造成容置於該些容置槽11中的該些晶片20在儲存或搬運的過程中會發生彈跳而造成損壞或滑出該些容置槽11。
Referring to FIG. 16, a conventional carrier tray 10 has a plurality of receiving slots 11 for receiving a plurality of wafers 20 or other small components. When a plurality of the wafers 20 are accommodated, When the carrier disks 10 are stacked on each other, the wafers 20 can be stored or transported for the next semiconductor process. However, due to different ambient temperatures, the carrier disks 10 are warped due to temperature differences at different ambient temperatures. When the carrier trays 10 are warped, the spacing between the carrier trays 10 stacked on each other may become larger as the carrier trays 10 are warped, thereby causing the contents to be accommodated. The wafers 20 in the slot 11 may bounce during storage or handling to cause damage or slip out of the accommodating slots 11.
本發明之主要目的在於提供一種晶片承載盤，其係藉由一吸嘴取放槽與複數個容置槽呈交叉狀，且吸嘴取放槽的一第一深度小於各該容置槽的一第二深度，當複數個晶片承載盤相互堆疊時，一晶片承載盤的限位凸肋容置於另一晶片承載盤的吸嘴取放槽，以使容置於該些容置槽中的晶片，仍可被限位於該些容置槽中，而不會發生彈跳而損壞或滑出該些容置槽。
本發明之一種晶片承載盤，其供放置複數個晶片，該晶片承載盤包含一第一表面、一第二表面、一基座及一堆疊限位槽，該第二表面係位於該第一表面下方，該基座係凸設於該第一表面，該基座具有一上表面、一吸嘴取放槽、複數個容置槽及複數個間隔肋，該吸嘴取放槽凹設於該上表面，該吸嘴取放槽具有二第一縱向邊緣及一第一底面，該些第一縱向邊緣之間具有一第一寬度，該第一底面與該上表面之間具有一第一深度，該些容置槽係凹設於該上表面，且該些容置槽與該吸嘴取放槽呈交叉狀，並形成有複數個交叉區域，該些容置槽分別具有一第二底面，該第二底面與該上表面之間具有一第二深度，該第一深度小於該第二深度，各該間隔肋及各該容置槽為間隔排列，且各該間隔肋具有一頂面，該頂面為該吸嘴取放槽的該第一底面的部分區域，該堆疊限位槽，其係對應該基座，且凹設於第二表面，該堆疊限位槽具有一第三底面及至少一限位凸肋，該限位凸肋係凸設於該第三底面，且該限位凸肋係位於該吸嘴取放槽下方，該限位凸肋的具有二第二縱向邊緣及一限位面，該些第二縱向邊緣之間具有一第二寬度，該第二寬度係小於該第一寬度，本發明藉由該些容置槽與該吸嘴取放槽呈交叉設置，且該吸嘴取放槽的該第一深度小於各該容置槽的該第二深度，當複數個晶片承載盤互相堆疊時，相鄰的一晶片承載盤的該限位凸肋容置於另一晶片承載盤的該吸嘴取放槽，以使容置於該些容置槽中的晶片，仍可被限位於該些容置槽中，而不會發生彈跳而損壞或滑出該些容置槽。
The main purpose of the present invention is to provide a wafer carrier tray that is intersected with a plurality of receiving slots by a nozzle pick-and-place slot, and a first depth of the nozzle pick-and-place slot is smaller than that of each of the receiving slots. a second depth, when a plurality of wafer carriers are stacked on each other, the limiting ribs of a wafer carrier are received in the nozzle pick-and-place grooves of the other wafer carrier, so as to be accommodated in the receiving slots The wafers can still be confined in the accommodating slots without bounce and damage or slip out of the accommodating slots.
A wafer carrier disk for placing a plurality of wafers, the wafer carrier disk comprising a first surface, a second surface, a base and a stacking limiting slot, the second surface being located on the first surface The pedestal has a top surface, a nozzle pick-and-place groove, a plurality of accommodating grooves, and a plurality of spaced ribs. The nozzle pick-and-place groove is recessed in the first surface. The upper surface of the nozzle has two first longitudinal edges and a first bottom surface, and the first longitudinal edges have a first width therebetween, and the first bottom surface and the upper surface have a first depth The accommodating grooves are recessed on the upper surface, and the accommodating grooves are intersected with the nozzle accommodating grooves, and a plurality of intersecting regions are formed, and the accommodating grooves respectively have a second bottom surface The second bottom surface and the upper surface have a second depth, the first depth is smaller than the second depth, and each of the spacer ribs and each of the accommodating grooves are spaced apart, and each of the spaced ribs has a top surface The top surface is a partial area of the first bottom surface of the nozzle pick-and-place groove, the stack a slot, which is corresponding to the base, and is recessed on the second surface, the stack limiting slot has a third bottom surface and at least one limiting rib, and the limiting rib is protruded from the third bottom surface. And the limiting rib is located under the nozzle pick-and-place groove, the limiting rib has two second longitudinal edges and a limiting surface, and the second longitudinal edges have a second width between the second longitudinal edges The second width is smaller than the first width. The first aspect of the present invention is that the first depth of the nozzle pick-and-place slot is smaller than the first one of the receiving slots. Two depths, when a plurality of wafer carriers are stacked on each other, the limiting ribs of an adjacent wafer carrier are received in the nozzle pick-and-place groove of another wafer carrier to accommodate the capacitors The wafers in the slots can still be confined in the accommodating slots without bounce and damage or slip out of the accommodating slots.
請參閱第1及2圖，為本發明之第一實施例，一種晶片承載盤100，其供放置複數個晶片200，該晶片承載盤100包含一第一表面110、一第二表面120、一基座130、一堆疊限位槽140及一缺角150，該缺角150位於該晶片承載盤100之一角隅，該第二表面120係位於該第一表面110下方，請參閱第1圖，該基座130係凸設於該第一表面110，該基座130具有一上表面131、一吸嘴取放槽132、複數個容置槽133及複數個間隔肋134。
請參閱第1、3及5圖，該吸嘴取放槽132係凹設於該上表面131，該吸嘴取放槽132具有二第一縱向邊緣Y1及一第一底面132a，該些第一縱向邊緣Y1之間具有一第一寬度W1，請參閱第5及6圖，該第一底面132a與該上表面131之間具有一第一深度D1。
請參閱第1、3及5圖，該些容置槽133係凹設於該上表面131，且該些容置槽133與該吸嘴取放槽132呈交叉狀設置，該些容置槽133與該吸嘴取放槽132並形成有複數個交叉區域S，請參閱第5及6圖，該些容置槽133分別具有一第二底面133a，該第二底面133a與該上表面131之間具有一第二深度D2，該第一深度D1小於該第二深度D2，各該第二深度D2大於各該晶片200之厚度0.4 mm到0.5 mm，可防止該晶片200前後左右滑出該容置槽133，請參閱第1及3圖，各該間隔肋134及各該容置槽133為間隔排列，且各該間隔肋134具有一頂面134a，該頂面134a為該吸嘴取放槽132的該第一底面132a的部分區域，較佳地，各該間隔肋134的該頂面134a與該吸嘴取放槽132的該第一底面132a為共平面。
請參閱第2、3、4、5及6圖，該堆疊限位槽140係對應該基座130，且該堆疊限位槽140凹設於第二表面120，該堆疊限位槽140具有一第三底面141及至少一限位凸肋142，該限位凸肋142係凸設於該第三底面141，請參閱第5圖，該限位凸肋142係位於該吸嘴取放槽132下方，且該限位凸肋142與該些容置槽133呈交叉狀設置，在本實施例中，該吸嘴取放槽132是對應一個限位凸肋142，該限位凸肋142具有二第二縱向邊緣Y2及一限位面142a，該些第二縱向邊緣Y2之間具有一第二寬度W2，該第二寬度W2係小於該第一寬度W1，在本實施例中，該限位面142a與該第三底面141之間具有一高度H，該高度H係不小於該第一深度D1。
請參閱第7、8、9及10圖，當複數個晶片承載盤100相互堆疊時，其中一晶片承載盤100A的一基座130係容置於相鄰的另一晶片承載盤100B的堆疊限位槽140中，且該晶片承載盤100B的至少一限位凸肋142係容置於該晶片承載盤100A的吸嘴取放槽132，藉由該晶片承載盤100B的該限位凸肋142與該晶片承載盤100A的該些容置槽133交叉堆疊，以使容置於該晶片承載盤100A的該些容置槽133的該些晶片200不會因該晶片承載盤100A或該晶片承載盤100B翹曲變型，而造成彈跳損壞或滑出該些容置槽133。
請參閱第11及12圖，其為本發明之第二實施例，其與第一實施例之差異在於該晶片承載盤100之該基座130另具有一固定槽135，該固定槽135凹設於該上表面131，該堆疊限位槽140另具有一支撐肋143，該支撐肋143凸設於該第三底面141，且該支撐肋143位於該固定槽135下方，請參閱第13圖，於本實施例中，當複數個承載盤100相互堆疊時，其中一晶片盤承載盤100B之該支撐肋143容置於另一晶片承載盤100A之該固定槽135中，使得該些承載盤100可更加穩固的堆疊。
請參閱第14及15圖，其為本發明之第三實施例，其與第一實施例的差異在於該晶片承載盤100之該推疊限位槽140具有複數個限位凸肋142，各該限位凸肋142為間隔排列，且各該限位凸肋142對應各該容置槽133，當複數個晶片承載100互相堆疊時，各該限位凸肋142將各該晶片200限位於各該容置槽133中，以防止各該晶片200滑出各該容置槽133，在本實施例中，各該限位凸肋142容置於各該容置槽133中。
本發明之保護範圍當視後附之申請專利範圍所界定者為準，任何熟知此項技藝者，在不脫離本發明之精神和範圍內所作之任何變化與修改，均屬於本發明之保護範圍。
Referring to FIGS. 1 and 2, a first embodiment of the present invention, a wafer carrier disk 100 for placing a plurality of wafers 200, the wafer carrier disk 100 includes a first surface 110, a second surface 120, and a The pedestal 130, a stacking limiting slot 140 and a notch 150 are located at a corner of the wafer carrier 100. The second surface 120 is located below the first surface 110. Referring to FIG. The pedestal 130 is disposed on the first surface 110. The pedestal 130 has an upper surface 131, a nozzle accommodating groove 132, a plurality of accommodating grooves 133, and a plurality of spaced ribs 134.
Referring to the first, third, and fifth views, the nozzle receiving and receiving groove 132 is recessed on the upper surface 131. The nozzle receiving and receiving groove 132 has two first longitudinal edges Y1 and a first bottom surface 132a. A first width W1 is defined between a longitudinal edge Y1. Referring to FIGS. 5 and 6, the first bottom surface 132a and the upper surface 131 have a first depth D1.
The accommodating slots 133 are recessed on the upper surface 131, and the accommodating slots 133 are disposed in a cross shape with the nozzle accommodating slots 132. The accommodating slots are provided. 133 and the nozzle receiving and receiving slot 132 are formed with a plurality of intersecting regions S. Referring to FIGS. 5 and 6, the receiving slots 133 respectively have a second bottom surface 133a, and the second bottom surface 133a and the upper surface 131 There is a second depth D2, which is smaller than the second depth D2, and each of the second depths D2 is greater than the thickness of each of the wafers 200 by 0.4 mm to 0.5 mm, which prevents the wafer 200 from slipping out of the front, back, left, and right. The accommodating groove 133, as shown in FIGS. 1 and 3, each of the spacing ribs 134 and each of the accommodating grooves 133 are spaced apart, and each of the spacing ribs 134 has a top surface 134a for the nozzle. Preferably, the top surface 134a of each of the spacer ribs 134 is coplanar with the first bottom surface 132a of the nozzle pick-and-place groove 132.
Referring to the figures 2, 3, 4, 5 and 6, the stack limiting slot 140 is corresponding to the base 130, and the stack limiting slot 140 is recessed on the second surface 120. The stack limiting slot 140 has a The third bottom surface 141 and the at least one limiting rib 142 are protruded from the third bottom surface 141. Referring to FIG. 5 , the limiting rib 142 is located in the nozzle receiving and receiving slot 132 . The lower limit rib 142 is disposed in a crosswise manner with the accommodating groove 133. In the embodiment, the nozzle accommodating groove 132 corresponds to a limiting rib 142, and the limiting rib 142 has The second longitudinal edge Y2 and the limiting surface 142a have a second width W2 between the second longitudinal edges Y2, and the second width W2 is smaller than the first width W1. In this embodiment, the limit A height H is formed between the plane 142a and the third bottom surface 141, and the height H is not less than the first depth D1.
Referring to Figures 7, 8, 9 and 10, when a plurality of wafer carriers 100 are stacked on each other, a susceptor 130 of one of the wafer carriers 100A is placed in a stacking limit of another adjacent wafer carrier 100B. In the slot 140, the at least one limiting rib 142 of the wafer carrier 100B is received in the nozzle receiving and receiving slot 132 of the wafer carrier 100A, and the limiting rib 142 of the wafer carrier 100B. The plurality of accommodating grooves 133 of the wafer carrier 100A are stacked and stacked so that the wafers 200 accommodated in the accommodating grooves 133 of the wafer carrier 100A are not carried by the wafer carrier 100A or the wafer. The disk 100B is warped and deformed, causing bounce damage or slipping out of the accommodating grooves 133.
Referring to FIGS. 11 and 12, which is a second embodiment of the present invention, the difference from the first embodiment is that the base 130 of the wafer carrier 100 further has a fixing groove 135, and the fixing groove 135 is recessed. In the upper surface 131, the stacking limiting slot 140 further has a supporting rib 143 protruding from the third bottom surface 141, and the supporting rib 143 is located below the fixing groove 135. In this embodiment, when a plurality of carrier trays 100 are stacked on each other, the support ribs 143 of one of the wafer carrier trays 100B are received in the fixing slots 135 of the other wafer carrier tray 100A, so that the carrier trays 100 are Can be more stable stacking.
Referring to FIGS. 14 and 15 , which is a third embodiment of the present invention, the difference from the first embodiment is that the push-restricted slot 140 of the wafer carrier 100 has a plurality of limiting ribs 142 , each of which The limiting ribs 142 are spaced apart, and each of the limiting ribs 142 corresponds to each of the receiving grooves 133. When the plurality of wafer carriers 100 are stacked on each other, each of the limiting ribs 142 limits each of the wafers 200 to Each of the accommodating grooves 133 is disposed in each of the accommodating grooves 133. In this embodiment, the ribs 142 are accommodated in the accommodating grooves 133.
The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. .
10．．．承載盤10. . . Carrier disk
11．．．容置槽11. . . Locating slot
20．．．晶片20. . . Wafer
100．．．晶片承載盤100. . . Wafer carrier
100A．．．晶片承載盤100A. . . Wafer carrier
100B．．．晶片承載盤100B. . . Wafer carrier
110．．．第一表面110. . . First surface
120．．．第二表面120. . . Second surface
130．．．基座130. . . Pedestal
131．．．上表面131. . . Upper surface
132．．．吸嘴取放槽132. . . Nozzle pick-and-place
132a．．．第一底面132a. . . First bottom
133．．．容置槽133. . . Locating slot
133a．．．第二底面133a. . . Second bottom
134．．．間隔肋134. . . Spacer
134a．．．頂面134a. . . Top surface
135．．．固定槽135. . . Fixed slot
140．．．堆疊限位槽140. . . Stack limit slot
141．．．第三底面141. . . Third bottom
142．．．限位凸肋142. . . Limit rib
142a．．．限位面142a. . . Limit surface
143．．．支撐肋143. . . Support rib
150．．．缺角150. . . Missing angle
200．．．晶片200. . . Wafer
S．．．交叉區域S. . . Cross area
Y1．．．第一縱向邊緣Y1. . . First longitudinal edge
Y2．．．第二縱向邊緣Y2. . . Second longitudinal edge
W1．．．第一寬度W1. . . First width
W2．．．第二寬度W2. . . Second width
D1．．．第一深度D1. . . First depth
D2．．．第二深度D2. . . Second depth
H．．．高度H. . . height
第1圖：依據本發明之第一實施例，一種晶片承載盤之立體俯視圖。
第2圖：依據本發明之第一實施例，該晶片承載盤之立體仰視圖。
第3圖：依據本發明之第一實施例，該晶片承載盤之俯視圖。
第4圖：依據本發明之第一實施例，該晶片承載盤之仰視圖。
第5圖：沿第3圖之A-A方向，該晶片承載盤之橫剖視圖。
第6圖：沿第3圖之B-B方向，該晶片承載盤之縱剖視圖。
第7圖：依據本發明之第一實施例，該晶片承載盤堆疊之立體分解圖。
第8圖：依據本發明之第一實施例，該晶片承載盤堆疊之立體圖。
第9圖：依據本發明之第一實施例，該晶片承載盤堆疊之橫剖視圖。
第10圖：依據本發明之第一實施例，該晶片承載盤堆疊之縱剖視圖。
第11圖：依據本發明之第二實施例，一種晶片承載盤之立體俯視圖。
第12圖：依據本發明之第二實施例，該晶片承載盤之立體仰視圖。
第13圖：依據本發明之第二實施例，該晶片承載盤堆疊之橫剖視圖。
第14圖：依據本發明之第三實施例，一種晶片承載盤之立體俯視圖。
第15圖：依據本發明之第三實施例，該晶片承載盤之立體仰視圖。
第16圖：一種習知承載盤之立體圖。
Figure 1 is a perspective top view of a wafer carrier disk in accordance with a first embodiment of the present invention.
Figure 2: A perspective bottom view of the wafer carrier in accordance with a first embodiment of the present invention.
Figure 3 is a plan view of the wafer carrier in accordance with a first embodiment of the present invention.
Figure 4: A bottom view of the wafer carrier tray in accordance with a first embodiment of the present invention.
Figure 5: A cross-sectional view of the wafer carrier disk along the AA direction of Figure 3.
Fig. 6 is a longitudinal sectional view of the wafer carrier in the BB direction of Fig. 3.
Figure 7 is an exploded perspective view of the wafer carrier tray stack in accordance with a first embodiment of the present invention.
Figure 8 is a perspective view of the wafer carrier tray stack in accordance with a first embodiment of the present invention.
Figure 9 is a cross-sectional view of the wafer carrier tray stack in accordance with a first embodiment of the present invention.
Figure 10 is a longitudinal cross-sectional view of the wafer carrier tray stack in accordance with a first embodiment of the present invention.
Figure 11 is a perspective top plan view of a wafer carrier disk in accordance with a second embodiment of the present invention.
Figure 12 is a perspective bottom view of the wafer carrier in accordance with a second embodiment of the present invention.
Figure 13 is a cross-sectional view of the wafer carrier tray stack in accordance with a second embodiment of the present invention.
Figure 14 is a perspective top plan view of a wafer carrier disk in accordance with a third embodiment of the present invention.
Figure 15 is a perspective bottom plan view of the wafer carrier in accordance with a third embodiment of the present invention.
Figure 16: A perspective view of a conventional carrier disk.
100．．．晶片承載盤100. . . Wafer carrier
131．．．上表面131. . . Upper surface
132．．．吸嘴取放槽132. . . Nozzle pick-and-place
132a．．．第一底面132a. . . First bottom
133．．．容置槽133. . . Locating slot
133a．．．第二底面133a. . . Second bottom
134．．．間隔肋134. . . Spacer
134a．．．頂面134a. . . Top surface
141．．．第三底面141. . . Third bottom
142．．．限位凸肋142. . . Limit rib
142a．．．限位面142a. . . Limit surface
W1．．．第一寬度W1. . . First width
W2．．．第二寬度W2. . . Second width
D1．．．第一深度D1. . . First depth
D2．．．第二深度D2. . . Second depth
H．．．高度H. . . height
Claims (6)
一第一表面；
一第二表面，其係位於該第一表面下方；
一基座，其係凸設於該第一表面，該基座具有：
一上表面；
一吸嘴取放槽，其係凹設於該上表面，該吸嘴取放槽具有二第一縱向邊緣及一第一底面，該些第一縱向邊緣之間具有一第一寬度，該第一底面與該上表面之間具有一第一深度；
複數個容置槽，其係凹設於該上表面，且該些容置槽與該吸嘴取放槽呈交叉狀，並形成有複數個交叉區域，該些容置槽分別具有一第二底面，該第二底面與該上表面之間具有一第二深度，該第一深度小於該第二深度；及
複數個間隔肋，各該間隔肋及各該容置槽為間隔排列，且各該間隔肋具有一頂面，該頂面為該吸嘴取放槽的該第一底面的部分區域；以及
一堆疊限位槽，其係對應該基座，且凹設於第二表面，該堆疊限位槽具有一第三底面及至少一限位凸肋，該限位凸肋係凸設於該第三底面，且該限位凸肋係位於該吸嘴取放槽下方，該限位凸肋具有二第二縱向邊緣及一限位面，該些第二縱向邊緣之間具有一第二寬度，該第二寬度係小於該第一寬度。A wafer carrier tray for placing a plurality of wafers, the wafer carrier tray comprising:
a first surface;
a second surface located below the first surface;
a pedestal protruding from the first surface, the pedestal having:
An upper surface;
a nozzle accommodating groove is recessed on the upper surface, the nozzle accommodating groove has two first longitudinal edges and a first bottom surface, and the first longitudinal edges have a first width, the first a first depth between a bottom surface and the upper surface;
a plurality of accommodating grooves are recessed on the upper surface, and the accommodating grooves are intersected with the nozzle accommodating grooves, and a plurality of intersecting regions are formed, and the accommodating grooves respectively have a second a bottom surface having a second depth between the second bottom surface and the upper surface, the first depth being less than the second depth; and a plurality of spacer ribs, each of the spacer ribs and each of the accommodating grooves being spaced apart The spacer rib has a top surface which is a partial area of the first bottom surface of the nozzle pick-and-place groove; and a stacking limiting groove corresponding to the base and recessed on the second surface, The stacking limiting slot has a third bottom surface and at least one limiting rib. The limiting rib is protruded from the third bottom surface, and the limiting rib is located below the nozzle pick-and-place slot. The rib has two second longitudinal edges and a limiting surface, and the second longitudinal edges have a second width therebetween, and the second width is smaller than the first width.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101125698A TWI440118B (en) | 2012-07-17 | 2012-07-17 | Chip tray |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101125698A TWI440118B (en) | 2012-07-17 | 2012-07-17 | Chip tray |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201405687A true TW201405687A (en) | 2014-02-01 |
| TWI440118B TWI440118B (en) | 2014-06-01 |
Family
ID=50550111
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW101125698A TWI440118B (en) | 2012-07-17 | 2012-07-17 | Chip tray |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI440118B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104979250A (en) * | 2014-04-11 | 2015-10-14 | 勤辉科技股份有限公司 | Wafer placing frame |
-
2012
- 2012-07-17 TW TW101125698A patent/TWI440118B/en active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104979250A (en) * | 2014-04-11 | 2015-10-14 | 勤辉科技股份有限公司 | Wafer placing frame |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI440118B (en) | 2014-06-01 |
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