KR101710578B1 - Semiconductor chip tray - Google Patents

Semiconductor chip tray Download PDF

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Publication number
KR101710578B1
KR101710578B1 KR1020160056383A KR20160056383A KR101710578B1 KR 101710578 B1 KR101710578 B1 KR 101710578B1 KR 1020160056383 A KR1020160056383 A KR 1020160056383A KR 20160056383 A KR20160056383 A KR 20160056383A KR 101710578 B1 KR101710578 B1 KR 101710578B1
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air vent
pocket
tray
chip
semiconductor device
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KR1020160056383A
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Korean (ko)
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윤재원
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주식회사 명성세미트론
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/67333—Trays for chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/67346—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders characterized by being specially adapted for supporting a single substrate or by comprising a stack of such individual supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/6735—Closed carriers
    • H01L21/67356—Closed carriers specially adapted for containing chips, dies or ICs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/6735—Closed carriers
    • H01L21/67363—Closed carriers specially adapted for containing substrates other than wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/6735—Closed carriers
    • H01L21/67379—Closed carriers characterised by coupling elements, kinematic members, handles or elements to be externally gripped
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67703—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
    • H01L21/6773—Conveying cassettes, containers or carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67763—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67784—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations using air tracks
    • H01L21/6779—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations using air tracks the workpieces being stored in a carrier, involving loading and unloading

Abstract

The present invention relates to a semiconductor device tray. More specifically, the present invention relates to the semiconductor device tray, having an air vent (12) provided to an upper surface of a center of a plurality of pocket groups (11) where pockets (11a) where a semiconductor device (C) is mounted are gathered and having a support rib (13) and an air vent rib (14) provided to a bottom surface of a lower portion of a chip mounting unit (10). Therefore, the present invention prevents the semiconductor device (C) from being scattered to be easily stored and transferred.

Description

반도체소자 트레이{Semiconductor chip tray}Semiconductor chip tray

본 발명은 반도체소자 트레이에 관한 것으로, 보다 상세하게는 반도체소자를 포켓에 안정적으로 적층하여 수납하고 보관시 흐트러짐이 방지되도록 상기 포켓을 구분하는 에어벤트와 상기 에어벤트의 상면 일측에 지지되는 에어벤트리브가 구비됨으로써, 적층 해제시 트레이의 층간 사이에서 발생된 공기압의 변화에 따른 반도체소자의 흐트러짐과 이탈이 방지되는 반도체소자 트레이에 관한 것이다.The present invention relates to a semiconductor device tray, and more particularly, to a semiconductor device tray that stably laminates semiconductor devices in pockets and stores the air devices so as to prevent disturbance during storage, and an air vent which is supported on one side of the upper surface of the air vent The present invention relates to a semiconductor device tray in which breakage and disconnection of a semiconductor device due to a change in air pressure generated between layers of a tray during stacking can be prevented.

일반적으로 웨이퍼, 다이, 칩 등의 반도체소자나 전자 디바이스의 제조업은 절단, 접착, 절삭, 전달, 전송, 보관 등의 그 중요성이 매우 강조되고 있다. 특히 가공이 완료된 웨이퍼, 칩, 다이 등을 보관 및 운반하는데 있어서 이들을 담아 보관 및 운반할 수 있는 보관용기는 이들의 신뢰성에 결정적인 영향을 미치고 있기도 하다.2. Description of the Related Art In general, the importance of cutting, bonding, cutting, transferring, transferring, storing, etc. of semiconductor devices such as wafers, dies, Especially, in storing and transporting processed wafers, chips, dies, and the like, storage containers capable of storing and transporting these wafers, chips, and dies have a decisive influence on their reliability.

현재 상기 보관 및 운반체로서 가장 널리 사용되고 있는 칩 트레이(TRAY)는 바둑판 모양으로 칩이 들어갈 수 있는 포켓이 각 칩의 크기에 맞게 형성된 구성이다. 이는 생산되는 포켓에 맞게 칩의 크기가 일치하여야만 운반시 흔들림에 움직임이 없어 칩의 손상을 줄일 수 있도록 하였으나 칩의 크기는 균일하지 못하기 때문에 모든 칩을 포켓에 정확히 일치시켜 움직이지 못하도록 내재시키지 못하여 어느 정도의 흔들림은 피할 수 없었다.Currently, a chip tray (TRAY), which is most widely used as a storage and carrier, has a structure in which a pocket into which chips can be inserted in a checkerboard shape is formed according to the size of each chip. This is because the size of chips to be produced must match the sizes of the produced pockets, so that there is no movement due to shaking during transportation. However, since chips are not uniform in size, all the chips can not be precisely aligned with the pockets A certain amount of shaking was inevitable.

또한 상기와 같이 정확한 크기에 맞게 형성하여 제작되었다 하더라도 깊이는 일정하게 여유를 두고 제작되어야만 한다. 그 이유로는 고객에 따라 원하는 칩의 두께가 달라지기 때문에 각 칩의 두께에 따라 칩 트레이를 일일이 제작 할 수 없어 가장 두꺼운 칩에 맞추어 제작이 되어야만 하기 때문이다. In addition, even if it is formed in accordance with the exact size as described above, the depth must be made with a constant margin. This is because the thickness of the desired chip varies depending on the customer, so the chip tray can not be manufactured individually according to the thickness of each chip, so that it must be manufactured in accordance with the thickest chip.

이런 경우 칩에 따라 공차가 발생되어 칩의 운반시 포켓 내에서 요동이 심하게 발생됨으로써 칩의 표면을 손상시키게 되는 요인이 되고 나아가서는 충격이 심하여 칩이 깨지는 경우도 발생되는 등의 문제점이 있었다.In this case, there is a problem that a tolerance is generated according to the chip, and the chip is shaken in the pocket when the chip is transported, thereby damaging the surface of the chip, and furthermore, the chip is broken due to a severe impact.

이를 개선한 종래기술로 한국공개특허공보 특2000-0025590호 (2000.05.06.)에는 '곡면 처리된 꼭지점을 갖는 트레이 및 그를 이용한 적층 트레이'가 개시되었다.Korean Patent Laid-Open Publication No. 2000-0025590 (May 05, 2000) discloses a tray having a curved surface vertex and a laminated tray using the same.

상기한 종래기술은 도 1에 도시된 바와 같이 반도체 소자(116)가 수용되는 캐버티(112)가 복수개 형성된 탑재부(110)와 탑재부가 상면(122)에 돌출 되고 탑재부에 대응하는 수용부(126)가 하면(124)에 형성된 장방체(長方體)의 몸체(120)를 포함하며, 각각의 트레이(130)는 탑재부(110)와 수용부(126)가 서로 맞물리면서 수직으로 적층될 수 있으며, 약 10개의 트레이들(130)이 적층된 후 그 최상부에 덮개 트레이(140)가 놓여질 수 있다. 또한, 덮개 트레이(140)는 평평한 상면(142)과 수용부(146)가 형성된 하면(144)을 포함하는 구조를 가지며, 덮개 트레이(140)의 바로 밑에 놓여진 트레이(130)로부터 반도체 소자들(116)이 분리되지 않도록 한다.1, a mounting part 110 in which a plurality of cavities 112 in which semiconductor elements 116 are accommodated is mounted, a receiving part protruding from the upper surface 122 and corresponding to the mounting part, Each of the trays 130 can be stacked vertically with the mounting portion 110 and the receiving portion 126 interlocked with each other, After the trays 130 are stacked, the cover tray 140 may be placed at the top. The lid tray 140 has a structure including a flat upper surface 142 and a lower surface 144 on which the receiving portion 146 is formed and extends from the tray 130 directly below the lid tray 140 to the semiconductor elements 116 are not separated.

각 트레이들(130)과 덮개 트레이(140)는 운반이 용이하도록 손잡이(114, 148)가 형성되어 있다. 적층된 트레이들(130)과 그 위로 적층된 덮개 트레이(140)를 포함하여 반도체 소자들(116)의 포장 및 운반 단위인 적층 트레이(100)를 형성하는 것을 특징으로 한다.The trays 130 and the cover tray 140 are formed with handles 114 and 148 for easy transportation. The stacking tray 100 is formed by stacking the stacked trays 130 and the cover tray 140 stacked thereon to form a packaging and conveying unit of the semiconductor elements 116. [

다만, 상기한 종래기술은 적층된 트레이들(130)들은 별도의 손잡이 들이 구비되어 반도체 소자를 포장하고 운반하기가 용이한 반면, 적층상태 해제시 반도체 소자들(116)이 따라 올라옴에 따라 분리시 이탈되는 문제점이 있었다.However, in the above-described prior art, the stacked trays 130 are provided with separate knobs to facilitate packaging and transportation of the semiconductor devices. On the other hand, when the stacked state is released, There was a problem of being separated.

그리고, 상기한 종래기술은 상기 반도체소자의 수납과 분리가 용이토록 곡면 처리된 꼭지점과 모서리가 구비되나, 일정 이상의 트레이 적층시 충격에 의해 흔들림이 발생되어 반도체소자가 흐트러짐이 발생되는 문제점이 있었다.In addition, although the above-mentioned prior art has vertexes and corners that are subjected to a curved surface treatment for accommodating and separating the semiconductor devices, there is a problem that a semiconductor device is disturbed by shaking due to an impact when a certain number of trays are stacked.

본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위해 창작된 것으로 본 발명의 목적은 반도체소자가 수납되는 포켓이 일방향으로 군집된 포켓군의 상면 중앙에 상기 반도체소자가 분리되도록 에어벤트와, 적층시 상기 에어벤트의 상면 일측에 지지되는 리브가 구비됨으로써, 상기 포켓의 구획을 구분함으로써, 반도체소자의 이탈을 방지하여 보관이 용이하고 적층상태의 해제시 상기 반도체소자의 흐트러짐을 방지하여 보관과 이송이 안정적인 반도체소자 트레이를 제공함에 있다.SUMMARY OF THE INVENTION The present invention has been made in order to solve the problems of the prior art as described above, and it is an object of the present invention to provide an air vent and an air vent so that the semiconductor element is separated at the center of the upper surface of a pocket group, Since the ribs supported on one side of the upper surface of the air vent are provided, the division of the pockets is provided to prevent the semiconductor elements from being separated from each other, thereby facilitating storage and preventing the semiconductor elements from being disturbed when the laminated state is released, And a stable semiconductor element tray.

상기와 같은 목적을 달성하기 위해 본 발명에 따른 반도체소자 트레이는 반도체소자가 안착되도록 요입된 장방형상의 포켓이 일방향으로 군집된 사각형상의 포켓군과, 상기 포켓군의 중앙 상면에 하부 방향으로 요입된 장방형상의 에어벤트가 다수개 구비된 칩안착부와; 상기 칩안착부의 외주면의 둘레를 따라 외측으로 연장된 외곽지지부로 이루어지며,In order to achieve the above object, a semiconductor device tray according to the present invention includes: a rectangular pocket group in which rectangular pockets recessed to receive a semiconductor device are clustered in one direction; A chip mounting part having a plurality of air vent holes; And an outer frame portion extending outward along the periphery of the outer surface of the chip seating portion,

상기 칩안착부의 하부 저면에는 적층시 상기 포켓의 상부 선단에 지지되도록 하부 방향으로 연장된 다수개의 지지리브와, 상기 에어벤트의 일측 상면에 지지되어 상기 반도체소자의 흐트러짐이 방지되도록 하부 방향으로 돌출된 에어벤트리브가 구비된 것을 특징으로 한다.A plurality of support ribs extending downward to be supported at an upper end of the pocket at the time of stacking on the lower bottom surface of the chip seating part; And an air vent rib is provided.

상기 외곽지지부의 상단에는 상기 에어벤트에 외부공기가 연통되도록 하부로 요입된 연통홈이 구비된 것을 특징으로 한다.And an upper end of the outer brim part is provided with a communication groove recessed downward so that external air communicates with the air vent.

상기 외곽지지부의 하단에는 적층시 상기 칩안착부의 외주면의 둘레를 감싸며 안착되도록 하부 방향으로 연장된 적층연장단이 구비된 것을 특징으로 한다.And a lower end of the outer frame is provided with a lamination extension extending downward so as to surround and surround the outer circumferential surface of the chip seating part when the chip is stacked.

상기 연통홈은 마주보는 대향면에 서로 엇갈리게 형성된 것을 특징으로 한다.And the communication grooves are formed to be offset from each other on opposite facing surfaces.

상기 지지리브는 적층시 상기 반도체소자가 상부로 이탈되는 것을 방지토록 격자 형상으로 이루어진 것을 특징으로 한다.The support ribs are formed in a lattice shape to prevent the semiconductor elements from being separated upward when stacked.

이와 같은 본 발명의 반도체소자 트레이는 다음과 같은 효과가 있다.The semiconductor device tray of the present invention has the following effects.

첫째, 반도체소자가 안착되는 포켓이 형성된 포켓군의 상면에 하방으로 요입된 에어벤트가 구비되어, 적층시 상기 포켓에 수납된 반도체소자를 상기 에어벤트로 구분함으로써, 상기 포켓에 수납된 반도체소자의 흐트러짐이 방지되며,First, an air vent which is recessed downward is provided on an upper surface of a pocket group on which a pocket where a semiconductor element is placed is formed. By dividing a semiconductor element housed in the pocket into the air vent during stacking, And is prevented from being disturbed,

둘째, 상기 에어벤트의 일측 상면에 안착되어 지지되는 에어벤트리브가 지지리브보다 더 돌출됨으로써, 적층된 상기 트레이를 상부로 이송시 상기 에어벤트로 공기가 유입되어 상기 반도체소자가 표면장력에 의해 딸려 올라가며 이탈되는 것을 방지하고, Secondly, since the air vent ribs, which are seated on one upper surface of the air vent, protrude more than the support ribs, air is introduced into the air vent when the stacked tray is transferred to the upper side, And thus,

셋째, 상기 에어벤트와 연통되는 외부 유입통로인 연통홈이 외곽지지부에 구비됨으로써, 상기 에어벤트리브와 함께 상기 반도체소자의 이탈을 방지하여 상기 반도체소자를 보다 안정적으로 보관하고 이송할 수 있어 생산성이 향상되는 효과가 있다.Thirdly, since the communication groove, which is an external inflow passage communicating with the air vent, is provided in the outer peripheral portion, the semiconductor element can be prevented from being separated with the air vent rib, and the semiconductor element can be stored and transported more stably, There is an effect to be improved.

도 1은 종래기술에 따른 반도체 소자의 보관장치를 나타낸 도면이고,
도 2는 본 발명에 따른 반도체소자 트레이의 사시도이며,
도 3은 본 발명에 따른 반도체소자 트레이의 측면을 나타낸 도면이고,
도 4는 본 발명에 따른 반도체소자 트레이의 공기유입통로를 설명하는 단면도이며,
도 5는 본 발명에 따른 반도체소자 트레이의 적층시 작용을 설명하는 도면이다.1 is a view showing a conventional semiconductor device storage device,
2 is a perspective view of a semiconductor device tray according to the present invention,
3 is a side view of a semiconductor device tray according to the present invention,
4 is a cross-sectional view illustrating an air inflow path of a semiconductor device tray according to the present invention,
FIG. 5 is a view for explaining the operation of stacking semiconductor element trays according to the present invention. FIG.

이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체소자 트레이의 일 실시예를 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of a semiconductor device tray according to the present invention will be described in detail with reference to the accompanying drawings.

본 발명의 반도체소자 트레이는 도 2 내지 도 5에 도시된 바와 같이 반도체소자(C)가 안착되도록 요입된 장방형상의 포켓(11a)이 일방향으로 군집된 사각형상의 포켓군(11)과, 상기 포켓(11a)이 양측으로 구분되도록 상기 포켓군(11)의 중앙 상면에서 하부 방향으로 요입된 장방형상의 에어벤트(12)가 다수개 구비된 칩안착부(10)와; 상기 칩안착부(10)의 외주면의 둘레를 따라 외측으로 연장된 외곽지지부(20)로 이루어지며,2 to 5, the semiconductor device tray of the present invention includes a rectangular pocket group 11 in which rectangular pockets 11a recessed so as to seat semiconductor elements C are grouped in one direction, (10) having a plurality of rectangular air vents (12) recessed in a downward direction from a central upper surface of the pocket group (11) so as to be divided into two sides; And an outer frame portion 20 extending outward along the periphery of the chip seating portion 10,

상기 칩안착부(10)의 하부 저면에는 적층시 상기 포켓(11a)의 상부 선단에 지지되도록 하부 방향으로 연장된 다수개의 지지리브(13)와, 상기 에어벤트(12)의 일측 상면에 지지되도록 상기 지지리브(13)의 사이에서 하부 방향으로 더 돌출된 에어벤트리브(14)가 구비된다.A plurality of support ribs 13 extending downward to be supported at an upper end of the pocket 11a at the time of lamination and a plurality of support ribs 13 extending upwardly from the upper end of the pocket 11a to be supported on one upper surface of the air vent 12 And an air vent rib 14 protruding further downward between the support ribs 13 is provided.

여기서, 상기 지지리브(13)는 적층시 상기 포켓(11a)의 상부 선단에 지지되고, 상기 에어벤트리브(14)는 상기 에어벤트(12)의 상면에 지지됨으로써, 상기 포켓(11a)이 양측으로 구분되어, 상기 반도체소자(C)가 좌우 또는 상하로 이탈되는 것이 방지되게 된다.The air vent ribs 14 are supported on the upper surface of the air vent 12 so that the pockets 11a are supported on the upper ends of the pockets 11a on both sides So that the semiconductor element C is prevented from being deviated rightward or leftward or up and down.

그리고, 상기 외곽지지부(20)의 상단에는 상기 에어벤트(12)에 외부공기가 연통되도록 하부로 요입된 연통홈(21)이 구비되며, 상기 연통홈(21)은 적층된 상태에서 상기 외곽지지부(20) 사이의 틈을 넓히는 구조로 적층 해제시 이송을 용이하게 하는 기능도 수행하게 된다.The upper end of the outer brim part 20 is provided with a communication groove 21 which is recessed downward so that external air communicates with the air vent 12. The communication groove 21, And a function of expanding the clearance between the upper and lower plates 20 is facilitated.

또한, 상기 외곽지지부(20)의 하단에는 적층시 상기 칩안착부(10)의 외주면의 둘레를 감싸며 안착되도록 하부 방향으로 연장된 적층연장단(22)이 구비됨으로써, 반도체소자(C) 트레이의 적층을 안정적으로 유지할 수 있게 된다.The lower end of the outer frame portion 20 is provided with a laminated extension 22 extending downward so as to surround and surround the periphery of the chip seating portion 10 during stacking, The lamination can be stably maintained.

한편, 상기 연통홈(21)은 마주보는 대향면에 서로 엇갈리게 형성된다. 이때 다른 대향면에는 상기 연통홈(21)이 중앙에 구비됨으로써, 외부 공기의 소통을 원활히 하여 빠르게 들어올리거나 쌓을 때 보다 안정적인 작업을 수행할 수 있게 된다. On the other hand, the communication grooves 21 are formed to be offset from each other on opposite facing surfaces. At this time, since the communication grooves 21 are provided in the other opposite surfaces at the center, communication of the outside air is smoothly performed, so that it is possible to perform a more stable operation when the gas is rapidly lifted or piled.

그리고, 상기 지지리브(13)는 적층시 상기 반도체소자(C)가 상부로 이탈되는 것을 방지토록 격자 형상으로 이루어진다. 즉, 상기 지지리브(13)는 적층시 다른 상기 칩안착부(10)의 상부면에 안착되며, 상기 포켓(11a)에 삽입된 상기 반도체소자(C)의 이탈을 방지하게 된다.
The support ribs 13 are formed in a lattice shape to prevent the semiconductor elements C from being separated upward when stacked. That is, the support ribs 13 are seated on the upper surface of the chip seating part 10 at the time of stacking, and the semiconductor element C inserted into the pocket 11a is prevented from being separated.

상기와 같은 구성으로 이루어진 본 발명의 반도체소자 트레이의 작용은 다음과 같다.The operation of the semiconductor device tray of the present invention having the above-described structure is as follows.

본 발명의 반도체소자 트레이는 도 2 내지 도 5에 도시된 바와 같이 트레이를 적층하여 수납할 수 있도록 외곽지지부(20)의 내측면이 칩안착부(10)의 외주면에 안착되며, 상기 칩안착부(10)의 하면이 아래층에 적층된 칩안착부(10)의 상면에 지지되게 된다.As shown in FIGS. 2 to 5, the semiconductor element tray of the present invention has an inner surface of the outer frame portion 20 that is seated on the outer peripheral surface of the chip seating portion 10 so that the tray can be stacked and housed, (10) is supported on the upper surface of the chip mounting part (10) stacked on the lower layer.

여기서, 상기 칩안착부(10)의 하면에는 지지리브(13)와 에어벤트리브(14)가 구비되고, 상면에는 포켓(11a)이 일방향으로 군집된 다수개의 포켓군(11)과 에어벤트(12)가 구비되며, 상기 지지리브(13)는 상기 포켓(11a)에 수납된 상기 반도체소자(C)의 상부 방향 이탈을 방지하고 상기 에어벤트리브(14)는 상기 반도체소자(C)의 측부 방향 이송을 방지하여 상기 반도체소자(C)의 흐트러짐을 방지하게 된다.A plurality of pocket groups 11 and air vents 11 are provided on the upper surface of the chip mounting portion 10 and a plurality of pocket groups 11 are formed on the upper surface of the chip mounting portion 10, The support ribs 13 prevent an upward deviation of the semiconductor element C housed in the pockets 11a and the air vent ribs 14 are arranged on the side of the semiconductor element C, Directional transfer is prevented to prevent the semiconductor device (C) from being disturbed.

이때, 상기 에어벤트리브(14)는 상기 에어벤트(12)의 상면 일측에만 지지됨으로써 상기 에어벤트(12)로 공기가 유입되는 것이 용이하게 된다.At this time, since the air vent ribs 14 are supported only on one side of the upper surface of the air vent 12, air can be easily introduced into the air vents 12.

그리고, 상기 에어벤트(12)에 공기 유입은 트레이의 적층 상태에서 분리시 상기 반도체소자(C)가 표면장력에 의해 흐트러짐이 방지되며, 상기 에어벤트리브(14)는 적층 상태에서 상기 반도체소자(C)의 좌우 이동을 막는 분리단 역할을 하게 된다.The air vent 12 is prevented from being disturbed by the surface tension when the tray is separated from the laminated state of the tray, and the air vent rib 14 is disposed on the semiconductor element C) to the left and right.

한편, 상기 외곽지지부(20)의 상단에 구비된 연통홈(21)은 마주보는 대응면에 서로 대칭되게 구비되거나, 서로 엇갈리게 설치되어, 적층상태의 분리가 용이하고 외부공기가 연통되는 공기 유로 역할을 하게 되어 상기 반도체소자(C)를 안정적으로 수납하여 이송이 용이해진다.On the other hand, the communication grooves 21 provided at the upper end of the outer frame support portion 20 are provided symmetrically with each other on opposite faces or are staggered with each other, so that the laminated state can be easily separated, So that the semiconductor device (C) can be stably stored and transported easily.

그리고, 상기 트레이의 적층시 상기 외곽지지부(20)의 적층연장단(22)이 칩안착부(10)의 외주면의 둘레를 감싸며 안착됨으로써, 적층작업을 안정적으로 수행할 수 있게 된다.
In addition, when the trays are stacked, the lamination extension ends 22 of the outer support portions 20 surround the outer circumferential surface of the chip seating portion 10 and are seated thereon, so that the stacking operation can be stably performed.

본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변형실시가 가능한 것은 물론이고, 그와 같은 변경은 청구범위 기재의 범위 내에 있게 된다.It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims and their equivalents. Of course, such modifications are within the scope of the claims.

<도면의 주요부분에 대한 부호의 설명>
10 : 칩안착부 11 : 포켓군
11a : 포켓 12 : 에어벤트
13 : 지지리브 14 : 에어벤트리브
20 : 외곽지지부 21 : 연통홈
22 : 적층연장단
C : 반도체소자Description of the Related Art
10: chip mounting part 11: pocket group
11a: Pocket 12: Air vent
13: Support ribs 14: Air vent ribs
20: outer frame portion 21: communicating groove
22:
C: Semiconductor device

Claims (5)

반도체소자(C)가 안착되도록 요입된 장방형상의 포켓(11a)이 일방향으로 군집된 사각형상의 포켓군(11)과, 상기 포켓(11a)이 양측으로 구분되도록 상기 포켓군(11)의 중앙 상면에서 하부 방향으로 요입된 장방형상의 에어벤트(12)가 다수개 구비된 칩안착부(10)와;
상기 칩안착부(10)의 외주면의 둘레를 따라 외측으로 연장된 외곽지지부(20)로 이루어지며,
상기 칩안착부(10)의 하부 저면에는 적층시 상기 포켓(11a)의 상부 선단에 지지되도록 하부 방향으로 연장된 다수개의 지지리브(13)와, 상기 에어벤트(12)의 일측 상면에 지지되도록 상기 지지리브(13)의 사이에서 하부 방향으로 더 돌출된 에어벤트리브(14)가 구비되며,
상기 외곽지지부(20)의 상단에는
상기 에어벤트(12)에 외부공기가 연통되도록 하부로 요입된 연통홈(21)이 구비된 것을 특징으로 하는 반도체소자 트레이.A rectangular pocket group 11 in which the rectangular pockets 11a recessed so as to seat the semiconductor element C are grouped in one direction and a rectangular pocket group 11 in which the pocket 11a is divided into two on the central upper surface of the pocket group 11 A chip mounting part (10) having a plurality of rectangular air bubbles (12) recessed in a downward direction;
And an outer frame portion 20 extending outward along the periphery of the chip seating portion 10,
A plurality of support ribs 13 extending downward to be supported at an upper end of the pocket 11a at the time of lamination and a plurality of support ribs 13 extending upwardly from the upper end of the pocket 11a to be supported on one upper surface of the air vent 12 An air vent rib 14 protruding further downward is provided between the support ribs 13,
At the upper end of the outer frame portion 20
Wherein the air vent (12) is provided with a communication groove (21) recessed downward so that external air can communicate with the air vent (12). 삭제delete 제 1항에 있어서,
상기 외곽지지부(20)의 하단에는
적층시 상기 칩안착부(10)의 외주면의 둘레를 감싸며 안착되도록 하부 방향으로 연장된 적층연장단(22)이 구비된 것을 특징으로 하는 반도체소자 트레이.The method according to claim 1,
At the lower end of the outer frame portion 20
(22) extending downward so as to surround and surround the periphery of the chip mounting part (10) when stacked. 제 1항에 있어서,
상기 연통홈(21)은 마주보는 대향면에 서로 엇갈리게 형성된 것을 특징으로 하는 반도체소자 트레이.The method according to claim 1,
Wherein the communication grooves (21) are formed to be offset from each other on opposing surfaces facing each other. 제 1항에 있어서,
상기 지지리브(13)는
적층시 상기 반도체소자(C)가 상부로 이탈되는 것을 방지토록 격자 형상으로 이루어진 것을 특징으로 하는 반도체소자 트레이.The method according to claim 1,
The support ribs 13
Wherein the semiconductor element is formed in a lattice shape to prevent the semiconductor element (C) from being separated upward when stacked.
KR1020160056383A 2016-05-09 2016-05-09 Semiconductor chip tray KR101710578B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007145358A (en) * 2005-11-25 2007-06-14 Nec Saitama Ltd Part housing tray
KR20110017735A (en) * 2009-08-14 2011-02-22 주식회사 에스.제이테크 Semiconductor chip tray
KR101549099B1 (en) * 2015-03-09 2015-09-03 주식회사 명성세미트론 Semiconductor chip tray
KR101632828B1 (en) * 2015-02-12 2016-06-23 주식회사 케이엠에이치하이텍 The chip tray device for semiconductor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007145358A (en) * 2005-11-25 2007-06-14 Nec Saitama Ltd Part housing tray
KR20110017735A (en) * 2009-08-14 2011-02-22 주식회사 에스.제이테크 Semiconductor chip tray
KR101632828B1 (en) * 2015-02-12 2016-06-23 주식회사 케이엠에이치하이텍 The chip tray device for semiconductor
KR101549099B1 (en) * 2015-03-09 2015-09-03 주식회사 명성세미트론 Semiconductor chip tray

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