TW201403704A - Method for forming semiconductor structure - Google Patents
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本發明關於一種半導體的製作，特別是關於一種半導體結構的形成方法。 This invention relates to the fabrication of a semiconductor, and more particularly to a method of forming a semiconductor structure.
隨著積體電路向次微米尺寸發展，器件的密集程度和技術的複雜程度不斷增加，對技術過程的嚴格控制變得更為重要。其中，通孔作為多層金屬層間互連以及器件有源區與外界電路之間的連接的通道，由於其在器件結構組成中具有的重要作用，使得通孔的形成技術歷來為本領域技術人員所重視。 As integrated circuits move toward sub-micron sizes, the density of devices and the complexity of the technology continue to increase, and strict control of the technical process becomes more important. Among them, the via hole serves as a channel for interconnecting the multilayer metal layers and the connection between the active region of the device and the external circuit. Due to its important role in the structural composition of the device, the formation technology of the via hole has been conventionally known to those skilled in the art. Pay attention to it.
圖1~圖3為習知通孔形成過程的結構示意圖。 1 to 3 are schematic structural views of a conventional through hole forming process.
參考圖1，提供半導體襯底100，在所述半導體襯底上形成待刻蝕材料層101，所述待刻蝕材料層101為單層結構或多層堆疊結構，例如：所述待刻蝕材料層101為氮化矽層和氧化矽層交替分佈的多層堆疊結構；在所述待刻蝕材料層101表面形成掩膜層102，所述掩膜層102具有暴露待刻蝕材料層101表面的開口103。 Referring to FIG. 1, a semiconductor substrate 100 is provided on which a material layer 101 to be etched is formed, and the material layer 101 to be etched is a single layer structure or a multilayer stack structure, for example, the material to be etched. The layer 101 is a multi-layered stack structure in which a tantalum nitride layer and a tantalum oxide layer are alternately distributed; a mask layer 102 is formed on the surface of the material layer 101 to be etched, and the mask layer 102 has a surface exposing the layer of the material to be etched 101. Opening 103.
參考圖2，採用等離子體刻蝕技術，沿開口103刻蝕所述待刻蝕材料層101，形成通孔104，等離子體刻蝕採用的氣體為CF4或C4F8。 Referring to FIG. 2, the material layer 101 to be etched is etched along the opening 103 by a plasma etching technique to form a via 104. The gas used for plasma etching is CF 4 or C 4 F 8 .
然而，在實際的生產發現，隨著器件的尺寸的縮小，通孔的尺寸也隨之縮小，尤其是採用習知的等離子體刻蝕技術在形成具有高的深寬比的通孔時，容易使形成的通孔104的側壁具有如圖3所述的波浪形缺陷。 However, in actual production, it has been found that as the size of the device is reduced, the size of the via hole is also reduced, especially when a conventional plasma etching technique is used to form a via hole having a high aspect ratio. The sidewall of the formed through hole 104 is made to have a wavy defect as described in FIG.
更多關於通孔的形成方法，請參考公開號為US2009/0224405A1的美國專利。 For more details on the formation of vias, please refer to US Patent Publication No. US 2009/0224405 A1.
本發明解決的問題是提供一種半導體結構的形成方法，使形成通孔的側壁具有較好的形貌。 The problem to be solved by the present invention is to provide a method of forming a semiconductor structure such that the sidewalls forming the via holes have a good topography.
為解決上述問題，本發明提供了一種半導體結構的形成方法，包括步驟：提供基底，在所述基底上形成氮化矽層和氧化矽層交替分佈的多層堆疊結構；對所述堆疊結構進行等離子體刻蝕，偏置功率源以脈衝的方式輸出偏置功率，當偏置功率源打開時，刻蝕部分所述堆疊結構，形成刻蝕孔，當偏置功率源關閉時，在已形成的刻蝕孔的側壁和底部形成聚合物，重複偏置功率源打開和偏置功率源關閉的過程，直至形成通孔。 In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising the steps of: providing a substrate on which a multilayer stack structure in which a tantalum nitride layer and a tantalum oxide layer are alternately distributed; and plasma deposition on the stacked structure The body etch, the bias power source outputs the bias power in a pulsed manner, and when the bias power source is turned on, etches part of the stacked structure to form an etched hole, and when the bias power source is turned off, the formed The sidewalls and the bottom of the etched holes form a polymer, and the process of turning off the bias power source to turn on and biasing the power source off is repeated until a via is formed.
可選的，所述堆疊結構的厚度大於等於1微米。 Optionally, the stacked structure has a thickness of 1 micrometer or more.
可選的，所述氮化矽層和氧化矽層交替分佈的次數大於等於8次。 Optionally, the tantalum nitride layer and the tantalum oxide layer are alternately distributed eight times or more.
可選的，所述等離子體刻蝕採用的氣體為碳氟氣體、碳氟氫氣體、氧氣和氬氣。 Optionally, the gas used in the plasma etching is a fluorocarbon gas, a fluorocarbon gas, an oxygen gas, and an argon gas.
可選的，所述碳氟氣體為C4F8、C4F6中的一種或幾種，所述碳氟氫氣體為CHF3、CH2F2、CH3F中的一種或幾種。 Optionally, the fluorocarbon gas is one or more of C 4 F 8 and C 4 F 6 , and the fluorocarbon gas is one or more of CHF 3 , CH 2 F 2 , and CH 3 F .
可選的，所述等離子體刻蝕的射頻功率源功率為500~4000瓦，射頻頻率為60~120兆赫茲，偏置功率源功率為2000~8000瓦，偏置頻率為2~15兆赫茲，刻蝕腔壓力為20~100毫托耳。 Optionally, the plasma etched RF power source has a power of 500 to 4000 watts, an RF frequency of 60 to 120 MHz, a bias power source of 2000 to 8000 watts, and a bias frequency of 2 to 15 MHz. The etching chamber pressure is 20~100 mTorr.
可選的，所述偏置功率源打開和關閉的頻率小於50千赫茲。 Optionally, the bias power source is turned on and off at a frequency less than 50 kHz.
可選的，所述等離子體刻蝕的一個脈衝週期內，所述偏置功 率源打開的時間為第一時間，所述偏置功率源關閉的時間為第二時間，第一時間與第一時間和第二時間之和的比值為占空比，等離子體刻蝕過程中，所述占空比保持不變。 Optionally, the biasing work is performed in one pulse period of the plasma etching The time when the rate source is turned on is the first time, and the time when the bias power source is turned off is the second time. The ratio of the first time to the sum of the first time and the second time is the duty ratio, during the plasma etching process. The duty cycle remains unchanged.
可選的，所述占空比的範圍為10%~90%。 Optionally, the duty ratio ranges from 10% to 90%.
可選的，所述等離子體刻蝕的一個脈衝週期內，所述偏置功率源打開的時間為第一時間，所述偏置功率源關閉的時間為第二時間，第一時間與第一時間和第二時間之和的比值為占空比，等離子體刻蝕過程中，所述占空比逐漸減小，每個脈衝週期內第一時間和第二時間之和保持不變。 Optionally, during one pulse period of the plasma etching, the bias power source is turned on for a first time, and the bias power source is turned off for a second time, the first time and the first time. The ratio of the sum of time and the second time is the duty cycle. During the plasma etching, the duty ratio is gradually decreased, and the sum of the first time and the second time in each pulse period remains unchanged.
可選的，等離子體刻蝕過程中，所述占空比隨著刻蝕時間的增大逐漸減小。 Optionally, during the plasma etching process, the duty ratio gradually decreases as the etching time increases.
可選的，等離子體刻蝕過程中，所述占空比隨著通孔刻蝕深度的增加逐漸減小。 Optionally, during the plasma etching process, the duty ratio gradually decreases as the depth of the via etch increases.
可選的，所述占空比的減小為階梯式的減小。 Optionally, the reduction in the duty cycle is a stepwise reduction.
可選的，所述占空比階梯式減小時，相鄰階梯間的占空比的減小幅度相同或不同。 Optionally, when the duty ratio is stepwise reduced, the duty ratios between adjacent steps are reduced by the same or different.
可選的，所述占空比從90%逐漸減小到10%。 Optionally, the duty cycle is gradually reduced from 90% to 10%.
可選的，進行等離子體刻蝕時，首先採用占空比不變的等離子體刻蝕所述堆疊結構，形成第一刻蝕孔，接著沿第一刻蝕孔，採用占空比不斷減小的等離子體刻蝕堆疊結構，形成第二刻蝕孔，第一刻蝕孔和第二刻蝕孔構成通孔。 Optionally, when plasma etching is performed, the stacked structure is first etched by plasma with a constant duty cycle to form a first etched hole, and then the duty ratio is continuously reduced along the first etched hole. The plasma etch stack structure forms a second etched hole, and the first etched hole and the second etched hole constitute a through hole.
可選的，所述第一刻蝕孔的深度為通孔深度的30%~60%。 Optionally, the depth of the first etched hole is 30% to 60% of the depth of the through hole.
可選的，對所述堆疊結構進行等離子體刻蝕之前，採用連續等離子體刻蝕技術刻蝕所述堆疊結構，形成第三刻蝕孔，接著沿第三刻蝕孔對堆疊結構進行偏置功率源以脈衝的方式輸出偏置功率的等離子體刻 蝕，形成第四刻蝕孔，第三刻蝕孔和第四刻蝕孔構成通孔。 Optionally, before the plasma etching of the stacked structure, the stacked structure is etched by a continuous plasma etching technique to form a third etched hole, and then the stacked structure is biased along the third etched hole. Plasma source that outputs bias power in a pulsed manner The etch forms a fourth etched hole, and the third etched hole and the fourth etched hole constitute a through hole.
可選的，所述第三刻蝕孔的深度為通孔深度的10%~50%。 Optionally, the third etched hole has a depth of 10% to 50% of the through hole depth.
可選的，所述偏置功率源以脈衝的方式輸出偏置功率的等離子體刻蝕為占空比不變的等離子體刻蝕或占空比不斷減小的等離子體刻蝕。 Optionally, the bias power source pulsates the plasma output of the bias power to a duty cycle plasma etching or a duty cycle decreasing plasma etching.
可選的，所述通孔的深寬比為15：1~100：1。 Optionally, the through hole has an aspect ratio of 15:1 to 100:1.
可選的，所述堆疊結構的表面還形成有掩膜層。 Optionally, a surface of the stacked structure is further formed with a mask layer.
與習知技術相比，本發明技術方案具有以下優點： 採用偏置功率源以脈衝的方式輸出偏置功率的等離子體刻蝕技術刻蝕氮化矽層和氧化矽層交替分佈的多層堆疊結構，形成通孔，由於刻蝕步驟和聚合物形成步驟交替進行，刻蝕形成部分深度的刻蝕孔後，會相應的在刻蝕孔的側壁形成聚合物，後續沿刻蝕孔繼續刻蝕堆疊結構時，保護已形成的刻蝕孔不會被過刻蝕，從而使最終形成的通孔保持垂直的側壁形貌。 Compared with the prior art, the technical solution of the present invention has the following advantages: A plasma etching technique that uses a bias power source to output a bias power in a pulsed manner etches a multilayer stack structure in which a tantalum nitride layer and a tantalum oxide layer are alternately arranged to form via holes, which are alternated by an etching step and a polymer formation step. After etching and forming a partially deep etched hole, a polymer is formed on the sidewall of the etched hole, and when the etched hole continues to etch the stacked structure, the formed etched hole is not overetched. The etch causes the resulting via to maintain a vertical sidewall topography.
進一步，採用占空比不斷減小的等離子體刻蝕，隨著刻蝕過程的進行，由於占空比的不斷減小，一個脈衝週期內，偏置功率源打開的時間變短，即刻蝕步驟的時間在減少，聚合物形成步驟的時間在增加，從而保證刻蝕孔深度增加時，刻蝕孔的側壁形成一定量的聚合物。 Further, by using a plasma etching with a decreasing duty cycle, as the etching process progresses, the bias power source is turned on for a short period of time, that is, the etching step, due to the continuous reduction of the duty ratio. The time is decreasing and the time for the polymer formation step is increased to ensure that the sidewalls of the etched holes form a certain amount of polymer when the depth of the etched holes is increased.
更進一步，採用占空比不變的等離子體刻蝕形成的第一刻蝕孔，接著採用占空比不斷減小的等離子體刻蝕沿第一刻蝕孔繼續刻蝕堆疊結構，直至形成通孔，在使形成的通孔的側壁具有較好的形貌，減小了通孔的刻蝕時間，提高了效率。 Further, the first etch hole formed by plasma etching with constant duty ratio is used, and then the plasma etch with decreasing duty ratio is continued to etch the stacked structure along the first etch hole until the pass is formed. The hole has a better shape on the sidewall of the formed through hole, which reduces the etching time of the through hole and improves the efficiency.
再進一步，採用連續等離子刻蝕形成第三刻蝕孔後，接著採用偏置功率源以脈衝的方式輸出偏置功率的等離子體刻蝕沿第三刻蝕孔刻蝕堆疊結構，直至形成通孔，使形成的通孔具有較好的側壁形貌的同時， 減少可刻蝕時間，提高了效率。 Further, after the third etching hole is formed by continuous plasma etching, the plasma etching of the bias power is outputted by the bias power source to etch the stacked structure along the third etching hole until the through hole is formed. , so that the formed through holes have a better sidewall morphology, Reduce etchable time and increase efficiency.
100‧‧‧半導體襯底 100‧‧‧Semiconductor substrate
101‧‧‧待刻蝕材料層 101‧‧‧ layer of material to be etched
102‧‧‧掩膜層 102‧‧‧ mask layer
103‧‧‧開口 103‧‧‧ openings
104‧‧‧通孔 104‧‧‧through hole
200‧‧‧基底 200‧‧‧Base
201‧‧‧氮化矽層 201‧‧‧ layer of tantalum nitride
202‧‧‧氧化矽層 202‧‧‧Oxide layer
203‧‧‧掩膜層 203‧‧ ‧ mask layer
204‧‧‧堆疊結構 204‧‧‧Stack structure
205‧‧‧開口 205‧‧‧ openings
206‧‧‧刻蝕孔 206‧‧‧ etching holes
207‧‧‧聚合物 207‧‧‧ polymer
208‧‧‧通孔 208‧‧‧through hole
300‧‧‧基底 300‧‧‧Base
301‧‧‧氮化矽層 301‧‧‧ layer of tantalum nitride
302‧‧‧氧化矽層 302‧‧‧Oxide layer
303‧‧‧掩膜層 303‧‧ ‧ mask layer
304‧‧‧堆疊結構 304‧‧‧Stack structure
305‧‧‧開口 305‧‧‧ openings
306‧‧‧刻蝕孔 306‧‧‧ etching holes
307‧‧‧聚合物 307‧‧‧ polymer
308‧‧‧通孔 308‧‧‧through hole
400‧‧‧基底 400‧‧‧Base
401‧‧‧氮化矽層 401‧‧‧ nitride layer
402‧‧‧氧化矽層 402‧‧‧Oxide layer
403‧‧‧掩膜層 403‧‧‧ mask layer
404‧‧‧堆疊結構 404‧‧‧Stack structure
405‧‧‧開口 405‧‧‧ openings
406‧‧‧第一刻蝕孔 406‧‧‧First etched hole
407‧‧‧聚合物 407‧‧‧ polymer
408‧‧‧通孔 408‧‧‧through hole
500‧‧‧基底 500‧‧‧Base
501‧‧‧氮化矽層 501‧‧‧ nitride layer
502‧‧‧氧化矽層 502‧‧‧Oxide layer
503‧‧‧掩膜層 503‧‧ ‧ mask layer
504‧‧‧堆疊結構 504‧‧‧Stack structure
505‧‧‧開口 505‧‧‧ openings
506‧‧‧第三刻蝕孔 506‧‧‧3rd etched hole
507‧‧‧聚合物 507‧‧‧ polymer
508‧‧‧通孔 508‧‧‧through hole
圖1~圖3為習知通孔形成過程的結構示意圖；圖4為本發明第一實施例半導體結構的形成方法的流程示意圖；圖5~圖8為本發明第一實施例半導體結構的形成過程的剖面結構示意圖；圖9為本發明第二實施例半導體結構的形成方法的流程示意圖；圖10~13為本發明第二實施例半導體結構形成過程的剖面結構示意圖；圖14為本發明第三實施例半導體結構的形成方法的流程示意圖；圖15~圖17為本發明第三實施例半導體結構的形成過程的剖面結構示意圖；圖18為本發明第四實施例半導體結構的形成方法的流程示意圖；圖19~圖21為本發明第四實施例半導體結構的形成過程的剖面結構示意圖。 1 to 3 are schematic structural views of a conventional via forming process; FIG. 4 is a schematic flow chart showing a method of forming a semiconductor structure according to a first embodiment of the present invention; and FIGS. 5-8 are a semiconductor structure according to a first embodiment of the present invention. FIG. 9 is a schematic flow chart of a method for forming a semiconductor structure according to a second embodiment of the present invention; and FIGS. 10-13 are schematic cross-sectional views showing a semiconductor structure forming process according to a second embodiment of the present invention; 3 is a schematic flow chart of a method for forming a semiconductor structure according to a third embodiment of the present invention; and FIG. 18 is a flow chart showing a method for forming a semiconductor structure according to a fourth embodiment of the present invention; FIG. 19 to FIG. 21 are schematic cross-sectional structural views showing a process of forming a semiconductor structure according to a fourth embodiment of the present invention.
發明人在習知採用等離子刻蝕形成通孔的過程中發現，隨著刻蝕的通孔的深寬比的不斷變大，進入到刻蝕孔內的活性刻蝕成分會越來越少，會導致刻蝕的速率越來越慢，這時需要提高偏置功率來促進刻蝕孔內的氣體的交換，以增加刻蝕孔的刻蝕速率，但是隨著刻蝕深度的增加，活性刻蝕成分會對孔的側壁造成過刻蝕，特別是在氮化矽和氧化矽的交替分佈的多層堆疊結構中，對氧化矽層的刻蝕偏向於反應離子刻蝕，即先在氧化層表面形成氟碳的聚合物，然後等離子體中的正離子物理轟擊提供能量，使聚合物與氧化矽進行反應，完成刻蝕，而對氮化矽層的刻蝕則偏向於化學刻蝕，主要是通過含氟的自由基刻蝕氮化矽層，因此採用習知的等離子體刻蝕技術刻蝕氮化矽和氧化矽的交替分佈的多層堆疊結構時，隨著 刻蝕孔刻蝕深度的增加，氮化矽層的過刻蝕現象會加重，從而形成波浪形的通孔側壁形貌，後續形成金屬互連結構時，影響互連結構的穩定性。 In the process of forming a via hole by plasma etching, the inventors have found that as the aspect ratio of the etched via hole becomes larger, the active etching component entering the etched hole becomes less and less. The rate of etching will be slower and slower. At this time, the bias power needs to be increased to promote the exchange of gas in the etching hole to increase the etching rate of the etching hole. However, as the etching depth increases, the active etching increases. The composition causes over-etching of the sidewalls of the holes, especially in a multi-layer stack structure in which the tantalum nitride and the tantalum oxide are alternately distributed, and the etching of the tantalum oxide layer is biased toward reactive ion etching, that is, first on the surface of the oxide layer. The fluorocarbon polymer, then the physical ion bombardment in the plasma provides energy, reacts the polymer with cerium oxide to complete the etching, and the etching of the tantalum nitride layer is biased toward chemical etching, mainly through The fluorine-containing radical etches the tantalum nitride layer, so when a conventional plasma etching technique is used to etch an alternately stacked multilayer stack of tantalum nitride and tantalum oxide, When the etching depth of the etching hole is increased, the over-etching phenomenon of the tantalum nitride layer is aggravated, thereby forming a wave-shaped sidewall shape of the via hole, and the subsequent formation of the metal interconnection structure affects the stability of the interconnection structure.
為此發明人提出一種半導體結構的形成方法，參考圖4，圖4為本發明第一實施例半導體結構的形成方法的流程示意圖，包括：步驟S21，提供基底，在所述基底上形成氮化矽層和氧化矽層交替分佈的多層堆疊結構，在所述堆疊結構表面形成掩膜層，所述掩膜層具有暴露堆疊結構表面的開口；步驟S22，對所述堆疊結構進行等離子體刻蝕，偏置功率源以脈衝的方式輸出偏置功率，所述等離子體刻蝕為占空比保持不變的等離子體刻蝕，當偏置功率源打開時，刻蝕部分所述堆疊結構，形成刻蝕孔，當偏置功率源關閉時，在已形成的刻蝕孔的側壁和底部形成聚合物，重複偏置功率源打開和偏置功率源關閉的過程，直至形成通孔。 For this reason, the inventors have proposed a method for forming a semiconductor structure. Referring to FIG. 4, FIG. 4 is a schematic flow chart of a method for forming a semiconductor structure according to a first embodiment of the present invention, comprising: step S21, providing a substrate, forming a nitride on the substrate a multilayer stack structure in which a tantalum layer and a tantalum oxide layer are alternately distributed, a mask layer is formed on the surface of the stacked structure, the mask layer has an opening exposing a surface of the stacked structure; and in step S22, the stacked structure is plasma-etched The bias power source outputs the bias power in a pulsed manner, the plasma etching is a plasma etching in which the duty ratio remains unchanged, and when the bias power source is turned on, the portion of the stacked structure is etched to form The holes are etched to form a polymer at the sidewalls and bottom of the formed etched holes when the bias power source is turned off, repeating the process of biasing the power source to turn on and biasing the power source off until a via is formed.
圖5~圖8為本發明第一實施例半導體結構的形成過程的剖面結構示意圖。 5 to 8 are schematic cross-sectional views showing a process of forming a semiconductor structure according to a first embodiment of the present invention.
參考圖5，提供基底200，在所述基底200上形成氮化矽層201和氧化矽層202交替分佈的多層堆疊結構204，在所述堆疊結構204表面形成掩膜層203，所述掩膜層203具有暴露堆疊結構204表面的開口205。 Referring to FIG. 5, a substrate 200 is provided on which a multilayer stack structure 204 in which a tantalum nitride layer 201 and a tantalum oxide layer 202 are alternately distributed is formed, and a mask layer 203 is formed on the surface of the stacked structure 204, the mask Layer 203 has an opening 205 that exposes the surface of stack structure 204.
所述基底200為矽襯底、鍺襯底、矽鍺襯底、碳化矽襯底、氮化鎵襯底其中的一種。所述基底200內形成有離子摻雜區、矽通孔等(圖中未示出)；所述基底200上還可以形成電晶體、電阻、電容、記憶體等半導體器件(圖中未示出)。 The substrate 200 is one of a germanium substrate, a germanium substrate, a germanium substrate, a tantalum carbide substrate, and a gallium nitride substrate. An ion doping region, a germanium via hole, or the like (not shown) is formed in the substrate 200; a semiconductor device such as a transistor, a resistor, a capacitor, or a memory may be formed on the substrate 200 (not shown in the drawing) ).
在本發明的其他實施例中，所述基底200上還形成有一層或多層層間介質層(圖中未示出)，所述層間介質層的材料為氧化矽、低K介電材料或超低K介電材料，所述介質層中形成有金屬互連線、導電插塞等半導體結構。 In other embodiments of the present invention, the substrate 200 is further formed with one or more interlayer dielectric layers (not shown), and the interlayer dielectric layer is made of yttria, low-k dielectric material or ultra-low a K dielectric material in which a semiconductor structure such as a metal interconnection or a conductive plug is formed.
所述堆疊結構204為氮化矽層201和氧化矽層202交替分佈的多層結構，本實施例中，形成堆疊結構204具體過程為：在基底表面形成第一氮化矽層，接著在第一氮化矽層表面形成第一氧化矽層，然後在第一氧化矽層表面形成第二氮化矽層，在第二氮化矽層表面形成第二氧化矽層，依次類推，多次交替後，形成堆疊結構204。所述堆疊結構204的厚度大於等於1微米，所述氮化矽層201和氧化矽層202的交替的次數大於等於8次。所述堆疊結構用於DRAM元件，採用多層堆疊結構可以增加材料的K值，從而改進電容器存儲電子的性能。 The stack structure 204 is a multi-layer structure in which the tantalum nitride layer 201 and the tantalum oxide layer 202 are alternately distributed. In this embodiment, the stack structure 204 is formed by forming a first tantalum nitride layer on the surface of the substrate, and then in the first Forming a first tantalum oxide layer on the surface of the tantalum nitride layer, then forming a second tantalum nitride layer on the surface of the first tantalum oxide layer, forming a second tantalum oxide layer on the surface of the second tantalum nitride layer, and so on, after multiple alternations Forming a stacked structure 204. The thickness of the stacked structure 204 is greater than or equal to 1 micrometer, and the number of alternating layers of the tantalum nitride layer 201 and the tantalum oxide layer 202 is greater than or equal to 8 times. The stacked structure is used for DRAM components, and the multi-layer stacked structure can increase the K value of the material, thereby improving the performance of the capacitor storage electrons.
在本發明的其他實施例中，形成交疊結構時，所述氮化矽層位於氧化矽層表面。 In other embodiments of the invention, the tantalum nitride layer is on the surface of the tantalum oxide layer when the overlapping structure is formed.
所述掩膜層203的材料為無定形碳或光刻膠，作為後續刻蝕堆疊結構204時的掩膜，通過圖形化所述掩膜層203在掩膜層203中形成暴露堆疊結構204表面的開口205，所述開口205的位置與後續堆疊結構204中形成的通孔的位置相對應。 The material of the mask layer 203 is amorphous carbon or photoresist. As a mask for subsequently etching the stacked structure 204, the surface of the exposed stacked structure 204 is formed in the mask layer 203 by patterning the mask layer 203. The opening 205 has a position corresponding to the position of the through hole formed in the subsequent stacked structure 204.
參考圖6，對所述堆疊結構204進行等離子體刻蝕，偏置功率源以脈衝的方式週期性的輸出偏置功率，即偏置功率源間隔的打開或關閉，偏置功率源打開時有偏置功率輸出，偏置功率源關閉時沒有偏置功率輸出，偏置功率源打開和相鄰的關閉的過程為一個脈衝週期，所述偏置功率源打開的時間為第一時間，所述偏置功率源關閉的時間為第二時間，第一時間與第一時間和第二時間之和的比值為占空比，本實施例中，等離子體刻蝕過程中，每一個脈衝週期中所述占空比保持不變，即所述等離子體刻蝕為占空比保持不變的等離子體刻蝕。本實施例中，等離子體刻蝕時，射頻功率源以連續的方式輸出射頻功率，在本發明的其他實施例中，射頻功率源以脈衝的方式輸出射頻功率。 Referring to FIG. 6, the stack structure 204 is plasma etched, and the bias power source periodically outputs the bias power in a pulse manner, that is, the bias power source interval is turned on or off, and the bias power source is turned on. The bias power output has no bias power output when the bias power source is off, the bias power source is turned on and the adjacent shutdown process is one pulse period, and the bias power source is turned on for the first time, The time when the bias power source is turned off is the second time, and the ratio of the first time to the sum of the first time and the second time is the duty ratio. In this embodiment, in the plasma etching process, each pulse period is The duty cycle remains the same, ie the plasma etch is a plasma etch with a constant duty cycle. In this embodiment, during plasma etching, the RF power source outputs RF power in a continuous manner. In other embodiments of the invention, the RF power source outputs RF power in a pulsed manner.
需要說明的是，本實施例以及後續實施例中進行等離子體刻 蝕採用的刻蝕裝置可以是電感耦合等離子體刻蝕裝置(ICP)也可以是電容耦合等離子體刻蝕裝置(CCP)，電感耦合等離子體刻蝕裝置和電容耦合等離子體刻蝕裝置提供的射頻功率源頻率大於等於27兆赫茲，偏置功率源頻率小於等於15兆赫茲。當所述刻蝕裝置為電容耦合等離子體刻蝕裝置時，射頻功率源可以施加在上電極上或者施加在上下電極上，用於產生射頻功率，電離刻蝕氣體，產生等離子體，並控制等離子體的密度；偏置功率源施加在下電極，用於產生偏置功率，影響鞘層特性(鞘層電壓或加速電壓)，並控制等離子體的能量分佈。當所述刻蝕裝置為電感耦合等離子體刻蝕裝置時，射頻功率源可以施加在電感線圈，用於產生射頻功率，電離刻蝕氣體，產生等離子體，並控制等離子體的密度；偏置功率源施加在下電極，用於產生偏置功率，影響鞘層特性(鞘層電壓或加速電壓)，並控制等離子體的能量分佈。 It should be noted that plasma etching is performed in this embodiment and subsequent embodiments. The etching device used for the etching may be an inductively coupled plasma etching device (ICP) or a capacitively coupled plasma etching device (CCP), an inductively coupled plasma etching device, and a capacitively coupled plasma etching device. The power source frequency is greater than or equal to 27 MHz, and the bias power source frequency is less than or equal to 15 MHz. When the etching device is a capacitively coupled plasma etching device, a radio frequency power source may be applied to the upper electrode or applied to the upper and lower electrodes for generating radio frequency power, ionizing the etching gas, generating a plasma, and controlling the plasma. The density of the body; a bias power source is applied to the lower electrode for generating bias power, affecting sheath properties (sheath voltage or accelerating voltage), and controlling the energy distribution of the plasma. When the etching device is an inductively coupled plasma etching device, a radio frequency power source can be applied to the inductor coil for generating radio frequency power, ionizing the etching gas, generating a plasma, and controlling the density of the plasma; bias power A source is applied to the lower electrode for generating bias power, affecting sheath properties (sheath voltage or accelerating voltage), and controlling the energy distribution of the plasma.
所述等離子體刻蝕的射頻功率源功率為500~4000瓦，射頻頻率為60~120兆赫茲，偏置功率源功率為2000~8000瓦，偏置頻率為2~15兆赫茲，刻蝕腔壓力為20~100毫托耳，所述偏置功率源打開和關閉的頻率小於50千赫茲，所述占空比的範圍為10%~90%，較佳的，所述占空比的範圍為40%~60%，在進行等離子體刻蝕時，在提高刻蝕效率的同時，保證已形成的刻蝕孔的側壁形成足量的聚合物，保護側壁不會被過刻蝕。 The plasma etched RF power source has a power of 500 to 4000 watts, an RF frequency of 60 to 120 MHz, a bias power source of 2000 to 8000 watts, and an offset frequency of 2 to 15 MHz. The pressure is 20~100 mTorr, the bias power source is turned on and off at a frequency less than 50 kHz, and the duty cycle ranges from 10% to 90%. Preferably, the duty cycle ranges. 40%~60%, in the plasma etching, while improving the etching efficiency, the sidewall of the formed etched hole is formed to form a sufficient amount of polymer, and the protective sidewall is not overetched.
在等離子體刻蝕的一個脈衝週期內，包括刻蝕步驟和聚合物形成步驟，參考圖6，射頻功率電離刻蝕氣體形成等離子體，當偏置功率源打開時進行刻蝕步驟，刻蝕部分所述堆疊結構，形成刻蝕孔206，接著參考圖7，當偏置功率源關閉時，進行聚合物形成步驟，在已形成的刻蝕孔206的側壁和底部形成聚合物207，所述聚合物207在後續沿刻蝕孔206刻蝕堆疊結構204時保護刻蝕孔206的側壁不會被刻蝕到，底部的聚合物在後續刻蝕步驟中被去除。 In one pulse period of the plasma etching, including an etching step and a polymer forming step, referring to FIG. 6, the RF power ionizing etching gas forms a plasma, and when the bias power source is turned on, an etching step is performed, and the etching portion is performed. The stacked structure forms an etched hole 206. Referring to FIG. 7, when the bias power source is turned off, a polymer forming step is performed to form a polymer 207 at the sidewall and bottom of the formed etched hole 206. The material 207 protects the sidewalls of the etched holes 206 from being etched when the stacked structure 204 is subsequently etched along the etched holes 206, and the polymer at the bottom is removed in a subsequent etching step.
所述等離子體刻蝕採用的氣體為碳氟氣體、碳氟氫氣體、氧氣(O2)和氬氣(Ar)，所述碳氟氣體為C4F8、C4F6中的一種或幾種，所述碳氟氫氣體為CHF3、CH2F2、CH3F中的一種或幾種，CHF3、CH2F2、CH3F用於提高聚合物濃度，O2用於控制聚合物的量，CO用於控制氟碳的比例，Ar用於形成正離子，提供反應的能量。 The gas used in the plasma etching is a fluorocarbon gas, a fluorocarbon gas, an oxygen gas (O 2 ), and an argon gas (Ar), and the fluorocarbon gas is one of C 4 F 8 and C 4 F 6 or some of the hydrogen gas to fluorocarbon CHF 3, CH 2 F 2, CH 3 F in one or more of, CHF 3, CH 2 F 2, CH 3 F for increasing polymer concentration, O 2 for The amount of polymer is controlled, CO is used to control the proportion of fluorocarbon, and Ar is used to form positive ions, providing the energy of the reaction.
本實施例中所述等離子體刻蝕採用的氣體為C4F8、C4F6、CHF3、CH2F2、CH3F、O2和Ar的混合氣體，以保證等離子體刻蝕過程中，在已形成的刻蝕孔側壁形成足夠的聚合物。射頻功率源打開，偏置功率源也打開時，進行刻蝕步驟，C4F6、C4F8、CHF3、CH2F2、CH3F等會被射頻功率電離生成氟自由基、中性的CF2等分子碎片，同時也會生成一些正離子，如：CF3 +等，Ar也會失去電子生成Ar+正離子，正離子經過等離子體鞘層(plasma sheath)和偏置功率的加速，會轟擊待刻蝕材料，去除部分待刻蝕材料，同時F自由基也會和待刻蝕材料發生化學反應，去除部分待刻蝕材料；當射頻功率源保持打開，而偏置功率源關閉時，此時腔室內還存在刻蝕步驟殘留的部分活性基團或新形成活性基團，而中性的活性成分如CF2等會複合生成氟碳聚合物沉積在刻蝕孔的側壁和底部表面，由於偏置功率源關閉，不存在加速電場或加速電場減小，正離子不會轟擊形成的聚合物或只會去除部分形成的聚合物，使形成的聚合物全部或部分得以保存，後續繼續刻蝕時保護已形成的刻蝕孔的側壁不會被過刻蝕。 The gas used in the plasma etching in this embodiment is a mixed gas of C 4 F 8 , C 4 F 6 , CHF 3 , CH 2 F 2 , CH 3 F, O 2 and Ar to ensure plasma etching. During the process, sufficient polymer is formed on the sidewalls of the etched holes that have been formed. When the RF power source is turned on and the bias power source is also turned on, the etching step is performed, and C 4 F 6 , C 4 F 8 , CHF 3 , CH 2 F 2 , C H3 F, etc. are ionized by the RF power to generate fluorine radicals. Neutral molecular fragments such as CF 2 will also generate some positive ions, such as CF 3 +, etc., Ar will also lose electrons to form Ar + positive ions, positive ions pass through plasma sheath and bias power. The acceleration will bombard the material to be etched, remove some of the material to be etched, and the F radical will also chemically react with the material to be etched to remove some of the material to be etched; when the RF power source remains open, the bias power When the source is turned off, there are still some active groups or newly formed active groups remaining in the etching step in the chamber, and a neutral active ingredient such as CF 2 is compounded to form a fluorocarbon polymer deposited on the sidewall of the etched hole. And the bottom surface, because the bias power source is off, there is no acceleration electric field or the acceleration electric field is reduced, the positive ions will not bombard the formed polymer or only partially form the polymer, so that all or part of the formed polymer can be preserved. Follow-up The sidewalls of the etched holes that have been formed during the etch are not overetched.
參考圖8，重複上述刻蝕步驟和聚合物的形成步驟，沿刻蝕孔206(參考圖7)刻蝕所述堆疊結構204，直至形成通孔208。 Referring to FIG. 8, the above etching step and polymer forming step are repeated, and the stacked structure 204 is etched along the etching hole 206 (refer to FIG. 7) until the via hole 208 is formed.
所述通孔208的深寬比為15：1~100：1，形成高的深寬比的通孔208時，偏置功率源以脈衝的方式週期性的輸出偏置功率，偏置功率的占空比保持不變，由於刻蝕步驟和聚合物形成步驟交替進行，刻蝕形成部分深度的刻蝕孔後，會相應的在刻蝕孔的側壁形成聚合物，後續沿刻蝕孔 繼續刻蝕堆疊結構時，保護已形成的刻蝕孔不會被過刻蝕，從而使最終形成的通孔208保持垂直的側壁形貌。 The through hole 208 has an aspect ratio of 15:1 to 100:1, and when the through hole 208 of the high aspect ratio is formed, the bias power source periodically outputs the bias power in a pulse manner, and the bias power is The duty ratio remains unchanged. Since the etching step and the polymer forming step are alternately performed, after etching to form a partially deep etching hole, a polymer is formed on the sidewall of the etching hole correspondingly, and the subsequent etching hole is formed. As the etched stack structure continues, the etched vias that have been formed are protected from overetching, thereby maintaining the resulting via 208 with a vertical sidewall topography.
第二實施例 Second embodiment
參考圖9，圖9為本發明第二實施例半導體結構的形成方法的流程示意圖，包括：步驟S31，提供基底，在所述基底上形成氮化矽層和氧化矽層交替分佈的多層堆疊結構，在所述堆疊結構表面形成掩膜層，所述掩膜層具有暴露堆疊結構表面的開口；步驟S32，對所述堆疊結構進行等離子體刻蝕，偏置功率源以脈衝的方式輸出偏置功率，所述等離子體刻蝕為占空比不斷減小的等離子體刻蝕，當偏置功率源打開時，刻蝕部分所述堆疊結構，形成刻蝕孔，當偏置功率源關閉時，在已形成的刻蝕孔的側壁和底部形成聚合物，重複偏置功率源打開和偏置功率源關閉的過程，直至形成通孔。 9 is a schematic flow chart of a method for forming a semiconductor structure according to a second embodiment of the present invention, comprising: step S31, providing a substrate on which a multilayer stack structure in which a tantalum nitride layer and a tantalum oxide layer are alternately distributed is formed on the substrate. Forming a mask layer on the surface of the stacked structure, the mask layer having an opening exposing a surface of the stacked structure; in step S32, performing plasma etching on the stacked structure, and biasing the power source to output the bias in a pulse manner Power, the plasma etching is a plasma etching with decreasing duty ratio, and when the bias power source is turned on, etching part of the stacked structure to form an etching hole, when the bias power source is turned off, A polymer is formed at the sidewalls and bottom of the formed etched holes, and the process of biasing the power source to turn on and biasing the power source off is repeated until a via is formed.
圖10~13為本發明第二實施例半導體結構形成過程的剖面結構示意圖。 10 to 13 are schematic cross-sectional views showing a process of forming a semiconductor structure according to a second embodiment of the present invention.
參考圖10，提供基底300，在所述基底300上形成氮化矽層301和氧化矽層302交替分佈的多層堆疊結構304，在所述堆疊結構304表面形成掩膜層303，所述掩膜層303具有暴露堆疊結構304表面的開口305。 Referring to FIG. 10, a substrate 300 is provided on which a multilayer stack structure 304 in which a tantalum nitride layer 301 and a tantalum oxide layer 302 are alternately distributed is formed, and a mask layer 303 is formed on a surface of the stacked structure 304, the mask Layer 303 has an opening 305 that exposes the surface of stack structure 304.
所述基底300為矽襯底、鍺襯底、矽鍺襯底、碳化矽襯底、氮化鎵襯底其中的一種。所述基底300內形成有離子摻雜區、矽通孔(圖中未示出)等；所述基底300上還可以形成電晶體、電阻、電容、記憶體等半導體器件(圖中未示出)。 The substrate 300 is one of a germanium substrate, a germanium substrate, a germanium substrate, a tantalum carbide substrate, and a gallium nitride substrate. An ion doping region, a through hole (not shown), and the like are formed in the substrate 300; a semiconductor device such as a transistor, a resistor, a capacitor, or a memory may be formed on the substrate 300 (not shown in the drawing) ).
在本發明的其他實施例中，所述基底300上還形成有一層或多層層間介質層(圖中未示出)，所述層間介質層的材料為氧化矽、低K介電材料或超低K介電材料，所述介質層中形成有金屬互連線、導電插塞等 半導體結構。 In other embodiments of the present invention, the substrate 300 is further formed with one or more interlayer dielectric layers (not shown), and the interlayer dielectric layer is made of yttria, low-k dielectric material or ultra-low a K dielectric material in which metal interconnect lines, conductive plugs, etc. are formed Semiconductor structure.
所述堆疊結構304為氮化矽層301和氧化矽層302交替分佈的多層結構，本實施例中，形成堆疊結構304具體過程為：先在基底表面形成第一氮化矽層，接著在第一氮化矽層表面形成第一氧化矽層，然後在第一氧化矽層表面形成第二氮化矽層，在第二氮化矽層表面形成第二氧化矽層，依次類推，多次交替後，形成堆疊結構304。所述堆疊結構304的厚度大於等於1微米，所述氮化矽層301和氧化矽層302的交替的次數大於等於8次。 The stack structure 304 is a multi-layer structure in which the tantalum nitride layer 301 and the tantalum oxide layer 302 are alternately distributed. In this embodiment, the stack structure 304 is formed by first forming a first tantalum nitride layer on the surface of the substrate, and then Forming a first tantalum oxide layer on the surface of the tantalum nitride layer, then forming a second tantalum nitride layer on the surface of the first tantalum oxide layer, forming a second tantalum oxide layer on the surface of the second tantalum nitride layer, and so on, and alternately Thereafter, a stacked structure 304 is formed. The thickness of the stacked structure 304 is greater than or equal to 1 micrometer, and the number of alternating layers of the tantalum nitride layer 301 and the tantalum oxide layer 302 is greater than or equal to 8 times.
在本發明的其他實施例中，形成交疊結構時，所述氮化矽層位於氧化矽層表面。 In other embodiments of the invention, the tantalum nitride layer is on the surface of the tantalum oxide layer when the overlapping structure is formed.
參考圖11，對所述堆疊結構304進行等離子體刻蝕，偏置功率源以脈衝的方式週期性的輸出偏置功率，偏置功率源打開時有偏置功率輸出，偏置功率源關閉時沒有偏置功率輸出，偏置功率源打開和相鄰的關閉的過程為一個脈衝週期，所述偏置功率源打開的時間為第一時間，所述偏置功率源關閉的時間為第二時間，第一時間與第一時間和第二時間之和的比值為占空比。本實施例中，等離子體刻蝕過程中，所述偏置功率源輸出脈衝的占空比逐漸減小，每個脈衝週期內第一時間和第二時間之和保持不變。本實施例中，等離子體刻蝕時，射頻功率源以連續的方式輸出射頻功率，在本發明的其他實施例中，射頻功率源以脈衝的方式輸出射頻功率。 Referring to FIG. 11, the stack structure 304 is plasma etched, and the bias power source periodically outputs a bias power in a pulse manner. When the bias power source is turned on, there is a bias power output, and when the bias power source is turned off, Without bias power output, the bias power source is turned on and the adjacent shutdown process is one pulse period, the bias power source is turned on for the first time, and the bias power source is turned off for the second time. The ratio of the first time to the sum of the first time and the second time is the duty cycle. In this embodiment, during the plasma etching process, the duty ratio of the output pulse of the bias power source is gradually decreased, and the sum of the first time and the second time in each pulse period remains unchanged. In this embodiment, during plasma etching, the RF power source outputs RF power in a continuous manner. In other embodiments of the invention, the RF power source outputs RF power in a pulsed manner.
採用第一實施例的占空比不變的等離子體刻蝕方法形成通孔時，發明人發現，隨著刻蝕孔深度的增加，刻蝕孔側壁形成的聚合物的量會逐漸減小，會影響通孔下部形成的形貌，因此本實施例中，採用占空比不斷減小的等離子體刻蝕，隨著刻蝕過程的進行，由於占空比的不斷減小，一個脈衝週期內，偏置功率源打開的時間變短，即刻蝕步驟的時間在 減少，聚合物形成步驟的時間在增加，從而保證刻蝕孔深度增加時，刻蝕孔的側壁形成一定量的聚合物。 When the through hole is formed by the plasma etching method with the constant duty ratio of the first embodiment, the inventors have found that as the depth of the etching hole increases, the amount of the polymer formed on the sidewall of the etching hole gradually decreases. It will affect the shape of the lower part of the through hole. Therefore, in this embodiment, the plasma etching with decreasing duty ratio is adopted. As the etching process progresses, the duty cycle is continuously reduced, within one pulse period. The time during which the bias power source is turned on becomes shorter, that is, the time of the etching step is By decreasing, the time for the polymer formation step is increased to ensure that the sidewalls of the etched holes form a certain amount of polymer when the depth of the etched holes is increased.
在本實施例中，占空比不斷減小的等離子體刻蝕過程中，所述占空比隨著刻蝕時間的增大逐漸減小，所述占空比的減小為階梯式的減小，所述占空比隨著刻蝕時間的增加從90%逐漸減小到10%，相鄰階梯間的占空比的減小幅度相同或不同，採用這種方式控制過程簡單，且刻蝕孔側壁的聚合物具有較好的均勻性。具體的，將刻蝕時間分成T1、T2.....TN個時間段，每個時間段可以相等也可以不等，相應的每個時間段對應占空比為A1、A2.....AN，A1>A2>.....AN。 In the present embodiment, during the plasma etching process in which the duty ratio is continuously reduced, the duty ratio is gradually decreased as the etching time increases, and the duty ratio is reduced in a stepwise manner. Small, the duty ratio gradually decreases from 90% to 10% as the etching time increases, and the duty ratio between adjacent steps decreases by the same or different. In this way, the control process is simple and precise. The polymer of the etched sidewall has better uniformity. Specifically, the etching time is divided into T 1 , T 2 ..... T N time periods, and each time period may be equal or unequal, and the corresponding duty ratio for each time period is A 1 , A 2 .....A N , A 1 >A 2 >.....A N .
在本發明其他實施例中，占空比不斷減小的等離子體刻蝕過程中，所述占空比隨著通孔刻蝕深度的增加逐漸減小。所述占空比的減小為階梯式的減小，所述占空比隨著刻蝕深度的增加從90%逐漸減小到10%，相鄰階梯間的占空比的減小幅度相同或不同，採用這種方式控制比較精確，使刻蝕孔側壁的聚合物具有較好的均勻性。具體的，將通孔的刻蝕深度分成T1、T2.....TN個深度段，每個深度段可以相等也可以不等，相應的每個深度段對應占空比為A1、A2.....AN，A1>A2>.....AN，較佳的，每個深度段的距離相等，相鄰占空比的減小幅度也相等。 In other embodiments of the present invention, during the plasma etching process in which the duty ratio is continuously reduced, the duty ratio gradually decreases as the etching depth of the via hole increases. The reduction of the duty ratio is a stepwise decrease, which gradually decreases from 90% to 10% as the etching depth increases, and the duty ratio between adjacent steps decreases by the same amount. Or differently, the control in this way is more precise, so that the polymer of the sidewall of the etched hole has better uniformity. Specifically, the etching depth of the through hole is divided into T 1 , T 2 ..... T N depth segments, and each depth segment may be equal or unequal, and each corresponding depth segment corresponds to a duty ratio A. 1 , A 2 .....A N , A 1 >A 2 >.....A N , preferably, the distances of each depth segment are equal, and the reduction ratios of adjacent duty ratios are also equal.
所述占空比不斷減小的等離子體刻蝕的射頻功率源功率為500~4000瓦，射頻頻率為60~120兆赫茲，偏置功率源功率為2000~8000瓦，偏置頻率為2~15兆赫茲，刻蝕腔壓力為20~100毫托耳，所述偏置功率源打開和關閉的頻率小於50千赫茲，在進行等離子體刻蝕時，在提高刻蝕效率的同時，保證已形成的刻蝕孔的側壁形成足量的聚合物，保護側壁不會被過刻蝕。 The plasma etched RF power source with reduced duty cycle is 500~4000 watts, the RF frequency is 60~120 megahertz, the bias power source power is 2000~8000 watts, and the bias frequency is 2~. At 15 MHz, the etch chamber pressure is 20-100 mTorr, and the bias power source is turned on and off at a frequency of less than 50 kHz. When plasma etching is performed, the etching efficiency is improved while ensuring that The sidewalls of the formed etched holes form a sufficient amount of polymer to protect the sidewalls from overetching.
在占空比不斷減小的等離子體刻蝕的一個脈衝週期內，包括刻蝕步驟和聚合物形成步驟，參考圖11，射頻功率電離刻蝕氣體形成等離 子體，當偏置功率源打開時，進行刻蝕步驟，刻蝕部分所述堆疊結構，形成刻蝕孔306，接著參考圖12，當偏置功率源關閉時，進行聚合物形成步驟，在已形成的刻蝕孔306的側壁和底部形成聚合物307，所述聚合物307在後續沿刻蝕孔306刻蝕堆疊結構304時保護刻蝕孔306的側壁不會被刻蝕到。 In one pulse period of the plasma etching with decreasing duty cycle, including an etching step and a polymer forming step, referring to FIG. 11, the RF power ionization etching gas is formed into a plasma a sub-body, when the bias power source is turned on, performing an etching step, etching part of the stacked structure to form an etch hole 306, and then referring to FIG. 12, when the bias power source is turned off, performing a polymer forming step, The sidewalls and the bottom of the formed etched holes 306 form a polymer 307 that protects the sidewalls of the etched holes 306 from being etched when the stacked structures 304 are subsequently etched along the etched holes 306.
所述占空比不斷減小的等離子體刻蝕採用的氣體為碳氟氣體、碳氟氫氣體、氧氣(O2)和氬氣(Ar)，所述碳氟氣體為C4F8、C4F6中的一種或幾種，所述碳氟氫氣體為CHF3、CH2F2、CH3F中的一種或幾種，CHF3、CH2F2、CH3F用於提高聚合物濃度，O2用於控制聚合物的量，CO用於控制氟碳的比例，Ar用於形成正離子，提供反應的能量。 The gas used for plasma etching with decreasing duty ratio is fluorocarbon gas, fluorocarbon gas, oxygen (O 2 ) and argon (Ar), and the fluorocarbon gas is C 4 F 8 , C One or more of 4 F 6 , the fluorocarbon gas is one or more of CHF 3 , CH 2 F 2 , CH 3 F, and CHF 3 , CH 2 F 2 , CH 3 F are used to increase polymerization. The concentration of the substance, O 2 is used to control the amount of the polymer, CO is used to control the proportion of fluorocarbon, and Ar is used to form a positive ion, providing the energy of the reaction.
本實施例中所述占空比不斷減小的等離子體刻蝕採用的氣體為C4F8、C4F6、CHF3、CH2F2、CH3F、O2和Ar的混合氣體，以保證等離子體刻蝕過程中，在已形成的刻蝕孔側壁形成足夠的聚合物。射頻功率源打開，偏置功率源也打開時，進行刻蝕步驟，C4F8、C4F6、CHF3、CH2F2、CH3F等會被射頻功率電離生成氟自由基、中性的CF2等分子碎片，同時也會生成一些正離子，如：CF3 +等，Ar也會失去電子生成Ar+正離子，正離子經過等離子體鞘層(plasma sheath)和偏置功率的加速，會轟擊待刻蝕材料，去除部分待刻蝕材料，同時F自由基也會和待刻蝕材料發生化學反應，去除部分待刻蝕材料；當射頻功率源保持打開，而偏置功率源關閉時，此時腔室內還存在刻蝕步驟殘留的部分活性基團或新形成活性基團，而中性的活性成分如CF2等會複合生成氟碳聚合物沉積在刻蝕孔的側壁和底部表面，由於偏置功率源關閉，不存在加速電場或加速電場減小，正離子不會轟擊形成的聚合物或只會去除部分形成的聚合物，使形成的聚合物全部或部分得以保存，後續繼續刻蝕時保護已形成的刻蝕孔的側壁不會被過刻蝕。本實施例中，偏置功率的占空比不斷減小，偏置功率的一個脈衝週期 內，第一時間會逐漸減少，第二時間會逐漸的增大，因此，等離子體刻蝕時，刻蝕步驟的時間會逐漸少，聚合物形成步驟的時間會逐漸增加，從而保證刻蝕孔深度增加時，刻蝕孔的側壁形成足夠的聚合物，並使形成的聚合物保持一定的均勻性，保護已形成的刻蝕孔不會被過刻蝕，從而使最終形成的通孔保持垂直的側壁形貌。 The gas used in the plasma etching in which the duty ratio is continuously reduced in this embodiment is a mixed gas of C 4 F 8 , C 4 F 6 , CHF 3 , CH 2 F 2 , CH 3 F, O 2 and Ar. In order to ensure that sufficient polymer is formed on the sidewalls of the formed etched holes during the plasma etching process. When the RF power source is turned on and the bias power source is also turned on, the etching step is performed, and C 4 F 8 , C 4 F 6 , CHF 3 , CH 2 F 2 , CH 3 F, etc. are ionized by the RF power to generate fluorine radicals. Neutral molecular fragments such as CF 2 will also generate some positive ions, such as CF 3 +, etc., Ar will also lose electrons to form Ar + positive ions, positive ions pass through plasma sheath and bias power. The acceleration will bombard the material to be etched, remove some of the material to be etched, and the F radical will also chemically react with the material to be etched to remove some of the material to be etched; when the RF power source remains open, the bias power When the source is turned off, there are still some active groups or newly formed active groups remaining in the etching step in the chamber, and a neutral active ingredient such as CF 2 is compounded to form a fluorocarbon polymer deposited on the sidewall of the etched hole. And the bottom surface, because the bias power source is off, there is no acceleration electric field or the acceleration electric field is reduced, the positive ions will not bombard the formed polymer or only partially form the polymer, so that all or part of the formed polymer can be preserved. Follow-up The sidewalls of the etched holes that have been formed during the etch are not overetched. In this embodiment, the duty ratio of the bias power is continuously reduced, and the first time is gradually decreased in one pulse period of the bias power, and the second time is gradually increased. Therefore, when the plasma is etched, the plasma is etched. The etching step time will gradually decrease, and the time of the polymer forming step will gradually increase, thereby ensuring that the sidewall of the etching hole forms sufficient polymer and the formed polymer maintains a certain uniformity when the etching hole depth is increased. The etched holes that have been formed are protected from being overetched so that the resulting vias maintain a vertical sidewall topography.
參考圖13，重複上述刻蝕步驟和聚合物的形成步驟，沿刻蝕孔306(參考圖12)刻蝕所述堆疊結構304，直至形成通孔308。 Referring to FIG. 13, the above etching step and polymer formation step are repeated, and the stacked structure 304 is etched along the etching hole 306 (refer to FIG. 12) until the via hole 308 is formed.
所述通孔308的深寬比為15：1~100：1，採用等離子體刻蝕形成高的深寬比的通孔308時，由於刻蝕步驟和聚合物形成步驟交替進行，並且在刻蝕的過程中，偏置功率源輸出脈衝的占空比不斷減小，一個脈衝週期內，偏置功率源打開的時間變短，即刻蝕步驟的時間在減少，聚合物形成步驟的時間在增加，從而保證刻蝕孔深度增加時，刻蝕孔的側壁形成足夠的聚合物，並使形成的聚合物保持一定的均勻性，保護已形成的刻蝕孔不會被過刻蝕，從而使最終形成的通孔308保持垂直的側壁形貌。 The through hole 308 has an aspect ratio of 15:1 to 100:1. When the plasma is etched to form the high aspect ratio via hole 308, the etching step and the polymer forming step are alternated and inscribed. During the eclipse process, the duty cycle of the output pulse of the bias power source is continuously reduced, and the time during which the bias power source is turned on becomes shorter in one pulse period, that is, the time of the etching step is decreased, and the time of the polymer forming step is increased. In order to ensure that the depth of the etched hole is increased, the sidewall of the etched hole forms sufficient polymer, and the formed polymer is maintained to have a certain uniformity, and the formed etched hole is protected from being over-etched, thereby finally The formed vias 308 maintain a vertical sidewall topography.
第三實施例 Third embodiment
參考圖14，圖14為本發明第三實施例半導體結構的形成方法的流程示意圖，包括：步驟S41，提供基底，在所述基底上形成氮化矽層和氧化矽層交替分佈的多層堆疊結構，在所述堆疊結構表面形成掩膜層，所述掩膜層具有暴露堆疊結構表面的開口；步驟S42，採用占空比不變的等離子體刻蝕所述堆疊結構，形成第一刻蝕孔；步驟S43，沿第一刻蝕孔，採用占空比不斷減小的等離子體刻蝕堆疊結構，形成第二刻蝕孔，第一刻蝕孔和第二刻蝕孔構成通孔。 14 is a schematic flow chart of a method for forming a semiconductor structure according to a third embodiment of the present invention, comprising: step S41, providing a substrate on which a multilayer stack structure in which a tantalum nitride layer and a tantalum oxide layer are alternately distributed is formed on the substrate. Forming a mask layer on the surface of the stacked structure, the mask layer having an opening exposing a surface of the stacked structure; and step S42, etching the stacked structure by using a plasma having a constant duty ratio to form a first etching hole In step S43, along the first etching hole, the stacked structure is etched by using a plasma having a decreasing duty ratio to form a second etching hole, and the first etching hole and the second etching hole constitute a through hole.
圖15~圖17為本發明第三實施例半導體結構的形成過程的 剖面結構示意圖。 15 to 17 are diagrams showing a process of forming a semiconductor structure according to a third embodiment of the present invention; Schematic diagram of the section structure.
參考圖15，提供基底400，在所述基底400上形成氮化矽層401和氧化矽層402交替分佈的多層堆疊結構404，在所述堆疊結構404表面形成掩膜層403，所述掩膜層403具有暴露堆疊結構404表面的開口405。 Referring to FIG. 15, a substrate 400 is provided on which a multilayer stack structure 404 in which a tantalum nitride layer 401 and a tantalum oxide layer 402 are alternately distributed is formed, and a mask layer 403 is formed on the surface of the stacked structure 404, the mask Layer 403 has an opening 405 that exposes the surface of stacked structure 404.
所述基底400為矽襯底、鍺襯底、矽鍺襯底、碳化矽襯底、氮化鎵襯底其中的一種。所述基底400內形成有離子摻雜區、矽通孔(圖中未示出)等；所述基底400上還可以形成電晶體、電阻、電容、記憶體等半導體器件(圖中未示出)。 The substrate 400 is one of a germanium substrate, a germanium substrate, a germanium substrate, a tantalum carbide substrate, and a gallium nitride substrate. An ion doping region, a through hole (not shown), and the like are formed in the substrate 400; a semiconductor device such as a transistor, a resistor, a capacitor, or a memory may be formed on the substrate 400 (not shown in the drawing) ).
在本發明的其他實施例中，所述基底400上還形成有一層或多層層間介質層(圖中未示出)，所述層間介質層的材料為氧化矽、低K介電材料或超低K介電材料，所述介質層中形成有金屬互連線、導電插塞等半導體結構。 In other embodiments of the present invention, the substrate 400 is further formed with one or more interlayer dielectric layers (not shown), and the interlayer dielectric layer is made of yttria, low-k dielectric material or ultra-low a K dielectric material in which a semiconductor structure such as a metal interconnection or a conductive plug is formed.
所述堆疊結構404為氮化矽層401和氧化矽層402交替分佈的多層結構，本實施例中，形成堆疊結構404具體過程為：先在基底表面形成第一氮化矽層，接著在第一氮化矽層表面形成第一氧化矽層，然後在第一氧化矽層表面形成第二氮化矽層，在第二氮化矽層表面形成第二氧化矽層，依次類推，多次交替後，形成堆疊結構404。所述堆疊結構404的厚度大於等於1微米，所述氮化矽層401和氧化矽層402的交替的次數大於等於8次。 The stack structure 404 is a multi-layer structure in which the tantalum nitride layer 401 and the tantalum oxide layer 402 are alternately distributed. In this embodiment, the stack structure 404 is formed by first forming a first tantalum nitride layer on the surface of the substrate, and then Forming a first tantalum oxide layer on the surface of the tantalum nitride layer, then forming a second tantalum nitride layer on the surface of the first tantalum oxide layer, forming a second tantalum oxide layer on the surface of the second tantalum nitride layer, and so on, and alternately Thereafter, a stacked structure 404 is formed. The thickness of the stacked structure 404 is greater than or equal to 1 micrometer, and the number of alternating layers of the tantalum nitride layer 401 and the tantalum oxide layer 402 is greater than or equal to 8 times.
在本發明的其他實施例中，形成交疊結構時，所述氮化矽層位於氧化矽層表面。 In other embodiments of the invention, the tantalum nitride layer is on the surface of the tantalum oxide layer when the overlapping structure is formed.
參考圖16，沿所述開口405，採用占空比不變的等離子體刻蝕所述堆疊結構404，形成第一刻蝕孔406。 Referring to FIG. 16, along the opening 405, the stacked structure 404 is etched using a plasma having a constant duty cycle to form a first etched hole 406.
所述占空比不變的等離子體刻蝕的射頻功率源功率為500~4000瓦，射頻頻率為60~120兆赫茲，偏置功率源功率為2000~8000 瓦，偏置頻率為2~15兆赫茲，刻蝕腔壓力為20~100毫托耳，偏置功率源以脈衝的方式輸出偏置功率，刻蝕過程中，偏置功率的占空比保持不變，所述偏置功率源打開和關閉的頻率小於50千赫茲，所述占空比的範圍為10%~90%，較佳的，所述占空比的範圍為40%~60%，在進行等離子體刻蝕時，在提高刻蝕效率的同時，保證已形成的刻蝕孔的側壁形成足量的聚合物，保護側壁不會被過刻蝕。 The RF power source of the plasma etching with constant duty ratio is 500-4000 watts, the RF frequency is 60-120 MHz, and the bias power source power is 2000-8000. Watt, bias frequency is 2~15 MHz, etching chamber pressure is 20~100 mTorr, bias power source outputs bias power in pulse mode, and duty cycle of bias power is maintained during etching The frequency of the bias power source being turned on and off is less than 50 kHz, and the duty ratio is in the range of 10% to 90%. Preferably, the duty ratio ranges from 40% to 60%. During the plasma etching, while improving the etching efficiency, the sidewall of the formed etched hole is formed to form a sufficient amount of polymer, and the protective sidewall is not overetched.
所述占空比不變的等離子體刻蝕採用的氣體為碳氟氣體、碳氟氫氣體、氧氣(O2)和氬氣(Ar)，所述碳氟氣體為C4F8、C4F6中的一種或幾種，所述碳氟氫氣體為CHF3、CH2F2、CH3F中的一種或幾種，CHF3、CH2F2、CH3F用於提高聚合物濃度，O2用於控制聚合物的量，CO用於控制氟碳的比例，Ar用於形成正離子，提供反應的能量。 The gas used for the plasma etching with constant duty ratio is fluorocarbon gas, fluorocarbon gas, oxygen (O 2 ) and argon (Ar), and the fluorocarbon gas is C 4 F 8 , C 4 One or more of F 6 , the fluorocarbon gas is one or more of CHF 3 , CH 2 F 2 , CH 3 F, and CHF 3 , CH 2 F 2 , CH 3 F are used to increase the polymer Concentration, O 2 is used to control the amount of polymer, CO is used to control the proportion of fluorocarbon, and Ar is used to form positive ions to provide energy for the reaction.
本實施例中所述占空比不斷的等離子體刻蝕採用的氣體為C4F8、C4F6、CHF3、CH2F2、CH3F、O2和Ar的混合氣體，以保證等離子體刻蝕過程中，在已形成的刻蝕孔側壁形成足夠的聚合物。 The gas used in the continuous duty plasma etching in this embodiment is a mixed gas of C 4 F 8 , C 4 F 6 , CHF 3 , CH 2 F 2 , CH 3 F, O 2 and Ar, It is ensured that sufficient polymer is formed on the sidewalls of the formed etched holes during the plasma etching process.
採用占空比不變的等離子體刻蝕形成的第一刻蝕孔406，所述第一刻蝕孔406的刻蝕深度為通孔深度的30%~60%，第一刻蝕孔406的深度相對較淺，採用占空比不變的等離子體刻蝕形成第一刻蝕孔406的過程中側壁形成的聚合物足以保護側壁不會被過刻蝕，後續採用占空比不斷減小的等離子體刻蝕沿第一刻蝕孔406繼續刻蝕堆疊結構404，採用占空比不斷減小的等離子體刻蝕時，使後續形成的刻蝕孔的側壁形成足夠的聚合物，直至形成通孔，使形成的通孔的側壁具有較好的形貌，相比于本發明第三實施例直接採用占空比不斷減小的等離子體刻蝕方法，本實施例中，採用占空比不變的等離子體刻蝕和占空比不斷減小的等離子體刻蝕減小了通孔的刻蝕時間，刻蝕時間較短，提高了效率，並且形成的通孔具有較好的側壁形貌。 The first etch hole 406 is formed by plasma etching with a constant duty ratio. The etched depth of the first etch hole 406 is 30% to 60% of the via depth, and the first etch hole 406 The depth is relatively shallow, and the polymer formed by the sidewall during the process of forming the first etched hole 406 by plasma etching with constant duty cycle is sufficient to protect the sidewall from over-etching, and the subsequent duty cycle is continuously reduced. The plasma etch continues to etch the stacked structure 404 along the first etch hole 406. When the plasma is etched with a decreasing duty cycle, the sidewall of the subsequently formed etched hole is formed into a sufficient polymer until the pass is formed. The hole has a better shape of the sidewall of the formed through hole. Compared with the third embodiment of the present invention, the plasma etching method with decreasing duty ratio is directly adopted. In this embodiment, the duty ratio is not adopted. Varying plasma etching and decreasing plasma duty cycle reduce the etching time of vias, etch time is shorter, efficiency is improved, and vias are formed with better sidewall morphology .
參考圖17，沿第一刻蝕孔406(參考圖16)，採用占空比不斷減小的等離子體刻蝕堆疊結構404，形成第二刻蝕孔，第一刻蝕孔和第二刻蝕孔構成通孔408。 Referring to FIG. 17, along the first etch hole 406 (refer to FIG. 16), the stacked structure 404 is etched using a plasma having a decreasing duty cycle to form a second etch hole, a first etch hole and a second etch. The holes constitute a through hole 408.
所述通孔408的深寬比為15：1~100：1，由於隨著刻蝕孔的深度的增加，刻蝕孔側壁形成的聚合物會不斷減少，因此第二刻蝕孔的形成採用占空比不斷減小的等離子體刻蝕，隨著刻蝕過程的進行，由於占空比的不斷減小，一個脈衝週期內，偏置功率源打開的時間變短，即刻蝕步驟的時間在減少，聚合物形成步驟的時間在增加，從而保證刻蝕孔深度增加時，刻蝕孔的側壁形成一定量的聚合物407。 The through-hole 408 has an aspect ratio of 15:1 to 100:1. Since the depth of the etched hole increases, the polymer formed on the sidewall of the etched hole is continuously reduced, so that the second etched hole is formed. The plasma etching with decreasing duty cycle, as the etching process progresses, the duty time of the bias power source becomes shorter in one pulse period due to the decreasing duty cycle, that is, the etching step time is By decreasing, the time for the polymer formation step is increased to ensure that the sidewalls of the etched holes form a certain amount of polymer 407 when the depth of the etched holes is increased.
在本實施例中，占空比不斷減小的等離子體刻蝕過程中，所述占空比隨著刻蝕時間的增大逐漸減小，所述占空比的減小為階梯式的減小，所述占空比隨著刻蝕時間的增加從90%逐漸減小到10%，相鄰階梯間的占空比的減小幅度相同或不同，採用這種方式控制過程簡單，且刻蝕孔側壁的聚合物具有較好的均勻性。具體的，將刻蝕時間分成T1、T2.....TN個時間段，每個時間段可以相等也可以不等，相應的每個時間段對應占空比為A1、A2.....AN，A1>A2>.....AN。較佳的，由於要刻蝕的第二刻蝕孔深度的減小，刻蝕形成第二刻蝕孔時，所述占空比從90%逐漸減小到50%，或者增大相鄰階梯間的占空比的變化幅度，以提高刻蝕和聚合物形成的效率。 In the present embodiment, during the plasma etching process in which the duty ratio is continuously reduced, the duty ratio is gradually decreased as the etching time increases, and the duty ratio is reduced in a stepwise manner. Small, the duty ratio gradually decreases from 90% to 10% as the etching time increases, and the duty ratio between adjacent steps decreases by the same or different. In this way, the control process is simple and precise. The polymer of the etched sidewall has better uniformity. Specifically, the etching time is divided into T 1 , T 2 ..... T N time periods, and each time period may be equal or unequal, and the corresponding duty ratio for each time period is A 1 , A 2 .....A N , A 1 >A 2 >.....A N . Preferably, the duty ratio is gradually reduced from 90% to 50%, or the adjacent step is increased when the second etched hole is formed by etching due to the decrease in the depth of the second etched hole to be etched. The variation in duty cycle between to increase the efficiency of etching and polymer formation.
在本發明其他實施例中，占空比不斷減小的等離子體刻蝕過程中，所述占空比隨著通孔刻蝕深度的增加逐漸減小。所述占空比的減小為階梯式的減小，所述占空比隨著刻蝕深度的增加從90%逐漸減小到10%，相鄰階梯間的占空比的減小幅度相同或不同，採用這種方式控制比較精確，使刻蝕孔側壁的聚合物具有較好的均勻性。具體的，將通孔的刻蝕深度分成T1、T2.....TN個深度段，每個深度段可以相等也可以不等，相應的 每個深度段對應占空比為A1、A2.....AN，A1>A2>.....AN。較佳的，由於要刻蝕的第二刻蝕孔深度的減小，刻蝕形成第二刻蝕孔時，所述占空比從90%逐漸減小到50%，或者減少刻蝕深度段的分段次數，抑或者增大相鄰階梯間的占空比的變化幅度，以提高刻蝕和聚合物形成的效率。 In other embodiments of the present invention, during the plasma etching process in which the duty ratio is continuously reduced, the duty ratio gradually decreases as the etching depth of the via hole increases. The reduction of the duty ratio is a stepwise decrease, which gradually decreases from 90% to 10% as the etching depth increases, and the duty ratio between adjacent steps decreases by the same amount. Or differently, the control in this way is more precise, so that the polymer of the sidewall of the etched hole has better uniformity. Specifically, the etching depth of the through hole is divided into T 1 , T 2 ..... T N depth segments, and each depth segment may be equal or unequal, and each corresponding depth segment corresponds to a duty ratio A. 1 , A 2 .....A N , A 1 >A 2 >.....A N . Preferably, the duty ratio is gradually reduced from 90% to 50%, or the etching depth is reduced, due to the decrease in the depth of the second etching hole to be etched, when the second etching hole is formed by etching. The number of segments, or the increase in the duty cycle between adjacent steps to increase the efficiency of etching and polymer formation.
所述占空比不斷減小的等離子體刻蝕的射頻功率源功率為500~4000瓦，射頻頻率為60~120兆赫茲，偏置功率源功率為2000~8000瓦，偏置頻率為2~15兆赫茲，刻蝕腔壓力為20~100毫托耳，所述偏置功率源打開和關閉的頻率小於50千赫茲，在進行等離子體刻蝕時，在提高刻蝕效率的同時，保證已形成的刻蝕孔的側壁形成足量的聚合物，保護側壁不會被過刻蝕。 The plasma etched RF power source with reduced duty cycle is 500~4000 watts, the RF frequency is 60~120 megahertz, the bias power source power is 2000~8000 watts, and the bias frequency is 2~. At 15 MHz, the etch chamber pressure is 20-100 mTorr, and the bias power source is turned on and off at a frequency of less than 50 kHz. When plasma etching is performed, the etching efficiency is improved while ensuring that The sidewalls of the formed etched holes form a sufficient amount of polymer to protect the sidewalls from overetching.
本實施例中所述占空比不斷減小的等離子體刻蝕採用的氣體為碳氟氣體、碳氟氫氣體、氧氣(O2)和氬氣(Ar)，所述碳氟氣體為C4F8、C4F6中的一種或幾種，所述碳氟氫氣體為CHF3、CH2F2、CH3F中的一種或幾種，CHF3、CH2F2、CH3F用於提高聚合物濃度，O2用於控制聚合物的量，CO用於控制氟碳的比例，Ar用於形成正離子，提供反應的能量。 The gas used in the plasma etching in which the duty ratio is continuously reduced in this embodiment is fluorocarbon gas, fluorocarbon gas, oxygen (O 2 ), and argon (Ar), and the fluorocarbon gas is C 4 . One or more of F 8 and C 4 F 6 , the fluorocarbon gas is one or more of CHF 3 , CH 2 F 2 , CH 3 F, CHF 3 , CH 2 F 2 , CH 3 F For increasing the polymer concentration, O 2 is used to control the amount of polymer, CO is used to control the proportion of fluorocarbon, and Ar is used to form positive ions to provide energy for the reaction.
本實施例中所述占空比不斷減小的等離子體刻蝕採用的氣體為C4F8、C4F6、CHF3、CH2F2、CH3F、O2和Ar的混合氣體，以保證等離子體刻蝕過程中，在已形成的刻蝕孔側壁形成足夠的聚合物。 The gas used in the plasma etching in which the duty ratio is continuously reduced in this embodiment is a mixed gas of C 4 F 8 , C 4 F 6 , CHF 3 , CH 2 F 2 , CH 3 F, O 2 and Ar. In order to ensure that sufficient polymer is formed on the sidewalls of the formed etched holes during the plasma etching process.
第四實施例 Fourth embodiment
參考圖18，圖18為本發明第四實施例半導體結構的形成方法的流程示意圖，包括：步驟S51，提供基底，在所述基底上形成氮化矽層和氧化矽層交替分佈的多層堆疊結構，在所述堆疊結構表面形成掩膜層，所述掩膜層具有暴露堆疊結構表面的開口；步驟S52，採用連續的等離子體刻蝕技術刻蝕所述堆疊結構，形成第 三刻蝕孔；步驟S53，接著沿第三刻蝕孔對堆疊結構進行偏置功率源以脈衝的方式輸出偏置功率的等離子體刻蝕，形成第四刻蝕孔，第三刻蝕孔和第四刻蝕孔構成通孔。 Referring to FIG. 18, FIG. 18 is a schematic flow chart of a method for forming a semiconductor structure according to a fourth embodiment of the present invention. The method includes the following steps: Step S51, providing a substrate on which a multilayer stack structure in which a tantalum nitride layer and a tantalum oxide layer are alternately distributed is formed. Forming a mask layer on the surface of the stacked structure, the mask layer having an opening exposing a surface of the stacked structure; and step S52, etching the stacked structure by a continuous plasma etching technique to form a Third etching the hole; step S53, then performing a bias power source on the stacked structure along the third etching hole to pulse-output the plasma etching of the bias power to form a fourth etching hole, a third etching hole and The fourth etched hole constitutes a through hole.
圖19~圖21為本發明第四實施例半導體結構的形成過程的剖面結構示意圖。 19 to 21 are schematic cross-sectional views showing a process of forming a semiconductor structure according to a fourth embodiment of the present invention.
參考圖19，提供基底500，在所述基底500上形成氮化矽層501和氧化矽層502交替分佈的多層堆疊結構504，在所述堆疊結構504表面形成掩膜層503，所述掩膜層503具有暴露堆疊結構504表面的開口505。 Referring to FIG. 19, a substrate 500 is provided on which a multilayer stack structure 504 in which a tantalum nitride layer 501 and a tantalum oxide layer 502 are alternately distributed is formed, and a mask layer 503 is formed on the surface of the stacked structure 504, the mask Layer 503 has an opening 505 that exposes the surface of stacked structure 504.
所述基底500為矽襯底、鍺襯底、矽鍺襯底、碳化矽襯底、氮化鎵襯底其中的一種。所述基底500內形成有離子摻雜區、矽通孔(圖中未示出)等；所述基底500上還可以形成電晶體、電阻、電容、記憶體等半導體器件(圖中未示出)。 The substrate 500 is one of a germanium substrate, a germanium substrate, a germanium substrate, a tantalum carbide substrate, and a gallium nitride substrate. An ion doping region, a through hole (not shown), and the like are formed in the substrate 500; a semiconductor device such as a transistor, a resistor, a capacitor, or a memory may be formed on the substrate 500 (not shown in the drawing) ).
在本發明的其他實施例中，所述基底500上還形成有一層或多層層間介質層(圖中未示出)，所述層間介質層的材料為氧化矽、低K介電材料或超低K介電材料，所述介質層中形成有金屬互連線、導電插塞等半導體結構。 In other embodiments of the present invention, the substrate 500 is further formed with one or more interlayer dielectric layers (not shown), and the interlayer dielectric layer is made of yttria, low-k dielectric material or ultra-low a K dielectric material in which a semiconductor structure such as a metal interconnection or a conductive plug is formed.
所述堆疊結構504為氮化矽層501和氧化矽層502交替分佈的多層結構，本實施例中，形成堆疊結構504具體過程為：先在基底表面形成第一氮化矽層，接著在第一氮化矽層表面形成第一氧化矽層，然後在第一氧化矽層表面形成第二氮化矽層，在第二氮化矽層表面形成第二氧化矽層，依次類推，多次交替後，形成堆疊結構504。所述堆疊結構504的厚度大於等於1微米，所述氮化矽層501和氧化矽層502的交替的次數大於等於8次。 The stack structure 504 is a multi-layer structure in which the tantalum nitride layer 501 and the tantalum oxide layer 502 are alternately distributed. In this embodiment, the stack structure 504 is formed by first forming a first tantalum nitride layer on the surface of the substrate, and then Forming a first tantalum oxide layer on the surface of the tantalum nitride layer, then forming a second tantalum nitride layer on the surface of the first tantalum oxide layer, forming a second tantalum oxide layer on the surface of the second tantalum nitride layer, and so on, and alternately Thereafter, a stacked structure 504 is formed. The thickness of the stacked structure 504 is greater than or equal to 1 micrometer, and the number of alternating layers of the tantalum nitride layer 501 and the tantalum oxide layer 502 is greater than or equal to 8 times.
在本發明的其他實施例中，形成交疊結構時，所述氮化矽層 位於氧化矽層表面。 In other embodiments of the invention, the tantalum nitride layer is formed when an overlapping structure is formed Located on the surface of the cerium oxide layer.
參考圖20，採用等離子體刻蝕技術刻蝕所述堆疊結構504， 形成第三刻蝕孔506。 Referring to FIG. 20, the stacked structure 504 is etched using a plasma etching technique, A third etch hole 506 is formed.
所述等離子刻蝕為習知的常規等離子刻蝕(連續等離子刻蝕)，偏置功率源和射頻功率源均是連續的輸出偏置功率和射頻功率，採用習知的常規的等離子刻蝕的刻蝕堆疊結構504是連續的刻蝕過程，相比於偏置功率源以脈衝的方式輸出偏置功率的等離子體刻蝕，刻蝕時間短，刻蝕效率高。 The plasma etching is a conventional conventional plasma etching (continuous plasma etching), and both the bias power source and the RF power source are continuous output bias power and RF power, using conventional conventional plasma etching. The etch stack structure 504 is a continuous etching process, and the plasma etching of the bias power is outputted in a pulse manner compared to the bias power source, the etching time is short, and the etching efficiency is high.
所述第三刻蝕孔506的深度為後續形成的通孔深度的10%~50%，由於第三刻蝕孔506的深度相對較淺，因此採用常規等離子刻蝕形成第三刻蝕孔506時，刻蝕過程對第三刻蝕孔506側壁的損傷忽略不計。 The depth of the third etch hole 506 is 10% to 50% of the depth of the subsequently formed via hole. Since the depth of the third etch hole 506 is relatively shallow, the third etch hole 506 is formed by conventional plasma etching. When the etching process damages the sidewall of the third etching hole 506, the damage is ignored.
採用常規等離子刻蝕形成第三刻蝕孔506後，後續沿第三刻蝕孔506採用偏置功率源以脈衝的方式輸出偏置功率的等離子體刻蝕技術刻蝕所述堆疊結構，直至形成通孔，採用偏置功率源以脈衝的方式輸出偏置功率的等離子體刻蝕技術刻蝕堆疊結構時會在第三刻蝕孔506和後續形成的刻蝕孔側壁形成聚合物，從而防止偏置功率源以脈衝的方式輸出偏置功率的等離子體刻蝕時，對第三刻蝕孔506和後續形成的刻蝕孔側壁的過刻蝕，使形成的通孔具有較好的側壁形貌的同時，減少了刻蝕時間，提高了效率。 After the third etched hole 506 is formed by conventional plasma etching, the stacked structure is etched by a plasma etching technique that outputs a bias power in a pulsed manner along the third etched hole 506 by using a bias power source until formation. Through-hole, a plasma etching technique that uses a bias power source to output a bias power in a pulsed manner. When the stacked structure is etched, a polymer is formed in the third etched hole 506 and a sidewall of the subsequently formed etched hole, thereby preventing partial bias. When the power source is plasma-etched to output the bias power in a pulse manner, the third etching hole 506 and the subsequently formed etching hole sidewall are over-etched to make the formed via hole have a better sidewall morphology. At the same time, the etching time is reduced and the efficiency is improved.
參考圖21，沿第三刻蝕孔506(參考圖20)對堆疊結構504進行偏置功率源以脈衝的方式輸出偏置功率的等離子體刻蝕，形成第四刻蝕孔，第三刻蝕孔506和第四刻蝕孔構成通孔508。 Referring to FIG. 21, a bias power source is applied to the stacked structure 504 along a third etch hole 506 (refer to FIG. 20) to output a plasma etch of bias power in a pulsed manner to form a fourth etch hole, a third etch. The hole 506 and the fourth etched hole constitute a through hole 508.
所述通孔508的深寬比為15：1~100：1，採用偏置功率源以脈衝的方式輸出偏置功率的等離子體刻蝕技術刻蝕堆疊結構504時會在第三 刻蝕孔506和第四刻蝕孔的側壁形成聚合物507，從而防止等離子體刻蝕時，對第三刻蝕孔506和第四刻蝕孔側壁的過刻蝕，使形成的通孔508具有較好的側壁形貌。 The via 508 has an aspect ratio of 15:1 to 100:1, and the plasma etching technique for outputting the bias power in a pulsed manner using a bias power source etches the stacked structure 504 in a third The sidewalls of the etched holes 506 and the fourth etched holes form a polymer 507, thereby preventing over-etching of the third etched holes 506 and the sidewalls of the fourth etched holes during plasma etching, so that the formed vias 508 are formed. Has a good sidewall morphology.
所述偏置功率源以脈衝的方式輸出偏置功率的等離子體刻蝕採用的氣體為碳氟氣體、碳氟氫氣體、氧氣(O2)和氬氣(Ar)，所述碳氟氣體為C4F8、C4F6中的一種或幾種，所述碳氟氫氣體為CHF3、CH2F2、CH3F中的一種或幾種，CHF3、CH2F2、CH3F用於提高聚合物濃度，O2用於控制聚合物的量，CO用於控制氟碳的比例，Ar用於形成正離子，提供反應的能量。 The gas used for the plasma etching of the bias power source to output the bias power in a pulsed manner is a fluorocarbon gas, a fluorocarbon gas, an oxygen gas (O 2 ), and an argon gas (Ar), wherein the fluorocarbon gas is One or more of C 4 F 8 and C 4 F 6 , the fluorocarbon gas is one or more of CHF 3 , CH 2 F 2 , CH 3 F, CHF 3 , CH 2 F 2 , CH 3 F is used to increase the polymer concentration, O 2 is used to control the amount of polymer, CO is used to control the proportion of fluorocarbon, and Ar is used to form positive ions to provide energy for the reaction.
本實施例中所述偏置功率源以脈衝的方式輸出偏置功率的等離子體刻蝕採用的氣體為C4F8、C4F6、CHF3、CH2F2、CH3F、O2和Ar的混合氣體，以保證等離子體刻蝕過程中，在已形成的刻蝕孔側壁形成足夠的聚合物。 In the embodiment, the bias power source outputs the bias power in a pulsed manner, and the gas used in the plasma etching is C 4 F 8 , C 4 F 6 , CHF 3 , CH 2 F 2 , CH 3 F, O. A mixed gas of 2 and Ar is used to ensure that sufficient polymer is formed on the sidewalls of the formed etched holes during the plasma etching process.
所述偏置功率源以脈衝的方式輸出偏置功率的等離子體刻蝕是指刻蝕時，偏置功率源以脈衝的方式輸出偏置功率，所述等離子體刻蝕為占空比不變的等離子體刻蝕或者占空比不斷減小的等離子體刻蝕，即偏置功率源輸出脈衝的占空比保持不變或不斷減小。 The plasma etch in which the bias power source outputs the bias power in a pulse manner means that the bias power source outputs the bias power in a pulsed manner during etching, and the plasma etching is constant in duty ratio. The plasma etch or the plasma etch with decreasing duty cycle, that is, the duty cycle of the output pulse of the bias power source remains unchanged or continuously decreases.
所述占空比不變的等離子體刻蝕的射頻功率源功率為500~4000瓦，射頻頻率為60~120兆赫茲，偏置功率源功率為2000~8000瓦，偏置頻率為2~15兆赫茲，刻蝕腔壓力為20~100毫托耳，偏置功率源輸出脈衝的占空比保持不變，所述偏置功率源打開和關閉的頻率小於50千赫茲，所述偏置功率源輸出脈衝的占空比的範圍為10%~90%，較佳的，所述占空比的範圍為40%~60%，在進行等離子體刻蝕時，在提高刻蝕效率的同時，保證已形成的刻蝕孔的側壁形成足量的聚合物，保護側壁不會被過刻蝕。 The RF power source with the duty cycle constant plasma is 500-4000 watts, the RF frequency is 60-120 MHz, the bias power source power is 2000-8000 watts, and the bias frequency is 2-15. Megahertz, the etch chamber pressure is 20~100 mTorr, the duty cycle of the bias power source output pulse remains unchanged, and the bias power source is turned on and off at a frequency less than 50 kHz, the bias power The duty ratio of the source output pulse ranges from 10% to 90%. Preferably, the duty ratio ranges from 40% to 60%. When plasma etching is performed, the etching efficiency is improved. It is ensured that the sidewalls of the formed etched holes form a sufficient amount of polymer, and the protective sidewalls are not overetched.
所述占空比不斷減小的等離子體刻蝕過程中，偏置功率源輸出脈衝的占空比不斷減小，所述占空比隨著刻蝕時間的增大逐漸減小，所述占空比的減小為階梯式的減小，所述占空比隨著刻蝕時間的增加從90%逐漸減小到10%，相鄰階梯間的占空比的減小幅度相同或不同，採用這種方式控制過程簡單，且刻蝕孔側壁的聚合物具有較好的均勻性。具體的，將刻蝕時間分成T1、T2.....TN個時間段，每個時間段可以相等也可以不等，相應的每個時間段對應占空比為A1、A2.....AN，A1>A2>.....AN。較佳的，由於要刻蝕的第二刻蝕孔深度的減小，刻蝕形成第二刻蝕孔時，所述占空比從90%逐漸減小到50%，或者減少刻蝕時間段的分段次數，抑或者增大相鄰階梯間的占空比的變化幅度，以提高刻蝕和聚合物形成的效率。 During the plasma etching process in which the duty ratio is continuously reduced, the duty ratio of the output pulse of the bias power source is continuously decreased, and the duty ratio is gradually decreased as the etching time increases, The reduction of the air ratio is a stepwise decrease, the duty ratio is gradually reduced from 90% to 10% as the etching time increases, and the duty ratios between adjacent steps are the same or different. In this way, the control process is simple, and the polymer of the sidewall of the etched hole has better uniformity. Specifically, the etching time is divided into T1, T2, ..., TN time periods, and each time period may be equal or unequal, and the corresponding duty ratio for each time period is A1, A2.... .AN, A1>A2>.....AN. Preferably, the duty ratio is gradually reduced from 90% to 50%, or the etching period is reduced, due to the decrease in the depth of the second etching hole to be etched, when the second etching hole is formed by etching. The number of segments, or the increase in the duty cycle between adjacent steps to increase the efficiency of etching and polymer formation.
在本發明其他實施例中，所述占空比不斷減小的等離子體刻蝕過程中，所述占空比隨著通孔刻蝕深度的增加逐漸減小。所述占空比的減小為階梯式的減小，所述占空比隨著刻蝕深度的增加從90%逐漸減小到10%，相鄰階梯間的占空比的減小幅度相同或不同，採用這種方式控制比較精確，使刻蝕孔側壁的聚合物具有較好的均勻性。具體的，將通孔的刻蝕深度分成T1、T2.....TN個深度段，每個深度段可以相等也可以不等，相應的每個深度段對應占空比為A1、A2.....AN，A1>A2>.....AN。較佳的，由於要刻蝕的第二刻蝕孔深度的減小，刻蝕形成第二刻蝕孔時，所述占空比從90%逐漸減小到50%，或者減少刻蝕深度段的分段次數，抑或者增大相鄰階梯間的占空比的變化幅度，以提高刻蝕和聚合物形成的效率。 In other embodiments of the present invention, during the plasma etching process in which the duty ratio is continuously reduced, the duty ratio gradually decreases as the etching depth of the via hole increases. The reduction of the duty ratio is a stepwise decrease, which gradually decreases from 90% to 10% as the etching depth increases, and the duty ratio between adjacent steps decreases by the same amount. Or differently, the control in this way is more precise, so that the polymer of the sidewall of the etched hole has better uniformity. Specifically, the etching depth of the through hole is divided into T 1 , T 2 ..... T N depth segments, and each depth segment may be equal or unequal, and each corresponding depth segment corresponds to a duty ratio A. 1 , A 2 .....A N , A 1 >A 2 >.....A N . Preferably, the duty ratio is gradually reduced from 90% to 50%, or the etching depth is reduced, due to the decrease in the depth of the second etching hole to be etched, when the second etching hole is formed by etching. The number of segments, or the increase in the duty cycle between adjacent steps to increase the efficiency of etching and polymer formation.
綜上，本發明實施例提供的半導體結構的形成方法，採用偏置功率源以脈衝的方式輸出偏置功率的等離子體刻蝕技術刻蝕氮化矽層和氧化矽層交替分佈的多層堆疊結構，形成通孔，由於刻蝕步驟和聚合物形成步驟交替進行，刻蝕形成部分深度的刻蝕孔後，會相應的在刻蝕孔的側壁形成聚合物，後續沿刻蝕孔繼續刻蝕堆疊結構時，保護已形成的刻蝕孔 不會被過刻蝕，從而使最終形成的通孔保持垂直的側壁形貌。 In summary, the method for forming a semiconductor structure provided by the embodiment of the present invention uses a plasma power etching technique in which a bias power source outputs a bias power in a pulse manner to etch a multilayer stacked structure in which a tantalum nitride layer and a tantalum oxide layer are alternately distributed. Forming a via hole. Since the etching step and the polymer forming step are alternately performed, after etching to form a partially deep etching hole, a polymer is formed on the sidewall of the etching hole correspondingly, and then continuing to etch the stack along the etching hole. Protect the formed etched holes when the structure It is not over-etched so that the resulting vias maintain a vertical sidewall topography.
進一步，採用占空比不斷減小的等離子體刻蝕，隨著刻蝕過程的進行，由於占空比的不斷減小，一個脈衝週期內，偏置功率源打開的時間變短，即刻蝕步驟的時間在減少，聚合物形成步驟的時間在增加，從而保證刻蝕孔深度增加時，刻蝕孔的側壁形成一定量的聚合物。 Further, by using a plasma etching with a decreasing duty cycle, as the etching process progresses, the bias power source is turned on for a short period of time, that is, the etching step, due to the continuous reduction of the duty ratio. The time is decreasing and the time for the polymer formation step is increased to ensure that the sidewalls of the etched holes form a certain amount of polymer when the depth of the etched holes is increased.
更進一步，採用占空比不變的等離子體刻蝕形成的第一刻蝕孔，接著採用占空比不斷減小的等離子體刻蝕沿第一刻蝕孔繼續刻蝕堆疊結構，直至形成通孔，使形成的通孔的側壁具有較好的形貌，減小了通孔的刻蝕時間，提高了效率。 Further, the first etch hole formed by plasma etching with constant duty ratio is used, and then the plasma etch with decreasing duty ratio is continued to etch the stacked structure along the first etch hole until the pass is formed. The holes have a better shape on the sidewalls of the formed through holes, which reduces the etching time of the through holes and improves the efficiency.
再進一步，採用常規等離子刻蝕形成第三刻蝕孔後，接著採用偏置功率源以脈衝的方式輸出偏置功率的等離子體刻蝕沿第三刻蝕孔刻蝕堆疊結構，直至形成通孔，使形成的通孔具有較好的側壁形貌的同時，減少刻蝕時間，提高了效率。 Further, after the third etch hole is formed by conventional plasma etching, the plasma etch which outputs the bias power in a pulse manner by using the bias power source etches the stacked structure along the third etch hole until the via hole is formed. The formed through holes have better sidewall morphology while reducing etching time and improving efficiency.
本發明雖然已以較佳實施例公開如上，但其並不是用來限定本發明，任何本領域技術人員在不脫離本發明的精神和範圍內，都可以利用上述揭示的方法和技術內容對本發明技術方案做出可能的變動和修改，因此，凡是未脫離本發明技術方案的內容，依據本發明的技術實質對以上實施例所作的任何簡單修改、等同變化及修飾，均屬於本發明技術方案的保護範圍。 The present invention has been disclosed in the preferred embodiments as described above, but it is not intended to limit the invention, and the present invention may be utilized by the method and technical contents disclosed above without departing from the spirit and scope of the invention. The technical solutions make possible changes and modifications. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments in accordance with the technical spirit of the present invention are not included in the technical solutions of the present invention. protected range.
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| CN107482010B (en) * | 2016-06-07 | 2020-11-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
| CN106468831B (en) * | 2016-09-28 | 2019-11-15 | 擎中科技（上海）有限公司 | A kind of naked eye 3D display equipment, visual barrier and preparation method thereof |
| US10163650B2 (en) * | 2016-11-18 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for selective nitride etch |
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| CN110190027A (en) * | 2019-07-02 | 2019-08-30 | 武汉新芯集成电路制造有限公司 | The production method of semiconductor devices |
| CN110600376B (en) * | 2019-09-20 | 2022-04-08 | 上海华力微电子有限公司 | Polymer removal process |
| CN115207203B (en) * | 2022-09-15 | 2022-12-02 | 材料科学姑苏实验室 | Method for realizing steep side wall of laminated etching in aluminum-based superconducting circuit |
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| US6846746B2 (en) * | 2002-05-01 | 2005-01-25 | Applied Materials, Inc. | Method of smoothing a trench sidewall after a deep trench silicon etch process |
| JP4512533B2 (en) * | 2005-07-27 | 2010-07-28 | 住友精密工業株式会社 | Etching method and etching apparatus |
| JP4812512B2 (en) * | 2006-05-19 | 2011-11-09 | オンセミコンダクター・トレーディング・リミテッド | Manufacturing method of semiconductor device |
| US8049327B2 (en) * | 2009-01-05 | 2011-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-silicon via with scalloped sidewalls |
| CN101930918B (en) * | 2009-06-19 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and lateral wall partitioning method |
| CN101958244A (en) * | 2009-07-21 | 2011-01-26 | 中微半导体设备(上海)有限公司 | Deep reactive ion etching method and gas flow control device thereof |
| CN102031525B (en) * | 2009-09-29 | 2014-02-12 | 中微半导体设备(上海)有限公司 | Method for etching deep through silicon via (TSV) |
| CN101789372A (en) * | 2010-02-11 | 2010-07-28 | 中微半导体设备(上海)有限公司 | Plasma etching method of insulating layer containing silicon |
| CN101800175B (en) * | 2010-02-11 | 2011-07-20 | 中微半导体设备(上海)有限公司 | Plasma etching method of silicon-containing insulating layer |
| CN102130045B (en) * | 2010-12-31 | 2015-12-02 | 上海集成电路研发中心有限公司 | Processing method of through holes |
| CN102420124B (en) * | 2011-05-26 | 2014-04-02 | 上海华力微电子有限公司 | Etching method of dielectric layer |
| CN102446832B (en) * | 2011-09-29 | 2014-02-05 | 上海华力微电子有限公司 | Method for avoiding contact hole blockage caused by dual etching barrier layers |
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| CN102738074A (en) | 2012-10-17 |
| TWI514466B (en) | 2015-12-21 |
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