TW201340396A - Light emitting diode and manufacturing method thereof - Google Patents
Light emitting diode and manufacturing method thereof Download PDFInfo
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Abstract
Description
本發明係關於一種發光二極體元件及其製造方法，特別是關於一種降低製程成本以及確保導線連接可靠度的發光二極體元件及其製造方法。The present invention relates to a light-emitting diode element and a method of manufacturing the same, and more particularly to a light-emitting diode element and a method of manufacturing the same that reduce process cost and ensure wire connection reliability.
發光二極體(light-emitting diode,LED)是一種由半導體材料製作而成的發光元件。由於發光二極體屬於冷發光，具有耗電量低、元件壽命長、反應速度快等優點，再加上體積小容易製成極小或陣列式元件的特性，因此近年來隨著技術不斷地進步，其應用範圍涵蓋了電腦或家電產品的指示燈、液晶顯示裝置的背光源乃至交通號誌或是車用指示燈。A light-emitting diode (LED) is a light-emitting element made of a semiconductor material. Since the light-emitting diode is a cold light-emitting device, it has the advantages of low power consumption, long component life, fast reaction speed, and the like, and the small size is easy to be made into a very small or array element, so that the technology has been continuously improved in recent years. Its application range covers the indicators of computers or home appliances, the backlight of liquid crystal display devices, traffic signs or vehicle lights.
由於傳統四元垂直式電極結構的LED係以砷化鎵材料作為基板，但由於砷化鎵基板本身不透光，因此LED所發出的光線會有一半以上被砷化鎵基板所吸收，造成LED發光效率不佳。Since the LED of the conventional quaternary vertical electrode structure uses a gallium arsenide material as a substrate, since the gallium arsenide substrate itself is opaque, more than half of the light emitted by the LED is absorbed by the gallium arsenide substrate, resulting in an LED. The luminous efficiency is not good.
另一種習知技術中，水平式電極的LED可將原本會吸光的砷化鎵基板去除，用氧化鋁基板取而代之成為LED的基板。雖然氧化鋁基板的透光性良好，可提高LED發光的萃取率，提升LED的發光效率，然而，由於氧化鋁基板導電性不佳，因此，電極的配置結構則需由原本傳統的垂直式電極改良為水平式電極結構。In another conventional technique, a horizontal electrode LED can remove a gallium arsenide substrate that would otherwise be absorbed, and replace it with an aluminum oxide substrate to form a substrate for the LED. Although the alumina substrate has good light transmittance, the extraction rate of the LED light emission can be improved, and the luminous efficiency of the LED can be improved. However, since the alumina substrate has poor conductivity, the arrangement structure of the electrode needs to be from the conventional vertical electrode. Improved to a horizontal electrode structure.
請參閱圖1A及圖1B，係為習知具有氧化鋁基板的改良式水平式電極的LED製程示意圖。如圖1A所示，首先，於磊晶基板(圖中未顯示)上成長磊晶層11，接著形成p型歐姆接觸層14於基板，再藉由一接合材料12與一鍵合基板13接合並移除磊晶基板，之後形成n型歐姆接觸層15於磊晶層11，習知之LED1係依序係具有鍵合基板13、接合材料12、p型歐姆接觸層14、一磊晶層11、以及n型歐姆接觸層15。Please refer to FIG. 1A and FIG. 1B , which are schematic diagrams of LED processes of a modified horizontal electrode having an alumina substrate. As shown in FIG. 1A, first, an epitaxial layer 11 is grown on an epitaxial substrate (not shown), then a p-type ohmic contact layer 14 is formed on the substrate, and then bonded to a bonding substrate 13 by a bonding material 12. And removing the epitaxial substrate, and then forming an n-type ohmic contact layer 15 on the epitaxial layer 11. The conventional LED1 has a bonding substrate 13, a bonding material 12, a p-type ohmic contact layer 14, and an epitaxial layer 11 in sequence. And an n-type ohmic contact layer 15.
如圖1A及圖1B所示，於LED 1中為了製作能與p型歐姆接觸層14電性導通的電極，在習知技術中係使用光阻P來協助定義開孔16的位置，以藉由感應耦合電漿(Inductively Coupled Plasma,ICP)蝕刻並貫穿磊晶層11，以暴露出p型歐姆接觸層14，然後使用電子槍蒸鍍形成金屬層161以及二電極171、172，其中，電極171係覆蓋部分的n型歐姆接觸層15而形成電性連接，電極172係藉由金屬層161而與暴露於開孔16的p型歐姆接觸層14電性連接。As shown in FIG. 1A and FIG. 1B, in order to fabricate an electrode that can be electrically connected to the p-type ohmic contact layer 14 in the LED 1, a photoresist P is used in the prior art to assist in defining the position of the opening 16 to borrow Etching and penetrating through the epitaxial layer 11 by inductively coupled plasma (ICP) to expose the p-type ohmic contact layer 14, and then forming a metal layer 161 and two electrodes 171, 172 by electron gun evaporation, wherein the electrode 171 The portion of the n-type ohmic contact layer 15 is covered to form an electrical connection, and the electrode 172 is electrically connected to the p-type ohmic contact layer 14 exposed to the opening 16 by the metal layer 161.
但由於開孔16的深度較大，也就是深寬比較大，在進行有方向性的電子槍蒸鍍時，常會造成於開孔16側壁的金屬層161厚度不足，甚至可能影響產品的可靠度。但若蒸鍍較厚的金屬層161來確保電性連結的可靠度的話，則會造成使用金屬材料的成本增加，以及製程時間的增加。However, since the depth of the opening 16 is large, that is, the depth is relatively large, when the directional electron gun evaporation is performed, the thickness of the metal layer 161 on the side wall of the opening 16 is often insufficient, and the reliability of the product may be affected. However, if the thick metal layer 161 is vapor-deposited to ensure the reliability of the electrical connection, the cost of using the metal material increases, and the processing time increases.
因此，如何提供一種提升可靠度以及降低成本的製造發光二極體元件之方法，已成為重要課題之一。Therefore, how to provide a method for manufacturing a light-emitting diode element that improves reliability and reduces cost has become one of important topics.
有鑑於上述課題，本發明之目的為提供一種提升可靠度以及降低成本的製造發光二極體元件之方法，避免習知技術中利用電子槍蒸鍍導電層於穿孔中造成的成本增加以及可靠度不足的問題。In view of the above problems, an object of the present invention is to provide a method for manufacturing a light-emitting diode element that improves reliability and reduces cost, and avoids the cost increase and reliability of the conductive layer in the perforation by using an electron gun in the prior art. The problem.
為達上述目的，依據本發明之一種發光二極體元件之製造方法係包括提供一磊晶基板；形成一磊晶層於磊晶基板上，磊晶層具有相對的一第一側表面與一第二側表面，第一側表面係與磊晶基板之一表面接合；形成一第一歐姆接觸層於磊晶層上之第二側表面；形成一接合層於第一歐姆接觸層上，藉由接合層將一鍵合基板接合於第一歐姆接觸層上；移除磊晶基板；形成一第二歐姆接觸層於磊晶層之第一側表面上；形成暴露第一歐姆接觸層之一穿孔；形成一導電層於穿孔中，並與第一歐姆接觸層電性連接；以及形成一第一電極及一第二電極於磊晶層上，第一電極係經由導電層電性連接第一歐姆接觸層，第二電極與第二歐姆接觸層電性連接。To achieve the above object, a method for fabricating a light emitting diode device according to the present invention includes providing an epitaxial substrate; forming an epitaxial layer on the epitaxial substrate, the epitaxial layer having an opposite first side surface and a a second side surface, the first side surface is bonded to a surface of the epitaxial substrate; forming a first ohmic contact layer on the second side surface of the epitaxial layer; forming a bonding layer on the first ohmic contact layer, Bonding a bonding substrate to the first ohmic contact layer; removing the epitaxial substrate; forming a second ohmic contact layer on the first side surface of the epitaxial layer; forming one of the exposed first ohmic contact layers a conductive layer is formed in the through hole and electrically connected to the first ohmic contact layer; and a first electrode and a second electrode are formed on the epitaxial layer, and the first electrode is electrically connected to the first through the conductive layer. The ohmic contact layer is electrically connected to the second ohmic contact layer.
於本發明之一較佳實施例中，更包含形成一隔離層覆蓋磊晶層與第二歐姆接觸層，但暴露出第一電極及第二電極。In a preferred embodiment of the present invention, the method further includes forming an isolation layer covering the epitaxial layer and the second ohmic contact layer, but exposing the first electrode and the second electrode.
於本發明之一較佳實施例中，磊晶基板係為砷化鎵基板或氮化物基板。In a preferred embodiment of the invention, the epitaxial substrate is a gallium arsenide substrate or a nitride substrate.
於本發明之一較佳實施例中，磊晶層係以有機金屬化學氣相沈積形成於該磊晶基板。In a preferred embodiment of the invention, the epitaxial layer is formed on the epitaxial substrate by organometallic chemical vapor deposition.
於本發明之一較佳實施例中，第一歐姆接觸層係為p型歐姆接觸層，第二歐姆接觸層係為n型歐姆接觸層。In a preferred embodiment of the invention, the first ohmic contact layer is a p-type ohmic contact layer and the second ohmic contact layer is an n-type ohmic contact layer.
於本發明之一較佳實施例中，穿孔係以感應耦合電漿離子蝕刻形成。In a preferred embodiment of the invention, the perforations are formed by inductively coupled plasma ion etching.
於本發明之一較佳實施例中，形成穿孔的步驟更包括以微影製程定義一光阻層覆蓋於第二歐姆接觸層與磊晶層上；以及蝕刻未被光阻層覆蓋之磊晶層，藉此定義一n型平台與一p型平台及露出第一歐姆接觸層。In a preferred embodiment of the present invention, the step of forming the via hole further comprises: defining a photoresist layer over the second ohmic contact layer and the epitaxial layer by a lithography process; and etching the epitaxial layer not covered by the photoresist layer The layer, thereby defining an n-type platform and a p-type platform and exposing the first ohmic contact layer.
於本發明之一較佳實施例中，蝕刻部分磊晶層後，係露出磊晶層之一磷化鎵層。In a preferred embodiment of the present invention, after etching a portion of the epitaxial layer, a gallium phosphide layer of one of the epitaxial layers is exposed.
於本發明之一較佳實施例中，導電層係以無電電鍍方法形成。In a preferred embodiment of the invention, the conductive layer is formed by electroless plating.
為達上述目的，依據本發明之一種發光二極體元件包括一磊晶層、一第一歐姆接觸層、一接合層、一鍵合基板、一導電層、一第一電極、一第二歐姆接觸層以及一第二電極。磊晶層具有相對的一第一側表面與一第二側表面，磊晶層係具有一穿孔。第一歐姆接觸層設置於磊晶層之第二側表面上。接合層設置於磊晶層之第二側表面上，且包覆第一歐姆接觸層。鍵合基板透過接合層接合於第一歐姆接觸層及磊晶層之第二側表面上。導電層填滿於穿孔之一部份深度，並與第一歐姆接觸層電性連接。第一電極設置於磊晶層上，第一電極係經由導電層電性連接第一歐姆接觸層。第二歐姆接觸層設置於磊晶層。第二電極設置於磊晶層上，且電性連接第二歐姆接觸層。In order to achieve the above object, a light emitting diode device according to the present invention comprises an epitaxial layer, a first ohmic contact layer, a bonding layer, a bonding substrate, a conductive layer, a first electrode, and a second ohm. a contact layer and a second electrode. The epitaxial layer has a first side surface and a second side surface, and the epitaxial layer has a through hole. The first ohmic contact layer is disposed on the second side surface of the epitaxial layer. The bonding layer is disposed on the second side surface of the epitaxial layer and covers the first ohmic contact layer. The bonding substrate is bonded to the first ohmic contact layer and the second side surface of the epitaxial layer through the bonding layer. The conductive layer fills a portion of the depth of the via and is electrically connected to the first ohmic contact layer. The first electrode is disposed on the epitaxial layer, and the first electrode is electrically connected to the first ohmic contact layer via the conductive layer. The second ohmic contact layer is disposed on the epitaxial layer. The second electrode is disposed on the epitaxial layer and electrically connected to the second ohmic contact layer.
於本發明之一較佳實施例中，磊晶層包括一砷化鎵層、一磷銦鎵鋁的複合層以及一磷化鎵層。In a preferred embodiment of the invention, the epitaxial layer comprises a gallium arsenide layer, a composite layer of indium gallium arsenide, and a gallium phosphide layer.
於本發明之一較佳實施例中，第一歐姆接觸層為一金/鈹/金或是一金/鈹金/金的金屬複合層。In a preferred embodiment of the invention, the first ohmic contact layer is a metal/germanium/gold or a gold/gold/gold metal composite layer.
於本發明之一較佳實施例中，導電層係於穿孔中形成一導電柱以填滿穿孔之部份深度。In a preferred embodiment of the invention, the conductive layer is formed in the via to form a conductive pillar to fill a portion of the depth of the via.
於本發明之一較佳實施例中，導電柱的厚度為4～6μm。In a preferred embodiment of the invention, the conductive pillars have a thickness of 4 to 6 μm.
於本發明之一較佳實施例中，第二歐姆接觸層之材質係包含鍺金合金(GeAu)。導電層之材質係包含金、銀或銅。In a preferred embodiment of the invention, the material of the second ohmic contact layer comprises a sheet metal alloy (GeAu). The material of the conductive layer is gold, silver or copper.
承上所述，本發明製造發光二極體元件及其製造方法方法，藉由無電電鍍方法形成導電層於穿孔中，以減少穿孔的深寬比。如此一來，即可克服習知技術中，利用電子槍蒸鍍導電層於穿孔中的側壁厚度較薄而影響可靠度的問題。另外，無電電鍍製程也較為便宜，所以還可節省製程成本。As described above, the present invention manufactures a light-emitting diode element and a method of manufacturing the same, and forms a conductive layer in the through hole by an electroless plating method to reduce the aspect ratio of the through hole. In this way, it is possible to overcome the problem that the thickness of the sidewall of the conductive layer in the perforation is thinned by the electron gun by the electron gun, which affects the reliability. In addition, the electroless plating process is also relatively cheap, so the process cost can also be saved.
以下將參照相關圖式，說明依本發明較佳實施例之一種發光二極體元件及其製造方法，其中相同的元件將以相同的參照符號加以說明。Hereinafter, a light-emitting diode element and a method of manufacturing the same according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings, wherein the same elements will be described with the same reference numerals.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“下”、“頂”、“側”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "lower", "top", "side" and "one" are used in the description for convenience of description and are not intended to limit the invention. The scope, the change or adjustment of the relative relationship, is also considered to be within the scope of the invention.
請參閱圖2、圖3A至圖3J，係為本發明製造發光二極體元件之方法流程圖及示意圖。發光二極體元件之製造方法包含以下步驟：步驟S01係提供一磊晶基板；步驟S02係形成一磊晶層於磊晶基板上，磊晶層具有相對的一第一側表面與一第二側表面，其中第一側表面係與磊晶基板之一表面接合；步驟S03係形成一第一歐姆接觸層於磊晶層之第二側表面上；步驟S04係形成一接合層於第一歐姆接觸層上，藉由一接合層將一鍵合基板接合於第一歐姆接觸層上；步驟S05移除磊晶基板；步驟S06形成一第二歐姆接觸層於磊晶層之第一側表面上，其中第一歐姆接觸層與第二歐姆接觸層係位於磊晶層之相對側；步驟S07係形成暴露第一歐姆接觸層之一穿孔。更詳細來說，由磊晶層之第一側表面形成貫穿磊晶層之穿孔，且暴露第一歐姆接觸層；步驟S08形成一導電層於穿孔中，並與第一歐姆接觸層電性連接；以及步驟S09形成一第一電極及一第二電極於磊晶層上，第一電極係經由導電層電性連接第一歐姆接觸層，第二電極與第二歐姆接觸層電性連接。Please refer to FIG. 2, FIG. 3A to FIG. 3J, which are flowcharts and schematic diagrams of a method for manufacturing a light-emitting diode element according to the present invention. The manufacturing method of the LED component includes the following steps: step S01 provides an epitaxial substrate; step S02 forms an epitaxial layer on the epitaxial substrate, the epitaxial layer has a first side surface and a second a side surface, wherein the first side surface is bonded to one surface of the epitaxial substrate; step S03 forms a first ohmic contact layer on the second side surface of the epitaxial layer; and step S04 forms a bonding layer on the first ohmic layer On the contact layer, a bonding substrate is bonded to the first ohmic contact layer by a bonding layer; step S05 removes the epitaxial substrate; and step S06 forms a second ohmic contact layer on the first side surface of the epitaxial layer. Wherein the first ohmic contact layer and the second ohmic contact layer are on opposite sides of the epitaxial layer; and step S07 forms a perforation exposing one of the first ohmic contact layers. In more detail, the first side surface of the epitaxial layer is formed with a through hole of the epitaxial layer, and the first ohmic contact layer is exposed; in step S08, a conductive layer is formed in the through hole and electrically connected to the first ohmic contact layer. And forming a first electrode and a second electrode on the epitaxial layer, the first electrode is electrically connected to the first ohmic contact layer via the conductive layer, and the second electrode is electrically connected to the second ohmic contact layer.
請同時參照圖2及圖3A所示，於步驟S01及S02中，係提供一磊晶基板21，並於磊晶基板21上形成一磊晶層22。其中，磊晶基板21的材質係以砷化鎵為例，當然磊晶基板21還可以是碳化矽、氧化鋁、氮化鎵、玻璃、石英或磷化鎵等材質。磊晶層22係為一複合層，形成磊晶層22的主要磊晶方法有液相磊晶法(Liquid Phase Epitaxy,LPE)、氣相磊晶法(Vapor Phase Epitaxy,VPE)以及有機金屬化學氣相沈積法(Metal-Organic Chemical Vapor Deposition,MOCVD)。另外，以磊晶層22的材料能隙來看，常用的Ⅲ族-Ⅴ族元素組成大至可分成四類，分別為GaP/GaAsP系列、AlGaAs系列、AlGaInP系列以及GaN系列，於此磊晶層22係包括一磷化銦鎵(InGaP)層221、一砷化鎵(GaAs)層222、一磷化鋁銦鎵(AlGaInP)層223以及一磷化鎵層224，並以有機金屬化學氣相依序沈積形成於磊晶基板21上為例，其中磊晶層22係具有相對的一第一側表面與一第二側表面，其中磊晶層22之第一側表面係與磊晶基板21之一表面相結合。本實施例之磊晶層22結構係以自磊晶基板21往上依序為一蝕刻阻擋層(stop layer)之磷化銦鎵層221、一半導體接觸層(n-contact layer)之砷化鎵層222、一磊晶結構之磷化鋁銦鎵層223以及一窗層(window layer)之磷化鎵層224。本實施例之磊晶層22係以具有上述四層為例，然其非限定。其中，磊晶結構之磷化鋁銦鎵層223係為複合層，其包含一n型披覆層(n-cladding)、一量子井層(quantum well)以及一p型披覆層(n-cladding)。其中，磊晶結構之磷化鋁銦鎵層223係為四元發光二極體的主要發光之磊晶結構，另外，窗層之磷化鎵層224主要係用來降低電阻值與增加光線射出。Referring to FIG. 2 and FIG. 3A simultaneously, in steps S01 and S02, an epitaxial substrate 21 is provided, and an epitaxial layer 22 is formed on the epitaxial substrate 21. The material of the epitaxial substrate 21 is GaAs. For example, the epitaxial substrate 21 may be made of tantalum carbide, aluminum oxide, gallium nitride, glass, quartz or gallium phosphide. The epitaxial layer 22 is a composite layer, and the main epitaxial methods for forming the epitaxial layer 22 are Liquid Phase Epitaxy (LPE), Vapor Phase Epitaxy (VPE), and organometallic chemistry. Metal-Organic Chemical Vapor Deposition (MOCVD). In addition, in view of the material gap of the epitaxial layer 22, the commonly used group III-V group elements are as large as four types, which are GaP/GaAsP series, AlGaAs series, AlGaInP series, and GaN series, respectively. The layer 22 includes an indium gallium phosphide (InGaP) layer 221, a gallium arsenide (GaAs) layer 222, an aluminum gallium indium gallium arsenide (AlGaInP) layer 223, and a gallium phosphide layer 224, and is an organometallic chemical gas. The phase-by-layer deposition is formed on the epitaxial substrate 21, wherein the epitaxial layer 22 has a first side surface and a second side surface, wherein the first side surface of the epitaxial layer 22 and the epitaxial substrate 21 One of the surfaces is combined. The structure of the epitaxial layer 22 of the present embodiment is an arsenic of an indium phosphide layer 221 and an n-contact layer which are sequentially an etch stop layer from the epitaxial substrate 21. A gallium layer 222, an epitaxially structured phosphide aluminum indium gallium layer 223, and a window layer phosphide layer 224. The epitaxial layer 22 of the present embodiment is exemplified by having the above four layers, but is not limited thereto. The phosphide aluminum indium gallium layer 223 of the epitaxial structure is a composite layer comprising an n-cladding layer, a quantum well layer and a p-type cladding layer (n- Cladding). The phosphide aluminum indium gallium layer 223 of the epitaxial structure is the main light-emitting epitaxial structure of the quaternary light-emitting diode, and the gallium phosphide layer 224 of the window layer is mainly used for reducing the resistance value and increasing the light emission. .
於步驟S03中，形成第一歐姆接觸層23於磊晶層22之第二側表面上，其中，第一歐姆接觸層23係為一金屬複合層，包含依序為金/鈹/金或是金/鈹金/金的金屬複合材料。此外，第一歐姆接觸層23係為p型歐姆接觸層，以作為一p型電極。In step S03, a first ohmic contact layer 23 is formed on the second side surface of the epitaxial layer 22, wherein the first ohmic contact layer 23 is a metal composite layer, including gold/germanium/gold or Gold/sheet metal/gold metal composite. Further, the first ohmic contact layer 23 is a p-type ohmic contact layer as a p-type electrode.
如圖3B所示，於步驟S04中，藉由接合層24將一鍵合基板25接合於第一歐姆接觸層23上，亦即鍵合基板25係接合於磊晶層22之第二側表面上。需注意的是，鍵合基板25接合於第一歐姆接觸層23「上」，係指鍵合基板25直接接觸第一歐姆接觸層23或是隔著其他層而連結於第一歐姆接觸層23上。於此，接合層24位於磊晶層22與鍵合基板25之間，而使磊晶層22連結於鍵合基板25上。本實施例中，接合層24係例如有機光阻層的材料(例如：聚醯亞胺，polyimide)或為金屬材料，以提供黏著性，而鍵合基板25則以藍寶石基板為例，當然鍵合基板25的材質還可以是碳化矽、氮化鎵、玻璃、石英或磷化鎵等等。後續，鍵合基板25係以熱壓合方式形成於接合層24之上。As shown in FIG. 3B, in step S04, a bonding substrate 25 is bonded to the first ohmic contact layer 23 by the bonding layer 24, that is, the bonding substrate 25 is bonded to the second side surface of the epitaxial layer 22. on. It should be noted that the bonding substrate 25 is bonded to the first ohmic contact layer 23, which means that the bonding substrate 25 directly contacts the first ohmic contact layer 23 or is connected to the first ohmic contact layer 23 via another layer. on. Here, the bonding layer 24 is located between the epitaxial layer 22 and the bonding substrate 25, and the epitaxial layer 22 is bonded to the bonding substrate 25. In this embodiment, the bonding layer 24 is made of, for example, a material of an organic photoresist layer (for example, polyimide) or a metal material to provide adhesion, and the bonding substrate 25 is exemplified by a sapphire substrate. The material of the composite substrate 25 may also be tantalum carbide, gallium nitride, glass, quartz or gallium phosphide or the like. Subsequently, the bonded substrate 25 is formed on the bonding layer 24 by thermocompression bonding.
如圖3C所示，於步驟S05中，將鍵合基板25接合於第一歐姆接觸層23之上後，進行磊晶基板21的移除。移除磊晶基板21的方法可使用化學蝕刻移除或是利用雷射聚焦於與磊晶基板21相連接之磊晶層22，使磊晶基板21與磊晶層22剝離(lift-off)。於本實施例中，係利用氨水與雙氧水之混合藥水去除砷化鎵之磊晶基板21，然後再以磷酸與鹽酸之混合藥水去除蝕刻阻擋層之磷化銦鎵層221，而暴露出半導體接觸層之砷化鎵層222。As shown in FIG. 3C, in step S05, after the bonding substrate 25 is bonded over the first ohmic contact layer 23, the epitaxial substrate 21 is removed. The method of removing the epitaxial substrate 21 may be performed by chemical etching or by focusing the epitaxial layer 22 connected to the epitaxial substrate 21 by laser, and the epitaxial substrate 21 and the epitaxial layer 22 are lifted-off. . In this embodiment, the epitaxial substrate 21 of gallium arsenide is removed by using a mixed solution of ammonia water and hydrogen peroxide, and then the phosphide layer 221 of the etch barrier layer is removed by a mixture of phosphoric acid and hydrochloric acid to expose the semiconductor contact. A layer of gallium arsenide layer 222.
如圖3D所示，其係將圖3C的結構翻轉，以進行後續製程的示意圖。在步驟S05移除磊晶基板21與蝕刻阻擋層之磷化銦鎵層221之後，於步驟S06中，係以微影、沈積與浮離製程將第二歐姆接觸層26形成於磊晶層22之第一側表面上。其中，完成第二歐姆接觸層26之圖形後，以第二歐姆接觸層26圖形為遮罩對半導體接觸層之砷化鎵層222進行蝕刻，以將半導體接觸層之砷化鎵層222圖案化，以於半導體接觸層之砷化鎵層222形成與第二歐姆接觸層26的相同圖形。第二歐姆接觸層26係以n型歐姆接觸層為例，其材質係包含例如鍺金合金(GeAu)。As shown in FIG. 3D, it is a schematic diagram in which the structure of FIG. 3C is inverted to perform subsequent processes. After the epitaxial substrate 21 and the etch barrier phosphide layer 221 are removed in step S05, the second ohmic contact layer 26 is formed on the epitaxial layer 22 by a lithography, deposition, and floating process in step S06. On the first side surface. After the pattern of the second ohmic contact layer 26 is completed, the GaAs layer 222 of the semiconductor contact layer is etched by using the pattern of the second ohmic contact layer 26 as a mask to pattern the GaAs layer 222 of the semiconductor contact layer. The gallium arsenide layer 222 for the semiconductor contact layer forms the same pattern as the second ohmic contact layer 26. The second ohmic contact layer 26 is exemplified by an n-type ohmic contact layer, and the material thereof is, for example, a sheet metal alloy (GeAu).
如圖3E所示，於步驟S07中，係利用微影製程，以形成穿孔271，而穿孔271之深度需暴露出第一歐姆接觸層23。亦即由磊晶層22之第一側表面形成貫穿磊晶層22之穿孔271，且穿孔271的位置需相對於磊晶層22第二側表面上的第一歐姆接觸層23而設置。本實施例中，穿孔271形成的步驟係於第二歐姆接觸層26與磊晶層22上形成一光阻層281，用以覆蓋以及保護第二歐姆接觸層26與磊晶層22；利用微影製程定義出穿孔271的位置，再以蝕刻製程蝕刻未被光阻層281覆蓋之磊晶層22區域，以形成暴露第一歐姆接觸層23的穿孔271。於此，蝕刻穿孔271係以例如感應耦合電漿(ICP)的方式。而且，藉由感應耦合電漿蝕刻的步驟，還可以一併定義出一n型平台(n-mesa)與一p型平台(p-mesa)，亦即定義n型電極的平台區域與p型電極的平台區域。As shown in FIG. 3E, in step S07, a lithography process is utilized to form the vias 271, and the depth of the vias 271 is exposed to expose the first ohmic contact layer 23. That is, the through hole 271 penetrating the epitaxial layer 22 is formed by the first side surface of the epitaxial layer 22, and the position of the through hole 271 is disposed with respect to the first ohmic contact layer 23 on the second side surface of the epitaxial layer 22. In this embodiment, the step of forming the via 271 is to form a photoresist layer 281 on the second ohmic contact layer 26 and the epitaxial layer 22 for covering and protecting the second ohmic contact layer 26 and the epitaxial layer 22; The shadow process defines the location of the via 271, and the region of the epitaxial layer 22 not covered by the photoresist layer 281 is etched by an etching process to form a via 271 exposing the first ohmic contact layer 23. Here, the etched vias 271 are, for example, inductively coupled plasma (ICP). Moreover, by the step of inductively coupled plasma etching, an n-type platform (n-mesa) and a p-type platform (p-mesa), that is, a platform region and a p-type defining an n-type electrode, can also be defined together. The platform area of the electrode.
此外，圖3E所示的形成穿孔271並非僅侷限於上述的一次微影製程的形成程序，也可以複數次的蝕刻製程來完成穿孔。例如，如圖3F及圖3G所示，在圖3F中可以先以微影製程定義一光阻層281覆蓋在第二歐姆接觸層26與磊晶層22上，光阻層281可以定義出n型平台與p型平台區域與穿孔272位置，接著再以感應耦合電漿蝕刻未被光阻層281覆蓋之磊晶層22以定義出一n型平台P1與一p型平台P2(如圖3J所示)，亦即定義n型電極的平台區域與p型電極的平台區域；同時蝕刻部分磊晶層22後，以露出磊晶層22中的磷化鎵層224形成穿孔272。接著，移除覆蓋於第二歐姆接觸層26與磊晶層22上之光阻層281，並重新塗佈一光阻層282並以微影製程定義出後續所需穿孔273之圖形後，蝕刻覆蓋於第一歐姆接觸層23上的磊晶層22，形成貫穿整個磊晶層22且露出部分第一歐姆接觸層23的穿孔273。In addition, the formation of the through-hole 271 shown in FIG. 3E is not limited to the above-described formation process of the one-time lithography process, and the puncturing process may be performed in plural etching processes. For example, as shown in FIG. 3F and FIG. 3G, in FIG. 3F, a photoresist layer 281 may be firstly covered on the second ohmic contact layer 26 and the epitaxial layer 22 by a lithography process, and the photoresist layer 281 may define n. The platform and the p-type platform region and the perforation 272 position, and then inductively coupled plasma etching the epitaxial layer 22 not covered by the photoresist layer 281 to define an n-type platform P1 and a p-type platform P2 (as shown in FIG. 3J) The substrate region of the n-type electrode and the plateau region of the p-type electrode are defined; after a portion of the epitaxial layer 22 is etched, the via 232 is formed to expose the gallium phosphide layer 224 in the epitaxial layer 22. Then, the photoresist layer 281 covering the second ohmic contact layer 26 and the epitaxial layer 22 is removed, and a photoresist layer 282 is recoated and the pattern of the subsequent desired vias 273 is defined by a lithography process. The epitaxial layer 22 overlying the first ohmic contact layer 23 forms a via 273 that extends through the entire epitaxial layer 22 and exposes a portion of the first ohmic contact layer 23.
如圖3H所示，於步驟S08中，形成上述穿孔273後，係以無電電鍍(Electroless Plating)方式於穿孔273中形成一導電層29，以與第一歐姆接觸層23電性連接。導電層29係由第一歐姆接觸層23表面開始沉積，並於穿孔273中形成一導電柱以填滿穿孔273的部份深度，通常希望導電柱厚度會希望大約與磷化鎵層224等高，而通常磷化鎵層224的厚度約為4～6μm，所以部份深度較佳地約為4～6μm，亦即導電層29所形成的導電柱之厚度約為4～6μm。所以在本發明中導電層29係填滿穿孔273的部份深度，隨著電鍍製程而導電層29逐漸成長，可減少穿孔271、272、273的深寬比，所以不存在如先前技術中以具有方向性的電子槍蒸鍍時，所造成於穿孔側壁的金屬層厚度不足，而影響產品的可靠度的情況。As shown in FIG. 3H, in step S08, after the via 273 is formed, a conductive layer 29 is formed in the via 273 by electroless plating to electrically connect with the first ohmic contact layer 23. The conductive layer 29 is deposited from the surface of the first ohmic contact layer 23, and a conductive pillar is formed in the via 273 to fill a portion of the depth of the via 273. It is generally desirable that the thickness of the conductive pillar be about the same as that of the GaN layer 224. Generally, the thickness of the gallium phosphide layer 224 is about 4-6 μm, so the partial depth is preferably about 4-6 μm, that is, the conductive pillar formed by the conductive layer 29 has a thickness of about 4-6 μm. Therefore, in the present invention, the conductive layer 29 fills a part of the depth of the through hole 273, and the conductive layer 29 gradually grows with the electroplating process, and the aspect ratio of the through holes 271, 272, and 273 can be reduced, so that there is no prior art as in the prior art. When the directional electron gun is vapor-deposited, the thickness of the metal layer on the side wall of the perforation is insufficient, which affects the reliability of the product.
其中，本實施例之導電層29之材質係包含例如金、銀或銅等導電金屬。而無電電鍍是沈積薄膜金屬層的一種電化學方法，就是在無需外加電壓的情形下，把溶液中的金屬離子藉由自動催化的化學反應方式，沉積在固體表面上。這種反應程序與電鍍極為類似，不同的是反應發生時，電子傳遞並不經由外部導線，而是利用與金屬離子與共同存在於鍍液中的還原劑，藉由化學反應在固體表面上將金屬離子還原成固態金屬，而逐層沉積於固體表面上。由於此氧化還原反應僅在具有活性物質的固態表面上發生，故無電電鍍的施行，並不會因為鍍件的表面形狀、大小或是否導電等因素而受到限制。The material of the conductive layer 29 of the present embodiment includes a conductive metal such as gold, silver or copper. Electroless plating is an electrochemical method for depositing a thin film metal layer by depositing metal ions in a solution on a solid surface by an autocatalytic chemical reaction without an applied voltage. This reaction procedure is very similar to electroplating, except that when the reaction occurs, the electron transfer does not pass through the external wires, but instead utilizes the metal ions and the reducing agent coexisting in the plating solution, and the chemical reaction will be on the solid surface. The metal ions are reduced to a solid metal and deposited layer by layer on a solid surface. Since this redox reaction occurs only on a solid surface having an active material, the electroless plating is not limited by the surface shape, size, or conductivity of the plated member.
於此，無電電鍍的操作條件例如可使用宏澤電子所生產之電鍍液CG-871，並且在100 ml/L KAu(CN)2、1.0g/L(0.8-2.5 g/L)、溫度85~90℃、時間進行3~15分鐘進行無電電鍍，當然也可根據實際製程的沈積厚度要求而設定。Here, the operating conditions of the electroless plating can be, for example, the plating solution CG-871 produced by Acer Electronics, and at 100 ml/L KAu (CN) 2, 1.0 g/L (0.8-2.5 g/L), temperature 85. Electroless plating can be carried out at ~90 ° C for 3 to 15 minutes, but it can also be set according to the deposition thickness requirements of the actual process.
如圖3I所示，係為沿圖3J中A-A線段的剖面圖。於步驟S09中，形成上述導電層29之後，移除光阻層282，並於磊晶層22上形成第一電極201及第二電極202，第一電極201係經由導電層29電性連接第一歐姆接觸層23，第二電極202係與第二歐姆接觸層26電性連接。其中，第一電極201及第二電極202之材質依序包含鉻/鉑/金。第一電極201及第二電極202例如係以電子槍蒸鍍之方式形成。第一電極201及第二電極202之厚度為4至6μm。As shown in Fig. 3I, it is a cross-sectional view taken along line A-A of Fig. 3J. After the conductive layer 29 is formed in step S09, the photoresist layer 282 is removed, and the first electrode 201 and the second electrode 202 are formed on the epitaxial layer 22. The first electrode 201 is electrically connected via the conductive layer 29. The first electrode 202 is electrically connected to the second ohmic contact layer 26. The materials of the first electrode 201 and the second electrode 202 sequentially include chromium/platinum/gold. The first electrode 201 and the second electrode 202 are formed, for example, by electron gun evaporation. The first electrode 201 and the second electrode 202 have a thickness of 4 to 6 μm.
此外，為保護上述發光二極體元件結構，本實施例之發光二極體製造方法可更包含：形成一隔離層31以覆蓋磊晶層22以及第二歐姆接觸層26，但暴露第一電極201及第二電極202作為與外部電源電性連接用。隔離層31之材質可例如為氧化矽或氮化矽。In addition, in order to protect the structure of the above-mentioned light-emitting diode element, the method for manufacturing the light-emitting diode of the present embodiment may further include: forming an isolation layer 31 to cover the epitaxial layer 22 and the second ohmic contact layer 26, but exposing the first electrode The 201 and the second electrode 202 are electrically connected to an external power source. The material of the isolation layer 31 may be, for example, hafnium oxide or tantalum nitride.
請參照圖3H所示，本發明亦提供一種發光二極體元件，發光二極體元件2包括一磊晶層22、一第一歐姆接觸層23、一接合層24、一鍵合基板25、一導電層29、一第一電極201、一第二歐姆接觸層26以及一第二電極202。磊晶層22具有相對的一第一側表面與一第二側表面，磊晶層22係具有一穿孔273。第一歐姆接觸層23設置於磊晶層22之第二側表面上。接合層24設置於磊晶層22之第二側表面上，且包覆第一歐姆接觸層23。導電層29填設於穿孔273之一部份深度，並與第一歐姆接觸層23電性連接。As shown in FIG. 3H , the present invention also provides a light emitting diode device. The light emitting diode device 2 includes an epitaxial layer 22 , a first ohmic contact layer 23 , a bonding layer 24 , and a bonding substrate 25 . A conductive layer 29, a first electrode 201, a second ohmic contact layer 26, and a second electrode 202. The epitaxial layer 22 has a first side surface and a second side surface, and the epitaxial layer 22 has a through hole 273. The first ohmic contact layer 23 is disposed on the second side surface of the epitaxial layer 22. The bonding layer 24 is disposed on the second side surface of the epitaxial layer 22 and covers the first ohmic contact layer 23. The conductive layer 29 is filled in a portion of the depth of the through hole 273 and electrically connected to the first ohmic contact layer 23.
磊晶層22係例如包括一砷化鎵層222、一磷銦鎵鋁層223以及一磷化鎵層224。第一歐姆接觸層23為一金/鈹/金或是一金/鈹金/金的金屬複合層。接合層24係為一光阻材料。本實施例之導電層29之材質係包含例如金、銀或銅等導電金屬。其中，磊晶層22、第一歐姆接觸層23、接合層24以及導電層29與上述實施例之中，磊晶層22、第一歐姆接觸層23、接合層24以及導電層29具有相同的技術特徵及形成方式，故於此不再贅述。The epitaxial layer 22 includes, for example, a gallium arsenide layer 222, an indium gallium aluminum oxide layer 223, and a gallium phosphide layer 224. The first ohmic contact layer 23 is a metal/germanium/gold or a gold/gold/gold metal composite layer. The bonding layer 24 is a photoresist material. The material of the conductive layer 29 of this embodiment contains a conductive metal such as gold, silver or copper. Wherein, the epitaxial layer 22, the first ohmic contact layer 23, the bonding layer 24, and the conductive layer 29 are the same as the epitaxial layer 22, the first ohmic contact layer 23, the bonding layer 24, and the conductive layer 29, among the above embodiments. Technical features and formation methods are therefore not described here.
鍵合基板25透過一接合層24而接合於第一歐姆接觸層23與磊晶層22之第二側表面上。第二歐姆接觸層26設置於磊晶層22之第一側表面上。第一電極201及第二電極202設置於磊晶層22上，第一電極201係經由導電層29電性連接第一歐姆接觸層23，第二電極202電性連接第二歐姆接觸層26。其中，第一電極201及第二電極202之材質依序包含鉻/鉑/金。第一電極201及第二電極202例如係以電子槍蒸鍍之方式形成。接合層24、鍵合基板25、第二歐姆接觸層26、第一電極201及第二電極202與上述實施例之中，接合層24、鍵合基板25、第二歐姆接觸層26、第一電極201及第二電極202具有相同的技術特徵及形成方式，故於此不再贅述。The bonding substrate 25 is bonded to the second side surface of the first ohmic contact layer 23 and the epitaxial layer 22 through a bonding layer 24. The second ohmic contact layer 26 is disposed on the first side surface of the epitaxial layer 22. The first electrode 201 and the second electrode 202 are disposed on the epitaxial layer 22 . The first electrode 201 is electrically connected to the first ohmic contact layer 23 via the conductive layer 29 , and the second electrode 202 is electrically connected to the second ohmic contact layer 26 . The materials of the first electrode 201 and the second electrode 202 sequentially include chromium/platinum/gold. The first electrode 201 and the second electrode 202 are formed, for example, by electron gun evaporation. The bonding layer 24, the bonding substrate 25, the second ohmic contact layer 26, the first electrode 201, and the second electrode 202, and the above embodiment, the bonding layer 24, the bonding substrate 25, the second ohmic contact layer 26, the first The electrode 201 and the second electrode 202 have the same technical features and formation modes, and thus will not be described again.
綜上所述，本發明製造發光二極體元件及其製造方法，藉由無電電鍍方法形成導電層於穿孔中，可克服習知技術中，利用電子槍蒸鍍導電層於穿孔中可能產生導電層厚度太厚或是太薄的問題，因此，可藉以節省製程成本以及克服導線連接可靠度的問題。因此，藉由本發明製造發光二極體元件之方法，利用無電電鍍方法形成導電層於穿孔中，可得以確保導電層形成於穿孔中的厚度而獲得較佳的可靠度。In summary, the present invention manufactures a light-emitting diode element and a method of manufacturing the same, and the conductive layer is formed in the through hole by electroless plating, which can overcome the prior art, and the conductive layer can be evaporated in the through hole by using an electron gun. The problem is that the thickness is too thick or too thin, so that the process cost can be saved and the reliability of the wire connection can be overcome. Therefore, by the method for fabricating a light-emitting diode element of the present invention, the conductive layer is formed in the through hole by the electroless plating method, and the thickness of the conductive layer formed in the through hole can be ensured to obtain better reliability.
以上所述僅為舉例性，而非為限制性者。任何未脫離本發明之精神與範疇，而對其進行之等效修改或變更，均應包含於後附之申請專利範圍中。The above is intended to be illustrative only and not limiting. Any equivalent modifications or alterations to the spirit and scope of the invention are intended to be included in the scope of the appended claims.
1．．．LED1. . . led
11．．．磊晶層11. . . Epitaxial layer
12．．．接合材料12. . . Bonding material
13．．．鍵合基板13. . . Bonded substrate
14．．．p型歐姆接觸層14. . . P-type ohmic contact layer
15．．．n型歐姆接觸層15. . . N-type ohmic contact layer
16．．．開孔16. . . Opening
161．．．金屬層161. . . Metal layer
171、172．．．電極171, 172. . . electrode
2．．．發光二極體元件2. . . Light-emitting diode component
201．．．第一電極201. . . First electrode
202．．．第二電極202. . . Second electrode
21．．．磊晶基板twenty one. . . Epitaxial substrate
22．．．磊晶層twenty two. . . Epitaxial layer
221．．．磷化銦鎵層221. . . Indium gallium phosphide layer
222．．．砷化鎵層222. . . Gallium arsenide layer
223．．．磷化鋁銦鎵層223. . . Aluminum indium gallium phosphide layer
224．．．磷化鎵層224. . . Gallium phosphide layer
23．．．第一歐姆接觸層twenty three. . . First ohmic contact layer
24．．．接合層twenty four. . . Bonding layer
25．．．鍵合基板25. . . Bonded substrate
26．．．第二歐姆接觸層26. . . Second ohmic contact layer
271、272、273．．．穿孔271, 272, 273. . . perforation
281、282．．．光阻層281, 282. . . Photoresist layer
29．．．導電層29. . . Conductive layer
31．．．隔離層31. . . Isolation layer
P．．．光阻P. . . Photoresist
P1．．．n型平台P1. . . N-type platform
P2．．．p型平台P2. . . P-type platform
S01～S09．．．步驟S01～S09. . . step
圖1A及圖1B係為習知具有氧化鋁基板的改良式水平式電極的LED製程示意圖；1A and FIG. 1B are schematic diagrams of LED processes of a modified horizontal electrode having an alumina substrate;
圖2係為本發明製造發光二極體元件之方法流程圖；以及2 is a flow chart of a method for manufacturing a light emitting diode element according to the present invention;
圖3A至圖3J，係為本發明製造發光二極體元件之方法流程圖及示意圖。3A to 3J are a flow chart and a schematic diagram of a method for fabricating a light-emitting diode element according to the present invention.
2．．．發光二極體元件2. . . Light-emitting diode component
201．．．第一電極201. . . First electrode
202．．．第二電極202. . . Second electrode
22．．．磊晶層twenty two. . . Epitaxial layer
222．．．砷化鎵層222. . . Gallium arsenide layer
223．．．磷化鋁銦鎵層223. . . Aluminum indium gallium phosphide layer
224．．．磷化鎵層224. . . Gallium phosphide layer
23．．．第一歐姆接觸層twenty three. . . First ohmic contact layer
24．．．接合層twenty four. . . Bonding layer
25．．．鍵合基板25. . . Bonded substrate
26．．．第二歐姆接觸層26. . . Second ohmic contact layer
271．．．穿孔271. . . perforation
29．．．導電層29. . . Conductive layer
31．．．隔離層31. . . Isolation layer
Claims (16)
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