TW201334036A - 降低擴散摻雜區之表面摻雜濃度之方法、超級介面結構之製作方法以及功率電晶體元件之製作方法 - Google Patents
降低擴散摻雜區之表面摻雜濃度之方法、超級介面結構之製作方法以及功率電晶體元件之製作方法 Download PDFInfo
- Publication number
- TW201334036A TW201334036A TW101103343A TW101103343A TW201334036A TW 201334036 A TW201334036 A TW 201334036A TW 101103343 A TW101103343 A TW 101103343A TW 101103343 A TW101103343 A TW 101103343A TW 201334036 A TW201334036 A TW 201334036A
- Authority
- TW
- Taiwan
- Prior art keywords
- trench
- diffusion
- semiconductor substrate
- layer
- fabricating
- Prior art date
Links
- 238000009792 diffusion process Methods 0.000 title claims abstract description 98
- 238000000034 method Methods 0.000 title claims abstract description 77
- 238000004519 manufacturing process Methods 0.000 title claims description 31
- 239000000758 substrate Substances 0.000 claims abstract description 75
- 239000004065 semiconductor Substances 0.000 claims abstract description 62
- 230000003647 oxidation Effects 0.000 claims abstract description 25
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 25
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 24
- 239000001301 oxygen Substances 0.000 claims abstract description 24
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 24
- 239000002019 doping agent Substances 0.000 claims description 45
- 239000007789 gas Substances 0.000 claims description 23
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 9
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 8
- 229910001868 water Inorganic materials 0.000 claims description 8
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 6
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 claims description 4
- 229910000041 hydrogen chloride Inorganic materials 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims 1
- 229910001873 dinitrogen Inorganic materials 0.000 claims 1
- 229910001882 dioxygen Inorganic materials 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 238000005530 etching Methods 0.000 description 7
- 239000011159 matrix material Substances 0.000 description 7
- 238000009826 distribution Methods 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000000313 electron-beam-induced deposition Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002294 plasma sputter deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
本發明提供一種降低擴散摻雜區之表面摻雜濃度之方法。首先,提供一半導體基底,半導體基底具有一擴散摻雜區設於其中,且擴散摻雜區與半導體基底之一表面相接觸,其中擴散摻雜區鄰近表面之摻雜濃度大於擴散摻雜區遠離表面之摻雜濃度。然後,進行一熱氧化製程,於半導體基底之表面形成一氧化層,其中與表面相接觸之擴散摻雜區之一部分與氧反應為氧化層之一部分。接著,移除氧化層。
Description
本發明係關於一種降低擴散摻雜區之表面摻雜濃度之方法、超級介面結構之製作方法以及功率電晶體元件之製作方法。
在功率電晶體元件中,汲極與源極間導通電阻RDS(on)的大小係與元件之功率消耗成正比,因此降低導通電阻RDS(on)的大小可減少功率電晶體元件所消耗之功率。於導通電阻RDS(on)中,用於耐壓之磊晶層所造成之電阻值所佔的比例係為最高。雖然增加磊晶層中導電物質之摻雜濃度可降低磊晶層之電阻值,但磊晶層的作用係為用於承受高電壓。若增加摻雜濃度會降低磊晶層之崩潰電壓,因而降低功率電晶體元件之耐壓能力。
為了維持或提升功率電晶體元件之耐壓能力,並降低磊晶層之電阻值,目前已發展出一種具有超級介面(super junction)結構之功率電晶體元件,以兼具高耐壓能力以及低導通電阻。習知製作功率電晶體元件之方法是在N型基底上形成一N型磊晶層,然後利用蝕刻製程於N型磊晶層中形成複數個深溝槽。接著,在深溝槽中填入摻雜物來源層,並利用高溫擴散之方法將摻雜物來源層中之P型摻雜物擴散至N型磊晶層中,以形成P型摻雜區,且N型磊晶層與P型摻雜區構成垂直基底之PN接面,即超級介面結構。然而,P型摻雜區是利用擴散方式所形成,因此其摻雜濃度是隨著越接近深溝槽之側壁而越高。藉此,P型摻雜區之表面摻雜濃度容易過高,使超級介面結構中之電洞濃度與電子濃度分布不均勻,導致超級介面結構的耐壓能力不佳。
有鑑於此,降低P型摻雜區之表面摻雜濃度,以解決超級介面結構中之電洞濃度與電子濃度分布不均勻之問題實為業界努力之目標。
本發明之主要目的在於提供一種降低擴散摻雜區之表面摻雜濃度之方法、超級介面結構之製作方法以及功率電晶體元件之製作方法,以解決超級介面結構中之電洞濃度與電子濃度分布不均勻之問題。
為達上述之目的,本發明提供一種超級介面結構之製作方法。首先,提供一半導體基底,具有一第一導電類型。接著,於半導體基底中形成至少一溝槽。然後,於溝槽之二側之半導體基底中分別形成二擴散摻雜區,其中各擴散摻雜區鄰近溝槽之側壁之摻雜濃度大於各擴散摻雜區遠離溝槽之側壁之摻雜濃度,且各擴散摻雜區具有不同於第一導電類型之一第二導電類型。隨後,進行一熱氧化製程,於溝槽之側壁以及底部形成一氧化層,其中與溝槽之側壁相接觸之各擴散摻雜區之一部分與氧反應為氧化層之一部分。然後,移除氧化層。
為達上述之目的,本發明提供一種功率電晶體元件之製作方法。首先,提供一半導體基底,具有一第一導電類型。接著,於半導體基底中形成至少一溝槽。然後,於溝槽之二側之半導體基底中分別形成二擴散摻雜區,其中各擴散摻雜區鄰近溝槽之側壁之摻雜濃度大於各擴散摻雜區遠離溝槽之側壁之摻雜濃度,且各擴散摻雜區具有不同於第一導電類型之一第二導電類型。隨後,進行一熱氧化製程,於溝槽之側壁以及底部形成一氧化層,其中與溝槽之側壁相接觸之各擴散摻雜區之一部分與氧反應為氧化層之一部分。然後,移除氧化層。接著,於溝槽中形成一絕緣層。之後,於溝槽之至少一側之半導體基底上形成一閘極結構。隨後,於閘極結構之二側的半導體基底中分別形成二基體摻雜區,且各基體摻雜區分別與各擴散摻雜區相接觸,其中基體摻雜區具有第二導電類型。接著,於各基體摻雜區中分別形成一源極摻雜區。
為達上述之目的,本發明提供一種降低擴散摻雜區之表面摻雜濃度之方法。首先,提供一半導體基底,半導體基底具有一擴散摻雜區設於其中,且擴散摻雜區與半導體基底之一表面相接觸,其中擴散摻雜區鄰近表面之摻雜濃度大於擴散摻雜區遠離表面之摻雜濃度。然後,進行一熱氧化製程,於半導體基底之表面形成一氧化層,其中與表面相接觸之擴散摻雜區之一部分與氧反應為氧化層之一部分。接著,移除氧化層。
本發明利用熱氧化製程,使具有較高濃度之各擴散摻雜區與氧反應而成為氧化層,藉此後續進行將氧化層移除之步驟會將具有較高濃度之擴散摻雜區之一部分移除,因此所留下之各擴散摻雜區之表面摻雜濃度可有效地被降低,以均勻化超級介面結構中之電洞濃度與電子濃度,進而提升超級介面結構的耐壓能力。
請參考第1圖至第3圖,第1圖至第3圖為本發明一較佳實施例之降低擴散摻雜區之表面摻雜濃度之方法示意圖。如第1圖所示,首先,提供一半導體基底10,例如矽晶圓。半導體基底10具有一擴散摻雜區12設於其中,且擴散摻雜區12與半導體基底10之一上表面10a相接觸。並且,擴散摻雜區12鄰近上表面10a之摻雜濃度大於擴散摻雜區12遠離上表面10a之摻雜濃度。如第2圖所示,隨後,進行一熱氧化製程,於半導體基底10之上表面10a形成一氧化層14。並且,與上表面10a相接觸之擴散摻雜區12之一部分會與氧反應為氧化層14之一部分,亦即鄰近上表面10a且具有較高濃度之擴散摻雜區12之一部分會因與氧反應而成為氧化層14。如第3圖所示,接著,移除氧化層14,亦即移除具有較高濃度且與氧反應而成為氧化層14之擴散摻雜區12之一部分,藉此擴散摻雜區12之表面摻雜濃度可有效地被降低。於本實施例中,擴散摻雜區12之導電類型與半導體基底10之導電類型可為N型或P型,且可彼此相同或彼此不同。
本發明進一步將上述降低擴散摻雜區之表面摻雜濃度之方法應用於功率電晶體元件之超級介面結構之製作方法中,以降低超級介面結構中之電洞濃度或電子濃度,進而均勻化超級介面結構中之電洞濃度與電子濃度,但本發明之降低擴散摻雜區之表面摻雜濃度之方法並不限應用於此。請參考第4圖至第13圖,第4圖至第13圖為本發明一較佳實施例之功率電晶體元件之製作方法示意圖,其中第4圖至第7圖為本發明較佳實施例之超級介面結構之製作方法示意圖。如第4圖所示,首先,提供一半導體基底102,且半導體基底102具有一第一導電類型。接著,於半導體基底102上形成一墊層104,例如二氧化矽(SiO2),但不限於此。然後,進行一沉積製程,於墊層104上形成一硬遮罩層106,例如氮化矽(Si3N4),但不限於此。接著,進行一微影暨蝕刻製程,圖案化墊層104與硬遮罩層106,於墊層104與硬遮罩層106中形成複數個開口108,分別貫穿墊層104與硬遮罩層106並曝露出半導體基底102。然後,以硬遮罩層106為遮罩,進行一蝕刻製程,經由各開口108於半導體基底102中形成複數個溝槽110,此時各溝槽110具有一第一寬度W1與各開口之寬度約略相同。於本實施例中,半導體基底102可包括一基材102a,例如矽晶圓,以及一磊晶層102b,且磊晶層102b設於基材102a上。並且,各溝槽110貫穿磊晶層102b,並曝露出基材102a,但本發明不限於此,各溝槽110亦可未貫穿磊晶層102b。此外,本發明之開口108與溝槽110之數量不限為複數個,亦可分別僅為單一個。
如第5圖所示,接著,於各溝槽110中填入一摻雜物來源層112,且摻雜物來源層112覆蓋於硬遮罩層106上。其中,摻雜物來源層112包含有複數個具有不同於第一導電類型之一第二導電類型的摻雜物。然後,進行一熱趨入製程,將第二導電類型之摻雜物擴散至半導體基底102中,以於各溝槽110之二側之半導體基底102中分別形成二擴散摻雜區114。由於各擴散摻雜區114是藉由熱來擴散摻雜物而形成的,因此各擴散摻雜區114亦具有第二導電類型,且各擴散摻雜區114之摻雜濃度分布會隨著越接近摻雜物來源層112而具有較高之摻雜濃度。亦即,各擴散摻雜區114鄰近各溝槽之側壁之摻雜濃度大於各擴散摻雜區114遠離各溝槽之側壁之摻雜濃度。於本實施例中,第一導電類型為N型,且第二導電類型為P型,但不限於此,本發明之第一導電類型與第二導電類型亦可互換。並且,形成摻雜物來源層112之材料包含有硼矽玻璃(Boron silicate glass,BSG),但不限於此,本發明之摻雜物來源層112之材料可根據所欲形成之擴散摻雜區114的導電類型來決定。於本發明之其他實施例中,形成P型摻雜物來源層之方法亦可利用P型離子佈植製程,於N型半導體基底中植入P型離子,然後進行熱趨入製程來形成P型摻雜物來源層,但不以此為限。
如第6圖所示,然後,進行另一蝕刻製程,移除摻雜物來源層112。隨後,進行一熱氧化製程,於各溝槽110之側壁以及底部形成一氧化層116。由於各P型擴散摻雜區114是藉由於含矽之N型半導體基底102中摻雜P型摻雜物而形成,因此各P型擴散摻雜區114包含矽。並且,各P型擴散摻雜區114之一部分與各溝槽110之各側壁相接觸而被曝露出,因此曝露出之各P型擴散摻雜區114之一部分會與氧反應,而成為氧化層116之一部分。換句話說,鄰近各溝槽之側壁且具有較高濃度之各P型擴散摻雜區114之一部分會因與氧反應而成為氧化層116。於本實施例中,氧化層116之厚度可約略介於10埃(angstrom)與10000埃之間,但本發明不以此為限。並且,熱氧化製程所通入之一氣體可包括水氣(H2O)、氧氣(O2)、氯化氫(HCl)與水氣之混合氣體、氯化氫與氧氣之混合氣體、氮氣(N2)與水氣之混合氣體或氮氣與氧氣之混合氣體。熱氧化製程之一溫度範圍可介於800℃與1200℃之間,且其壓力範圍可約略介於600托耳(Torr)至760托耳之間。但本發明之熱氧化製程之條件並不以上述為限。
如第7圖所示,接著,移除氧化層116,亦即移除具有較高濃度且與氧反應而成為氧化層116之各P型擴散摻雜區114之一部分,並曝露出具有較低摻雜濃度之各P型擴散摻雜區114。至此,所形成之各P型擴散摻雜區114與N型半導體基底102分別形成一PN接面,約略垂直N型半導體基底102,亦即本實施例之超級介面結構。於本實施例中,移除氧化層116之步驟包括一濕式蝕刻製程,以移除位於硬遮罩層106下方之氧化層116,但不限於此。並且,由於各P型擴散摻雜區114之一部分會被移除,因此各溝槽110在移除氧化層116之步驟之後會具有一第二寬度W2,且第二寬度W2大於各開口108之寬度。值得注意的是,由於具有較高濃度之各P型擴散摻雜區114會與氧反應而成為氧化層116,且在移除氧化層116之步驟會被移除,因此所留下之各P型擴散摻雜區114之表面摻雜濃度可有效地被降低,以均勻化超級介面結構中之電洞濃度與電子濃度,進而提升超級介面結構的耐壓能力。
如第8圖所示,然後,進行另一沉積製程,於硬遮罩層106上形成一絕緣材料層,例如:氧化矽,且絕緣材料層填滿於各溝槽110中。然後,進行一化學機械研磨(Chemical Mechanical Polishing,CMP)製程,移除位於硬遮罩層106上之絕緣材料層。接著,進行另一蝕刻製程,移除位於開口108中之絕緣材料層,以於各溝槽110中形成一絕緣層118。於本實施例中,絕緣層118之上表面約略與墊層104之上表面位於同一平面,但本發明並不限於此,絕緣層118之上表面亦可介於墊層104之上表面與N型半導體基底102之上表面之間,或與N型半導體基底102之上表面位於同一平面。
如第9圖所示,隨後,移除硬遮罩層106與墊層104,並曝露出N型半導體基底102。接著,進行另一熱氧化製程,於N型半導體基底102上形成一閘極絕緣層120。然後,於閘極絕緣層120與絕緣層118上覆蓋一導電材料層,例如多晶矽。隨後,進行另一微影暨蝕刻製程,圖案化導電材料層,以於二相鄰溝槽110之間的N型半導體基底102上分別形成一閘極導電層122,作為功率電晶體元件之閘極,且各閘極導電層122與位於各閘極導電層122以及N型半導體基底102之間的閘極絕緣層120構成一閘極結構124。於本實施例中,閘極絕緣層120之上表面約略與絕緣層118之上表面位於同一平面,但不限於此。於本發明之其他實施例中,閘極結構亦可僅為單一個,而可於其中一溝槽110之一側之N型半導體基底102上形成閘極結構124。
如第10圖所示,接著,以閘極導電層122為遮罩,進行一P型離子佈值製程以及另一熱趨入製程,於各閘極結構124之二側的N型半導體基底102中分別形成二P型基體摻雜區126,且各P型基體摻雜區126與各P型擴散摻雜區114相接觸,並與各閘極結構124部分重疊,以作為功率電晶體元件之基極。
如第11圖所示,然後,利用一光罩(圖未示),進行一N型離子佈值製程以及另一熱趨入製程,於各P型基體摻雜區126中形成一N型源極摻雜區128,分別與各閘極結構124部分重疊,以作為功率電晶體元件之源極。本發明之閘極結構124、P型基體摻雜區126以及N型源極摻雜區128並不限分別具有複數個,且亦可僅具有單一個,並可依據實際需求來作相對應調整。
如第12圖所示,接著,於閘極結構124以及絕緣層118上覆蓋一介電層130,例如氧化矽。然後,進行另一微影暨蝕刻製程,於介電層130中形成複數個接觸洞130a,並移除部分閘極絕緣層120以及絕緣層118。各接觸洞130a曝露出N型源極摻雜區128與P型基體摻雜區126。接著,進行另一P型離子佈植製程與另一熱趨入製程,以於各P型基體摻雜區126中形成一P型接觸摻雜區132。
如第13圖所示,然後,進行另一沉積製程,於介電層130上與接觸洞130a之側壁與底部覆蓋一阻障層134,例如鈦或氮化鈦。接著,於阻障層上形成一源極金屬層136,且源極金屬層136填滿接觸洞130a,並覆蓋於介電層130上。並且,於N型半導體基底102下形成一汲極金屬層138。至此已完成本實施例之功率電晶體元件100。於本實施例中,形成源極金屬層136與汲極金屬層138之步驟可分別包含進行電漿濺鍍或電子束沉積等製程,且源極金屬層136與汲極金屬層138可分別包括鈦、氮化鈦、鋁、鎢等金屬或金屬化合物,但不限於此。
本發明之功率電晶體元件之超級介面結構之製作方法並不以上述實施例為限。下文將繼續揭示本發明之其它實施例或變化形,然為了簡化說明並突顯各實施例或變化形之間的差異,下文中使用相同標號標注相同元件,並不再對重複部分作贅述。
請參考第14圖與第15圖,且一併參考第4圖至第7圖。第14圖與第15圖為本發明另一較佳實施例之超級介面結構之製作方法。相較於上述實施例,本實施例之製作方法另於移除摻雜物來源層之步驟與形成氧化層之熱氧化製程之間依序進行填入另一摻雜物來源層之步驟、另一熱趨入製程以及移除該另一摻雜物來源層之步驟至少一次,以用於調整P型擴散摻雜區之摻雜濃度,進而達到所欲之摻雜濃度。本實施例之製作方法於形成P型擴散摻雜區之步驟之前與上述實施例相同,如第4圖至第第5圖所示。接著,如第14圖所示,移除摻雜物來源層112,然後填入另一摻雜物來源層202。於本實施例中,摻雜物來源層202是與上述實施例之摻雜物來源層112相同,例如硼矽玻璃(Boron silicate glass,BSG),且亦具有複數個P型摻雜物,但本發明不限於此。隨後,進行另一熱趨入製程,將P型摻雜物擴散至P型擴散摻雜區114中,以增加P型擴散摻雜區114之摻雜濃度。然後,如第15圖所示,移除摻雜物來源層202。本實施例之後續步驟與上述實施例相同,如第6圖與第7圖所示,因此不再在此贅述。於本發明之其他實施例中,為了調整P型擴散摻雜區114之摻雜濃度,以達到所欲之摻雜濃度,亦可重複進行填入另一摻雜物來源層202之步驟、另一熱趨入製程以及移除該另一摻雜物來源層202之步驟複數次。
於本發明之其他實施例中,亦可藉由重複依序進行填入另一摻雜物來源層之步驟、另一熱趨入製程、移除該另一摻雜物來源層之步驟、熱氧化製程以及移除氧化層之步驟複數次,來達到所欲之P型擴散摻雜區之摻雜濃度,進而製作出所欲之超級介面結構。
綜上所述,本發明利用熱氧化製程,使鄰近各溝槽之側壁且具有較高濃度之各擴散摻雜區與氧反應而成為氧化層,藉此後續進行將氧化層移除之步驟會將具有較高濃度之擴散摻雜區之一部分移除,因此所留下之各擴散摻雜區之表面摻雜濃度可有效地被降低,以均勻化超級介面結構中之電洞濃度與電子濃度,進而提升超級介面結構的耐壓能力。
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
10...半導體基底
10a...上表面
12...擴散摻雜區
14...氧化層
100...功率電晶體元件
102...半導體基底
102a...基材
102b...磊晶層
104...墊層
106...硬遮罩層
108...開口
110...溝槽
112...摻雜物來源層
114...擴散摻雜區
116...氧化層
118...絕緣層
120...閘極絕緣層
122...閘極導電層
124...閘極結構
126...基體摻雜區
128...源極摻雜區
130...介電層
130a...接觸洞
132...接觸摻雜區
134...阻障層
136...源極金屬層
138...汲極金屬層
W1...第一寬度
W2...第二寬度
第1圖至第3圖為本發明一較佳實施例之降低擴散摻雜區之表面摻雜濃度之方法示意圖。
第4圖至第13圖為本發明一較佳實施例之功率電晶體元件之製作方法示意圖。
第14圖與第15圖為本發明另一較佳實施例之超級介面結構之製作方法。
102...半導體基底
102a...基材
102b...磊晶層
104...墊層
106...硬遮罩層
108...開口
110...溝槽
114...擴散摻雜區
116...氧化層
Claims (20)
- 一種超級介面結構之製作方法,包括:提供一半導體基底,具有一第一導電類型;於該半導體基底中形成至少一溝槽;於該溝槽之二側之該半導體基底中分別形成二擴散摻雜區,其中各該擴散摻雜區鄰近該溝槽之側壁之摻雜濃度大於各該擴散摻雜區遠離該溝槽之側壁之摻雜濃度,且各該擴散摻雜區具有不同於該第一導電類型之一第二導電類型;進行一熱氧化製程,於該溝槽之側壁形成一氧化層,其中與該溝槽之側壁相接觸之各該擴散摻雜區之一部分與氧反應為該氧化層之一部分;以及移除該氧化層。
- 如請求項1之超級介面結構之製作方法,其中形成該等擴散摻雜區之步驟包括:於該溝槽中填入一摻雜物來源層,其中該摻雜物來源層包括複數個摻雜物,且該等摻雜物具有該第二導電類型;以及進行一熱趨入製程,將該等摻雜物擴散至該半導體基底中,以形成該等擴散摻雜區。
- 如請求項2之超級介面結構之製作方法,其中於形成該等擴散摻雜區之步驟與進行該熱氧化製程之間,該製作方法另包括移除該摻雜物來源層。
- 如請求項3之超級介面結構之製作方法,其中於進行熱氧化製程與移除該摻雜物來源層之步驟之間,該製作方法另包括依序進行填入另一摻雜物來源層之步驟、另一熱趨入製程以及移除該另一摻雜物來源層之步驟至少一次。
- 如請求項1之超級介面結構之製作方法,其中提供該半導體基底之步驟與形成該溝槽之步驟之間,該製作方法另包括於該半導體基底上形成一硬遮罩層,且該硬遮罩層具有至少一開口。
- 如請求項5之超級介面結構之製作方法,其中於移除該氧化層之步驟之後,該溝槽具有一寬度,大於該開口之一寬度。
- 如請求項1之超級介面結構之製作方法,其中移除該氧化層之步驟包括一濕式蝕刻製程。
- 如請求項1之超級介面結構之製作方法,其中該熱氧化製程所通入之一氣體包括水氣(H2O)、氧氣(O2)、氯化氫(HCl)與水氣之混合氣體、氯化氫與氧氣之混合氣體、氮氣(N2)與水氣之混合氣體或氮氣與氧氣之混合氣體。
- 如請求項1之超級介面結構之製作方法,其中該熱氧化製程之一溫度範圍介於800℃與1200℃之間。
- 一種功率電晶體元件之製作方法,包括:提供一半導體基底,具有一第一導電類型;於該半導體基底中形成至少一溝槽;於該溝槽之二側之該半導體基底中分別形成二擴散摻雜區,其中各該擴散摻雜區鄰近該溝槽之側壁之摻雜濃度大於各該擴散摻雜區遠離該溝槽之側壁之摻雜濃度,且各該擴散摻雜區具有不同於該第一導電類型之一第二導電類型;進行一熱氧化製程,於該溝槽之側壁以及底部形成一氧化層,其中與該溝槽之側壁相接觸之各該擴散摻雜區之一部分與氧反應為該氧化層之一部分;移除該氧化層;於該溝槽中形成一絕緣層;於該溝槽之至少一該側之該半導體基底上形成一閘極結構;於該閘極結構之二側的該半導體基底中分別形成二基體摻雜區,且各該基體摻雜區分別與各該擴散摻雜區相接觸,其中該等基體摻雜區具有該第二導電類型;以及於各該基體摻雜區中分別形成一源極摻雜區。
- 如請求項10所述之功率電晶體元件之製作方法,其中形成該等擴散摻雜區之步驟包括:於該溝槽中填入一摻雜物來源層,其中該摻雜物來源層包括複數個摻雜物,且該等摻雜物具有該第二導電類型;以及進行一熱趨入製程,將該等摻雜物擴散至該半導體基底中,以形成該等擴散摻雜區。
- 如請求項11之功率電晶體元件之製作方法,其中於形成該等擴散摻雜區之步驟與進行該熱氧化製程之間,該製作方法另包括移除該摻雜物來源層。
- 如請求項12之功率電晶體元件之製作方法,其中於進行熱氧化製程與移除該摻雜物來源層之步驟之間,該製作方法另包括依序進行填入另一摻雜物來源層之步驟、另一熱趨入製程以及移除該另一摻雜物來源層之步驟至少一次。
- 如請求項10之功率電晶體元件之製作方法,其中提供該半導體基底之步驟與形成該溝槽之步驟之間,該製作方法另包括於該半導體基底上形成一硬遮罩層,且該硬遮罩層具有至少一開口。
- 如請求項14之功率電晶體元件之製作方法,其中於移除該氧化層之步驟之後,該溝槽具有一寬度,大於該開口之一寬度。
- 如請求項14之功率電晶體元件之製作方法,其中於形成該絕緣層之步驟與形成該閘極結構之步驟之間,該製作方法另包括移除該硬遮罩層。
- 如請求項10之功率電晶體元件之製作方法,其中移除該氧化層之步驟包括一濕式蝕刻製程。
- 如請求項10之功率電晶體元件之製作方法,其中該熱氧化製程所通入之一氣體包括水氣、氧氣、氯化氫與水氣之混合氣體、氯化氫與氧氣之混合氣體、氮氣與水氣之混合氣體或氮氣與氧氣之混合氣體。
- 如請求項10之功率電晶體元件之製作方法,其中該熱氧化製程之一溫度範圍介於800℃與1200℃之間。
- 一種降低擴散摻雜區之表面摻雜濃度之方法,包括:提供一半導體基底,該半導體基底具有一擴散摻雜區設於其中,且該擴散摻雜區與該半導體基底之一表面相接觸,其中該擴散摻雜區鄰近該表面之摻雜濃度大於該擴散摻雜區遠離該表面之摻雜濃度;進行一熱氧化製程,於該半導體基底之該表面形成一氧化層,其中與該表面相接觸之該擴散摻雜區之一部分與氧反應為該氧化層之一部分;以及移除該氧化層。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW101103343A TW201334036A (zh) | 2012-02-02 | 2012-02-02 | 降低擴散摻雜區之表面摻雜濃度之方法、超級介面結構之製作方法以及功率電晶體元件之製作方法 |
CN2012100841879A CN103247533A (zh) | 2012-02-02 | 2012-03-22 | 功率晶体管组件的制作方法 |
US13/537,080 US20130203229A1 (en) | 2012-02-02 | 2012-06-29 | Method of reducing surface doping concentration of doped diffusion region, method of manufacturing super junction using the same and method of manufacturing power transistor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW101103343A TW201334036A (zh) | 2012-02-02 | 2012-02-02 | 降低擴散摻雜區之表面摻雜濃度之方法、超級介面結構之製作方法以及功率電晶體元件之製作方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW201334036A true TW201334036A (zh) | 2013-08-16 |
Family
ID=48903245
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW101103343A TW201334036A (zh) | 2012-02-02 | 2012-02-02 | 降低擴散摻雜區之表面摻雜濃度之方法、超級介面結構之製作方法以及功率電晶體元件之製作方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20130203229A1 (zh) |
CN (1) | CN103247533A (zh) |
TW (1) | TW201334036A (zh) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104465389B (zh) * | 2013-09-25 | 2017-07-11 | 中国科学院微电子研究所 | FinFet器件源漏区的形成方法 |
CN110429140A (zh) * | 2019-08-06 | 2019-11-08 | 上海朕芯微电子科技有限公司 | 一种超结mosfet结构及其制备方法 |
CN113937156B (zh) * | 2021-10-11 | 2023-07-04 | 上海华虹宏力半导体制造有限公司 | 半导体结构及其形成方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4214919A (en) * | 1978-12-28 | 1980-07-29 | Burroughs Corporation | Technique of growing thin silicon oxide films utilizing argon in the contact gas |
US5279987A (en) * | 1991-10-31 | 1994-01-18 | International Business Machines Corporation | Fabricating planar complementary patterned subcollectors with silicon epitaxial layer |
US6461918B1 (en) * | 1999-12-20 | 2002-10-08 | Fairchild Semiconductor Corporation | Power MOS device with improved gate charge performance |
US6528850B1 (en) * | 2000-05-03 | 2003-03-04 | Linear Technology Corporation | High voltage MOS transistor with up-retro well |
US6660571B2 (en) * | 2000-06-02 | 2003-12-09 | General Semiconductor, Inc. | High voltage power MOSFET having low on-resistance |
US6982193B2 (en) * | 2004-05-10 | 2006-01-03 | Semiconductor Components Industries, L.L.C. | Method of forming a super-junction semiconductor device |
US7977766B2 (en) * | 2009-03-10 | 2011-07-12 | International Business Machines Corporation | Trench anti-fuse structures for a programmable integrated circuit |
US8159008B2 (en) * | 2009-09-18 | 2012-04-17 | International Business Machines Corporation | Method of fabricating a trench-generated transistor structure |
US8084811B2 (en) * | 2009-10-08 | 2011-12-27 | Monolithic Power Systems, Inc. | Power devices with super junctions and associated methods manufacturing |
US8648413B2 (en) * | 2009-12-28 | 2014-02-11 | Force Mos Technology Co., Ltd. | Super-junction trench MOSFET with multiple trenched source-body contacts |
US8372717B2 (en) * | 2009-12-28 | 2013-02-12 | Force Mos Technology Co., Ltd. | Method for manufacturing a super-junction trench MOSFET with resurf stepped oxides and trenched contacts |
TWI446521B (zh) * | 2011-04-21 | 2014-07-21 | Anpec Electronics Corp | 功率元件之耐壓終止結構 |
TWI441261B (zh) * | 2011-05-13 | 2014-06-11 | Anpec Electronics Corp | 半導體功率元件的製作方法 |
-
2012
- 2012-02-02 TW TW101103343A patent/TW201334036A/zh unknown
- 2012-03-22 CN CN2012100841879A patent/CN103247533A/zh active Pending
- 2012-06-29 US US13/537,080 patent/US20130203229A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20130203229A1 (en) | 2013-08-08 |
CN103247533A (zh) | 2013-08-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI668744B (zh) | 半導體裝置及其形成方法 | |
JP5203558B2 (ja) | トランジスタ及びこれの製造方法 | |
JP5173582B2 (ja) | 半導体装置 | |
KR100711520B1 (ko) | 리세스된 게이트 전극용 구조물과 그 형성 방법 및리세스된 게이트 전극을 포함하는 반도체 장치 및 그 제조방법. | |
TWI446459B (zh) | 具有超級介面之功率電晶體元件之製作方法 | |
TWI469351B (zh) | 具有超級介面之功率電晶體元件及其製作方法 | |
US9099321B2 (en) | Method for fabricating power semiconductor device | |
TWI572008B (zh) | 具有超接面結構的半導體元件及其製造方法 | |
JP2012004473A (ja) | 半導体装置及び半導体装置の製造方法 | |
TWI779616B (zh) | 具有石墨烯系元素的半導體元件及其製備方法 | |
TWI470699B (zh) | 具有超級介面之溝槽型功率電晶體元件及其製作方法 | |
US8835264B1 (en) | Method for fabricating power semiconductor device | |
US20130307064A1 (en) | Power transistor device and fabricating method thereof | |
TW201334036A (zh) | 降低擴散摻雜區之表面摻雜濃度之方法、超級介面結構之製作方法以及功率電晶體元件之製作方法 | |
TWI478341B (zh) | 功率電晶體元件及其製作方法 | |
JP2012227276A (ja) | 半導体装置およびその製造方法 | |
US8883587B2 (en) | Method of manufacturing semiconductor device | |
KR100832017B1 (ko) | 채널면적을 증가시킨 반도체소자 및 그의 제조 방법 | |
CN115101477B (zh) | 一种半导体结构及其制造方法 | |
KR20100089023A (ko) | 플라즈마 탈수소화를 이용한 반도체 장치의 제조 방법 및 이에 의해 형성된 장치 | |
TWI548090B (zh) | 半導體裝置及其製作方法 | |
JP2015070192A (ja) | 半導体装置の製造方法、半導体装置 | |
CN117153866B (zh) | 一种半导体器件及其制作方法 | |
TWI642116B (zh) | 製作半導體元件的方法 | |
TWI405271B (zh) | 製作具有超級介面之功率半導體元件之方法 |