TW201332238A - Optical tilted charge devices and methods - Google Patents
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
Abstract
Description
本發明係關於半導體發光裝置及技術之領域，且更特定而言，係關於傾斜電荷發光裝置及方法。 The present invention relates to the field of semiconductor light emitting devices and techniques, and more particularly to oblique charge light emitting devices and methods.
本發明之背景中包含與異質接面雙極電晶體(HBT，其係電傾斜電荷裝置)以及發光電晶體、電晶體雷射及傾斜電荷發光二極體(分別係LET、TL及TCLED，所有該等裝置係光學傾斜電荷裝置)相關之技術。一傾斜電荷裝置依據裝置之基極區域中之能量圖特性而得其名，該基極區域近似具有自射極介面至集極(或針對一個兩端子裝置，汲極)介面之一下降斜波形狀。此表示呈動態流(經由集極(或汲極)「快」載子復合且「慢」載子退出)之載子之一傾斜電荷群集。 The background of the present invention includes a heterojunction bipolar transistor (HBT, which is an electric tilt charge device) and a light-emitting transistor, a transistor laser, and a tilt-charge light-emitting diode (all LET, TL, and TCLED, respectively) These devices are related to optical tilt charge devices. A tilted charge device is named according to the characteristics of the energy map in the base region of the device, the base region having approximately one of the self-emitter interface to the collector (or for a two-terminal device, the drain) interface shape. This represents a tilt charge cluster that is a dynamic stream (via the collector (or bungee) "fast" carrier recombination and the "slow" carrier exit).
關於在裝置之基極區域中通常採用一或多個量子大小區域之光學傾斜電荷裝置及技術，可參考(舉例而言)第7,091,082、7,286,583、7,354,780、7,535,034、7,693,195、7,696,536、7,711,015、7,813,396、7,888,199、7,888,625、7,953,133、7,998,807、8,005,124、8,179,937及8,179,939號美國專利；第US 2005/0040432、US 2005/0054172、US 2008/0240173、US 2009/0134939、US 2010/0034228、US 2010/0202483、US 2010/0202484、US 2010/0272140、US 2010/0289427、US 2011/0150487及US 2012/0068151號美國專利申請公開 案；及第WO/2005/020287及WO/2006/093883號PCT國際專利公開案以及第US2012/0068151號美國專利申請公開案中所引用之公開案。 For optical tilting charge devices and techniques that typically employ one or more quantum-sized regions in the base region of the device, reference is made, for example, to 7,091,082, 7,286,583, 7,354,780, 7,535,034, 7,693,195, 7,696,536, 7,711,015, 7,813,396, 7,888,199 , U.S. Patent Nos. 7,888,625, 7,953,133, 7,998,807, 8,005,124, 8,179,937 and 8,179,939; US 2005/0040432, US 2005/0054172, US 2008/0240173, US 2009/0134939, US 2010/0034228, US 2010/0202483, US 2010/ US Patent Application Publication No. 0202484, US 2010/0272140, US 2010/0289427, US 2011/0150487, and US 2012/0068151 And the publications cited in the PCT International Patent Publication No. WO/2005/020287 and WO/2006/093883, and the US Patent Application Publication No. US-A-2012/0068151.
一光學傾斜電荷裝置包含一作用區域，該作用區域具有一個極性之內建自由多數載子。在此作用區域之一個輸入處，注入相反極性之一單個種類之少數載子且允許其跨越該作用區域擴散。此作用區域具有達成及增強多數載子之傳導及少數載子之輻射復合之特徵。在該區域之輸出側上，然後由一單獨及較快機構收集、排出、損耗或復合少數載子。電觸點耦合至此全功能區域。 An optical tilting charge device includes an active region having a built-in free majority carrier of one polarity. At one input of this active region, a small number of carriers of a single species of opposite polarity are injected and allowed to diffuse across the active region. This area of action has the characteristics of achieving and enhancing the conduction of majority carriers and the radiation recombination of minority carriers. On the output side of the zone, minority carriers are then collected, discharged, depleted or compounded by a single and faster mechanism. Electrical contacts are coupled to this fully functional area.
在2004年初，一公開案闡述一種光學傾斜電荷裝置，該光學傾斜電荷裝置將一量子井併入於該裝置之基極區域中以便增強輻射復合(參見M.Feng、N.Holonyak Jr.及R.Chan之Quantum-Well-Base Heterojunction Bipolar Light-Emitting Transistor，應用物理第84期，1952，2004)。在彼論文中，證明光學信號以高達1 GHz之速度跟隨正弦電輸入信號。5餘年之後，在進一步研究及基本開發(以及與操作方法、作用區設計及磊晶層結構相關之其他開發)之後，報道了作為自發發射發光體之高速傾斜電荷裝置以4.3 GHz(LET)之頻寬且稍後以7 GHz(TCLED)之頻寬操作。(參見G.Walter、C.H.Wu、H.W.Then、M.Feng及N.Holonyak Jr.之Titled-Charge High Speed(7 GHz)Light Emitting Diode，應用物理第94期，231125，2009)。儘管自彼時以來已達成進一步改良，但期望效率及頻寬之額外 進展以供達成商業上可行之光電裝置及技術。 In early 2004, a publication set forth an optical tilt charge device that incorporates a quantum well into the base region of the device to enhance radiation recombination (see M. Feng, N. Holonyak Jr., and R). .Chan's Quantum-Well-Base Heterojunction Bipolar Light-Emitting Transistor, Applied Physics No. 84, 1952, 2004). In his paper, it was demonstrated that the optical signal follows the sinusoidal electrical input signal at speeds up to 1 GHz. After more than five years, after further research and basic development (and other developments related to the method of operation, the design of the active zone and the structure of the epitaxial layer), a high-speed tilting charge device as a spontaneous emission illuminator was reported at 4.3 GHz (LET). The bandwidth is wide and later operates at a bandwidth of 7 GHz (TCLED). (See G. Walter, C. H. Wu, H. W. The, M. Feng, and N. Holonyak Jr., Titled-Charge High Speed (7 GHz) Light Emitting Diode, Applied Physics, 94, 231125, 2009). Although further improvements have been made since then, expectations for efficiency and bandwidth are additional Progress for the achievement of commercially viable optoelectronic devices and technologies.
舉例而言，上文所列舉之文件中所揭示類型之傾斜電荷發光裝置(舉例而言，呈發光電晶體及傾斜電荷發光電晶體及傾斜電荷發光二極體之形式)可以相對高之速度及頻寬產生自發發光。然而，對於某些應用，將期望具有可以高得多之速度及頻寬操作之傾斜電荷自發發光裝置及技術，且此等裝置及技術之達成在本發明之態樣中之一者之目標當中。 For example, tilt charge illuminating devices of the type disclosed in the documents listed above (for example, in the form of illuminating transistors and tilted charge illuminating transistors and tilting charge illuminating diodes) can be relatively high speed and The bandwidth produces spontaneous illumination. However, for certain applications, it would be desirable to have tilted charge spontaneous illumination devices and techniques that can operate at much higher speeds and bandwidths, and the achievement of such devices and techniques is among the objectives of one of the aspects of the present invention. .
在第US 2010/202484號美國專利申請公開案中，展示具有一深QW設計及均質摻雜之基極區域之一QW異質接面雙極發光電晶體(QW-HBLET)作為背景。可參考(舉例而言)上文所引用之專利。相對深之QW輔助所擷取載子橫向散佈且遠離光學腔復合。除彼狀況(如該等載子橫向散佈)之外，該等載子亦可再熱化，且朝向射極再熱化(回擴散)之載子大多數丟失至非輻射復合中。作為對其之一改良，陳述一種不對稱基極區域，該不對稱基極區域具有在射極側上之一相對較寬之帶隙基極子區域(QW)(與集極側上之一相對窄之帶隙子區域相比)。此外，出於包含限制所擷取載子之擴散及增加速度之原因而使用一或多個淺量子井。 In the U.S. Patent Application Publication No. US 2010/202,484, a QW heterojunction bipolar luminescent transistor (QW-HBLET) having a deep QW design and a homogeneously doped base region is shown as a background. Reference may be made, for example, to the patents cited above. The relatively deep QW assists the captured carriers to spread laterally and away from the optical cavity. In addition to the conditions (such as the lateral spread of the carriers), the carriers can be reheated, and most of the carriers that are reheated (back to diffuse) toward the emitter are lost to the non-radiative recombination. As a modification thereof, an asymmetric base region having a relatively wide bandgap base region (QW) on the emitter side is provided (as opposed to one of the collector sides) Compared to the narrow band gap sub-region). In addition, one or more shallow quantum wells are used for reasons that include limiting the spread and increasing speed of the captured carriers.
申請人之研究已指示，在一光學傾斜電荷裝置(OTCD)之基極區域中使用重摻雜高組合物合金(例如，三元或四元材料)可導致顯著較高之非輻射復合(ηnon-rad，基極復合之大約30%至90%)。此研究中之某些研究已集中於具有可耦合至基於InP/InGaAs之光偵測器之發射光子能量之一相 對淺InGaAs量子井(△E(量子井深度能量)係kT之一小倍數，△E~kT)之使用。(亦參見上文所引用之公開申請案US 2010/0202484)。使用一淺量子井允許利用聲子作為增加光學傾斜電荷裝置之速度之一方法。△然而，存在其中一深量子井(△E>>kT)有利之光學傾斜電荷裝置之特定應用，且裝置速度係為一較小擔憂問題；舉例而言，在於變化之偏壓電流特性或溫度下要求高基極電流密度操作及穩定電流增益之光學裝置中。對於此等應用，具有其附帶缺點之一高組合物合金基極(例如，AlGaAs)之使用將看似不可避免。 Applicant's research has indicated that the use of heavily doped high composition alloys (eg, ternary or quaternary materials) in the base region of an optically tilted charge device (OTCD) can result in significantly higher non-radiative recombination (η) Non-rad , approximately 30% to 90% of the base compound). Some of the research in this study has focused on a small multiple of a shallow InGaAs quantum well (ΔE (quantum well depth energy)) kT with one of the emitted photon energy that can be coupled to an InP/InGaAs based photodetector, Use of △E~kT). (See also published application US 2010/0202484, cited above). The use of a shallow quantum well allows the use of phonons as one of the ways to increase the speed of an optical tilt charge device. △ However, there is a specific application of an optical tilt charge device in which a deep quantum well (ΔE>>kT) is advantageous, and the device speed is a minor concern; for example, a varying bias current characteristic or temperature The optical device requires high base current density operation and stable current gain. For such applications, the use of a high composition alloy base (e.g., AlGaAs) with one of its attendant drawbacks would appear to be inevitable.
提供需要使用相對深之量子井之光學傾斜電荷裝置之改良同時避免伴隨缺陷在本發明之其他目的當中。 It would be advantageous to provide an improvement in optical tilt charge devices that require the use of relatively deep quantum wells while avoiding accompanying defects.
可提出以下問題：如何設計一種有效、高速自發發射傾斜電荷裝置？舉例而言，如何使一頻寬自0.1 GHz漸進至10 GHz？一種方法可係使裝置區較小且較窄以產生較小電阻(R)、較小電容(C)及較小電感(L)，或僅僅利用最快InGaP/GaAs異質接面雙極電晶體(HBT)之設計規則。此將達不成該目標。 The following questions can be asked: How to design an effective, high-speed spontaneous emission tilt charge device? For example, how do you make a bandwidth from 0.1 GHz to 10 GHz? One method is to make the device area smaller and narrower to produce a smaller resistance (R), a smaller capacitance (C), and a smaller inductance (L), or to use only the fastest InGaP/GaAs heterojunction bipolar transistor (HBT) design rules. This will not achieve this goal.
儘管其源自電晶體技術，但光學傾斜電荷裝置與高速HBT電晶體(一電傾斜電荷裝置)共用極少共同設計特質。一光學傾斜電荷裝置在其基極區域中具有一量子大小區域(通常為一或多個量子井)。舉例而言，在一電晶體之基極中添加一量子井不僅引入另一元素或缺陷以輔助復合，而 且引入能夠儲存電荷、橫向輸送及再熱化所擷取載子之一結構。此外，在顯著較低電增益(較高基極電流比率)之情形下，放大與基極薄片電阻相關聯之問題(加熱、射極群聚)及與基極電流密度相關聯之問題(可靠性)，且因對在低射極電流密度下之橫向電阻及射極群聚之關注而使基極渡越時間之重要性(HBT之設計中之一大問題)相形見絀。當設計一高速光學傾斜電荷裝置時，光學提取、光束形狀及光學功率輸出可與該裝置之電增益及電頻寬一樣重要。甚至不能將HBT社群已成功地遵循之設計規則(可藉由連續地縮減基極射極接面及基極集極接面之尺寸來增加一HBT之速度)用於一傾斜電荷發光體，此乃因此實體尺寸減小導致愈來愈小之輻射復合效率。因此，應理解，適合於一純電輸入/輸出傾斜電荷裝置之設計規則未必適合於亦要求一光學輸出之最佳化之裝置。 Although it is derived from transistor technology, optical tilt charge devices share very little co-design features with high speed HBT transistors (an electrically tilted charge device). An optical tilt charge device has a quantum size region (typically one or more quantum wells) in its base region. For example, adding a quantum well to the base of a transistor not only introduces another element or defect to aid recombination, but And introducing a structure capable of storing charge, laterally transporting, and reheating the captured carrier. In addition, in the case of significantly lower electrical gain (higher base current ratio), amplifying the problems associated with base sheet resistance (heating, emitter clustering) and problems associated with base current density (reliable Sexuality, and the importance of base transit time (a big problem in the design of HBT) is dwarfed by concerns about lateral resistance and emitter clustering at low emitter current densities. When designing a high speed optical tilt charge device, optical extraction, beam shape and optical power output can be as important as the device's electrical gain and electrical bandwidth. It is not even possible to successfully follow the design rules of the HBT community (which can increase the speed of an HBT by continuously reducing the size of the base emitter junction and the base collector junction) for a tilted charge illuminator, This is why the reduction in physical size results in increasingly smaller radiation recombination efficiencies. Accordingly, it should be understood that the design rules suitable for a purely electrical input/output tilt charge device are not necessarily suitable for devices that also require an optical output to be optimized.
類似地，高速光學傾斜電荷裝置與電荷儲存發光體(亦即，二極體雷射或發光二極體)共用極少共同設計特質。舉例而言，儘管兩者皆使用諸如一量子井之結構，但一光學電荷儲存裝置之設計規則需要最大化載子之侷限或儲存(以改良其中所擷取載子「等待」由一光子場激發或藉由自發發射復合之受激發射程序之機率)之方法，而一光學傾斜電荷裝置之設計規則需要所儲存載子之最小化。甚至電荷儲存裝置中所使用的用於光提取之設計規則由於強加於傾斜電荷裝置之實體設計約束(不同幾何形狀)及高速應用(例如，與一高速互連件之相容性)而並非簡單地適用於 傾斜電荷裝置。 Similarly, high speed optical tilt charge devices share little co-design features with charge storage illuminators (i.e., diode lasers or light emitting diodes). For example, although both use a structure such as a quantum well, the design rules of an optical charge storage device need to maximize the limitations or storage of the carriers (to improve the "waiting" of the captured carriers from a photon field. The method of exciting or by spontaneously emitting the probability of a compounded excited emission procedure, while the design rule of an optically tilted charge device requires the minimization of stored carriers. Even the design rules for light extraction used in charge storage devices are not simple due to the physical design constraints (different geometries) imposed on the tilt charge device and high speed applications (eg, compatibility with a high speed interconnect). Suitable for Tilt the charge device.
因此，對一光學傾斜電荷裝置之設計考量並非係關於找到用於一HBT之設計規則與用於一個二極體發光體之彼等設計規則之間的一平衡；換言之，並非關於決策該裝置應更似一HBT還是更似一個二極體發光體。而是，用於一傾斜電荷發光裝置之設計典範應取決於特定電荷動態、幾何形狀、光學特性及裝置所唯一之應用。如將揭示，本發明之一態樣涉及減少與基極表面復合相關聯之非輻射復合。本發明之另一態樣涉及與量子井中之電子之橫向輸送及無意侷限相關聯之基極電荷電容之減小。 Therefore, the design considerations for an optical tilt charge device are not related to finding a balance between the design rules for an HBT and their design rules for a diode illuminator; in other words, not for decision making the device should More like an HBT or more like a diode illuminator. Rather, the design paradigm for a tilted charge illuminator should depend on the particular charge dynamics, geometry, optical characteristics, and the application to which the device is unique. As will be disclosed, one aspect of the present invention relates to reducing non-radiative recombination associated with base surface recombination. Another aspect of the invention relates to a reduction in the base charge capacitance associated with lateral transport of electrons in a quantum well and unintentional limitations.
與QW與基極表面之間的一薄基極層厚度(「基極1」區域)(例如，小於約300埃之一層厚度)一起使用一異質接面雙極電晶體(HBT)中之一量子井(QW)引入載子自該量子井穿隧至該等載子於其處非輻射地復合之表面狀態中之問題。先前已揭示使用一不對稱基極區域作為用於減少QW中之所擷取電子朝向表面之熱化之一技術(參見第US 2010/0202484號美國專利申請公開案)。此有助於減少非輻射復合，且由於電子再熱化較佳地朝向集極，因此其亦輔助減少電子之橫向輸送。不對稱基極區域之較大帶隙區域亦用以減少表面復合。 One of a heterojunction bipolar transistor (HBT) is used with a thin base layer thickness ("base 1" region) between the QW and the base surface (eg, a layer thickness of less than about 300 angstroms) The quantum well (QW) introduces a problem that carriers are tunneled from the quantum well to the surface state in which the carriers are non-radiatively recombined. The use of an asymmetric base region as a technique for reducing the thermalization of the extracted electrons toward the surface in the QW has been previously disclosed (see U.S. Patent Application Publication No. US 2010/0202484). This helps to reduce non-radiative recombination, and because electron reheating tends to be toward the collector, it also helps reduce lateral transport of electrons. The larger band gap region of the asymmetric base region is also used to reduce surface recombination.
根據本發明之一態樣之原理，當有必要將基極1區域厚度保持為大約300埃或300埃以下時，包括(舉例而言)厚度較佳地在約15 nm至50 nm之間的一低摻雜(1E-16 cm-3至5E-17 cm-3)或無意摻雜之n型層結構之一穿隧障壁結構可 用於增加自量子井至表面之空間距離，藉此在不必須實體上增加量子井與射極區域之間的p型基極區域之情況下減少量子井中之所擷取載子至表面狀態之穿隧。該穿隧障壁結構材料應較佳地具有大於量子井之基本狀態之一能隙，且應可藉由將不影響基極1區域之一蝕刻製程選擇性地移除。對於包括GaAs或一低百分比Al(<20%)之AlGaAs層之一基極1區域，穿隧障壁可(舉例而言)由相對較高百分比Al(>35%)之AlGaAs製成或係晶格匹配的或者係一應變InAlGaP合金層。 In accordance with the principles of one aspect of the present invention, when it is necessary to maintain the thickness of the base 1 region to be less than about 300 angstroms or less, including, for example, a thickness of preferably between about 15 nm and 50 nm. A low-doping (1E-16 cm -3 to 5E-17 cm -3 ) or unintentionally doped n-type layer structure tunneling barrier structure can be used to increase the spatial distance from the quantum well to the surface, thereby not The tunneling of the captured carrier to the surface state in the quantum well must be reduced with the physical addition of the p-type base region between the quantum well and the emitter region. The tunneling barrier structure material should preferably have an energy gap greater than one of the basic states of the quantum well and should be selectively removed by etching the etching process without affecting one of the regions of the base 1. For a base 1 region of one of the AlGaAs layers comprising GaAs or a low percentage of Al (<20%), the tunneling barrier can be made, for example, of a relatively high percentage of Al (>35%) AlGaAs or systemic The grid matches or is a strained InAlGaP alloy layer.
亦可與上文所闡述之架狀突出物(ledge)一起採用具有愈來愈高之能量障壁之一不對稱基極設計以增加穿隧障壁高度，以產生朝向集極之載子再熱化之優先條件且增加障壁高度，此亦減少穿隧。 An asymmetric base design with an increasingly higher energy barrier can also be used with the ledge described above to increase the tunneling barrier height to produce reheating of the carrier towards the collector. The priority condition increases the barrier height, which also reduces tunneling.
根據本發明之一形式，陳述一種用於以經改良效率產生光學信號之方法，該方法包含以下步驟：提供一層式半導體結構，該層式半導體結構包含一基板、一第一導電類型之一半導體集極區域、安置於該集極區域上的一第二導電類型之一半導體基極區域及安置為該基極區域之一表面之一部分上方之一台面的該第一半導體類型之一半導體射極區域；在該基極區域中提供展現量子大小效應之至少一個區域；提供分別與該集極區域、該基極區域及該射極區域耦合之集極電極、基極電極及射極電極；在該基極區域之該表面之至少經曝露部分上方提供一穿隧障壁層；及相對於該集極電極、該基極電極及該射極電極施加信號以自該 基極區域產生光學信號。在本發明之此形式之一實施例中，提供該等電極之步驟包含：將該基極電極之至少一部分提供為安置於該基極區域之該表面上且與該射極台面間隔開；及提供該穿隧障壁層之該步驟包括：在該基極區域之該表面上在該台面與該基極電極之間提供該穿隧障壁層。在此實施例中，提供展現量子大小效應之該至少一個區域之該步驟包括提供一不連續或不平坦量子大小區域；亦即，量子點及/或量子線(不連續)或一波狀量子井(不平坦)。亦在此實施例中，提供該基極區域之該步驟包括：提供包含在該量子大小區域之射極側上之一第一基極子區域及在該量子大小區域之集極側上之一第二基極子區域之一基極區域，且該第一基極子區域及該第二基極子區域具備相對於彼此不對稱之帶結構。 According to one form of the invention, a method for producing an optical signal with improved efficiency is described, the method comprising the steps of providing a layered semiconductor structure comprising a substrate, a semiconductor of a first conductivity type a collector region, a semiconductor base region of a second conductivity type disposed on the collector region, and a semiconductor emitter of the first semiconductor type disposed as a mesa above a portion of a surface of the base region a region; providing at least one region exhibiting a quantum size effect in the base region; providing a collector electrode, a base electrode, and an emitter electrode respectively coupled to the collector region, the base region, and the emitter region; Providing a tunneling barrier layer over at least the exposed portion of the surface of the base region; and applying a signal to the collector electrode, the base electrode, and the emitter electrode The base region produces an optical signal. In an embodiment of this form of the invention, the step of providing the electrodes includes: providing at least a portion of the base electrode to be disposed on the surface of the base region and spaced apart from the emitter mesa; The step of providing the tunneling barrier layer includes providing the tunneling barrier layer between the mesa and the base electrode on the surface of the base region. In this embodiment, the step of providing the at least one region exhibiting a quantum size effect comprises providing a discontinuous or uneven quantum size region; that is, quantum dots and/or quantum wires (discontinuous) or a corrugated quantum Well (not flat). Also in this embodiment, the step of providing the base region includes: providing a first base region included on an emitter side of the quantum size region and one of a collector side of the quantum size region A base region of one of the two base regions, and the first base region and the second base region have a band structure that is asymmetric with respect to each other.
根據本發明之又一形式，陳述一種用於產生一傾斜電荷發光裝置之方法，該方法包含以下步驟：形成一層式半導體結構，該層式半導體結構包含一基板、一第一導電類型之一半導體集極區域、一第二導電類型之一半導體子基極區域、一量子大小區域及該第二導電類型之又一半導體子基極區域；在該又一子基極區域上沈積一穿隧障壁層；在該障壁層之表面之一部分上形成該第一導電類型之一半導體射極台面；及提供分別與該集極區域、該基極區域及該射極區域耦合之集極電極、基極電極及射極電極。在本發明之此形式之一實施例中，在該又一子基極區域之一表面之一非周邊部分上方沈積該障壁層，且形成該基極電極之 該步驟包括在該又一子基極區域之一周邊部分上形成與該射極台面間隔開之該基極電極。亦在此實施例中，形成該基極子區域及該又一基極子區域之該步驟包括：形成如具有相對於彼此不對稱之帶結構之該基極子區域及該又一基極子區域。可藉由形成具有比該子基極區域之半導體材料高之帶隙之半導體材料之該又一基極子區域來實施此操作。在本發明之此形式之一實施例中，該又一基極子區域形成有小於約30 nm之一厚度。 According to still another form of the present invention, a method for producing an oblique charge light-emitting device is disclosed, the method comprising the steps of: forming a layered semiconductor structure comprising a substrate, a semiconductor of a first conductivity type a collector region, a semiconductor sub-base region of a second conductivity type, a quantum-sized region, and a further semiconductor sub-base region of the second conductivity type; depositing a tunnel barrier on the further sub-base region Forming a semiconductor emitter mesa of the first conductivity type on a portion of the surface of the barrier layer; and providing a collector electrode and a base coupled to the collector region, the base region, and the emitter region, respectively Electrode and emitter electrode. In an embodiment of this form of the invention, the barrier layer is deposited over one of the non-peripheral portions of one of the surfaces of the further sub-base region, and the base electrode is formed The step includes forming the base electrode spaced apart from the emitter mesa on a peripheral portion of the further sub-base region. Also in this embodiment, the step of forming the base sub-region and the further base sub-region includes forming the base sub-region and the further base sub-region as having a strip structure that is asymmetric with respect to each other. This operation can be performed by forming the further base region of the semiconductor material having a higher band gap than the semiconductor material of the sub-base region. In an embodiment of this form of the invention, the further base region is formed with a thickness of less than about 30 nm.
根據本發明之另一形式，陳述一種傾斜電荷發光半導體裝置，該傾斜電荷發光半導體裝置包括：一層式半導體結構，其包含一基板、一第一導電類型之一半導體集極區域、安置於該集極區域上的一第二導電類型之一半導體基極區域及安置為該基極區域之一表面之一部分上方之一台面的該第一半導體類型之一半導體射極區域；該基極區域，其包含展現量子大小效應之至少一個區域；集極電極、基極電極及射極電極，其分別與該集極區域、該基極區域及該射極區域耦合；及一穿隧障壁層，其安置於該基極區域之該表面之至少經曝露部分上方；藉此，相對於該集極電極、該基極電極及該射極電極施加之信號可自該基極區域產生光學信號。在本發明之此形式之一實施例中，該基極電極之至少一部分安置於該基極區域之該表面上且與該射極台面間隔開，且該穿隧障壁層安置於該基極區域之該表面上在該台面與該基極電極之間。在本發明之此形式之一實施例中，展現量子大小效應之該至少一個區域包 括一不連續或不平坦量子大小區域。 According to another form of the invention, an oblique charge light emitting semiconductor device is disclosed, the tilt charge light emitting semiconductor device comprising: a layered semiconductor structure comprising a substrate, a semiconductor collector region of a first conductivity type, disposed in the episode a semiconductor base region of a second conductivity type on the polar region and a semiconductor emitter region of the first semiconductor type disposed as a mesa above a portion of one of the surfaces of the base region; the base region Included in at least one region exhibiting a quantum size effect; a collector electrode, a base electrode, and an emitter electrode respectively coupled to the collector region, the base region, and the emitter region; and a tunnel barrier layer disposed At least over the exposed portion of the surface of the base region; whereby signals applied relative to the collector electrode, the base electrode, and the emitter electrode can generate an optical signal from the base region. In an embodiment of this form of the invention, at least a portion of the base electrode is disposed on the surface of the base region and spaced apart from the emitter mesa, and the tunneling barrier layer is disposed in the base region The surface is between the mesa and the base electrode. In an embodiment of this form of the invention, the at least one region packet exhibiting a quantum size effect Includes a discontinuous or uneven quantum size region.
根據本發明之又一形式，陳述一種用於以經改良效率產生光學信號之方法，該方法包含以下步驟：提供一層式半導體結構，該層式半導體結構包含一基板、一第一導電類型之一半導體汲極區域、安置於該汲極區域上的一第二導電類型之一半導體基極區域及安置為該基極區域之一表面之一部分上方之一台面的該第一半導體類型之一半導體射極區域；在該基極區域中提供展現量子大小效應之至少一個區域；提供與該基極區域及該汲極區域耦合之一基極/汲極電極，並提供與該射極區域耦合之一射極電極；在該基極區域之該表面之至少經曝露部分上方提供一穿隧障壁層；及相對於該基極/汲極電極及該射極電極施加信號以自該基極區域產生光學信號。在本發明之此形式之一實施例中，提供該等電極之該步驟包含：將該基極/汲極電極之至少一部分提供為安置於該基極區域之該表面上且與該射極台面間隔開，且其中提供該穿隧障壁層之該步驟包括：在該基極區域之該表面上在該台面與該基極/汲極電極之間提供該穿隧障壁層。 According to yet another form of the invention, a method for producing an optical signal with improved efficiency is described, the method comprising the steps of providing a layered semiconductor structure comprising a substrate, one of a first conductivity type a semiconductor drain region, a semiconductor base region of a second conductivity type disposed on the drain region, and a semiconductor shot of the first semiconductor type disposed as a mesa above a portion of a surface of the base region a polar region; providing at least one region exhibiting a quantum size effect in the base region; providing a base/drain electrode coupled to the base region and the drain region, and providing one of coupling with the emitter region An emitter electrode; providing a tunneling barrier layer over at least the exposed portion of the surface of the base region; and applying a signal relative to the base/drain electrode and the emitter electrode to produce optics from the base region signal. In an embodiment of this form of the invention, the step of providing the electrodes includes providing at least a portion of the base/drain electrodes to be disposed on the surface of the base region and opposite the emitter mesa The step of spacing and providing the tunneling barrier layer includes providing the tunneling barrier layer between the mesa and the base/drain electrode on the surface of the base region.
一實際光學傾斜電荷裝置之設計包含數個複雜考量因素，其包含高內部量子效率、可製造性、相容性及可靠性之達成。因此，自一光學傾斜電荷裝置之一現有設計轉變至另一設計提出挑戰。根據本發明之另一態樣，提供一種具有一深量子井(其中至少約0.25 eV之△E>>kT)同時維持實質上二元之一重摻雜基極區域之光學傾斜電荷裝置。具 有此等特徵之該光學傾斜電荷裝置仍然能夠併入有在一種類型之半導體材料處選擇性地停止蝕刻之蝕刻停止層，以輔助射極台面、基極台面及集極台面之界定，此有益於製造性。另外，出於可靠性原因，該基極區域仍可摻雜有碳(p型，NPN結構)或矽(n型，PNP)。維持相容性，此乃因光學傾斜電荷裝置之發射光子能量仍可耦合至現有基於InP/InGaAs之光偵測器。又一優勢係本發明之所揭示基於GaAs之光學傾斜電荷裝置與基於矽之基板及透鏡之使用相容。 The design of an actual optical tilt charge device involves several complex considerations that include high internal quantum efficiency, manufacturability, compatibility, and reliability. Therefore, shifting from an existing design of one optical tilt charge device to another design presents a challenge. In accordance with another aspect of the present invention, an optically tilted charge device having a deep quantum well (where ΔE>>kT of at least about 0.25 eV) while maintaining substantially one of the binary heavily doped base regions is provided. With The optically tilted charge device having such features can still incorporate an etch stop layer that selectively stops etching at one type of semiconductor material to aid in the definition of the emitter mesa, the base mesa, and the collector mesa. Manufacturing. In addition, for reliability reasons, the base region may still be doped with carbon (p-type, NPN structure) or germanium (n-type, PNP). Compatibility is maintained because the emitted photon energy of the optical tilt charge device can still be coupled to existing InP/InGaAs based photodetectors. Yet another advantage is that the GaAs-based optical tilt charge device disclosed herein is compatible with the use of germanium-based substrates and lenses.
根據本發明之再一形式，提供一種用於製作與GaAs晶格常數實質上匹配之一光學傾斜電荷裝置之方法，該方法包含以下步驟：提供一層式半導體結構，層式半導體結構包含：一GaAs基板；一半導體集極區域；一半導體基極區域，其包含一經摻雜GaAs第二基極子區域、一InGaAsN量子大小區域及一經摻雜GaAs第一基極子區域；及一半導體射極區域；及提供分別與該集極區域、該基極區域及該射極區域耦合之集極電極、基極電極及射極電極。相對於該集極電極、該基極電極及該射極電極施加之電信號自該基極區域產生光發射。在本發明之此形式之一實施例中，提供該集極區域及該射極區域之步驟包括：將該等區域提供為實質上GaAs，且提供該第二基極子區域及該第一基極子區域之步驟包括：將該第二基極子區域及該第一基極子區域提供為重摻雜p型(其中，如本文中所使用，重摻雜意謂針對p型為至少約1018 cm-3且針對n型為1017 cm-3)。亦在此 實施例中，提供該InGaAsN量子大小區域之步驟包括在GaAs障壁層之間提供一InGaAsN量子井。另一選擇係，提供該InGaAsN量子大小區域之該步驟可包括提供各自在GaAs障壁層之間的複數個InGaAsN量子井。亦在此實施例中，該方法包含藉助用於使用選擇性地移除基於砷化物之材料之一蝕刻劑來界定基極台面及射極台面之介入InAlGaP合金蝕刻停止層來生長該層式半導體結構。(用於此蝕刻停止應用之InAlGaP合金亦包含InGaP或InAlAs蝕刻停止層之使用)。在此實施例之一形式中，在一Si上GaAs基板上沈積該層式半導體結構，且自該基板形成一Si透鏡。 According to still another aspect of the present invention, there is provided a method for fabricating an optically tilted charge device substantially matching a lattice constant of GaAs, the method comprising the steps of: providing a layered semiconductor structure comprising: a GaAs a semiconductor collector region; a semiconductor base region comprising a doped GaAs second base region, an InGaAsN quantum-sized region, and a doped GaAs first base region; and a semiconductor emitter region; A collector electrode, a base electrode, and an emitter electrode respectively coupled to the collector region, the base region, and the emitter region are provided. An electrical signal applied to the collector electrode, the base electrode, and the emitter electrode produces light emission from the base region. In an embodiment of this form of the invention, the step of providing the collector region and the emitter region comprises: providing the regions as substantially GaAs, and providing the second base region and the first base The step of region includes providing the second base sub-region and the first base sub-region as heavily doped p-type (wherein, as used herein, heavy doping means at least about 10 18 cm -3 for p-type And for the n type is 10 17 cm -3 ). Also in this embodiment, the step of providing the InGaAsN quantum size region includes providing an InGaAsN quantum well between the GaAs barrier layers. Alternatively, the step of providing the InGaAsN quantum-sized region can include providing a plurality of InGaAsN quantum wells each between the GaAs barrier layers. Also in this embodiment, the method includes growing the layered semiconductor by means of an intervening InAlGaP alloy etch stop layer for defining a base mesa and an emitter mesa using an etchant that selectively removes one of the arsenide-based materials structure. (The InAlGaP alloy used for this etch stop application also includes the use of an InGaP or InAlAs etch stop layer). In one form of this embodiment, the layered semiconductor structure is deposited on a Si GaAs substrate and a Si lens is formed from the substrate.
在本發明之再一形式中，陳述一種用於製作與GaAs晶格常數實質上匹配之一個兩端子光學傾斜電荷裝置之方法，該方法包含以下步驟：提供一層式半導體結構，該層式半導體結構包含：一GaAs基板；一半導體汲極區域；一半導體基極區域，其包含一經摻雜GaAs第二基極子區域、一InGaAsN量子大小區域及一經摻雜GaAs第一基極子區域；及一半導體射極區域；及提供與該集極電極及該基極區域耦合之一基極/集極電極及與該射極區域耦合之一射極電極。相對於該基極/汲極電極及該射極電極施加之電信號自該基極區域產生光發射。 In yet another form of the invention, a method for fabricating a two-terminal optically tilted charge device that substantially matches a lattice constant of GaAs is described, the method comprising the steps of: providing a layered semiconductor structure, the layered semiconductor structure The invention comprises: a GaAs substrate; a semiconductor drain region; a semiconductor base region comprising a doped GaAs second base region, an InGaAsN quantum-sized region, and a doped GaAs first base region; and a semiconductor shot a polar region; and a base/collector electrode coupled to the collector electrode and the base region and an emitter electrode coupled to the emitter region. An electrical signal is applied from the base region to the electrical signal applied to the base/drain electrode and the emitter electrode.
在本發明之又一形式中，陳述一種與GaAs晶格常數實質上匹配之光學傾斜電荷裝置，該光學傾斜電荷裝置包括：一層式半導體結構，其包含：一GaAs基板；一半導體 集極區域；一半導體基極區域，其包含一重摻雜GaAs第二基極子區域、一InGaAsN量子大小區域及一重摻雜GaAs第一基極子區域；及一半導體射極區域；該集極區域及該射極區域，其係為與該等基極子區域之導電類型相反之導電類型；及集極電極、基極電極及射極電極，其分別與該集極區域、該基極區域及該射極區域耦合；藉此相對於該集極電極、該基極電極及該射極電極施加電信號將自該基極區域產生光發射。在本發明之此形式之一實施例中，該基極區域中之該InGaAsN量子大小區域包括具有至少約0.25 eV之一深度之一量子井。在此實施例中，該InGaAsN量子大小區域包括在GaAs障壁層之間的一InGaAsN量子井。較佳地，該InGaAsN量子大小區域包括InxGa1-xAsN，其中x係至少約0.3。亦在此實施例中，該GaAs基板安置於矽上，且該矽呈一透鏡之形式。 In yet another form of the invention, an optical tilt charge device substantially mate with a lattice constant of GaAs is illustrated, the optical tilt charge device comprising: a layered semiconductor structure comprising: a GaAs substrate; a semiconductor collector region; a semiconductor base region comprising a heavily doped GaAs second base region, an InGaAsN quantum-sized region and a heavily doped GaAs first base region; and a semiconductor emitter region; the collector region and the emitter region a conductivity type opposite to a conductivity type of the base regions; and a collector electrode, a base electrode, and an emitter electrode, respectively coupled to the collector region, the base region, and the emitter region; Thereby, an electrical signal is applied to the collector electrode, the base electrode and the emitter electrode to generate light emission from the base region. In an embodiment of this form of the invention, the InGaAsN quantum-sized region in the base region comprises a quantum well having a depth of at least about 0.25 eV. In this embodiment, the InGaAsN quantum-sized region includes an InGaAsN quantum well between the GaAs barrier layers. Preferably, the InGaAsN quantum-sized region comprises In x Ga 1-x AsN, wherein x is at least about 0.3. Also in this embodiment, the GaAs substrate is disposed on the crucible and the crucible is in the form of a lens.
當與隨附圖式一起閱讀時，依據以下詳細說明將更易於明瞭本發明之其他特徵及優勢。 Other features and advantages of the present invention will become more apparent from the description of the appended claims.
參考圖1，其展示根據本發明之一實施例且可用於實踐本發明之方法之一實施例的呈一發光電晶體之形式之一光學傾斜電荷裝置之一剖視圖。在圖1中，一子集極區域125安置於一未經摻雜基板110上。子集極125上之一台面包含安置於一集極區域130與形成於又一台面上之一射極區域160之間的一基極區域140。該基極區域包含在一上部基極區域(基極1)與一下部基極區域(基極2)之間的一或多個量 子井145。在此實施例中，一集極電極127接觸子集極區域125之一表面，一基極電極147接觸基極區域140之一表面，且一射極電極167接觸射極區域160之一表面。一穿隧障壁層150安置於基極區域140之頂部表面上方在該基極區域與射極區域160之間，從而覆蓋(尤其)該基極區域之表面之經曝露部分。 Referring to Figure 1, there is shown a cross-sectional view of one optically tilted charge device in the form of an illuminating transistor in accordance with an embodiment of the present invention and which can be used to practice one embodiment of the method of the present invention. In FIG. 1, a subset collector region 125 is disposed on an undoped substrate 110. A mesa on the subset collector 125 includes a base region 140 disposed between a collector region 130 and an emitter region 160 formed on the other mesa. The base region includes one or more quantities between an upper base region (base 1) and a lower base region (base 2) Sub-well 145. In this embodiment, a collector electrode 127 contacts one surface of the sub-collector region 125, a base electrode 147 contacts one surface of the base region 140, and an emitter electrode 167 contacts one surface of the emitter region 160. A tunneling barrier layer 150 is disposed over the top surface of the base region 140 between the base region and the emitter region 160 to cover, in particular, the exposed portion of the surface of the base region.
圖2之表展示圖1之實施例之一代表性磊晶層結構之一實例。除非另有指示，否則可使用現有MOCVD(金屬有機汽相沈積)及/或MBE(分子束磊晶)沈積技術製成磊晶層結構，且使用現有光微影技術來形成裝置。在此實例中，在GaAs障壁內存在兩個In0.2Ga0.8As量子井(層7及層9)。上部量子井(層9)在至基極140之表面(亦即，基極1-層12之表面)之穿隧距離(24微米)內。在此實例中，使用與射極160(層14)相同之材料之一穿隧障壁150(層13)；即In0.49Ga0.51As。一不對稱基極用於幫助朝向集極之再熱化且增加障壁高度。穿隧障壁結構增加量子井中之載子至表面狀態之間的距離(且減小穿隧機率)。在不具有穿隧障壁之情況下，如所指示，量子井與表面狀態之間的穿隧距離係24 nm。在具有穿隧障壁之情況下，此距離增加至78 nm(大約3倍)。亦可藉由增加磊晶結構之層11及層12(基極1)之厚度而減小穿隧機率。穿隧障壁之使用允許並不需要一厚基極1區域之設計(例如，出於基極渡越時間原因或材料原因)。在該表(及本發明之其他表)中，第三行包含(對於某些層)名稱「ELDL」，其代表用於此等層之工程長擴散 長度材料之選用使用。就此而言，可參考闡述此類材料之使用之美國專利申請公開案US 2012/006815。然而，應理解，本發明並不需要使用此選用材料。本發明之表之第三行亦列舉與材料系統及量子大小區域相關聯之一特性發射波長。 The table of Figure 2 shows an example of a representative epitaxial layer structure of one of the embodiments of Figure 1. Unless otherwise indicated, epitaxial layer structures can be fabricated using existing MOCVD (Metal Organic Vapor Deposition) and/or MBE (Molecular Beam Epitaxy) deposition techniques, and existing photolithography techniques are used to form devices. In this example, there are two In 0.2 Ga 0.8 As quantum wells (layer 7 and layer 9) in the GaAs barrier. The upper quantum well (layer 9) is within a tunneling distance (24 microns) to the surface of the base 140 (i.e., the surface of the base 1 - layer 12). In this example, one of the same materials as the emitter 160 (layer 14) is used to tunnel the barrier 150 (layer 13); that is, In 0.49 Ga 0.51 As. An asymmetric base is used to help reheat the collector towards the collector and increase the barrier height. The tunneling barrier structure increases the distance between the carrier to the surface state in the quantum well (and reduces the tunneling probability). Without the tunnel barrier, as indicated, the tunneling distance between the quantum well and the surface state is 24 nm. In the case of a tunnel barrier, this distance is increased to 78 nm (approximately 3 times). The tunneling rate can also be reduced by increasing the thickness of layer 11 and layer 12 (base 1) of the epitaxial structure. The use of a tunnel barrier allows for the design of a thick base 1 region (for example, for base transit time reasons or material reasons). In this table (and other tables of the invention), the third row contains (for some layers) the name "ELDL" which represents the optional use of the engineered long diffusion length material for such layers. In this regard, reference is made to US Patent Application Publication No. US 2012/006815, which is incorporated herein by reference. However, it should be understood that the present invention does not require the use of such optional materials. The third row of the table of the invention also lists one characteristic emission wavelength associated with the material system and the quantum size region.
在圖1中，光子(波形)箭頭指示可自頂部或自底部側提取可用光。在此實施例中，將基極觸點(Ti-Pt-Au)製成為層12，將射極觸點(Au-Ge)製成為層15，且將集極觸點(Au-Ge)製成為層1。在基極-射極接面處於正向偏壓(例如，VBE>1.2伏)中且基極-集極接面處於高阻抗模式(未必係反向電壓-例如，-2.5伏<VBC<0.5伏)中之情況下操作該裝置。由實線箭頭繪示載子移動。 In Figure 1, photon (waveform) arrows indicate that available light can be extracted from the top or from the bottom side. In this embodiment, the base contact (Ti-Pt-Au) is made as layer 12, the emitter contact (Au-Ge) is made as layer 15, and the collector contact (Au-Ge) is made. Become layer 1. The base-emitter junction is in a forward bias (eg, V BE >1.2 volts) and the base-collector junction is in a high impedance mode (not necessarily a reverse voltage - for example, -2.5 volts < V BC The device was operated with <0.5 volts. The carrier movement is indicated by a solid arrow.
在本實施例中，由於穿隧障壁之材料相同於或類似於射極，因此在存在射極之情況下總有效穿隧障壁厚度更大。若需要，則用於射極及穿隧障壁(舉例而言，AlGaAs射極及InAlGaP穿隧障壁)之非類似材料之使用可允許在處理期間分離該等層。 In this embodiment, since the material of the tunneling barrier is the same or similar to the emitter, the total effective tunneling barrier thickness is greater in the presence of the emitter. If desired, the use of non-similar materials for the emitter and tunnel barriers (for example, AlGaAs emitters and InAlGaP tunnel barriers) may allow separation of the layers during processing.
在本實施例中，使用一薄21 nm經摻雜AlGaAs分級層式(層11及層12，其中Al含量為0.5%至5%)來增加障壁高度及幫助朝向集極之再熱化。添加一3 nm未經摻雜GaAs緩衝層(層10)以減少摻雜劑至量子井中之污染。傾斜電荷裝置磊晶層經設計以與HBT鑄造製程相容。圖3之表中展示經處理裝置DC特性。將所製作裝置研磨至150微米，且對其進行量測。 In this embodiment, a thin 21 nm doped AlGaAs graded layer (layer 11 and layer 12 with an Al content of 0.5% to 5%) is used to increase the barrier height and aid in reheating towards the collector. A 3 nm undoped GaAs buffer layer (layer 10) was added to reduce contamination of the dopant into the quantum well. The tilted charge device epitaxial layer is designed to be compatible with the HBT casting process. The processed device DC characteristics are shown in the table of Figure 3. The fabricated device was ground to 150 microns and was measured.
對使基極觸點與射極台面之間的距離(圖1中之距離d)變化之效應執行一研究。射極台面邊緣與基極金屬邊緣之間的距離自1.5微米變化至7微米同時將所有其他尺寸保持相同。增加距離d等效地增加基極電阻(電洞電阻)且因此促進(比較而言)量子井中之電子朝向基極觸點之橫向輸送。經由底部基板使用一大面積偵測器量測光且標繪光對基極電流(復合電流)。所量測資料展示，當距離在自約1.5微米至7微米之間變化時輻射復合效率並不改變。此在圖4中可見，其中針對介於1.5微米至7微米之範圍內之距離d之四條所標繪曲線實質上重疊且看似為一單個曲線。此指示涉及使用所闡述穿隧障壁之本發明技術成功隔離量子井中之所擷取電子與非輻射表面復合。表面處對非輻射復合之限制亦輔助減少在表面處形成可導致基極-射極洩漏及可靠性問題之熱點(其在諸如一發光電晶體之一低電流增益電晶體中係一經放大問題)。 A study was conducted on the effect of changing the distance between the base contact and the emitter mesa (distance d in Fig. 1). The distance between the edge of the emitter mesa and the edge of the base metal varies from 1.5 microns to 7 microns while keeping all other dimensions the same. Increasing the distance d equivalently increases the base resistance (hole resistance) and thus promotes (in comparison) the lateral transport of electrons in the quantum well towards the base contact. A large area detector is used to measure light through the bottom substrate and plot the light to base current (composite current). The measured data shows that the radiation recombination efficiency does not change when the distance varies from about 1.5 microns to 7 microns. This can be seen in Figure 4, where the plotted curves for the four distances d in the range of 1.5 microns to 7 microns substantially overlap and appear to be a single curve. This indication relates to the successful isolation of the extracted electrons from the non-radiative surface in the quantum well using the inventive technique of the illustrated tunneling barrier. The limitation of non-radiative recombination at the surface also assists in reducing the formation of hot spots at the surface that can cause base-emitter leakage and reliability issues (which are amplified in a low current gain transistor such as a light-emitting transistor) .
然而，其他研究指示QW中之電荷保存由於先前所闡述之技術而導致與電子動態相關之電容CD(亦即，基極所儲存電容、擴散電容)之一增加。此自圖5(其標繪電容CD對距離d)之圖表可見。AC分析指示當距離d自1.5微米變化至7微米時，與電子動態相關聯之電容(亦即，電荷儲存電容、擴散電容)增加。當僅橫向尺寸(d)經更改時，此指示電容面積已由於電子經由量子井之橫向行進而增加，因此填充量子井之一較大區。 However, other studies have indicated that the charge retention in the QW increases one of the capacitances CD (i.e., the stored capacitance of the base, the diffusion capacitance) that is dynamically related to the electrons due to the techniques previously described. This is visible from the graph of Figure 5, which plots the capacitance C D versus distance d. The AC analysis indicates that as the distance d changes from 1.5 microns to 7 microns, the capacitance associated with the electronic dynamics (i.e., charge storage capacitance, diffusion capacitance) increases. When only the lateral dimension (d) is altered, this indicates that the capacitance area has increased due to the lateral travel of electrons through the quantum well, thus filling a larger area of one of the quantum wells.
在其中期望減小CD之應用中，本發明之一實施例利用一 不連續量子結構(DQS)作為裝置之基極區域中之量子大小區域。諸如量子點或量子線之DQS沿著橫向軸提供能隙不連續點。實體不連續點及相關聯能隙不連續點(能量障壁)將所擷取載子之移動侷限於或阻止至不連續量子結構之邊界內。雖然圖解說明類似於圖1之裝置之一裝置之圖6中對此進行展示(其中相似元件符號表示類似元件)，但其中裝置基極區域(標示140')在該基極區域中具有呈量子點645之形式之一不連續量子結構。可在磊晶層之生長期間(參見圖7之表)或藉由圖案化量子結構後續接著一再生長方法併入該DQS結構。 In applications where it is desirable to reduce the sum of C D, for example, using a discrete quantum structure (the DQS) as the size of the quantum region the base region of the apparatus of one embodiment of the present invention. DQS such as quantum dots or quantum wires provide energy gap discontinuities along the lateral axis. Physical discontinuities and associated energy gap discontinuities (energy barriers) limit or prevent the movement of the captured carriers from being within the boundaries of the discontinuous quantum structure. Although illustrated in Figure 6 which is similar to one of the devices of Figure 1, wherein like reference numerals indicate like elements, the device base region (indicator 140') has quantum in the base region. One of the forms of point 645 is a discontinuous quantum structure. The DQS structure can be incorporated during growth of the epitaxial layer (see the table of Figure 7) or by patterning the quantum structure followed by a regrowth method.
如圖7之表中所表示，使用薄n型InGaAs層(小於100 nm)以便使得能夠使用與諸如AuGe之合金觸點相比光學較平滑之非合金觸點。所得較平滑接觸層將藉由向下反射光子而改良自基板之底部之光提取。對於其中僅期望底部發射之圖6實施例之設計，可減小或消除(例如，藉由自對準方法)所曝露射極台面寬度(W)以使得由反射非合金觸點覆蓋整個射極台面寬度以便增加底部光提取。InGaAs層之厚度較佳地薄得足以減少光子自吸收，但厚得足以使得能夠使用非金屬觸點。 As shown in the table of Figure 7, a thin n-type InGaAs layer (less than 100 nm) is used in order to enable the use of non-alloyed contacts that are optically smoother than alloyed contacts such as AuGe. The resulting smoother contact layer will improve light extraction from the bottom of the substrate by reflecting the photons downward. For the design of the embodiment of Figure 6 in which only the bottom emission is desired, the exposed emitter mesa width (W) can be reduced or eliminated (e.g., by a self-aligned method) such that the entire emitter is covered by the reflective non-alloy contacts. Countertop width to increase bottom light extraction. The thickness of the InGaAs layer is preferably thin enough to reduce photon self-absorption, but thick enough to enable the use of non-metallic contacts.
如圖7之表中所見，將一不對稱DQS併入至該設計中以幫助朝向集極之再熱化。如上文所指示，亦可使用諸如量子線等其他DQS替代量子點。使用相對薄之摻雜碲之InGaAs子射極層以使得Ti-Pt-Au觸點能夠用於射極。與Au-Ge合金觸點相比，Ti-Pt-Au提供較佳反射率，且將由 於使用低帶隙InGaAs子射極層而抵消光子吸收損失。 As seen in the table of Figure 7, an asymmetric DQS is incorporated into the design to aid in reheating towards the collector. As indicated above, other DQS such as quantum wires can also be used in place of quantum dots. A relatively thin doped yttrium InGaAs sub-emitter layer is used to enable the Ti-Pt-Au contact to be used for the emitter. Compared to Au-Ge alloy contacts, Ti-Pt-Au provides better reflectivity and will be The photon absorption loss is offset by the use of a low bandgap InGaAs sub-emitter layer.
在圖6實施例中，如所指示，使用不連續量子結構來防止電子朝向基極觸點之橫向輸送。此圖中之邊緣復合程序經擴大以指示傾斜電荷裝置係一邊緣復合裝置。將顯而易見，可能藉由縮減射極台面尺寸而最終在射極台面下方獲得一「均勻」復合分佈。光子箭頭指示可自頂部或自底部側提取可用光。將基極觸點(Ti-Pt-Au)製成為層13，將射極觸點(Ti-Pt-Au)製成為層18，且將集極觸點(Au-Ge)製成為層1(參考圖7之表)。如所述，使用相對薄之摻雜碲之InGaAs子射極層(層17及層18)以使得Ti-Pt-Au觸點能夠用於射極。Ti-Pt-Au觸點對Au-Ge合金觸點之較佳反射率將由於使用低帶隙InGaAs子射極層而抵消光子吸收損失。如圖1實施例中，在基極-射極接面處於正向偏壓中且基極-集極接面處於高阻抗模式(未必係反向偏壓)中之情況下操作該裝置。亦可將一部分DBR或全DBR腔併入至此結構中。亦可藉由提供一適合諧振光學腔而將此實施例及本發明之其他實施例操作為一雷射。 In the embodiment of Figure 6, as indicated, a discontinuous quantum structure is used to prevent lateral transport of electrons toward the base contacts. The edge recombination procedure in this figure is expanded to indicate that the tilted charge device is an edge composite device. It will be apparent that it is possible to ultimately obtain a "uniform" composite distribution below the emitter mesa by reducing the size of the emitter mesa. The photon arrow indicates that available light can be extracted from the top or from the bottom side. The base contact (Ti-Pt-Au) is made as layer 13, the emitter contact (Ti-Pt-Au) is made as layer 18, and the collector contact (Au-Ge) is made as layer 1 ( Refer to the table of Figure 7). As described, a relatively thin doped yttrium InGaAs sub-emitter layer (layer 17 and layer 18) is used to enable the Ti-Pt-Au contact to be used for the emitter. The better reflectivity of the Ti-Pt-Au contact to the Au-Ge alloy contact will offset the photon absorption loss due to the use of a low bandgap InGaAs sub-emitter layer. In the embodiment of Figure 1, the device is operated with the base-emitter junction in forward bias and the base-collector junction in a high impedance mode (not necessarily reverse biased). A portion of the DBR or full DBR cavity can also be incorporated into this structure. This embodiment and other embodiments of the present invention can also be operated as a laser by providing a suitable resonant optical cavity.
在本發明之又一實施例中，藉由使用單個或多個高度應變波狀(不平坦)量子井(C-QW)(舉例而言，一InGaP/GaAs LET中之InGaAs QW，其中銦組合物為約20%以上)而減少少數載子之橫向傳導，其中量子井寬度定義為侷限量子井之基本復合狀態之兩個障壁之間的距離。可使用諸如SIMS(二次離子質譜法)分析、AFM(原子力顯微術)、FIB(聚焦電子束)或高解析度TEM(透射式電子顯微鏡)等方法 來驗證量子井之銦組合物及波紋。高度應變表面導致不平坦(波狀)QW表面之生長。(可參考(舉例而言)T.Chung、G.Walter及N.Holonyak Jr.之「Coupled Strained Layer InGaAs Quantum Well Improvement of an InAs Quantum Dot AlGaAs-GaAs-InGaAs-InAs Heterostructure Laser」，應用物理第79期，4500-4502(2001)；G.Walter、T.Chung及N.Holonyak Jr.之「High Gain Coupled InGaAs Quantum Well InAs Quantum Dot AlGaAs-GaAs-InGaAs-InAs Heterostructure Diode Laser Operation」，應用物理第80期，1126-1128(2002)；G.Walter、T.Chung及N.Holonyak Jr.之「Coupled-Stripe Quantum-Well-Assisted AlGaAs-GaAs-InGaAs-InAs Quantum-Dot Laser」，應用物理第80期，3045(2002))。可藉助使用離軸基板或預圖案化基板(舉例而言，選擇性晶體平面)或藉由光微影/蝕刻製程來增強波狀QW之生長。一波狀或不平坦表面提供使載子遷移率扭曲之光學及電波函數擾動。 In yet another embodiment of the invention, a single or a plurality of highly strained wavy (uneven) quantum wells (C-QW) are used (for example, an InGaAs QW in an InGaP/GaAs LET, wherein the indium combination The material is about 20% or more and reduces the lateral conduction of a minority carrier, wherein the quantum well width is defined as the distance between the two barriers that limit the basic composite state of the quantum well. A method such as SIMS (Secondary Ion Mass Spectrometry) analysis, AFM (Atomic Force Microscopy), FIB (Focused Electron Beam), or High Resolution TEM (Transmission Electron Microscope) can be used. To verify the indium composition and ripple of the quantum well. A highly strained surface results in the growth of an uneven (wavy) QW surface. (For example, T. Chung, G. Walter, and N. Holonyak Jr. "Coupled Strained Layer InGaAs Quantum Well Improvement of an In As Quantum Dot AlGaAs-GaAs-InGaAs-InAs Heterostructure Laser", Applied Physics, 79th Period, 4500-502 (2001); G. Walter, T. Chung, and N. Holonyak Jr. "High Gain Coupled InGaAs Quantum Well InAs Quantum Dot AlGaAs-GaAs-InGaAs-InAs Heterostructure Diode Laser Operation", Applied Physics 80 Period, 1126-1128 (2002); G. Walter, T. Chung and N. Holonyak Jr. "Coupled-Stripe Quantum-Well-Assisted AlGaAs-GaAs-InGaAs-InAs Quantum-Dot Laser", Applied Physics No. 80 , 3045 (2002)). The growth of the wavy QW can be enhanced by using an off-axis substrate or a pre-patterned substrate (for example, a selective crystal plane) or by a photolithography/etching process. A wavy or uneven surface provides optical and electrical wave function perturbations that distort the carrier mobility.
圖8之表中所陳述之磊晶層結構用於其中一波狀量子井(C-QW)嵌入有設計為大約1020 nm之一主發射峰之一傾斜電荷裝置之一實施例。可與高OH(UV/VIS)光纖一起使用一1020 nm發射峰發光體。(可替代地採用用於其他發射波長之設計)。在此實施例中使用一不對稱C-QW以幫助朝向集極之再熱化且增加穿隧距離。若需要，則可在不必須減少銦組合物之情況下增加層6、層10及/或層11中之鋁組合物以將發射波長自1020 nm減小至(比如)1000 nm。 The epitaxial layer structure set forth in the table of Figure 8 is used in an embodiment in which a corrugated quantum well (C-QW) is embedded with one of the main charge peaks designed to be one of the main emission peaks of about 1020 nm. A 1020 nm emission peak illuminator can be used with high OH (UV/VIS) fibers. (Alternatively, designs for other emission wavelengths are used). An asymmetric C-QW is used in this embodiment to aid reheating towards the collector and increase the tunneling distance. If desired, the aluminum composition in layer 6, layer 10 and/or layer 11 can be increased to reduce the emission wavelength from 1020 nm to, for example, 1000 nm without necessarily reducing the indium composition.
在又一實施例(圖9之表中展示該實施例之磊晶層結構)中，結合一DQS使用一窄量子井(平坦QW或C-QW)以提供經改良載子擷取能力且輔助DQS之材料生長。如圖9中所陳述，傾斜電荷裝置包含一薄平坦量子井(QW)，該薄平坦量子井經由一穿隧障壁耦合至具有經設計為大約(但未必)1020 nm之一主發射峰之一5單層(ML)DQS。該量子井可經設計以具有1020 nm(大約相同能量)或980 nm(大約較高能量)之一峰發射波長。可與高OH光纖一起使用一1020 nm發射峰發光體。在此設計中使用一不對稱DQS以幫助朝向集極之再熱化且增加穿隧距離。 In yet another embodiment (the epitaxial layer structure of this embodiment is shown in the table of Figure 9), a narrow quantum well (flat QW or C-QW) is used in conjunction with a DQS to provide improved carrier extraction capability and assistance. DQS material growth. As illustrated in Figure 9, the tilted charge device comprises a thin flat quantum well (QW) coupled via a tunneling barrier to one of the main emission peaks designed to be approximately (but not necessarily) 1020 nm. Single layer (ML) DQS. The quantum well can be designed to have a peak emission wavelength of 1020 nm (about the same energy) or 980 nm (about a higher energy). A 1020 nm emission peak illuminator can be used with high OH fibers. An asymmetric DQS is used in this design to aid reheating towards the collector and increase the tunneling distance.
在又一實施例中，在第US 2010/0202483號美國專利申請公開案或第US 2012/0068151號美國專利申請公開案中所揭示之一般類型之一個兩端子傾斜電荷發光二極體中採用本發明之特徵。在此裝置中，使圖1實施例或圖6實施例之結構變化，其中基極區域下方之區域指定為一汲極區域，且一周邊基極/汲極電極與基極區域及汲極區域耦合。如在先前說明中提供包含較佳地不連續或波狀之至少一個量子大小區域之基極區域，且射極台面及射極觸點亦可與先前說明實質上對應。如之前所述，有利地在基極區域之經曝露部分上方提供一穿隧障壁層。 In a further embodiment, a two-terminal oblique charge light-emitting diode of the general type disclosed in the US Patent Application Publication No. US 2010/0202483 or the US Patent Application Publication No. US 2012/0068151 Features of the invention. In this device, the structure of the embodiment of FIG. 1 or the embodiment of FIG. 6 is changed, wherein the area under the base region is designated as a drain region, and a peripheral base/drain electrode and base region and drain region are coupling. The base region comprising at least one quantum sized region, preferably discontinuous or wavy, is provided as previously described, and the emitter mesa and emitter contacts may also substantially correspond to the previous description. As previously described, a tunneling barrier layer is advantageously provided over the exposed portion of the base region.
圖10展示根據本發明之另一實施例且可用於實踐本發明之方法之另一實施例之一裝置。圖10中所展示之半導體分層自底部向上包含：一GaAs基板1110；一GaAs緩衝區域1120；一子集極區域1130；一集極區域1140；一基極區域 1160，其包含稱為「基極-2」之一基極子區域1162、一量子大小區域1150(一或多個量子井或諸如量子點或量子線之其他適合量子大小區域)、稱為「基極-1」之一基極子區域1167；一射極區域1170；及一子射極區域1180。根據本發明之一特徵，在該基極區域中採用一InGaAsN量子大小區域。該集極電極、該基極電極及該射極電極分別展示為金屬集極觸點1135(其接觸該子集極區域)、金屬基極觸點1165(其接觸該基極-1區域)及金屬射極觸點1185(其接觸該子射極區域)。可將一準直器或聚焦透鏡1105模製至或貼附至GaAs基板1110。準直器或透鏡1105可有利地由矽形成。當該裝置生長於一Si上GaAs基板上時，可藉由蝕刻該矽形成該透鏡。儘管展示一底部發光體，但該裝置亦可經組態為一頂部發射體。 Figure 10 shows an apparatus of another embodiment of a method that can be used to practice the invention in accordance with another embodiment of the present invention. The semiconductor layer shown in FIG. 10 includes: a GaAs substrate 1110; a GaAs buffer region 1120; a subset collector region 1130; a collector region 1140; and a base region. 1160, comprising a base region 1162, referred to as "base-2", a quantum-sized region 1150 (one or more quantum wells or other suitable quantum-sized regions such as quantum dots or quantum wires), referred to as "base a base region 1167 of the pole-1"; an emitter region 1170; and a sub-emitter region 1180. According to a feature of the invention, an InGaAsN quantum-sized region is employed in the base region. The collector electrode, the base electrode and the emitter electrode are respectively shown as a metal collector contact 1135 (which contacts the subset region), a metal base contact 1165 (which contacts the base-1 region), and Metal emitter contact 1185 (which contacts the sub-emitter region). A collimator or focusing lens 1105 can be molded or attached to the GaAs substrate 1110. The collimator or lens 1105 can advantageously be formed from a crucible. When the device is grown on a Si GaAs substrate, the lens can be formed by etching the germanium. Although a bottom illuminator is shown, the device can also be configured as a top emitter.
圖11之表展示圖10實施例之一實例之較詳細半導體磊晶層。可使用現有MOCVD(金屬有機汽相沈積)及/或MBE(分子束磊晶)沈積技術製成磊晶層結構，且使用現有光微影技術形成裝置。基極-2區域包含一p型GaAs層(層6)，後續接著一較低摻雜p型GaAs材料(層7)以完成基極-2區域。在更靠近於量子井處減少摻雜劑以減少摻雜劑至量子井區域中之擴散。用於p型基極區域之摻雜劑較佳地係碳，與大多數其他p型摻雜劑(諸如，鋅)相比，碳具有一相對陡突擴散尾部。然後，包含一無意摻雜GaAs層(層8)之一量子井結構經生長以形成第一障壁層，後續接著與GaAs實質上晶格匹配之一薄(大約120埃)較低帶隙InGaAsN層(層9)，且 然後完成有如第二障壁層之另一薄GaAs層(層10)。可藉由使用重複InGaAsN層及GaAs障壁層替代地實施一多量子井結構，如圖12之表中所展示。然後藉助包含較低摻雜p型GaAs層(層11)及一較高摻雜GaAs接觸層(層12)之基極-1結構之生長完成該裝置之作用基極區域。在表中將層14展示為具有(諸如)針對使用橫向氧化之指標步階或侷限之一鋁含量機率。 Figure 11 is a table showing a more detailed semiconductor epitaxial layer of an example of the embodiment of Figure 10. The epitaxial layer structure can be formed using existing MOCVD (Metal Organic Vapor Deposition) and/or MBE (Molecular Beam Epitaxy) deposition techniques, and devices are formed using existing photolithography techniques. The base-2 region contains a p-type GaAs layer (layer 6) followed by a lower doped p-type GaAs material (layer 7) to complete the base-2 region. The dopant is reduced closer to the quantum well to reduce diffusion of dopants into the quantum well region. The dopant for the p-type base region is preferably carbon, and the carbon has a relatively steep diffusion tail compared to most other p-type dopants, such as zinc. Then, a quantum well structure comprising an unintentionally doped GaAs layer (layer 8) is grown to form a first barrier layer, followed by a substantially lattice-matched thin (about 120 angstroms) lower band gap InGaAsN layer with GaAs. (layer 9), and Another thin GaAs layer (layer 10) like the second barrier layer is then completed. A multiple quantum well structure can be implemented instead by using a repeating InGaAsN layer and a GaAs barrier layer, as shown in the table of FIG. The active base region of the device is then completed by growth of a base-1 structure comprising a lower doped p-type GaAs layer (layer 11) and a higher doped GaAs contact layer (layer 12). Layer 14 is shown in the table as having an aluminum content probability, such as one of the index steps or limitations for using lateral oxidation.
有利地用於本發明之量子井之InGaAsN半導體材料係一種四元材料，該四元材料使用較小氮原子以補償由較大銦原子誘發之應變，從而允許該材料保持與GaAs晶格常數實質上匹配。此允許較高之銦併入以降低InGaAsN層之能隙從而產生一較深量子井，而不必增加障壁層之能隙，此將需要依靠三元組合物。 An InGaAsN semiconductor material advantageously used in the quantum well of the present invention is a quaternary material that uses a smaller nitrogen atom to compensate for the strain induced by the larger indium atoms, thereby allowing the material to remain substantially constant with the lattice constant of GaAs. Match on. This allows for higher indium incorporation to reduce the energy gap of the InGaAsN layer to create a deeper quantum well without having to increase the energy gap of the barrier layer, which would require relying on a ternary composition.
使用InGaAsN材料用於量子井亦允許具有長於1100 nm之發射峰(該發射峰具有穿過矽之相對高透射)之裝置之設計。此允許光學傾斜電荷裝置有利地耦合至高指標矽透鏡(如圖10中)。由於整個OTCD結構與GaAs晶格常數實質上晶格匹配，且發射波長可經修整以使得能夠使用矽透鏡，因此所揭示裝置可直接生長於Si上GaAs基板上，且自Si蝕刻透鏡。此外，對於GaAs基板，一替代方案係在GaAs中蝕刻一透鏡。 The use of InGaAsN materials for quantum wells also allows for designs with devices having an emission peak longer than 1100 nm, which has a relatively high transmission through the crucible. This allows the optical tilt charge device to be advantageously coupled to a high index 矽 lens (as in Figure 10). Since the entire OTCD structure is substantially lattice matched to the GaAs lattice constant and the emission wavelength can be tailored to enable the use of a germanium lens, the disclosed device can be grown directly on the Si GaAs substrate and the lens is etched from Si. Furthermore, for GaAs substrates, an alternative is to etch a lens in GaAs.
在本實施例中，低摻雜且與GaAs晶格常數實質上匹配之InAlGaP合金(例如，In0.49Ga0.51P)蝕刻停止層放置於層1、層4及層13中，該等層亦界定基極接觸層(層13)、集極 接觸層(層3)之邊界及經摻雜緩衝區與未經摻雜緩衝區之間的邊界(層1)。可使用層1以藉由允許移除所有導電材料且因此自另一毗鄰裝置電解耦一個裝置而輔助GaAs基板移除或裝置隔離。此等基於磷化物之材料(例如，InGaP或InAlGaP)相對於用於移除基於砷化物之材料(諸如，GaAs及InGaAs)之蝕刻劑係穩定的。同樣地，可使用對基於砷化物之材料穩定之蝕刻劑來移除基於磷化物之材料。因此，可在不影響砷化物材料之情況下移除基於磷化物之材料，且反之亦然。亦可將一部分DBR或全DBR腔併入至此結構中。亦可藉由提供一適合諧振光學腔而將此實施例及本發明之其他實施例操作為一雷射。 In this embodiment, an InAlGaP alloy (eg, In 0.49 Ga 0.51 P) etch stop layer that is lowly doped and substantially matched to the GaAs lattice constant is placed in layer 1, layer 4, and layer 13, which are also defined The boundary between the base contact layer (layer 13), the collector contact layer (layer 3), and the boundary between the doped buffer and the undoped buffer (layer 1). Layer 1 can be used to aid in GaAs substrate removal or device isolation by allowing removal of all conductive material and thus electrolytic coupling of one device from another adjacent device. Such phosphide-based materials (eg, InGaP or InAlGaP) are stable relative to etchant systems used to remove arsenide-based materials such as GaAs and InGaAs. Likewise, an etchant that is stable to arsenide-based materials can be used to remove the phosphide-based material. Thus, the phosphide-based material can be removed without affecting the arsenide material, and vice versa. A portion of the DBR or full DBR cavity can also be incorporated into this structure. This embodiment and other embodiments of the present invention can also be operated as a laser by providing a suitable resonant optical cavity.
在又一實施例中，在第US 2010/0202483號美國專利申請公開案或第US 2012/0068151號美國專利申請公開案中所揭示之一般類型之一個兩端子傾斜電荷發光二極體中採用本發明之特徵。在此裝置中，使圖10實施例之結構變化，其中基極區域下方之區域指定為一汲極區域，且一周邊基極/汲極電極與該基極區域及該汲極區域耦合。圖13中展示一實例，其中透鏡1105、基板1110、緩衝區域1120、基極-2區域1162、量子大小區域1150、基極-1區域1167、射極區域1170、子射極區域1180及射極觸點1185類似於圖10中之相似元件符號之元件。然而，替代子集極區域及集極區域，圖13裝置具有子汲極區域1430及汲極區域1440。此外，替代基極電極及汲極電極，此實施例之裝置具有一基極/汲極電極1465。如上文所引用之專利申請公 開案中所闡述，將電信號施加至該基極/汲極電極及該射極電極自該基極區域產生光發射。此實施例之傾斜電荷發光二極體具有與圖10實施例之三端子光學傾斜電荷裝置相同之製作優點及操作優點。 In a further embodiment, a two-terminal oblique charge light-emitting diode of the general type disclosed in the US Patent Application Publication No. US 2010/0202483 or the US Patent Application Publication No. US 2012/0068151 Features of the invention. In this arrangement, the configuration of the embodiment of Fig. 10 is varied wherein the region below the base region is designated as a drain region and a peripheral base/drain electrode is coupled to the base region and the drain region. An example is shown in FIG. 13 in which lens 1105, substrate 1110, buffer region 1120, base-2 region 1162, quantum size region 1150, base-1 region 1167, emitter region 1170, sub-emitter region 1180, and emitter Contact 1185 is similar to the elements of similar component symbols in FIG. However, instead of the subset collector region and the collector region, the device of FIG. 13 has a daughterd drain region 1430 and a drain region 1440. Furthermore, instead of the base electrode and the drain electrode, the device of this embodiment has a base/drain electrode 1465. Patent application cited above As explained in the opening, an electrical signal is applied to the base/drain electrode and the emitter electrode produces light emission from the base region. The oblique charge light-emitting diode of this embodiment has the same manufacturing advantages and operational advantages as the three-terminal optical tilt charge device of the embodiment of Fig. 10.
雖然已參考特定較佳實施例闡述本發明，但熟習此項技術者將想到在本發明之精神及範疇內之變化形式。舉例而言，雖然已闡述npn發光電晶體，但應理解，本發明之特定原理將同樣適用於pnp發光電晶體。 Although the present invention has been described with reference to the preferred embodiments thereof, it will be apparent to those skilled in the art that For example, while npn luminescent transistors have been described, it should be understood that the particular principles of the invention are equally applicable to pnp luminescent transistors.
110‧‧‧未經摻雜基板 110‧‧‧Undoped substrate
125‧‧‧子集極區域/子集極 125‧‧‧Subset polar regions/subsets
127‧‧‧集極電極 127‧‧‧ Collector electrode
130‧‧‧集極區域 130‧‧‧ Collecting area
140‧‧‧基極區域/基極 140‧‧‧base area/base
145‧‧‧量子井 145‧‧‧Quantum Well
147‧‧‧基極電極 147‧‧‧ base electrode
150‧‧‧穿隧障壁層/穿隧障壁 150‧‧‧Through barrier layer/shield barrier
160‧‧‧射極區域/射極 160‧‧ ‧ emitter area / emitter
167‧‧‧射極電極 167‧‧ ‧ emitter electrode
1105‧‧‧準直器/透鏡 1105‧‧ collimator / lens
1110‧‧‧GaAs基板/基板 1110‧‧‧GaAs substrate/substrate
1120‧‧‧GaAs緩衝區域/緩衝區域 1120‧‧‧GaAs buffer area/buffer area
1130‧‧‧子集極區域 1130‧‧‧ subset polar region
1135‧‧‧金屬集極觸點 1135‧‧‧Metal collector contacts
1140‧‧‧集極區域 1140‧‧‧ Collecting area
1150‧‧‧量子大小區域 1150‧‧‧Quantum size area
1160‧‧‧基極區域 1160‧‧‧base area
1162‧‧‧基極子區域/基極-2區域 1162‧‧‧Base region/base-2 region
1165‧‧‧金屬基極觸點 1165‧‧‧Metal base contacts
1167‧‧‧基極子區域/基極-1/基極-1區域 1167‧‧‧base region/base-1/base-1 region
1170‧‧‧射極區域 1170‧‧ ‧ emitter area
1180‧‧‧子射極區域 1180‧‧ ‧ sub-shooting area
1185‧‧‧金屬射極觸點/射極觸點 1185‧‧Metal emitter contacts/emitter contacts
CD‧‧‧電容 C D ‧‧‧ capacitor
d‧‧‧距離/橫向尺寸 d‧‧‧Distance/lateral dimension
QW‧‧‧量子井 QW‧‧·Quantum Well
w‧‧‧經曝露射極台面寬度 w‧‧‧Exposed emitter table width
圖1係根據本發明之一實施例且可用於實踐本發明之方法之一實施例的呈一發光電晶體之形式之一光學傾斜電荷裝置之一剖視圖。 1 is a cross-sectional view of one optical tilting charge device in the form of an illuminating transistor in accordance with an embodiment of the present invention and which can be used to practice one embodiment of the method of the present invention.
圖2係展示其中量子井在至基極之表面之穿隧距離內之圖1裝置之一實例之磊晶層結構之一表。使用與射極相同之材料之一穿隧障壁。一不對稱基極用於幫助朝向集極之再熱化及增加障壁高度。傾斜電荷裝置磊晶層經設計以與HBT鑄造製程相容。 2 is a table showing an epitaxial layer structure of one example of the apparatus of FIG. 1 in which the quantum well is within a tunneling distance to the surface of the base. Use one of the same materials as the emitter to tunnel the barrier. An asymmetric base is used to help reheat the collector toward the collector and increase the barrier height. The tilted charge device epitaxial layer is designed to be compatible with the HBT casting process.
圖3係展示使用圖1及圖2之結構來製作之裝置之經處理裝置DC特性之一表。 3 is a table showing DC characteristics of a processed device of a device fabricated using the structures of FIGS. 1 and 2.
圖4係隨用於圖1及圖2之裝置之基極電流而變之光輸出之一圖表。射極台面邊緣與基極金屬邊緣之間的距離自1.5微米變化至7微米同時將所有其他尺寸保持相同。增加距離d等效地增加基極電阻(電洞電阻)且因此促進(比較而言)量子井中之電子朝向基極觸點之橫向輸送。經由底部 基板使用一大面積偵測器來量測光，且標繪光對基極電流(復合電流)。所量測資料展示當距離變化時輻射復合效率並不改變，如圖4中可見，其中針對介於自1.5微米至7微米之範圍內之距離d之四條所標繪曲線實質上重疊且看似為一單個曲線。 Figure 4 is a graph of light output as a function of the base current for the devices of Figures 1 and 2. The distance between the edge of the emitter mesa and the edge of the base metal varies from 1.5 microns to 7 microns while keeping all other dimensions the same. Increasing the distance d equivalently increases the base resistance (hole resistance) and thus promotes (in comparison) the lateral transport of electrons in the quantum well towards the base contact. Via the bottom The substrate uses a large area of the detector to measure the light and plot the light to the base current (composite current). The measured data shows that the radiation recombination efficiency does not change when the distance changes, as can be seen in Figure 4, where the plotted curves for the distance d between the range from 1.5 microns to 7 microns substantially overlap and appear to Is a single curve.
圖5係標繪電容CD對距離d之一圖表。AC分析指示當距離d自1.5微米變化至7微米時，與電子動態相關聯之電容(亦即，電荷儲存電容、擴散電容)增加。當僅橫向尺寸(d)經更改時，此指示電容面積已由於電子經由QW之橫向行進而增加，因此填充該量子井之一較大區。 Figure 5 is a graph plotting the capacitance C D versus distance d. The AC analysis indicates that as the distance d changes from 1.5 microns to 7 microns, the capacitance associated with the electronic dynamics (i.e., charge storage capacitance, diffusion capacitance) increases. When only the lateral dimension (d) is altered, this indicates that the capacitance area has increased due to the lateral travel of electrons through the QW, thus filling a larger area of the quantum well.
圖6係類似於圖1之裝置之另一光學傾斜電荷裝置之一剖視圖(其中相似元件符號表示類似元件)，但其中裝置基極區域在該基極區域中具有呈量子點之形式之一不連續量子結構。 Figure 6 is a cross-sectional view of another optical tilting charge device similar to the device of Figure 1 (where like symbol indicates similar elements), but wherein the device base region has one of the quantum dots in the base region. Continuous quantum structure.
圖7係展示根據本發明之另一實施例之一裝置之磊晶層結構之一表。將一不對稱基極及不連續量子結構併入至該設計中。幫助朝向集極之再熱化。 Figure 7 is a table showing a structure of an epitaxial layer of a device in accordance with another embodiment of the present invention. An asymmetric base and discontinuous quantum structure are incorporated into the design. Help to reheat the collector.
圖8係展示根據本發明之另一實施例之一裝置之磊晶層結構之一表，其中採用一波狀量子井。 Figure 8 is a table showing the structure of an epitaxial layer of a device in accordance with another embodiment of the present invention, wherein a corrugated quantum well is employed.
圖9係展示根據本發明之另一實施例之一裝置之磊晶層結構之一表，其中結合一不連續量子結構使用一窄量子井。 Figure 9 is a table showing the structure of an epitaxial layer of a device in accordance with another embodiment of the present invention, wherein a narrow quantum well is used in conjunction with a discontinuous quantum structure.
圖10係根據本發明之另一實施例且可用於實踐本發明之方法之另一實施例的呈一發光電晶體之形式之一光學傾斜 電荷裝置之一剖視圖。 10 is an optical tilt in the form of a light-emitting transistor in accordance with another embodiment of the present invention and which can be used to practice another embodiment of the method of the present invention. A cross-sectional view of one of the charge devices.
圖11係展示本發明之圖10實施例之一實例之磊晶層結構之一表。 Figure 11 is a table showing the structure of an epitaxial layer of an example of the embodiment of Figure 10 of the present invention.
圖12係展示根據本發明之另一實施例之一裝置之磊晶層結構之一表。 Figure 12 is a table showing a structure of an epitaxial layer of a device in accordance with another embodiment of the present invention.
圖13係根據本發明之又一實施例且可用於實踐本發明之方法之又一實施例的呈一個兩端子傾斜電荷發光二極體之形式之另一光學傾斜電荷裝置之一剖視圖。 13 is a cross-sectional view of another optical tilting charge device in the form of a two-terminal oblique charge light emitting diode in accordance with yet another embodiment of the present invention and that can be used to practice yet another embodiment of the method of the present invention.
110‧‧‧未經摻雜基板 110‧‧‧Undoped substrate
125‧‧‧子集極區域/子集極 125‧‧‧Subset polar regions/subsets
127‧‧‧集極電極 127‧‧‧ Collector electrode
130‧‧‧集極區域 130‧‧‧ Collecting area
140‧‧‧基極區域/基極 140‧‧‧base area/base
145‧‧‧量子井 145‧‧‧Quantum Well
147‧‧‧基極電極 147‧‧‧ base electrode
150‧‧‧穿隧障壁層/穿隧障壁 150‧‧‧Through barrier layer/shield barrier
160‧‧‧射極區域/射極 160‧‧ ‧ emitter area / emitter
167‧‧‧射極電極 167‧‧ ‧ emitter electrode
d‧‧‧距離/橫向尺寸 d‧‧‧Distance/lateral dimension
w‧‧‧經曝露射極台面寬度 w‧‧‧Exposed emitter table width
Claims (34)
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| US201161629181P | 2011-11-14 | 2011-11-14 | |
| US201161629175P | 2011-11-14 | 2011-11-14 |
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| CN (1) | CN103930994A (en) |
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| US6593589B1 (en) * | 1998-01-30 | 2003-07-15 | The University Of New Mexico | Semiconductor nitride structures |
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| US7244997B2 (en) * | 2003-07-08 | 2007-07-17 | President And Fellows Of Harvard College | Magneto-luminescent transducer |
| JP2007066981A (en) * | 2005-08-29 | 2007-03-15 | Toshiba Corp | Semiconductor device |
| WO2007121524A1 (en) * | 2006-04-20 | 2007-11-01 | Epitactix Pty Ltd. | Method of manufacture and resulting structures for semiconductor devices |
| WO2010080694A2 (en) * | 2009-01-08 | 2010-07-15 | The Board Of Trustees Of The University Of Illinois | Light emitting and lasing semiconductor devices and methods |
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| EP2780945A4 (en) | 2015-11-04 |
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