TW201327839A - Thin-film transistor, method for manufacturing same, and display device - Google Patents
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- TW201327839A TW201327839A TW101140841A TW101140841A TW201327839A TW 201327839 A TW201327839 A TW 201327839A TW 101140841 A TW101140841 A TW 101140841A TW 101140841 A TW101140841 A TW 101140841A TW 201327839 A TW201327839 A TW 201327839A
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- 239000010409 thin film Substances 0.000 title claims abstract description 58
- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000010408 film Substances 0.000 claims abstract description 280
- 239000004065 semiconductor Substances 0.000 claims abstract description 67
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- 239000001257 hydrogen Substances 0.000 claims description 75
- 229910052739 hydrogen Inorganic materials 0.000 claims description 75
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 70
- 239000010936 titanium Substances 0.000 claims description 57
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 56
- 229910052719 titanium Inorganic materials 0.000 claims description 56
- 238000010438 heat treatment Methods 0.000 claims description 53
- 238000002161 passivation Methods 0.000 claims description 40
- 239000000758 substrate Substances 0.000 claims description 37
- 229910052751 metal Inorganic materials 0.000 claims description 28
- 239000002184 metal Substances 0.000 claims description 28
- 230000015572 biosynthetic process Effects 0.000 claims description 20
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 11
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 8
- 229910052733 gallium Inorganic materials 0.000 claims description 8
- 229910052738 indium Inorganic materials 0.000 claims description 8
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 8
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 6
- 239000011733 molybdenum Substances 0.000 claims description 6
- 239000011159 matrix material Substances 0.000 claims description 5
- 239000011787 zinc oxide Substances 0.000 claims description 5
- 229910001182 Mo alloy Inorganic materials 0.000 claims description 4
- 229910001069 Ti alloy Inorganic materials 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 4
- 238000003860 storage Methods 0.000 claims description 2
- YZCKVEUIGOORGS-IGMARMGPSA-N Protium Chemical compound [1H] YZCKVEUIGOORGS-IGMARMGPSA-N 0.000 claims 1
- 230000009467 reduction Effects 0.000 abstract description 168
- 230000002349 favourable effect Effects 0.000 abstract 2
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- 239000004973 liquid crystal related substance Substances 0.000 description 17
- 239000010949 copper Substances 0.000 description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 13
- 229910052802 copper Inorganic materials 0.000 description 13
- 238000005530 etching Methods 0.000 description 13
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 9
- 238000004544 sputter deposition Methods 0.000 description 9
- 229910001936 tantalum oxide Inorganic materials 0.000 description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 8
- DIOQZVSQGTUSAI-UHFFFAOYSA-N decane Chemical compound CCCCCCCCCC DIOQZVSQGTUSAI-UHFFFAOYSA-N 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 8
- 239000001301 oxygen Substances 0.000 description 8
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 6
- 229910000449 hafnium oxide Inorganic materials 0.000 description 6
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 6
- 238000009826 distribution Methods 0.000 description 5
- 238000005259 measurement Methods 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 5
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 5
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 5
- 238000010521 absorption reaction Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 239000011701 zinc Substances 0.000 description 4
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 150000002431 hydrogen Chemical class 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 229910052725 zinc Inorganic materials 0.000 description 3
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005401 electroluminescence Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000009751 slip forming Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 108091006149 Electron carriers Proteins 0.000 description 1
- 229910018557 Si O Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 229910007541 Zn O Inorganic materials 0.000 description 1
- 229910007604 Zn—Sn—O Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910000420 cerium oxide Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- -1 hydrogen ions Chemical class 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000001272 nitrous oxide Substances 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
本發明係關於一種薄膜電晶體、其製造方法、及顯示裝置，尤其關於一種具有包含氧化物半導體膜之通道層的薄膜電晶體、其製造方法、及顯示裝置。 The present invention relates to a thin film transistor, a method of manufacturing the same, and a display device, and more particularly to a thin film transistor having a channel layer including an oxide semiconductor film, a method of manufacturing the same, and a display device.
近年來，著重於氧化銦鎵鋅(以下稱為「IGZO」)等氧化物半導體膜之優異性質，而不斷發展具有包含氧化物半導體膜之通道層的薄膜電晶體(Thin Film Transistor：以下稱為「TFT」)之開發。 In recent years, focusing on the excellent properties of oxide semiconductor films such as indium gallium zinc oxide (hereinafter referred to as "IGZO"), thin film transistors having a channel layer including an oxide semiconductor film have been developed (Thin Film Transistor: hereinafter referred to as Development of "TFT").
氧化物半導體膜之氧化還原狀態係因氧化物半導體膜及絕緣膜之膜厚或熱處理下其等之膜質之變動而變化，故TFT之特性較大地變動。例如，具有包含氧化物半導體膜之通道層的TFT會產生如下問題，即，若氧化物半導體膜過度地被氧化，則TFT之閾值電壓增高，接通電流降低。另一方面，若氧化物半導體膜過度地被還原，則TFT之閾值電壓降低，即便將閘極電壓設為0 V亦無法截止電流。 The redox state of the oxide semiconductor film changes depending on the film thickness of the oxide semiconductor film and the insulating film or the film quality of the insulating film, and the characteristics of the TFT largely fluctuate. For example, a TFT having a channel layer including an oxide semiconductor film has a problem that if the oxide semiconductor film is excessively oxidized, the threshold voltage of the TFT is increased, and the on-current is lowered. On the other hand, when the oxide semiconductor film is excessively reduced, the threshold voltage of the TFT is lowered, and the current cannot be turned off even if the gate voltage is set to 0 V.
因此，為獲得良好之TFT特性，需要使氧化物半導體膜成為適當之還原狀態。例如，於日本專利特開2010-232647號公報中記載有如下技術：利用鈦(Ti)膜形成與IGZO膜相接之源極/汲極電極，且使鈦膜與IGZO膜反應，使IGZO膜在膜厚方向上還原，藉此，製造具有良好特性之TFT。 Therefore, in order to obtain good TFT characteristics, it is necessary to make the oxide semiconductor film into an appropriate reduced state. For example, JP-A-2010-232647 discloses a technique of forming a source/drain electrode that is in contact with an IGZO film using a titanium (Ti) film, and reacting the titanium film with the IGZO film to form an IGZO film. Reduction in the film thickness direction, whereby a TFT having good characteristics is produced.
[專利文獻1]日本專利特開2010-232647號公報 [Patent Document 1] Japanese Patent Laid-Open Publication No. 2010-232647
然而，日本專利特開2010-232647號公報中記載之TFT之通道層之膜厚極薄僅為40~50 nm左右。以nm單位控制如此薄之氧化物半導體膜之還原反應極為困難。因此，製造具有良好特性之TFT較為困難。 However, the film thickness of the channel layer of the TFT described in Japanese Laid-Open Patent Publication No. 2010-232647 is extremely thin only about 40 to 50 nm. It is extremely difficult to control the reduction reaction of such a thin oxide semiconductor film in units of nm. Therefore, it is difficult to manufacture a TFT having good characteristics.
因此，本發明之目的在於提供一種藉由將氧化物半導體膜在其長度方向上還原而具有良好特性之薄膜電晶體及其製造方法。 Accordingly, it is an object of the present invention to provide a thin film transistor having excellent characteristics by reducing an oxide semiconductor film in its longitudinal direction and a method for producing the same.
第1態樣係一種薄膜電晶體，其特徵在於：其係形成於絕緣基板上者，且包括通道層，其包含氧化物半導體層；閘極絕緣膜，其係與上述通道層相接地形成；閘極電極，其係以隔著上述閘極絕緣膜而與上述通道層對向之方式形成；以及源極電極及汲極電極，其等係於上述通道層之長度方向之兩側，分別與上述通道層電性連接；上述通道層之載子濃度係自源極電極及汲極電極所連接之位置朝向上述通道層之內側變低。 The first aspect is a thin film transistor characterized in that it is formed on an insulating substrate, and includes a channel layer including an oxide semiconductor layer; and a gate insulating film which is formed in contact with the channel layer a gate electrode formed to face the channel layer via the gate insulating film; and a source electrode and a drain electrode, which are respectively on both sides of the length direction of the channel layer, respectively The channel layer is electrically connected to the channel layer; the carrier concentration of the channel layer is lower from a position where the source electrode and the drain electrode are connected toward the inner side of the channel layer.
第2態樣係如第1態樣，其中上述通道層係於將上述閘極絕緣膜內之電場強度成為1 MV/cm之閘極電壓施加至上述 閘極電極時，包含2個第1區域，其等具有特定之載子濃度；2個第2區域，其等分別與上述2個第1區域之內側鄰接，且載子濃度低於上述第1區域；及第3區域，其由上述2個第2區域夾持，且載子濃度低於上述第2區域；上述源極電極及上述汲極電極係分別連接於上述2個第1區域。 The second aspect is the first aspect, wherein the channel layer is applied to the gate voltage at which the electric field intensity in the gate insulating film becomes 1 MV/cm. The gate electrode includes two first regions, and the like has a specific carrier concentration; the two second regions are adjacent to the inner sides of the two first regions, respectively, and the carrier concentration is lower than the first And a third region sandwiched by the two second regions and having a carrier concentration lower than the second region; wherein the source electrode and the drain electrode are connected to the two first regions.
第3態樣係如第2態樣，其中電通道長度為上述第2區域之長度與上述第3區域之長度之和。 The third aspect is the second aspect, wherein the length of the electrical path is the sum of the length of the second region and the length of the third region.
第4態樣係如第3態樣，其中上述電通道長度為2~6 μm。 The fourth aspect is as in the third aspect, wherein the length of the electrical channel is 2-6 μm.
第5態樣係如第3態樣，其中上述電通道長度為3~5 μm。 The fifth aspect is the third aspect, wherein the length of the electrical channel is 3 to 5 μm.
第6態樣係如第3態樣，其中上述源極電極及上述汲極電極包含單一之金屬層或複數個金屬層積層所得之積層金屬膜，且至少與上述通道層電性連接之上述金屬層包含可吸氫1×1020 cm-3以上之材料。 The sixth aspect is the third aspect, wherein the source electrode and the drain electrode comprise a single metal layer or a plurality of metal laminated layers, and at least the metal layer electrically connected to the channel layer The layer contains a material which can absorb hydrogen of 1 × 10 20 cm -3 or more.
第7態樣係如第6態樣，其中上述材料係鈦、鈦合金、鉬或鉬合金之任一者。 The seventh aspect is as in the sixth aspect, wherein the above material is any one of titanium, titanium alloy, molybdenum or molybdenum alloy.
第8態樣係如第6態樣，其中上述閘極電極係形成於上述絕緣基板上，上述閘極絕緣膜係以覆蓋上述閘極電極之方式形成，上述通道層係以與上述閘極電極對向之方式形成於上述閘極絕緣膜上，且上述源極電極及上述汲極電極分別與形成於上述通道層上之上述2個第1區域電性連接。 The eighth aspect is the sixth aspect, wherein the gate electrode is formed on the insulating substrate, the gate insulating film is formed to cover the gate electrode, and the channel layer is connected to the gate electrode The opposite direction is formed on the gate insulating film, and the source electrode and the drain electrode are electrically connected to the two first regions formed on the channel layer.
第9態樣係如第8態樣，其中更包含覆蓋上述源極電極及上述汲極電極之鈍化膜，上述源極電極及上述汲極電極係於上述通道層之長度方向之兩側，以分別與上述2個第1區相接之方式形成，且上述鈍化膜進而覆蓋由上述源極電極與上述汲極電極夾持之上述通道層之表面。 The ninth aspect is the eighth aspect, further comprising a passivation film covering the source electrode and the drain electrode, wherein the source electrode and the drain electrode are on both sides of the length direction of the channel layer, Each of the two first regions is formed in contact with each other, and the passivation film further covers a surface of the channel layer sandwiched between the source electrode and the drain electrode.
第10態樣係如第8態樣，其中更包含以覆蓋由上述源極電極與上述汲極電極夾持之上述通道層之表面之方式形成之蝕刻終止層，且上述源極電極及上述汲極電極係經由形成於上述蝕刻終止層之接觸孔，分別與上述通道層之上述2個第1區域電性連接。 The tenth aspect is the eighth aspect, further comprising an etch stop layer formed to cover a surface of the channel layer sandwiched by the source electrode and the drain electrode, and the source electrode and the 汲The electrode electrodes are electrically connected to the two first regions of the channel layer via contact holes formed in the etching stopper layer.
第11態樣係如第8態樣，其中上述通道層之一端係以覆蓋上述源極電極之一端之方式形成，上述通道層之另一端係以覆蓋上述汲極電極之一端之方式形成。 The eleventh aspect is the eighth aspect, wherein one end of the channel layer is formed to cover one end of the source electrode, and the other end of the channel layer is formed to cover one end of the gate electrode.
第12態樣係如第6態樣，其中上述通道層係形成於上述絕緣基板上，上述閘極絕緣膜係以覆蓋上述通道層之方式形成，上述閘極電極係以與上述閘極電極對向之方式形成於上述閘極絕緣膜上，且上述源極電極及上述汲極電極係分別與形成於上述通道層上之上述2個第1區域電性連接。 The twelfth aspect is the sixth aspect, wherein the channel layer is formed on the insulating substrate, the gate insulating film is formed to cover the channel layer, and the gate electrode is opposite to the gate electrode The method is formed on the gate insulating film, and the source electrode and the drain electrode are electrically connected to the two first regions formed on the channel layer.
第13態樣係如第6態樣，其中上述通道層係包含氧化銦鎵鋅層。 The thirteenth aspect is the sixth aspect, wherein the channel layer comprises an indium gallium zinc oxide layer.
第14態樣係如第6態樣，其中上述通道層係包含微晶氧化物半導體。 The 14th aspect is as in the sixth aspect, wherein the channel layer comprises a microcrystalline oxide semiconductor.
第15態樣係一種薄膜電晶體之製造方法，其特徵在於：其係形成於絕緣基板上之薄膜電晶體之製造方法，且包括如下步驟：形成包含氧化物半導體層之通道層；形成與上述通道層相接地形成之閘極絕緣膜；以隔著上述閘極絕緣膜而與上述通道層對向之方式形成閘極電極；於上述通道層之長度方向之兩側，分別連接吸存氫之源極電極及汲極電極；及將上述源極電極及上述汲極連接於上述通道層後進行熱處理；上述熱處理步驟係將吸存於上述源極電極及上述汲極電極中之氫供給至上述通道層，並使其沿上述通道層之長度方向擴散。 The fifteenth aspect is a method for manufacturing a thin film transistor, which is characterized in that it is a method for manufacturing a thin film transistor formed on an insulating substrate, and includes the steps of: forming a channel layer including an oxide semiconductor layer; forming the above a gate insulating film formed by the channel layer being grounded; forming a gate electrode opposite to the channel layer via the gate insulating film; and respectively connecting hydrogen storage on both sides of the length direction of the channel layer a source electrode and a drain electrode; and heat-treating the source electrode and the drain electrode connected to the channel layer; and the heat treatment step of supplying hydrogen stored in the source electrode and the drain electrode to The channel layer is diffused along the length of the channel layer.
第16態樣係如第15態樣，其中上述源極電極及上述汲極電極至少於上述熱處理步驟之前已吸存氫1×1020 cm-3以上。 The 16th aspect is the 15th aspect, wherein the source electrode and the drain electrode have absorbed hydrogen of at least 1 × 10 20 cm -3 at least before the heat treatment step.
第17態樣係一種顯示裝置，其特徵在於：其係顯示圖像之主動矩陣型顯示裝置，且包含：顯示部，其包含複數條閘極配線、與上述複數條閘極配線交叉之複數條源極配線、分別對應於上述複數條閘極配線與上述複數條源極配線之交叉點以矩陣狀配置之複數個 像素形成部；及驅動電路，其驅動上述複數個像素形成部；用於寫入自上述源極配線對上述像素形成部賦予圖像信號的開關元件係第2態樣之薄膜電晶體。 The seventh aspect is a display device characterized in that it is an active matrix display device that displays an image, and includes: a display portion including a plurality of gate wirings and a plurality of strips crossing the plurality of gate wirings; Source wirings respectively corresponding to a plurality of intersections of the plurality of gate wirings and the plurality of source wirings in a matrix a pixel forming unit; and a driving circuit that drives the plurality of pixel forming portions; and a thin film transistor for writing a second aspect of the switching element that supplies an image signal from the source wiring to the pixel forming portion.
根據上述第1態樣，於意圖藉由控制作為通道層之氧化物半導體層之載子濃度來獲得良好之電晶體特性之情形時，使載子濃度自通道層之兩側朝向內側變化相較於膜厚方向上使該載子濃度變化更易於控制。因此，可藉由使載子濃度自通道層之兩側朝向內側變化而獲得具有良好特性之薄膜電晶體。 According to the first aspect described above, when it is intended to obtain good crystal characteristics by controlling the carrier concentration of the oxide semiconductor layer as the channel layer, the carrier concentration is changed from the both sides of the channel layer toward the inner side. This carrier concentration change is more easily controlled in the film thickness direction. Therefore, a thin film transistor having good characteristics can be obtained by changing the carrier concentration from both sides of the channel layer toward the inside.
根據上述第2態樣，當施加使閘極絕緣膜內之電場強度成為1 MV/cm之類的閘極電壓時，於通道層上以載子濃度自其兩側朝向內側依序降低之方式，形成有第1區域、第2區域及第3區域。藉此，通道層之載子濃度朝向內側降低，故可獲得具有良好特性之薄膜電晶體。 According to the second aspect described above, when a gate voltage such that the electric field intensity in the gate insulating film is 1 MV/cm is applied, the carrier concentration is sequentially lowered from the both sides toward the inner side on the channel layer. The first region, the second region, and the third region are formed. Thereby, the carrier concentration of the channel layer is lowered toward the inside, so that a thin film transistor having good characteristics can be obtained.
根據上述第3態樣，於施加使閘極絕緣膜內之電場強度成為1 MV/cm之類的閘極電壓時，薄膜電晶體之電通道長度成為第2區域之長度與第3區域之長度之和。可藉由如此地於通道區域內包含第2區域及第3區域，而獲得陷阱能階減少(薄膜電晶體之特性測定時之閾值電壓之偏移減小)且閘極電壓為0 V時之漏電流減小等特性良好之薄膜電晶體。 According to the third aspect, when the gate voltage of the gate insulating film is set to a gate voltage of 1 MV/cm, the length of the electric path of the thin film transistor becomes the length of the second region and the length of the third region. Sum. By including the second region and the third region in the channel region, the trap level can be reduced (the shift of the threshold voltage when the characteristics of the thin film transistor is measured is reduced) and the gate voltage is 0 V. Thin film transistors with good characteristics such as reduced leakage current.
根據上述第4態樣，可藉由將電通道長度設為2~6 μm， 而獲得具有良好特性之薄膜電晶體。 According to the fourth aspect described above, the length of the electrical channel can be set to 2 to 6 μm. A thin film transistor having good characteristics is obtained.
根據上述第5態樣，可藉由將電通道長度設為3~5 μm，而獲得具有更良好之特性之薄膜電晶體。 According to the fifth aspect described above, a thin film transistor having better characteristics can be obtained by setting the length of the electric path to 3 to 5 μm.
根據上述第6態樣，源極電極及汲極電極之金屬層係由可吸氫1×1020 cm-3以上之材料形成。因此，將吸存於金屬層內之氫於熱處理時供給至通道層，於通道層內擴散，將通道層還原。可藉由以此方式將電通道長度控制為最佳長度，而獲得具有良好特性之薄膜電晶體。 According to the sixth aspect described above, the metal layers of the source electrode and the drain electrode are formed of a material capable of absorbing hydrogen of 1 × 10 20 cm -3 or more. Therefore, hydrogen absorbed in the metal layer is supplied to the channel layer during heat treatment, diffused in the channel layer, and the channel layer is reduced. A thin film transistor having good characteristics can be obtained by controlling the length of the electrical channel to an optimum length in this manner.
根據上述第7態樣，鈦、鈦合金、鉬、或鉬合金均為可吸氫1×1020 cm-3以上之材料。於熱處理時可將充分量之氫供給至通道層。藉此，電通道長度之控制變得容易，從而可獲得具有良好特性之薄膜電晶體。 According to the seventh aspect described above, the titanium, the titanium alloy, the molybdenum, or the molybdenum alloy are all materials capable of absorbing hydrogen of 1 × 10 20 cm -3 or more. A sufficient amount of hydrogen can be supplied to the channel layer during the heat treatment. Thereby, the control of the length of the electrical path becomes easy, and a thin film transistor having good characteristics can be obtained.
根據上述第8態樣，可藉由於絕緣基板上配置有閘極電極之結構之薄膜電晶體中，將由氫還原之氧化物半導體層作為通道層，而獲得具有良好特性之薄膜電晶體。 According to the eighth aspect described above, a thin film transistor having a structure in which a gate electrode is disposed on an insulating substrate can be used as a channel layer by a hydrogen-reduced oxide semiconductor layer, thereby obtaining a thin film transistor having excellent characteristics.
根據上述第9態樣，可藉由於通道蝕刻結構之薄膜電晶體中，將由氫還原之氧化物半導體層作為通道層，而獲得具有良好特性之薄膜電晶體。 According to the ninth aspect described above, the thin film transistor having good characteristics can be obtained by using the oxide semiconductor layer reduced by hydrogen as a channel layer in the thin film transistor of the channel etching structure.
根據上述第10態樣，可藉由於蝕刻終止結構之薄膜電晶體中，將由氫還原之氧化物半導體層作為通道層，而獲得具有良好特性之薄膜電晶體。 According to the tenth aspect described above, the thin film transistor having good characteristics can be obtained by using the oxide semiconductor layer reduced by hydrogen as a channel layer in the thin film transistor of the etching termination structure.
根據上述第11態樣，可藉由於底端接觸結構之薄膜電晶體中，將由氫還原之氧化物半導體層作為通道層，而獲得具有良好特性之薄膜電晶體。 According to the eleventh aspect described above, the thin film transistor having good characteristics can be obtained by using the oxide semiconductor layer reduced by hydrogen as the channel layer in the thin film transistor of the bottom contact structure.
根據上述第12態樣，可藉由於頂閘極結構之薄膜電晶體中，將由氫還原之氧化物半導體層作為通道層，而獲得具有良好特性之薄膜電晶體。 According to the twelfth aspect described above, the thin film transistor having good characteristics can be obtained by using the oxide semiconductor layer reduced by hydrogen as the channel layer in the thin film transistor of the top gate structure.
根據上述第13態樣，由於通道層包含氧化銦鎵鋅，故而，易於藉由氫而沿該通道層之長度方向將該通道層還原。藉此，電通道長度之控制變得容易，從而可獲得具有良好特性之薄膜電晶體。 According to the thirteenth aspect described above, since the channel layer contains indium gallium zinc oxide, it is easy to reduce the channel layer along the length direction of the channel layer by hydrogen. Thereby, the control of the length of the electrical path becomes easy, and a thin film transistor having good characteristics can be obtained.
根據上述第14態樣，由於通道層包含微晶氧化物半導體層，故而，薄膜電晶體之接通電阻減小。藉此，可增大接通電流。 According to the above-described fourteenth aspect, since the channel layer contains the microcrystalline oxide semiconductor layer, the on-resistance of the thin film transistor is reduced. Thereby, the on current can be increased.
根據上述第15態樣，於將吸存有氫之源極電極及汲極電極連接於通道層後，藉由進行熱處理，而自源極電極及汲極電極對通道層供給氫，進而，供給之氫於通道層內沿其長度方向進行擴散。藉此，可容易地進行電通道長度之控制，從而可製造具有良好特性之薄膜電晶體。 According to the fifteenth aspect, after the source electrode and the drain electrode which store hydrogen are connected to the channel layer, hydrogen is supplied from the source electrode and the drain electrode to the channel layer by heat treatment, and further, the supply is performed. The hydrogen diffuses along its length in the channel layer. Thereby, the control of the length of the electric path can be easily performed, so that a thin film transistor having good characteristics can be manufactured.
根據上述第16態樣，源極電極及汲極電極係至少於熱處理步驟之前已吸存氫1×1020 cm-3以上，故而，可藉由熱處理而將充分量之氫供給至通道層，從而有效地還原通道層。藉此，可製造具有更良好特性之薄膜電晶體。 According to the sixteenth aspect, the source electrode and the drain electrode have absorbed hydrogen of 1 × 10 20 cm -3 or more at least before the heat treatment step, so that a sufficient amount of hydrogen can be supplied to the channel layer by heat treatment. Thereby the channel layer is effectively restored. Thereby, a thin film transistor having more excellent characteristics can be manufactured.
根據上述第17態樣，可藉由使用具有良好特性之薄膜電晶體作為設於顯示部中之各像素形成部之開關元件，而於截止時避免漏電流流動，或者，避免接通電流因閾值電壓變高而降低。藉此，可提昇顯示部中顯示之圖像之顯示品質。 According to the seventeenth aspect, the thin film transistor having good characteristics can be used as the switching element of each pixel forming portion provided in the display portion, thereby avoiding leakage current flow at the time of turning off, or avoiding the on current due to the threshold value. The voltage becomes higher and lowers. Thereby, the display quality of the image displayed on the display unit can be improved.
<1.1 TFT之構成> <1.1 Structure of TFT>
圖1係表示基礎研究中使用之通道蝕刻結構之TFT10之構成之剖面圖。如圖1所示，TFT10係包含閘極電極20，其形成於絕緣基板15上；閘極絕緣膜30，其以覆蓋閘極電極20之方式形成；島狀通道層40，其形成於與閘極電極20對向之閘極絕緣膜30上之位置；源極電極60a，其自通道層40之左上表面延伸至左側之閘極絕緣膜30上；汲極電極60b，其自通道層40之右上表面延伸至右側之閘極絕緣膜30上；及鈍化膜70，其以覆蓋包含源極電極60a及汲極電極60b之基板之整體之方式形成。 Fig. 1 is a cross-sectional view showing the constitution of a TFT 10 of a channel etching structure used in the basic research. As shown in FIG. 1, the TFT 10 includes a gate electrode 20 formed on the insulating substrate 15, a gate insulating film 30 formed to cover the gate electrode 20, and an island-shaped channel layer 40 formed on the gate. a position of the electrode electrode 20 opposite to the gate insulating film 30; a source electrode 60a extending from the upper left surface of the channel layer 40 to the left gate insulating film 30; and a drain electrode 60b from the channel layer 40 The upper right surface extends to the right gate insulating film 30; and the passivation film 70 is formed to cover the entirety of the substrate including the source electrode 60a and the drain electrode 60b.
於TFT10中，通道層40包含IGZO膜等氧化物半導體膜。源極電極60a及汲極電極60b包含於鈦層上積層有銅(Cu)層之積層金屬膜，且鈦層以與通道層40相接之方式形成。再者，於以下說明中，亦存在將通道層40稱為氧化物半導體層之情形。 In the TFT 10, the channel layer 40 includes an oxide semiconductor film such as an IGZO film. The source electrode 60a and the drain electrode 60b include a laminated metal film in which a copper (Cu) layer is laminated on the titanium layer, and the titanium layer is formed in contact with the channel layer 40. Further, in the following description, there is also a case where the channel layer 40 is referred to as an oxide semiconductor layer.
鈦層係藉由自氧化物半導體層中奪取作為其構成元素之一的氧而還原氧化物半導體層，並且由所奪取之氧進行氧化而成為氧化鈦(TiO2)。又，鈦層係將鈍化膜70之成膜時吸存之氫供給至氧化物半導體層。自鈦層供給之氫係一面沿橫向(通道層40之長度方向)在氧化物半導體層中擴散一面還原氧化物半導體層。其結果，靠近源極電極60a及汲極電極60b之端部之氧化物半導體層因自鈦層供給之氫之 量較多而成為高還原區域(亦稱為「第1區域」)40a。相較2個高還原區域40a為內側之氧化物半導體層因供給之氫之量減少而分別成為低還原區域(亦稱為「第2區域」)40b。進而，由2個低還原區域40b夾持之區域成為所供給之氫之量更少之非還原區域(亦稱為「第3區域」)40c。如此般，於氧化物半導體層上，自源極電極60a及汲極電極60b之端部朝向內側，依序形成高還原區域40a、低還原區域40b及非還原區域40c。 The titanium layer reduces the oxide semiconductor layer by taking oxygen as one of its constituent elements from the oxide semiconductor layer, and oxidizes it by the trapped oxygen to become titanium oxide (TiO 2 ). Further, the titanium layer supplies hydrogen which is stored during the film formation of the passivation film 70 to the oxide semiconductor layer. The hydrogen-based layer supplied from the titanium layer is diffused in the oxide semiconductor layer in the lateral direction (the longitudinal direction of the channel layer 40) to reduce the oxide semiconductor layer. As a result, the oxide semiconductor layer near the end portions of the source electrode 60a and the drain electrode 60b becomes a high reduction region (also referred to as a "first region") 40a due to the large amount of hydrogen supplied from the titanium layer. The oxide semiconductor layer which is the inner side of the two high reduction regions 40a is reduced to a low reduction region (also referred to as a "second region") 40b due to a decrease in the amount of hydrogen supplied. Further, the region sandwiched by the two low reduction regions 40b is a non-reduction region (also referred to as "third region") 40c having a smaller amount of supplied hydrogen. In the oxide semiconductor layer, the high reduction region 40a, the low reduction region 40b, and the non-reduction region 40c are sequentially formed from the end portions of the source electrode 60a and the drain electrode 60b toward the inside.
圖2係表示施加6 V之閘極電壓Vg時求出電通道長度Leff之方法之圖。圖2之橫軸係表示TFT10之通道長度Lch。於本說明書中，通道長度Lch係與源極電極60a之端部至汲極電極60b之端部為止之距離(以下稱為「源極/汲極間距離」)Lsd相等。縱軸係表示根據施加0.1 V汲極電壓Vd時之TFT10之電阻值求出的通道寬度為1 μm時之電阻值Rmeas。 Fig. 2 is a view showing a method of determining the length Lef of the electric path when a gate voltage Vg of 6 V is applied. The horizontal axis of Fig. 2 indicates the channel length Lch of the TFT 10. In the present specification, the channel length Lch is equal to the distance from the end of the source electrode 60a to the end of the drain electrode 60b (hereinafter referred to as "source/drain distance") Lsd. The vertical axis indicates the resistance value Rmeas when the channel width is 1 μm obtained from the resistance value of the TFT 10 when the 0.1 V gate voltage Vd is applied.
如圖2所示，為求出施加6 V之閘極電壓Vg時之電通道長度Leff，而對通道長度Lch不同之複數個TFT10求出施加5 V之閘極電壓Vg時、及施加7 V之閘極電壓Vg時之電阻值Rmeas。繼而，求出表示閘極電壓Vg為5 V時之測定結果之直線與表示閘極電壓Vg為7 V時之測定結果之直線的交點。如此求出之交點之X座標係表示還原區域之長度△L，Y座標係表示還原區域之電阻值Rmeas。 As shown in FIG. 2, in order to obtain the electric path length Leff when the gate voltage Vg of 6 V is applied, and to apply the gate voltage Vg of 5 V to the plurality of TFTs 10 having different channel lengths Lch, and apply 7 V The resistance value Rmeas at the gate voltage Vg. Then, the intersection of the straight line indicating the measurement result when the gate voltage Vg is 5 V and the straight line indicating the measurement result when the gate voltage Vg is 7 V is obtained. The X coordinate of the intersection thus obtained indicates the length ΔL of the reduction region, and the Y coordinate indicates the resistance value Rmeas of the reduction region.
圖3係表示TFT10中之各區域之圖。如圖3所示，自源極電極60a及汲極電極60b之端部分別朝向內側延伸長度為 L/2之還原區域，由左右還原區域夾持之區域之長度成為電通道長度Leff。左右還原區域之長度為△L，故單側之長度為△L/2。通道長度Lch為還原區域之長度△L與電通道長度Leff之和，再者，還原區域於以下稱為△區域。又，△區域之電阻值除以△區域之長度△L所得之值為下述平均片電阻Rs。 FIG. 3 is a view showing each region in the TFT 10. As shown in FIG. 3, the lengths from the end portions of the source electrode 60a and the drain electrode 60b respectively extend toward the inside. In the reduction region of L/2, the length of the region sandwiched by the left and right reduction regions becomes the electric channel length Leff. The length of the left and right reduction regions is ΔL, so the length of one side is ΔL/2. The channel length Lch is the sum of the length ΔL of the reduction region and the length Leff of the electric channel, and the reduction region is hereinafter referred to as the Δ region. Further, the value obtained by dividing the resistance value of the Δ region by the length ΔL of the Δ region is the average retort resistance Rs described below.
亦由圖3可知，電通道長度Leff由下式(1)表示。 As is also apparent from Fig. 3, the electric path length Leff is expressed by the following formula (1).
Leff=Lch-△L (1) Leff=Lch-△L (1)
△區域之長度△L係相應於閘極電壓Vg而變化，故電通道長度Leff亦相應於閘極電壓Vg而變化。於閘極電壓Vg較低之情形時，△區域中包含高還原區域40a及低還原區域40b，由電通道長度Leff表示之區域中包含低還原區域40b及非還原區域40c。即，低還原區域40b不僅包含於△區域中所包含之區域，亦包含於由電通道長度Leff表示之區域中。又，若施加較高之閘極電壓Vg，閘極絕緣膜30內之電場強度成為1 MV/cm，則如下所述，△區域僅成為高還原區域40a，且由電通道長度Leff表示之區域成為低還原區域40b及非還原區域40c。 The length ΔL of the Δ region changes in accordance with the gate voltage Vg, so the length Leff of the electric path also changes in accordance with the gate voltage Vg. When the gate voltage Vg is low, the Δ region includes the high reduction region 40a and the low reduction region 40b, and the region indicated by the electrical channel length Leff includes the low reduction region 40b and the non-reduction region 40c. That is, the low reduction region 40b is included not only in the region included in the Δ region but also in the region indicated by the electric channel length Leff. Further, when a higher gate voltage Vg is applied and the electric field intensity in the gate insulating film 30 becomes 1 MV/cm, as described below, the Δ region becomes only the high reduction region 40a, and the region represented by the electric channel length Leff The low reduction region 40b and the non-reduction region 40c are formed.
<1.2高還原區域及低還原區域> <1.2 High reduction area and low reduction area>
對通道層40中形成高還原區域40a及低還原區域40b之機制進行說明。於藉由電漿化學氣相沈積法(Chemical Vapor Deposition：以下稱為「電漿CVD法」)形成作為鈍化膜70之氧化矽(SiO2)膜時，若例如將矽烷(SiH4)氣體或正矽酸四乙酯(Tetraethyl orthosilicate：Si(OC2H5)4，TEOS)氣體 用作原料氣體，則所生成之電漿中將生成氫離子或氫自由基(以下將其等統稱為「氫」)。氫被吸存於構成源極電極60a及汲極電極60b之鈦層中，且藉由此後之熱處理而自鈦層擴散至氧化物半導體層內。擴散至氧化物半導體層內之氫將與氧化物半導體層之氧鍵結而形成OH鍵，或自氧化物半導體層中奪取氧而生成H2O，從而將氧化物半導體層還原。經還原之氧化物半導層將產生電子載體(以下稱為「載子」)，故氧化物半導體層之電阻值低下。△區域係以此方式經氫還原之氧化物半導體層內之區域，且藉由自鈦層供給之氫之擴散而形成。因此，氧化物半導體層之載子之濃度分佈係表示表示起因於擴散之分佈。 The mechanism for forming the high reduction region 40a and the low reduction region 40b in the channel layer 40 will be described. When a cerium oxide (SiO 2 ) film as the passivation film 70 is formed by a chemical vapor deposition method (hereinafter referred to as "plasma CVD method"), for example, silane (SiH 4 ) gas or When Tetraethyl orthosilicate (Si(OC 2 H 5 ) 4 , TEOS) gas is used as a raw material gas, hydrogen ions or hydrogen radicals are generated in the generated plasma (hereinafter referred to as "hydrogen"). Hydrogen is absorbed in the titanium layer constituting the source electrode 60a and the drain electrode 60b, and is diffused from the titanium layer into the oxide semiconductor layer by the subsequent heat treatment. The hydrogen diffused into the oxide semiconductor layer is bonded to the oxide semiconductor layer to form an OH bond, or oxygen is taken from the oxide semiconductor layer to form H 2 O, thereby reducing the oxide semiconductor layer. The reduced oxide semiconductor layer generates an electron carrier (hereinafter referred to as "carrier"), so that the oxide semiconductor layer has a low resistance value. The Δ region is a region in the oxide semiconductor layer which is reduced by hydrogen in this manner, and is formed by diffusion of hydrogen supplied from the titanium layer. Therefore, the concentration distribution of the carrier of the oxide semiconductor layer indicates a distribution resulting from diffusion.
圖4係表示與源極電極60a(或汲極電極60b)之端部相距之距離x與氧化物半導體層內之載子濃度Next之分佈的關係之圖。如圖4所示，氧化物半導體層內之載子濃度Next係於源極電極60a之端部濃度最高，且隨著遠離端部，載子濃度Next緩慢下降。因此，根據圖4所示之載子濃度分佈分別決定高還原區域40a及低還原區域40b之長度較為困難。 4 is a view showing the relationship between the distance x from the end of the source electrode 60a (or the gate electrode 60b) and the distribution of the carrier concentration Next in the oxide semiconductor layer. As shown in FIG. 4, the carrier concentration Next in the oxide semiconductor layer is the highest at the end of the source electrode 60a, and the carrier concentration Next gradually decreases as it goes away from the end. Therefore, it is difficult to determine the lengths of the high reduction region 40a and the low reduction region 40b based on the carrier concentration distribution shown in Fig. 4, respectively.
因此，高還原區域40a及低還原區域40b之長度Lhigh、Llow分別利用下述方法決定。根據其結果，高還原區域40a之載子濃度Next約為5×1017 cm-3以上，且自源極電極60a之端部起載子濃度Next成為約5×1017 cm-3之位置P1成為高還原區域40a之端部。又，高還原區域40a之端部之位置P1至內側之低於載子濃度Next之位置P2為止成為低還原 區域40b。然而，低還原區域40b無法如高還原區域40a般由閘極電壓Vg明確定義，故需要利用與高還原區域40a不同之方法進行定義。 Therefore, the lengths Lhigh and Llow of the high reduction region 40a and the low reduction region 40b are determined by the following methods, respectively. According to the result, the carrier concentration Next of the high reduction region 40a is about 5 × 10 17 cm -3 or more, and the carrier concentration Next from the end portion of the source electrode 60a becomes the position P1 of about 5 × 10 17 cm -3 . It becomes the end of the high reduction region 40a. Further, the low-reduction region 40b is formed from the position P1 of the end portion of the high-reduction region 40a to the position P2 at the inner side lower than the carrier concentration Next. However, the low reduction region 40b cannot be clearly defined by the gate voltage Vg as in the high reduction region 40a, and therefore it needs to be defined by a method different from the high reduction region 40a.
<1.3高還原區域及低還原區域之長度之求出方法> <1.3 Method for determining the length of the high reduction region and the low reduction region>
對求出高還原區域40a及低還原區域40b之長度Lhigh、Llow之方法進行說明。圖5係表示閘極電壓Vg與△區域之長度△L之關係之圖。再者，熱處理係於鈍化膜70之成膜後在300℃下進行1小時。 A method of determining the lengths Lhigh and Llow of the high reduction region 40a and the low reduction region 40b will be described. Fig. 5 is a view showing the relationship between the gate voltage Vg and the length ΔL of the Δ region. Further, the heat treatment was performed at 300 ° C for 1 hour after the film formation of the passivation film 70.
高還原區域40a之長度Lhigh以如下方式定義。即，於將閘極絕緣膜30之膜厚換算為氧化矽膜之膜厚時，定義為施加使閘極絕緣膜30內之電場強度成為1 MV/cm之閘極電壓Vg時之△區域之長度△L。因此，閘極絕緣膜之電場強度由下式(2)定義，(閘極電壓-閾值電壓)/閘極絕緣膜之膜厚 (2) The length Lhigh of the high reduction region 40a is defined as follows. In other words, when the film thickness of the gate insulating film 30 is converted into the film thickness of the yttrium oxide film, it is defined as the Δ region when the gate voltage Vg in the gate insulating film 30 is set to 1 MV/cm. Length △ L. Therefore, the electric field strength of the gate insulating film is defined by the following formula (2), (gate voltage - threshold voltage) / film thickness of the gate insulating film (2)
又，閘極絕緣膜之膜厚係指將作為電容之膜厚換算為氧化矽膜之膜厚時之膜厚。再者，求出△區域之長度△L之方法係記載於文獻(IEEE Trans.Electron Devices,Vol.ED-34,No.12(1987)2469.)中。 In addition, the film thickness of the gate insulating film refers to the film thickness when the film thickness of the capacitor is converted into the film thickness of the yttrium oxide film. Further, a method of obtaining the length ΔL of the Δ region is described in the literature (IEEE Trans. Electron Devices, Vol. ED-34, No. 12 (1987) 2469.).
閘極絕緣膜30係於氮化矽(SiN)膜上積層有氧化矽膜之積層絕緣膜，且例如氮化矽膜之膜厚為300 nm，氧化矽膜之膜厚為50 nm。又，氮化矽膜之比介電係數為氧化矽膜之比介電係數之1.5倍。因此，將300 nm之氮化矽膜之膜厚換算為氧化矽膜之膜厚時為300 nm/1.5=200 nm。據此，將閘極絕緣膜30之膜厚換算為氧化矽膜之膜厚時為250 nm。 若將施加至閘極電極20之閘極電壓Vg設為30 V，且將TFT10之閾值電壓設為5 V，則可追加地施加約25V至閘極絕緣膜30。此時，閘極絕緣膜30之電場強度根據上述定義為25 V/250 nm=1 MV/cm。因此，施加30 V至閘極電極20時之△區域之長度△L為高還原區域40a之長度Lhigh。 The gate insulating film 30 is a laminated insulating film in which a tantalum oxide film is laminated on a tantalum nitride (SiN) film, and for example, a film thickness of the tantalum nitride film is 300 nm, and a film thickness of the tantalum oxide film is 50 nm. Further, the specific dielectric constant of the tantalum nitride film is 1.5 times the specific dielectric constant of the tantalum oxide film. Therefore, when the film thickness of the 300 nm tantalum nitride film is converted to the film thickness of the tantalum oxide film, it is 300 nm/1.5=200 nm. According to this, when the film thickness of the gate insulating film 30 is converted to the film thickness of the yttrium oxide film, it is 250 nm. When the gate voltage Vg applied to the gate electrode 20 is set to 30 V and the threshold voltage of the TFT 10 is set to 5 V, about 25 V can be additionally applied to the gate insulating film 30. At this time, the electric field intensity of the gate insulating film 30 is 25 V / 250 nm = 1 MV / cm as defined above. Therefore, the length ΔL of the Δ region when 30 V is applied to the gate electrode 20 is the length Lhigh of the high reduction region 40a.
對求出高還原區域40a之長度Lhigh之方法進行具體說明。為使閘極絕緣膜30之電場強度成為1 MV/cm而將閘極電壓Vg設為30 V時，根據圖5，△區域之長度△L為2.2 μm。該2.2 μm係表示高還原區域40a之長度Lhigh。如圖4所示，如此求出之高還原區域40a成為載子濃度Next約為5×1017 cm-3以上之低電阻區域。 A method of determining the length Lhigh of the high reduction region 40a will be specifically described. When the gate voltage Vg is set to 30 V for the electric field intensity of the gate insulating film 30 to be 1 MV/cm, the length ΔL of the Δ region is 2.2 μm according to Fig. 5 . This 2.2 μm represents the length Lhigh of the high reduction region 40a. As shown in FIG. 4, the high reduction region 40a thus obtained has a low resistance region in which the carrier concentration Next is about 5 × 10 17 cm -3 or more.
相對於此，低還原區域40b之載子濃度Next為5×1016~5×1017 cm-3，且越靠近通道區域之內側，濃度越低。因此，若使閘極電壓Vg變化，改變通道區域之載子濃度Next，則低還原區域40b之長度Llow變動。於該情形時，可知閘極電壓Vg越低，則低還原區域40b之長度Llow越長，於最長時單側約為1 μm，兩側約為2 μm。然而，載子濃度Next係自低還原區域40b至非還原區域40c連續地變化，故難以求出僅低還原區域40b之長度Llow。 On the other hand, the carrier concentration Next of the low reduction region 40b is 5 × 10 16 to 5 × 10 17 cm -3 , and the concentration is lower as it is closer to the inner side of the channel region. Therefore, if the gate voltage Vg is changed and the carrier concentration Next of the channel region is changed, the length Llow of the low reduction region 40b fluctuates. In this case, it is understood that the lower the gate voltage Vg, the longer the length Llow of the low reduction region 40b is, and is about 1 μm on one side and about 2 μm on both sides at the longest time. However, since the carrier concentration Next continuously changes from the low reduction region 40b to the non-reduction region 40c, it is difficult to obtain the length Llow of only the low reduction region 40b.
因此，對求出低還原區域40b之長度Llow之方法進行說明。首先，將低還原區域40b之長度Llow定義如下。即，將低還原區域40b之長度Llow定義為自△區域之平均片電阻Rs約為300~500 kΩ/□之長度△L減去利用上述方法求出之高還原區域40a之長度Lhigh所得之值。如此定義之低還原區 域40b之長度Llow成為形成於通道層40兩側之2個低還原區域40b之長度Llow/2之和。 Therefore, a method of determining the length Llow of the low reduction region 40b will be described. First, the length Llow of the low reduction region 40b is defined as follows. That is, the length Llow of the low reduction region 40b is defined as the value obtained by subtracting the length Lhigh of the high reduction region 40a obtained by the above method from the length ΔL of the average sheet resistance Rs of the Δ region of about 300 to 500 kΩ/□. . Low reduction zone The length Llow of the domain 40b becomes the sum of the lengths Llow/2 of the two low reduction regions 40b formed on both sides of the channel layer 40.
圖6係表示閘極電壓Vg與△區域之平均片電阻Rs之關係之圖。根據圖6，求出△區域之平均片電阻Rs成為300 kΩ/□之閘極電壓Vg為17 V。進而，根據圖5，求出閘極電壓Vg為17 V時之△區域之長度△L為3.4 μm。以同樣方式，根據圖6，求出平均片電阻Rs成為500 kΩ/□之閘極電壓Vg為12 V，且根據圖5，求出此時之△區域之長度△L為4.2 μm。 Fig. 6 is a graph showing the relationship between the gate voltage Vg and the average sheet resistance Rs of the Δ region. According to Fig. 6, the gate voltage Vg at which the average sheet resistance Rs of the Δ region became 300 kΩ/□ was 17 V. Further, according to Fig. 5, the length ΔL of the Δ region when the gate voltage Vg is 17 V is found to be 3.4 μm. In the same manner, the gate voltage Vg of the average sheet resistance Rs of 500 kΩ/□ was found to be 12 V according to Fig. 6, and the length ΔL of the Δ region at this time was found to be 4.2 μm based on Fig. 5 .
另一方面，高還原區域40a之長度Lhigh已求出為2.2 μm。於該情形時，低還原區域40b之長度Llow根據其定義成為自平均片電阻Rs為300 kΩ/□時之△區域之長度△L即3.4 μm、及平均片電阻Rs為500 kΩ/□時之△區域之長度△L即4.2 μm分別減去高還原區域40a之長度Lhigh即2.2 μm所得之值。以此方式求出之低還原區域40b之長度Llow為1.2~2.0 μm。低還原區域40b係形成於源極電極60a側及汲極電極60b側，故各低還原區域40b之長度Llow/2為該高還原區域40a之一半即0.6~1.0 μm。 On the other hand, the length Lhigh of the high reduction region 40a has been found to be 2.2 μm. In this case, the length Llow of the low reduction region 40b is defined as the length ΔL of the Δ region when the average sheet resistance Rs is 300 kΩ/□, that is, 3.4 μm, and the average sheet resistance Rs is 500 kΩ/□. The length ΔL of the Δ region, that is, 4.2 μm, is obtained by subtracting the length Lhigh of the high reduction region 40a, that is, 2.2 μm. The length Llow of the low reduction region 40b obtained in this way is 1.2 to 2.0 μm. Since the low reduction region 40b is formed on the source electrode 60a side and the drain electrode 60b side, the length Llow/2 of each of the low reduction regions 40b is one half of the high reduction region 40a, that is, 0.6 to 1.0 μm.
由於熱處理溫度越高則自鈦層供給至氧化物半導體層之氫之量越多，又，越易於在氧化物半導體層內進行擴散，故高還原區域40a之長度Lhigh因製程條件、尤其因熱處理溫度而較大地變化。然而，已知低還原區域40b之長度Llow不易受製程條件影響，該長度Llow為1~2 μm，不取決於製程條件。 The higher the heat treatment temperature, the greater the amount of hydrogen supplied from the titanium layer to the oxide semiconductor layer, and the easier it is to diffuse in the oxide semiconductor layer, so the length Lhigh of the high reduction region 40a is due to process conditions, particularly heat treatment. The temperature changes greatly. However, it is known that the length Llow of the low reduction region 40b is not easily affected by the process conditions, and the length Llow is 1 to 2 μm, which does not depend on the process conditions.
<2.1 TFT之構成> <2.1 Structure of TFT>
圖7(a)係表示本發明第1實施形態之通道蝕刻結構之TFT100之構成之平面圖，圖7(b)係沿圖7(a)所示之切割線A-A之剖面圖。參照圖7(a)及圖7(b)，說明TFT100之構成。再者，TFT100之構成係與基礎研究中使用之TFT10之構成基本相同。 Fig. 7 (a) is a plan view showing a configuration of a TFT 100 of a channel etching structure according to a first embodiment of the present invention, and Fig. 7 (b) is a cross-sectional view taken along a cutting line A-A shown in Fig. 7 (a). The configuration of the TFT 100 will be described with reference to FIGS. 7(a) and 7(b). Further, the constitution of the TFT 100 is basically the same as that of the TFT 10 used in the basic research.
於玻璃基板等絕緣基板15上形成有閘極電極20。閘極電極20係包含例如鈦層上積層有銅層之積層金屬膜。再者，閘極電極20亦可包含自絕緣基板15側依序積層有鈦層、鋁(Al)層、鈦層之積層金屬膜。 A gate electrode 20 is formed on an insulating substrate 15 such as a glass substrate. The gate electrode 20 includes, for example, a laminated metal film in which a copper layer is laminated on a titanium layer. Further, the gate electrode 20 may include a laminated metal film in which a titanium layer, an aluminum (Al) layer, and a titanium layer are sequentially laminated from the side of the insulating substrate 15.
以覆蓋包含閘極電極20之絕緣基板15之整體之方式，形成有閘極絕緣膜30。閘極絕緣膜30係包含氮化矽膜35上積層有氧化矽膜36之積層絕緣膜。如此地於氮化矽膜35上積層氧化矽膜36之原因在於不易自作為下述通道層40之氧化物半導體層中奪取氧。於該情形時，氮化矽膜35之膜厚為300 nm，氧化矽膜36之膜厚為50 nm。因此，如基礎研究中所說明，換算為氧化矽膜之閘極絕緣膜30之膜厚為250 nm。再者，閘極絕緣膜30亦可為僅包含氧化矽膜之單層膜。例如，閘極絕緣膜30之膜厚亦可為積層絕緣膜之電容成為相同之250 nm、或者絕緣崩潰電壓與積層絕緣膜成為相同程度之350 nm。如此一來，閘極絕緣膜30之膜厚考量電晶體特性、可靠性及良率適當最佳化即可。 A gate insulating film 30 is formed to cover the entirety of the insulating substrate 15 including the gate electrode 20. The gate insulating film 30 includes a laminated insulating film in which a tantalum oxide film 36 is laminated on the tantalum nitride film 35. The reason why the tantalum oxide film 36 is laminated on the tantalum nitride film 35 in this manner is that it is not easy to extract oxygen from the oxide semiconductor layer which is the channel layer 40 described below. In this case, the film thickness of the tantalum nitride film 35 is 300 nm, and the film thickness of the tantalum oxide film 36 is 50 nm. Therefore, as described in the basic research, the gate insulating film 30 converted to the hafnium oxide film has a film thickness of 250 nm. Further, the gate insulating film 30 may be a single layer film including only a hafnium oxide film. For example, the thickness of the gate insulating film 30 may be such that the capacitance of the laminated insulating film becomes the same 250 nm, or the insulating breakdown voltage is 350 nm which is the same as that of the laminated insulating film. As a result, the film thickness of the gate insulating film 30 can be appropriately optimized in consideration of the transistor characteristics, reliability, and yield.
在與閘極電極20對向之閘極絕緣膜30上之位置，形成有島狀通道層40。通道層40係含有包含銦(In)、鎵(Ga)、鋅 (Zn)及氧(O)之IGZO層。於通道層40之兩側分別形成高還原區域40a，且於高還原區域40a之內側分別形成低還原區域40b，由2個低還原區域40b夾持之區域作為非還原區域40c殘留。 An island-shaped channel layer 40 is formed at a position on the gate insulating film 30 opposed to the gate electrode 20. The channel layer 40 contains indium (In), gallium (Ga), and zinc. IGZO layer of (Zn) and oxygen (O). A high reduction region 40a is formed on both sides of the channel layer 40, and a low reduction region 40b is formed inside the high reduction region 40a, and a region sandwiched by the two low reduction regions 40b remains as the non-reduction region 40c.
IGZO層之膜厚較佳為30~50 nm左右。此情況取決於以下原因。若IGZO層之膜厚小於30 μm，則TFT100之TFT特性變得不穩定，又，產生溫度應力及閘極電壓應力導致之閾值電壓之偏移。另一方面，若膜厚變得厚於50 nm，則閘極電壓Vg之控制性變差，漏電流(尤其閘極電壓Vg為0 V時之漏電流)增大。 The film thickness of the IGZO layer is preferably about 30 to 50 nm. This situation depends on the following reasons. When the film thickness of the IGZO layer is less than 30 μm, the TFT characteristics of the TFT 100 become unstable, and the threshold voltages due to temperature stress and gate voltage stress are generated. On the other hand, when the film thickness is thicker than 50 nm, the controllability of the gate voltage Vg is deteriorated, and the leak current (especially, the leakage current when the gate voltage Vg is 0 V) is increased.
本實施形態中使用之IGZO層之組成比示於下式(3)中。 The composition ratio of the IGZO layer used in the present embodiment is shown in the following formula (3).
銦：鎵：鋅=1：1：1 (3) Indium: Gallium: Zinc = 1:1:1 (3)
然而，IGZO層之組成比亦可為其他組成比。又，本實施形態中使用之IGZO層最佳為非晶膜，但亦可為微晶膜或多晶膜等結晶性膜。於微晶膜之情形時，TFT100之接通電阻變小，接通電流增加。 However, the composition ratio of the IGZO layer may also be other composition ratios. Further, the IGZO layer used in the present embodiment is preferably an amorphous film, but may be a crystalline film such as a microcrystalline film or a polycrystalline film. In the case of the microcrystalline film, the on-resistance of the TFT 100 becomes small, and the on-current increases.
再者，可用作TFT100之通道層40之氧化物半導體膜並不限定於IGZO膜，亦可為In-Zn-O系、In-Zn-Sn-O系或In-Zn-Si-O系等。具體而言，亦可為IZO膜、ITO膜、ZnO膜、SnO膜、WO膜、IO膜等。 Further, the oxide semiconductor film which can be used as the channel layer 40 of the TFT 100 is not limited to the IGZO film, and may be an In-Zn-O system, an In-Zn-Sn-O system or an In-Zn-Si-O system. Wait. Specifically, it may be an IZO film, an ITO film, a ZnO film, a SnO film, a WO film, an IO film, or the like.
於通道層40之上表面形成有隔開特定距離左右分離之源極電極60a及汲極電極60b。源極電極60a係以自通道層40之左上表面延伸至左側之閘極絕緣膜30上為止之方式形成。汲極電極60b係以自通道層40之右上表面延伸至右側 之閘極絕緣膜30上為止之方式形成。源極電極60a及汲極電極60b之端部係以分別位於2個高還原區域40a上之方式形成。 A source electrode 60a and a drain electrode 60b separated from each other by a predetermined distance are formed on the upper surface of the channel layer 40. The source electrode 60a is formed so as to extend from the upper left surface of the channel layer 40 to the left gate insulating film 30. The drain electrode 60b extends from the upper right surface to the right side of the channel layer 40 The gate insulating film 30 is formed on the upper side. The end portions of the source electrode 60a and the drain electrode 60b are formed so as to be located on the two high reduction regions 40a, respectively.
源極電極60a及汲極電極60b係包含例如於膜厚為100 nm之鈦層65上積層有膜厚為300~1000 nm之銅層66之積層金屬膜。如此地藉由積層金屬膜而構成源極電極60a及汲極電極60b之原因在於，鈦層65之電阻值較高，故藉由積層電阻值較低之銅層66而降低源極電極60a及汲極電極60b之電阻值。 The source electrode 60a and the drain electrode 60b include, for example, a laminated metal film in which a copper layer 66 having a film thickness of 300 to 1000 nm is laminated on a titanium layer 65 having a film thickness of 100 nm. The reason why the source electrode 60a and the drain electrode 60b are formed by laminating the metal film is that the resistance value of the titanium layer 65 is high, so that the source electrode 60a is lowered by the copper layer 66 having a low build-up resistance value. The resistance value of the drain electrode 60b.
又，在與IGZO層相接之源極電極60a及汲極電極60b之表面設置鈦層65係取決於以下之原因。即，該原因在於：鈦層65藉由將形成下述鈍化膜70時所吸存之氫於熱處理時供給至IGZO層而還原IGZO層之能力較高。又，為減小鈦層65與IGZO層之接觸電阻，而必需減小源極電極60a及汲極電極60b之下部之IGZO層之電阻。具體而言，為避免對TFT特性造成影響，而必需將與源極電極60a及汲極電極60b相接之IGZO層之平均片電阻Rs設為10 kΩ/□以下，且與該平均片電阻Rs對應之載子濃度約為1×1019 cm-3以上。因此，為還原IGZO層，使該載子濃度設成為約1×1019 cm-3以上，與IGZO層相接之金屬層必需由可吸存濃度大於其1位數左右之氫、具體而言為1×1020 cm-3以上之氫之材料形成。作為可如此地吸存大量氫之材料除了鈦以外，尚有鉬(Mo)、鈦合金或鉬合金等。 Further, the provision of the titanium layer 65 on the surface of the source electrode 60a and the drain electrode 60b which are in contact with the IGZO layer depends on the following reasons. That is, the reason is that the titanium layer 65 has a high ability to reduce the IGZO layer by supplying hydrogen occluded when the passivation film 70 described below is supplied to the IGZO layer during heat treatment. Further, in order to reduce the contact resistance between the titanium layer 65 and the IGZO layer, it is necessary to reduce the resistance of the IGZO layer under the source electrode 60a and the drain electrode 60b. Specifically, in order to avoid affecting the TFT characteristics, it is necessary to set the average sheet resistance Rs of the IGZO layer that is in contact with the source electrode 60a and the drain electrode 60b to 10 kΩ/□ or less, and to the average sheet resistance Rs. The corresponding carrier concentration is approximately 1 × 10 19 cm -3 or more. Therefore, in order to reduce the IGZO layer, the carrier concentration is set to be about 1×10 19 cm −3 or more, and the metal layer that is in contact with the IGZO layer must have a hydrogen concentration greater than about 1 digit thereof, specifically, hydrogen. It is formed of a material of hydrogen of 1 × 10 20 cm -3 or more. As a material which can store a large amount of hydrogen as such, in addition to titanium, there are molybdenum (Mo), a titanium alloy, a molybdenum alloy, and the like.
再者，源極電極60a及汲極電極60b之積層於鈦層上之金 屬層之材料除了銅以外，亦可為鋁、鎢(W)、鉭(Ta)等金屬、以其等為主成分之合金、或將其等適當組合而成之積層金屬。又，源極電極60a及汲極電極60b亦可由鈦、鉬、銅、鋁、鎢、鉭等金屬、及以其等為主成分之合金中之任一者形成。 Furthermore, the gold of the source electrode 60a and the drain electrode 60b is laminated on the titanium layer. The material of the genus layer may be a metal such as aluminum, tungsten (W) or tantalum (Ta), an alloy containing the same as the main component, or a laminated metal obtained by appropriately combining the materials. Further, the source electrode 60a and the drain electrode 60b may be formed of any one of a metal such as titanium, molybdenum, copper, aluminum, tungsten or tantalum, or an alloy containing the same as a main component.
源極電極60a及汲極電極60b係以俯視圖中與閘極電極20局部重疊之方式配置。因此，於對閘極電極20施加特定之電壓時，藉由來自閘極電極20之電場，而於通道層40之各高還原區域40a載子受到感應，形成高濃度載子層。藉由形成高濃度載子層，而將源極電極60a及汲極電極60b分別與2個高還原區域40a歐姆連接。 The source electrode 60a and the drain electrode 60b are disposed so as to partially overlap the gate electrode 20 in plan view. Therefore, when a specific voltage is applied to the gate electrode 20, the carrier of each of the high-reduction regions 40a of the channel layer 40 is induced by the electric field from the gate electrode 20 to form a high-concentration carrier layer. The source electrode 60a and the drain electrode 60b are ohmically connected to the two high reduction regions 40a, respectively, by forming a high concentration carrier layer.
以覆蓋包含源極電極60a及汲極電極60b之絕緣基板15之整體之方式，形成有鈍化膜70。鈍化膜70係包含膜厚為300 nm之氧化矽膜。於鈍化膜70上分別開設有到達源極電極60a及汲極電極60b之表面之接觸孔71a、71b。源極電極60a及汲極電極60b係經由接觸孔71a、71b而分別與形成於鈍化膜70上之外部配線80a、80b電性連接。 A passivation film 70 is formed to cover the entirety of the insulating substrate 15 including the source electrode 60a and the drain electrode 60b. The passivation film 70 is a ruthenium oxide film having a film thickness of 300 nm. Contact holes 71a and 71b that reach the surfaces of the source electrode 60a and the drain electrode 60b are respectively formed on the passivation film 70. The source electrode 60a and the drain electrode 60b are electrically connected to the external wirings 80a and 80b formed on the passivation film 70 via the contact holes 71a and 71b, respectively.
<2.2 TFT特性> <2.2 TFT characteristics>
對在TFT100中閘極電壓-汲極電流特性(以下稱為「TFT特性」)因通道長度Lch(源極/汲極電極間距離Lsd)不同而如何變化進行研究。圖8(a)係表示通道長度Lch為3 μm時之TFT特性之圖，圖8(b)係具有圖8(a)所示之TFT特性之TFT之剖面圖。圖9(a)係表示通道長度Lch為6 μm時之TFT特性之圖，圖9(b)係具有圖9(a)所示之TFT特性之TFT之剖 面圖。圖10(a)係表示通道長度Lch為16 μm時之TFT特性之圖，圖10(b)係具有圖10(a)所示之TFT特性之TFT之剖面圖。 The gate voltage-thin current characteristic (hereinafter referred to as "TFT characteristic") in the TFT 100 is changed depending on the channel length Lch (source/drain electrode distance Lsd). Fig. 8(a) is a view showing the characteristics of the TFT when the channel length Lch is 3 μm, and Fig. 8(b) is a cross-sectional view of the TFT having the TFT characteristics shown in Fig. 8(a). Fig. 9(a) is a view showing the characteristics of the TFT when the channel length Lch is 6 μm, and Fig. 9(b) is a view showing the TFT having the TFT characteristics shown in Fig. 9(a). Surface map. Fig. 10(a) is a view showing the characteristics of the TFT when the channel length Lch is 16 μm, and Fig. 10(b) is a cross-sectional view of the TFT having the TFT characteristics shown in Fig. 10(a).
再者，於任一情形時，根據基礎研究結果，TFT100之高還原區域40a之長度Lhigh約為2 μm，低還原區域40b之長度Llow為1~2 μm。又，汲極電流Id之測定係首先施加0.1 V之汲極電壓Vd而進行，繼而，施加10 V之汲極電壓Vd而進行。 Further, in either case, according to the results of the basic research, the length Lhigh of the high reduction region 40a of the TFT 100 is about 2 μm, and the length Llow of the low reduction region 40b is 1 to 2 μm. Further, the measurement of the drain current Id is performed by first applying a drain voltage Vd of 0.1 V, and then applying a drain voltage Vd of 10 V.
首先，參照圖8(a)，說明通道長度Lch為3 μm時之TFT特性。如圖8(a)所示，TFT100呈現即便閘極電壓Vg為0 V時電流亦流入通道區域內之空乏型特性。又，高還原區域40a之長度Lhigh為2 μm，低還原區域40b之長度Llow為1~2 μm。根據該等情況可知，如圖8(b)所示，於通道長度Lch為3 μm之氧化物半導體層上僅形成有高還原區域40a及低還原區域40b，而未形成非還原區域。因此，為使TFT100不呈現空乏型特性，非還原區域之形成必不可少。 First, referring to Fig. 8(a), the TFT characteristics when the channel length Lch is 3 μm will be described. As shown in Fig. 8(a), the TFT 100 exhibits a depletion characteristic in which a current flows into the channel region even when the gate voltage Vg is 0 V. Further, the length Lhigh of the high reduction region 40a is 2 μm, and the length Llow of the low reduction region 40b is 1 to 2 μm. As can be seen from the above, as shown in FIG. 8(b), only the high reduction region 40a and the low reduction region 40b are formed on the oxide semiconductor layer having the channel length Lch of 3 μm, and the non-reduction region is not formed. Therefore, in order for the TFT 100 not to exhibit depletion characteristics, the formation of a non-reduction region is indispensable.
繼而，參照圖9(a)及圖9(b)，說明通道長度Lch為6 μm時之TFT特性。於該情形時，電通道長度Leff根據式(1)為6 μm-約2 μm=約4 μm。又，於閘極絕緣膜30內之電場強度為1 MV/cm時，電通道長度Leff由下式(4)表示。 Next, the TFT characteristics when the channel length Lch is 6 μm will be described with reference to Figs. 9(a) and 9(b). In this case, the electric path length Leff is from 6 μm to about 2 μm to about 4 μm according to the formula (1). Further, when the electric field intensity in the gate insulating film 30 is 1 MV/cm, the electric path length Leff is expressed by the following formula (4).
Leff=Llow+Lnon (4) Leff=Llow+Lnon (4)
因此，根據式(4)，非還原區域40c之長度Lnon約為4 μm-(1~2 μm)=2~3 μm。如圖9(b)所示，於通道長度Lch為6 μm之TFT100之氧化物半導體層上形成有高還原區域40a、低 還原區域40b及非還原區域40c，並且非還原區域40c之長度Lnon為2~3 μm即合適之長度。於該情形時，如圖9(a)所示，TFT呈現出次閾值特性急遽上升，閾值電壓較低之良好特性。 Therefore, according to the formula (4), the length Lnon of the non-reducing region 40c is about 4 μm - (1 to 2 μm) = 2 to 3 μm. As shown in FIG. 9(b), a high reduction region 40a is formed on the oxide semiconductor layer of the TFT 100 having a channel length Lch of 6 μm, which is low. The reduction region 40b and the non-reduction region 40c, and the length Lnon of the non-reduction region 40c is 2 to 3 μm, that is, a suitable length. In this case, as shown in FIG. 9(a), the TFT exhibits a good characteristic that the subthreshold characteristic is rapidly increased and the threshold voltage is low.
繼而，參照圖10(a)及圖10(b)，說明通道長度Lch為16 μm時之TFT特性。該情形時之電通道長度Leff根據式(1)為16 μm-約2 μm=約14 μm。因此，若以與通道長度Lch為6 μm之情形相同之方式，藉由式(4)自電通道長度Leff求出非還原區域40c之長度Lnon，則該長度Lnon約為14 μm-(1~2 μm)=12~13 μm。如此般，亦於通道長度Lch為16 μm之TFT100之氧化物半導體層中，形成高還原區域40a、低還原區域40b及非還原區域40c，但非還原區域40c之長度Llow極長為12~13 μm。 Next, the TFT characteristics when the channel length Lch is 16 μm will be described with reference to Figs. 10(a) and 10(b). The electric passage length Leff in this case is from 16 μm to about 2 μm to about 14 μm according to the formula (1). Therefore, if the length Lnon of the non-reduction region 40c is obtained from the electric path length Leff by the equation (4) in the same manner as the case where the channel length Lch is 6 μm, the length Lnon is about 14 μm-(1~ 2 μm) = 12~13 μm. In this manner, also in the oxide semiconductor layer of the TFT 100 having a channel length Lch of 16 μm, the high reduction region 40a, the low reduction region 40b, and the non-reduction region 40c are formed, but the length Llow of the non-reduction region 40c is extremely long 12 to 13 Mm.
如圖10(a)所示，因汲極電壓Vd之不同，汲極電流Id上升之閘極電壓Vg之值較大地偏移。考慮其原因在於，於施加0.1 V作為及極電壓Vd，對閘極電壓Vg掃描至-15 V~+35 V為止時，於通道層40與閘極絕緣膜30之界面捕獲電子，因此，閾值電壓偏移至正側。若非還原區域40c之長度Lnon如此地變長，則會產生閘極電壓應力導致之閾值電壓之偏移之類的問題。 As shown in FIG. 10(a), the value of the gate voltage Vg at which the drain current Id rises largely shifts due to the difference in the drain voltage Vd. The reason for this is that when 0.1 V is applied as the gate voltage Vd and the gate voltage Vg is swept to -15 V to +35 V, electrons are trapped at the interface between the channel layer 40 and the gate insulating film 30, and therefore, the threshold The voltage is offset to the positive side. If the length Lnon of the non-reduction region 40c becomes so long, a problem such as a shift in the threshold voltage due to the gate voltage stress occurs.
根據上述說明可知，TFT100之最佳通道長度Lch之範圍為包含6 μm之範圍，但最佳範圍之上限及下限並不明確。因此，對藉由使用通道長度Lch不同之複數個TFT100，測定汲極電流Id之通道長度依存性及閾值電壓之偏移量△Vth 之通道長度依存性來求出最佳通道長度Lch之範圍的方法進行說明。圖11係表示通道長度Leh與汲極電流Id之關係之圖，圖12係表示通道長度Lch與閾值電壓之偏移量△Vth之關係之圖。再者，圖11及圖12係表示使用如下TFT100進行測定所得之結果之圖，該TFT100係於350℃下進行熱處理，且將閾值電壓設為5 V，以於與作為通道層40之氧化物半導體層相接之源極電極60a及汲極電極60b之表面形成鉬層，將氧化物半導體層還原。 As can be seen from the above description, the range of the optimum channel length Lch of the TFT 100 is in the range of 6 μm, but the upper and lower limits of the optimum range are not clear. Therefore, by using a plurality of TFTs 100 having different channel lengths Lch, the channel length dependency of the drain current Id and the offset of the threshold voltage ΔVth are measured. A method of determining the range of the optimum channel length Lch by the channel length dependency will be described. Fig. 11 is a view showing the relationship between the channel length Leh and the drain current Id, and Fig. 12 is a view showing the relationship between the channel length Lch and the threshold voltage shift amount ΔVth. Further, Fig. 11 and Fig. 12 are views showing the results of measurement by using the TFT 100 which is heat-treated at 350 ° C and has a threshold voltage of 5 V to form an oxide as the channel layer 40. A surface of the source electrode 60a and the drain electrode 60b where the semiconductor layers are in contact with each other forms a molybdenum layer to reduce the oxide semiconductor layer.
若通道長度Lch縮短，則通道區域僅成為高還原區域40a及低還原區域40b，而不形成非還原區域40c。因此，閾值電壓變低，閘極電壓Vg為0 V時之汲極電流Id(漏電流)增大。若使用漏電流增大之TFT100構成電路，則存在電路之消耗電流增大，又，易於產生誤動作之類的問題。因此，於通道寬度為20 μm之TFT100中，為使漏電流成為100 pA以下，根據圖11可知，必需使通道長度Lch為至少4 μm以上，更佳為5 μm以上。 If the channel length Lch is shortened, the channel region becomes only the high reduction region 40a and the low reduction region 40b, and the non-reduction region 40c is not formed. Therefore, the threshold voltage becomes low, and the drain current Id (leakage current) when the gate voltage Vg is 0 V increases. When the TFT 100 having a large leakage current is used to constitute a circuit, there is a problem that the current consumption of the circuit increases and the malfunction is liable to occur. Therefore, in the TFT 100 having a channel width of 20 μm, in order to make the leakage current 100 pA or less, it is necessary to make the channel length Lch at least 4 μm or more, and more preferably 5 μm or more, as shown in Fig. 11 .
又，圖12係對閘極電壓-汲極電流特性進行2次測定，且將第1次與第2次之閾值電壓之差(偏移量△Vth)相對通道長度繪製成曲線之圖。於圖12中表示偏移量△Vth越大則特性越易於變動且可靠性低之TFT。因此，為使閾值電壓為5 V時之偏移量△Vth成為±1 V以下，根據圖12可知，必需使通道長度Lch處於至少4~8 μm之範圍，更佳為5~7 μm之範圍。 Further, Fig. 12 is a graph in which the gate voltage-thin current characteristic is measured twice, and the difference between the first and second threshold voltages (offset amount ΔVth) is plotted against the channel length. FIG. 12 shows a TFT in which the characteristics are more likely to fluctuate and the reliability is lower as the shift amount ΔVth is larger. Therefore, in order to make the shift amount ΔVth when the threshold voltage is 5 V is ±1 V or less, it can be understood from Fig. 12 that the channel length Lch is in the range of at least 4 to 8 μm, more preferably in the range of 5 to 7 μm. .
如上所述，TFT100之高還原區域40a之長度Lhigh為2 μm。此時之電通道長度Leff、即低還原區域40b之長度Llow與非還原區域40c之長度Lnon之和根據其定義成為將通道長度Lch減去高還原區域40a之長度Lhigh所得之值。因此，電通道長度Leff之較佳範圍為2~6 μm，進而更佳之範圍為3~5 μm。 As described above, the length Lhigh of the high reduction region 40a of the TFT 100 is 2 Mm. The sum of the electric passage length Leff at this time, that is, the length Llow of the low reduction region 40b and the length Lnon of the non-reduction region 40c is a value obtained by subtracting the length Lhigh of the high reduction region 40a from the channel length Lch. Therefore, the preferred range of the electrical channel length Leff is 2 to 6 μm, and more preferably 3 to 5 μm.
<2.3 TFT之製造方法> <2.3 Manufacturing method of TFT>
圖13(a)~圖13(c)及圖14(a)~圖14(c)係表示圖7(a)及圖7(b)所示之TFT100之各製造步驟之步驟剖面圖。 13(a) to 13(c) and Figs. 14(a) to 14(c) are cross-sectional views showing the steps of the manufacturing steps of the TFT 100 shown in Figs. 7(a) and 7(b).
如圖13(a)所示，例如使用濺鍍法於絕緣基板15上連續地形成鈦膜(未圖示)及銅膜(未圖示)。繼而，使用光微影法於銅膜表面上形成光阻圖案(未圖示)。將該光阻圖案作為光罩，且藉由濕式蝕刻法而依序蝕刻銅膜、鈦膜，形成閘極電極20。其後，將光阻圖案剝離。藉此，形成鈦層上積層有銅層之閘極電極20。 As shown in FIG. 13(a), a titanium film (not shown) and a copper film (not shown) are continuously formed on the insulating substrate 15 by sputtering, for example. Then, a photoresist pattern (not shown) is formed on the surface of the copper film by photolithography. The photoresist pattern is used as a photomask, and a copper film or a titanium film is sequentially etched by a wet etching method to form a gate electrode 20. Thereafter, the photoresist pattern is peeled off. Thereby, the gate electrode 20 in which the copper layer is laminated on the titanium layer is formed.
如圖13(b)所示，以覆蓋包含閘極電極20之絕緣基板15之整體之方式，使用電漿CVD法，連續地形成膜厚為300 nm之氮化矽膜35及膜厚為50 nm之氧化矽膜36，從而形成閘極絕緣膜30。 As shown in FIG. 13(b), a tantalum nitride film 35 having a film thickness of 300 nm and a film thickness of 50 are continuously formed by a plasma CVD method so as to cover the entirety of the insulating substrate 15 including the gate electrode 20. The yttrium oxide film 36 of nm is formed to form the gate insulating film 30.
如圖13(c)所示，於閘極絕緣膜30之表面，使用濺鍍法，形成包含銦、鎵、鋅及氧之IGZO膜(未圖示)。IGZO膜係使用將氧化銦(In2O3)、氧化鎵(Ga2O3)及氧化鋅(ZnO)分別以等莫耳混合地燒結而成之靶材，藉由直流(Direct Current，DC)濺鍍法而成膜。IGZO膜之膜厚為30~50 nm。 As shown in FIG. 13(c), an IGZO film (not shown) containing indium, gallium, zinc, and oxygen is formed on the surface of the gate insulating film 30 by sputtering. The IGZO film uses a target obtained by sintering indium oxide (In 2 O 3 ), gallium oxide (Ga 2 O 3 ), and zinc oxide (ZnO) in a molar mixture, respectively, by direct current (DC). ) Sputtering to form a film. The film thickness of the IGZO film is 30 to 50 nm.
繼而，於IGZO膜之表面上形成光阻圖案48。將光阻圖 案48作為光罩，藉由乾式蝕刻法蝕刻IGZO膜，並將光阻圖案48剝離。藉此，在與閘極電極20對向之閘極絕緣膜30上之位置，形成作為島狀通道層40之IGZO層。 Then, a photoresist pattern 48 is formed on the surface of the IGZO film. Photoresist As a mask, the IGZO film was etched by dry etching, and the photoresist pattern 48 was peeled off. Thereby, an IGZO layer as the island-shaped channel layer 40 is formed at a position on the gate insulating film 30 opposed to the gate electrode 20.
繼而，剝離光阻圖案48，於大氣環境中將溫度設為350℃，進行1小時之熱處理。藉由進行熱處理，閘極絕緣膜30之膜質提昇，從而可抑制溫度應力及閘極電壓應力導致之閾值電壓之偏移量△Vth。又，由於閘極絕緣膜30與通道層40之界面之缺陷減少，故可改善TFT100之上升特性。於以此方式，在形成源極電極60a及汲極電極60b之前進行熱處理之情形時，無需考慮鈦層65對IGZO層之還原，故可進行僅以改善TFT特性為目的之高溫熱處理。 Then, the photoresist pattern 48 was peeled off, and the temperature was set to 350 ° C in an air atmosphere, and heat treatment was performed for 1 hour. By performing the heat treatment, the film quality of the gate insulating film 30 is increased, so that the threshold voltage ΔVth due to the temperature stress and the gate voltage stress can be suppressed. Further, since the defects at the interface between the gate insulating film 30 and the channel layer 40 are reduced, the rising characteristics of the TFT 100 can be improved. In this manner, in the case where the heat treatment is performed before the source electrode 60a and the drain electrode 60b are formed, it is not necessary to consider the reduction of the IGZO layer by the titanium layer 65, so that high-temperature heat treatment for the purpose of improving the TFT characteristics can be performed.
如圖14(a)所示，使用濺鍍法，形成源極金屬膜61。源極金屬膜61係由在膜厚為30~100 nm之鈦膜62上積層膜厚為300~1000 nm之銅膜63之積層金屬膜所構成。此時，鈦膜62之膜厚及濺鍍時之功率係與下述熱處理一併對高還原區域40a及低還原區域40b之長度Lhigh、Llow造成較大影響。因此，本實施形態係將鈦膜62之膜厚設為30~70 nm，且將濺鍍時之功率設為7 kW。繼而，使用光微影法，於源極金屬膜61上，形成於閘極電極20之上方具有開口部之光阻圖案68。此處，將濺鍍時之功率設為7 kW係基於以下原因。濺鍍時之功率係依存於濺鍍裝置之大小、即玻璃基板等絕緣基板15之尺寸。於本實施形態中，使用之絕緣基板15之尺寸為320×400 mm，故最佳功率為2~7 kW。 As shown in FIG. 14(a), the source metal film 61 is formed by a sputtering method. The source metal film 61 is composed of a laminated metal film of a copper film 63 having a film thickness of 300 to 1000 nm laminated on a titanium film 62 having a film thickness of 30 to 100 nm. At this time, the film thickness of the titanium film 62 and the power at the time of sputtering are largely affected by the heat treatment described below and the lengths Lhigh and Llow of the high reduction region 40a and the low reduction region 40b. Therefore, in the present embodiment, the film thickness of the titanium film 62 is set to 30 to 70 nm, and the power at the time of sputtering is set to 7 kW. Then, a photoresist pattern 68 having an opening above the gate electrode 20 is formed on the source metal film 61 by photolithography. Here, setting the power at the time of sputtering to 7 kW is based on the following reasons. The power at the time of sputtering depends on the size of the sputtering apparatus, that is, the size of the insulating substrate 15 such as a glass substrate. In the present embodiment, the size of the insulating substrate 15 used is 320 × 400 mm, so the optimum power is 2 to 7 kW.
如圖14(b)所示，將光阻圖案68作為光罩，藉由濕式蝕 刻法而依序蝕刻源極金屬膜61之銅膜63及鈦膜62，形成積層有鈦層65及銅層66之源極電極60a及汲極電極60b。藉此，源極電極60a自通道層40之左上表面延伸至左側之閘極絕緣膜30上為止。汲極電極60b自通道層40之右上表面延伸至右側之閘極絕緣膜30上為止。再者，於通道層40上未形成蝕刻終止層。然而，由於藉由濕式蝕刻法蝕刻源極金屬膜61，故於形成源極電極60a及汲極電極60b時，通道層40之膜幾乎不減少。 As shown in FIG. 14(b), the photoresist pattern 68 is used as a mask by wet etching. The copper film 63 and the titanium film 62 of the source metal film 61 are sequentially etched to form a source electrode 60a and a drain electrode 60b in which the titanium layer 65 and the copper layer 66 are laminated. Thereby, the source electrode 60a extends from the upper left surface of the channel layer 40 to the left gate insulating film 30. The drain electrode 60b extends from the upper right surface of the channel layer 40 to the right gate insulating film 30. Furthermore, an etch stop layer is not formed on the channel layer 40. However, since the source metal film 61 is etched by the wet etching method, the film of the channel layer 40 hardly decreases when the source electrode 60a and the drain electrode 60b are formed.
以覆蓋包含源極電極60a及汲極電極60b之絕緣基板15之整體之方式，使用電漿CVD法，生成將矽烷氣體及一氧化二氮(N2O)氣體或TEOS氣體等作為原料氣體之電漿，從而形成作為鈍化膜70之氧化矽膜。再者，鈍化膜70係與通道層40相接，故鈍化膜70較佳為難以還原作為通道層40之IGZO層的氧化矽膜。於鈍化膜70之成膜時，電漿中所含之氫被吸存於構成源極電極60a及汲極電極60b之鈦層65中。 A plasma CVD method is used to form a decane gas, a nitrous oxide (N 2 O) gas, or a TEOS gas as a material gas by covering the entirety of the insulating substrate 15 including the source electrode 60a and the drain electrode 60b. The plasma is formed to form a ruthenium oxide film as the passivation film 70. Further, since the passivation film 70 is in contact with the channel layer 40, it is preferable that the passivation film 70 is difficult to reduce the yttrium oxide film as the IGZO layer of the channel layer 40. At the time of film formation of the passivation film 70, hydrogen contained in the plasma is absorbed in the titanium layer 65 constituting the source electrode 60a and the drain electrode 60b.
使用乾式蝕刻法，於鈍化膜70上開設分別到達源極電極60a及汲極電極60b之表面之接觸孔71a、71b。繼而，於大氣環境中進行溫度為300℃且時間為2小時之熱處理。藉由熱處理，而將被吸存於源極電極60a及汲極電極60b之鈦層65中之氫供給至IGZO層，且於IGZO層內沿該IGZO層之長度方向擴散。藉此，於靠近源極電極60a及汲極電極60b之通道層40形成高還原區域40a，且於其等之內側分別形成低還原區域40b。於由2個低還原區域40b夾持之通道層40 之中央殘留非還原區域40c。如此般，藉由該熱處理，而決定高還原區域40a之長度Lhigh、低還原區域40b之長度Llow及非還原區域40c之長度Lnon。又，可藉由該熱處理，而使在蝕刻接觸孔71a、71b時於源極電極60a及汲極電極60b中產生之損壞恢復。再者，熱處理之溫度較佳為300~350℃。又，用於還原IGZO膜之氫亦可為自氫(H2)氣體中生成之氫電漿。於該情形時，源極電極60a及汲極電極60b可有效地吸存氫。又，熱處理只要在鈍化膜70之成膜後進行即可。 Contact holes 71a and 71b reaching the surfaces of the source electrode 60a and the drain electrode 60b are formed in the passivation film 70 by dry etching. Then, heat treatment was carried out in an atmospheric environment at a temperature of 300 ° C for 2 hours. Hydrogen absorbed in the titanium layer 65 of the source electrode 60a and the drain electrode 60b is supplied to the IGZO layer by heat treatment, and is diffused in the longitudinal direction of the IGZO layer in the IGZO layer. Thereby, the high-reduction region 40a is formed in the channel layer 40 close to the source electrode 60a and the gate electrode 60b, and the low-reduction region 40b is formed on the inner side of the source electrode 60a and the drain electrode 60b. The non-reduction region 40c remains in the center of the channel layer 40 sandwiched by the two low reduction regions 40b. In this manner, the length Lhigh of the high reduction region 40a, the length Llow of the low reduction region 40b, and the length Lnon of the non-reduction region 40c are determined by the heat treatment. Moreover, the damage generated in the source electrode 60a and the drain electrode 60b at the time of etching the contact holes 71a and 71b can be recovered by the heat treatment. Further, the temperature of the heat treatment is preferably from 300 to 350 °C. Further, the hydrogen used to reduce the IGZO film may be a hydrogen plasma generated from a hydrogen (H 2 ) gas. In this case, the source electrode 60a and the drain electrode 60b can effectively store hydrogen. Further, the heat treatment may be performed after the formation of the passivation film 70.
如圖14(c)所示，於包含接觸孔71a、71b之鈍化膜70上形成金屬膜(未圖示)，且將光阻圖案(未圖示)作為光罩，將金屬膜圖案化。藉此，形成分別經由接觸孔71a、71b而與源極電極60a及汲極電極60b電性連接之外部配線80a、80b。 As shown in FIG. 14(c), a metal film (not shown) is formed on the passivation film 70 including the contact holes 71a and 71b, and a photoresist pattern (not shown) is used as a mask to pattern the metal film. Thereby, external wirings 80a and 80b which are electrically connected to the source electrode 60a and the drain electrode 60b via the contact holes 71a and 71b, respectively, are formed.
再者，於上述說明中，熱處理係於源極金屬膜61之成膜前及接觸孔71a、71b形成後進行。然而，亦可省略將源極金屬膜61成膜前之熱處理，而於接觸孔71a、71b之形成後一併進行熱處理。當於接觸孔71a、71b之形成後進行熱處理之情形時，由於鈦層65對IGZO層之還原進行，故無法於高溫下進行長時間之熱處理。因此，無法充分提昇TFT特性。然而，由於可將熱處理次數減少1次，故可簡化TFT100之製造製程。 Further, in the above description, the heat treatment is performed before the formation of the source metal film 61 and after the formation of the contact holes 71a and 71b. However, the heat treatment before the formation of the source metal film 61 may be omitted, and the heat treatment may be performed after the formation of the contact holes 71a and 71b. When the heat treatment is performed after the formation of the contact holes 71a and 71b, since the reduction of the IGZO layer by the titanium layer 65 is performed, the heat treatment for a long period of time cannot be performed at a high temperature. Therefore, the TFT characteristics cannot be sufficiently improved. However, since the number of heat treatments can be reduced by one time, the manufacturing process of the TFT 100 can be simplified.
<2.4效果> <2.4 effect>
根據本實施形態，於施加使閘極絕緣膜30內之電場強度 成為1 MV/cm之閘極電壓Vg時，TFT100之電通道長度Leff成為低還原區域40b之長度Llow與非還原區域40c之長度Lnon之和。如此般，因於通道區域內包含低還原區域40b及非還原區域40c，故可獲得陷阱能階減小(TFT特性之測定時之閾值電壓之偏移量△Vth減小)且閘極電壓Vg為0 V時之漏電流減小等特性良好之TFT100。 According to this embodiment, the electric field strength in the gate insulating film 30 is applied. When the gate voltage Vg of 1 MV/cm is obtained, the electric path length Leff of the TFT 100 becomes the sum of the length Llow of the low reduction region 40b and the length Lnon of the non-reduction region 40c. In this way, since the low reduction region 40b and the non-reduction region 40c are included in the channel region, the trap level can be reduced (the threshold voltage ΔVth at the time of measurement of the TFT characteristic is decreased) and the gate voltage Vg is obtained. The TFT 100 has excellent characteristics such as a decrease in leakage current at 0 V.
又，源極電極60a及汲極電極60b之鈦層65可吸氫1×1020 cm-3以上。因此，使吸存於鈦層65中之氫供給至氧化物半導體層，且於氧化物半導體層內進行擴散。藉此，將氧化物半導體層還原，TFT100之電通道長度Leff變為最佳長度，故TFT特性變得良好。 Further, the titanium layer 65 of the source electrode 60a and the drain electrode 60b can absorb hydrogen by 1 × 10 20 cm -3 or more. Therefore, hydrogen absorbed in the titanium layer 65 is supplied to the oxide semiconductor layer, and diffusion is performed in the oxide semiconductor layer. Thereby, the oxide semiconductor layer is reduced, and the electric path length Leff of the TFT 100 becomes an optimum length, so that the TFT characteristics become good.
又，於形成覆蓋已吸氫之源極電極60a及汲極電極60b之鈍化膜70，進而在鈍化膜70上開設接觸孔71a、71b後，進行熱處理。藉此，自源極電極60a及汲極電極60b對氧化物半導體層供給氫，且使供給之氫於氧化物半導體層內沿其長度方向進行擴散。可以此方式，容易地進行電通道長度Leff之控制。又，由於源極電極60a及汲極電極60b之鈦層65係與氧化物半導體層相接，故可有效地還原氧化物半導體層。藉此，可製造具有更良好之特性之TFT100。 Further, a passivation film 70 covering the source electrode 60a and the drain electrode 60b having hydrogen absorption is formed, and further, contact holes 71a and 71b are formed in the passivation film 70, and then heat treatment is performed. Thereby, hydrogen is supplied to the oxide semiconductor layer from the source electrode 60a and the drain electrode 60b, and the supplied hydrogen is diffused in the longitudinal direction of the oxide semiconductor layer. In this way, the control of the electrical path length Leff can be easily performed. Further, since the titanium layer 65 of the source electrode 60a and the drain electrode 60b is in contact with the oxide semiconductor layer, the oxide semiconductor layer can be effectively reduced. Thereby, the TFT 100 having better characteristics can be manufactured.
<3.1 TFT之構成> <3.1 Structure of TFT>
圖15(a)係表示本發明第2實施形態之蝕刻終止結構之TFT200之構成之平面圖，圖15(b)係沿圖15(a)所示之TFT200之B-B線之剖面圖。 Fig. 15 (a) is a plan view showing a configuration of a TFT 200 of an etching termination structure according to a second embodiment of the present invention, and Fig. 15 (b) is a cross-sectional view taken along line B-B of the TFT 200 shown in Fig. 15 (a).
參照圖15(a)及圖15(b)，說明TFT200之構成。於玻璃基板等絕緣基板15上形成有閘極電極20。以覆蓋包含閘極電極20之絕緣基板15之整體之方式，形成有閘極絕緣膜30。再者，閘極電極20及閘極絕緣膜30之構成係與第1實施形態之TFT100相同，故標註相同參照符號，且省略該等之說明。 The configuration of the TFT 200 will be described with reference to Figs. 15(a) and 15(b). A gate electrode 20 is formed on an insulating substrate 15 such as a glass substrate. A gate insulating film 30 is formed to cover the entirety of the insulating substrate 15 including the gate electrode 20. The configuration of the gate electrode 20 and the gate insulating film 30 is the same as that of the TFT 100 of the first embodiment, and the same reference numerals will be given thereto, and the description thereof will be omitted.
在與閘極電極20對向之閘極絕緣膜30上之位置形成有島狀通道層40。通道層40係包含IGZO層。通道層40係包含形成於其兩側之高還原區域40a、分別形成於高還原區域40a之內側之低還原區域40b、及殘留於由2個低還原區域40b夾持之通道層40之中央之非還原區域40c。再者，由於IGZO層之膜厚、結晶性、組成比等與第1實施形態之TFT100相同，故省略該等之說明。 An island-shaped channel layer 40 is formed at a position on the gate insulating film 30 opposed to the gate electrode 20. The channel layer 40 includes an IGZO layer. The channel layer 40 includes a high reduction region 40a formed on both sides thereof, a low reduction region 40b formed on the inner side of the high reduction region 40a, and a center portion of the channel layer 40 sandwiched by the two low reduction regions 40b. Non-reducing area 40c. In addition, since the film thickness, crystallinity, composition ratio, and the like of the IGZO layer are the same as those of the TFT 100 of the first embodiment, the description thereof will be omitted.
與TFT100之情形不同，於通道層40及閘極絕緣膜30上形成有蝕刻終止層150。蝕刻終止層150具有如下功能：於藉由蝕刻而形成下述源極電極160a及汲極電極160b時，保護通道層40之表面不被蝕刻，並且降低配線之寄生電容。因此，較佳為，蝕刻終止層150之膜厚較厚，但若過厚則存在成膜時問變長，產量降低之類的問題。考慮到此情況，而將蝕刻終止層150之較佳膜厚設為100~500 nm。又，蝕刻終止層150係與IGZO層相接，故為了不易自IGZO層奪取氧而藉由氧化矽膜形成。再者，於圖15(a)中已省略蝕刻終止層150之圖示，但蝕刻終止層150覆蓋除接觸孔151a、151b以外之整面。 Unlike the case of the TFT 100, an etch stop layer 150 is formed on the channel layer 40 and the gate insulating film 30. The etch stop layer 150 has a function of preventing the surface of the protective via layer 40 from being etched and reducing the parasitic capacitance of the wiring when the source electrode 160a and the drain electrode 160b described below are formed by etching. Therefore, it is preferable that the thickness of the etching stopper layer 150 is thick, but if it is too thick, there is a problem that the film formation time becomes long and the yield is lowered. In view of this, the preferred film thickness of the etch stop layer 150 is set to 100 to 500 nm. Further, since the etch stop layer 150 is in contact with the IGZO layer, it is formed of a ruthenium oxide film in order to prevent oxygen from being trapped from the IGZO layer. Further, the illustration of the etch stop layer 150 has been omitted in FIG. 15(a), but the etch stop layer 150 covers the entire surface except the contact holes 151a, 151b.
於蝕刻終止層150上分別開設有到達通道層40之低還原區域40b之接觸孔151a、151b。如圖15(b)所示，形成有於蝕刻終止層150之上表面隔開特定距離左右分離之源極電極160a及汲極電極160b。源極電極160a係以自蝕刻終止層150之左上表面延伸至左側之閘極絕緣膜30上為止之方式形成，並且經由接觸孔151a而亦與通道層40之高還原區域40a電性連接。汲極電極160b係以自蝕刻終止層150之右上表面延伸至右側之閘極絕緣膜30上為止之方式形成，並且經由接觸孔151b而亦與通道層40之高還原區域40a電性連接。再者，源極電極160a及汲極電極160b之膜厚及材料係與TFT100之情形相同，故省略該等之說明。 Contact holes 151a, 151b reaching the low reduction region 40b of the channel layer 40 are respectively formed on the etch stop layer 150. As shown in FIG. 15(b), a source electrode 160a and a drain electrode 160b which are separated from each other by a predetermined distance on the upper surface of the etch stop layer 150 are formed. The source electrode 160a is formed so as to extend from the upper left surface of the etch stop layer 150 to the left gate insulating film 30, and is also electrically connected to the high reduction region 40a of the channel layer 40 via the contact hole 151a. The gate electrode 160b is formed so as to extend from the upper right surface of the etch stop layer 150 to the gate insulating film 30 on the right side, and is also electrically connected to the high reduction region 40a of the channel layer 40 via the contact hole 151b. The thicknesses and materials of the source electrode 160a and the drain electrode 160b are the same as those of the TFT 100, and the description thereof will be omitted.
以覆蓋包含源極電極160a及汲極電極160b之絕緣基板15之整體之方式形成有鈍化膜70。鈍化膜70係包含膜厚為300 nm之氧化矽膜。於鈍化膜70上分別開設有到達源極電極160a及汲極電極160b之表面之接觸孔71a、71b。源極電極160a及汲極電極160b係分別經由接觸孔71a、71b而與形成於鈍化膜70上之外部配線80a、80b電性連接。 A passivation film 70 is formed to cover the entirety of the insulating substrate 15 including the source electrode 160a and the drain electrode 160b. The passivation film 70 is a ruthenium oxide film having a film thickness of 300 nm. Contact holes 71a and 71b that reach the surfaces of the source electrode 160a and the drain electrode 160b are respectively formed on the passivation film 70. The source electrode 160a and the drain electrode 160b are electrically connected to the external wirings 80a and 80b formed on the passivation film 70 via the contact holes 71a and 71b, respectively.
於形成鈍化膜70時，TFT200之源極電極160a及汲極電極160b曝露於包含自作為原料氣體之矽烷氣體或TEOS氣體中生成之氫的電漿中。此時，源極電極160a及汲極電極160b吸存電漿中之氫。繼而，於在鈍化膜70上形成接觸孔151a、151b之後，在大氣環境中進行溫度為300℃且時間為2小時之熱處理。藉由該熱處理，而自源極電極160a及汲極電極160b之鈦層165對IGZO層供給氫，且使氫於IGZO 層內沿其長度方向進行擴散。藉此，於靠近源極電極160a及汲極電極160b之通道層40形成高還原區域40a，且於其等之內側分別形成低還原區域40b。於由2個低還原區域40b夾持之通道層40之中央殘留有非還原區域40c。藉由該熱處理，而決定高還原區域40a之長度Lhigh、低還原區域40b之長度Llow及非還原區域40c之長度Lnon。又，可藉由該熱處理，而使蝕刻接觸孔71a、71b時在源極電極160a及汲極電極160b中產生之損壞恢復。再者，熱處理之溫度較佳為300~350℃。又，用於還原IGZO膜之氫亦可為自氫氣生成之氫電漿。於該情形時，源極電極160a及汲極電極160b可有效地進行吸氫。又，熱處理若為鈍化膜70之成膜後，則可於任何時候進行。 When the passivation film 70 is formed, the source electrode 160a and the drain electrode 160b of the TFT 200 are exposed to a plasma containing hydrogen generated from a decane gas or a TEOS gas as a source gas. At this time, the source electrode 160a and the drain electrode 160b absorb hydrogen in the plasma. Then, after the contact holes 151a and 151b were formed on the passivation film 70, heat treatment was performed in an air atmosphere at a temperature of 300 ° C for 2 hours. By this heat treatment, hydrogen is supplied to the IGZO layer from the titanium layer 165 of the source electrode 160a and the drain electrode 160b, and hydrogen is made to IGZO. The layer spreads along its length. Thereby, the high reduction region 40a is formed in the channel layer 40 close to the source electrode 160a and the drain electrode 160b, and the low reduction region 40b is formed inside the other. A non-reducing region 40c remains in the center of the channel layer 40 sandwiched by the two low reduction regions 40b. By the heat treatment, the length Lhigh of the high reduction region 40a, the length Llow of the low reduction region 40b, and the length Lnon of the non-reduction region 40c are determined. Moreover, the damage generated in the source electrode 160a and the drain electrode 160b when the contact holes 71a and 71b are etched can be recovered by the heat treatment. Further, the temperature of the heat treatment is preferably from 300 to 350 °C. Further, the hydrogen used to reduce the IGZO film may also be a hydrogen plasma generated from hydrogen. In this case, the source electrode 160a and the drain electrode 160b can efficiently perform hydrogen absorption. Further, the heat treatment may be carried out at any time if it is formed by the passivation film 70.
又，亦於TFT200之情形時，可在形成通道層40之步驟至形成源極電極160a及汲極電極160b之步驟為止之任一步驟中，進行例如溫度為350℃且時間為1小時之熱處理，以提昇TFT特性。 Further, in the case of the TFT 200, heat treatment such as a temperature of 350 ° C and a time of 1 hour may be performed in any of the steps from the step of forming the channel layer 40 to the step of forming the source electrode 160 a and the drain electrode 160 b. To improve TFT characteristics.
<3.2效果> <3.2 effect>
根據本實施形態，與第1實施形態之TFT100之情形同樣地可獲得具有良好特性之TFT200。 According to the present embodiment, the TFT 200 having good characteristics can be obtained in the same manner as in the case of the TFT 100 of the first embodiment.
<4.1 TFT之構成> <4.1 Structure of TFT>
圖16(a)係表示本發明之第3實施形態之底端接觸結構之TFT300之構成之平面圖，圖16(b)係圖16(a)所示之TFT300之沿C-C線之剖面圖。 Fig. 16 (a) is a plan view showing the configuration of a TFT 300 of a bottom contact structure according to a third embodiment of the present invention, and Fig. 16 (b) is a cross-sectional view taken along line C-C of the TFT 300 shown in Fig. 16 (a).
參照圖16(a)及圖16(b)，說明TFT300之構成。於絕緣基板15上形成有閘極電極20。以覆蓋包含閘極電極20之絕緣基板15之整體之方式形成有閘極絕緣膜30。再者，閘極電極20及閘極絕緣膜30之構成係與第1實施形態之TFT100之情形相同，故標註相同參照符號，且省略該等之說明。 The configuration of the TFT 300 will be described with reference to Figs. 16(a) and 16(b). A gate electrode 20 is formed on the insulating substrate 15. A gate insulating film 30 is formed to cover the entirety of the insulating substrate 15 including the gate electrode 20. In addition, the configuration of the gate electrode 20 and the gate insulating film 30 is the same as that of the TFT 100 of the first embodiment, and the same reference numerals will be given thereto, and the description thereof will be omitted.
於閘極電極20之上方之閘極絕緣膜30上，形成有隔開特定距離左右分離之源極電極260a及汲極電極260b。源極電極260a及汲極電極260b係包含閘極絕緣膜30之表面上依序積層有鈦層265、銅層266、鈦層267之積層金屬膜。 On the gate insulating film 30 above the gate electrode 20, a source electrode 260a and a drain electrode 260b which are separated by a predetermined distance are formed. The source electrode 260a and the drain electrode 260b are a laminated metal film in which a titanium layer 265, a copper layer 266, and a titanium layer 267 are sequentially laminated on the surface of the gate insulating film 30.
於由源極電極260a與汲極電極260b夾持之閘極絕緣膜30上，形成有包含IGZO層之通道層240。通道層240之一端係延伸至源極電極260a之上表面為止，而另一端延伸至汲極電極260b之上表面為止。與源極電極260a相接之通道層240之一端、及與汲極電極260b相接之通道層240之另一端均與鈦層265及鈦層267相接。因此，於通道層240之兩側，以分別覆蓋源極電極260a及汲極電極260b之方式形成有高還原區域240a。於高還原區域240a之內側分別形成低還原區域240b，且於由2個低還原區域240b夾持之通道層240之中央殘留非還原區域240c。再者，於TFT300中，由於IGZO層與鈦層265及鈦層267相接，故易於進行IGZO層之還原。然而，若至少形成鈦層265及鈦層267之任一者，則可進行IGZO層之還原，從而形成高還原區域240a、低還原區域240b及非還原區域240c。 A channel layer 240 including an IGZO layer is formed on the gate insulating film 30 sandwiched between the source electrode 260a and the drain electrode 260b. One end of the channel layer 240 extends to the upper surface of the source electrode 260a, and the other end extends to the upper surface of the drain electrode 260b. One end of the channel layer 240 that is in contact with the source electrode 260a and the other end of the channel layer 240 that is in contact with the drain electrode 260b are in contact with the titanium layer 265 and the titanium layer 267. Therefore, a high reduction region 240a is formed on both sides of the channel layer 240 so as to cover the source electrode 260a and the drain electrode 260b, respectively. The low reduction region 240b is formed inside the high reduction region 240a, and the non-reduction region 240c remains in the center of the channel layer 240 sandwiched by the two low reduction regions 240b. Further, in the TFT 300, since the IGZO layer is in contact with the titanium layer 265 and the titanium layer 267, the reduction of the IGZO layer is facilitated. However, if at least one of the titanium layer 265 and the titanium layer 267 is formed, the reduction of the IGZO layer can be performed to form the high reduction region 240a, the low reduction region 240b, and the non-reduction region 240c.
以覆蓋包含源極電極260a及汲極電極260b之絕緣基板15 之整體之方式形成有鈍化膜70。鈍化膜70係包含膜厚為300 nm之氧化矽膜。於鈍化膜70上分別開設有到達源極電極260a及汲極電極260b之表面之接觸孔71a、71b。源極電極260a及汲極電極260b係分別經由接觸孔71a、71b而與形成於鈍化膜70上之外部配線80a、80b電性連接。 To cover the insulating substrate 15 including the source electrode 260a and the drain electrode 260b The passivation film 70 is formed in a holistic manner. The passivation film 70 is a ruthenium oxide film having a film thickness of 300 nm. Contact holes 71a and 71b that reach the surfaces of the source electrode 260a and the drain electrode 260b are respectively formed on the passivation film 70. The source electrode 260a and the drain electrode 260b are electrically connected to the external wirings 80a and 80b formed on the passivation film 70 via the contact holes 71a and 71b, respectively.
於鈍化膜70之成膜時，TFT300之源極電極260a及汲極電極260b曝露於包含自作為原料氣體之矽烷氣體或TEOS氣體生成之氫的電漿中。此時，源極電極260a及汲極電極260b吸存電漿中之氫。繼而，當於鈍化膜70上形成接觸孔71a、71b之後，在大氣環境中進行溫度為300℃且時間為2小時之熱處理。藉由該熱處理，而自源極電極260a及汲極電極260b之鈦層265、267對IGZO層供給氫，且使氫於IGZO層內沿其長度方向進行擴散。藉此，於靠近源極電極260a及汲極電極260b之通道層240形成高還原區域240a，且於其等之內側分別形成低還原區域240b。由2個低還原區域240b夾持之通道層240之中央殘留非還原區域240c。藉由該熱處理，而決定高還原區域240a之長度Lhigh、低還原區域240b之長度Llow及非還原區域240c之長度Lnon。又，可藉由該熱處理，而使於蝕刻接觸孔71a、71b時在源極電極260a及汲極電極260b中產生之損壞恢復。再者，熱處理之溫度較佳為300~350℃。又，用於還原IGZO膜之氫亦可為自氫氣生成之氫電漿。於該情形時，源極電極260a及汲極電極260b可有效地進行吸氫。又，熱處理若為鈍化膜70之成膜後，則可於任何時候進 行。 When the passivation film 70 is formed, the source electrode 260a and the drain electrode 260b of the TFT 300 are exposed to a plasma containing hydrogen generated from a decane gas or a TEOS gas as a source gas. At this time, the source electrode 260a and the drain electrode 260b absorb hydrogen in the plasma. Then, after the contact holes 71a and 71b were formed on the passivation film 70, heat treatment was performed in an atmosphere at a temperature of 300 ° C for 2 hours. By this heat treatment, hydrogen is supplied to the IGZO layer from the titanium layers 265 and 267 of the source electrode 260a and the drain electrode 260b, and hydrogen is diffused in the IGZO layer along the longitudinal direction thereof. Thereby, the high reduction region 240a is formed in the channel layer 240 close to the source electrode 260a and the drain electrode 260b, and the low reduction region 240b is formed inside the other. The non-reduction region 240c remains in the center of the channel layer 240 sandwiched by the two low reduction regions 240b. By this heat treatment, the length Lhigh of the high reduction region 240a, the length Llow of the low reduction region 240b, and the length Lnon of the non-reduction region 240c are determined. Moreover, the damage generated in the source electrode 260a and the drain electrode 260b at the time of etching the contact holes 71a and 71b can be recovered by the heat treatment. Further, the temperature of the heat treatment is preferably from 300 to 350 °C. Further, the hydrogen used to reduce the IGZO film may also be a hydrogen plasma generated from hydrogen. In this case, the source electrode 260a and the drain electrode 260b can efficiently perform hydrogen absorption. Moreover, if the heat treatment is formed by the passivation film 70, it can be advanced at any time. Row.
又，亦於TFT300之情形時，可在形成通道層240之步驟至形成源極電極260a及汲極電極260b之步驟為止之任一步驟中進行例如溫度為350℃且時間為1小時之熱處理，以提昇TFT特性。 Further, in the case of the TFT 300, heat treatment such as a temperature of 350 ° C and a time of 1 hour may be performed in any step from the step of forming the channel layer 240 to the step of forming the source electrode 260a and the drain electrode 260b. To improve TFT characteristics.
<4.2效果> <4.2 effect>
根據本實施形態，與第1實施形態之TFT100之情形同樣地可獲得良好之TFT300。 According to the present embodiment, a good TFT 300 can be obtained in the same manner as in the case of the TFT 100 of the first embodiment.
<5.1 TFT之構成> <5.1 Structure of TFT>
圖17(a)係表示本發明第4實施形態之頂閘極結構之TFT400之構成之平面圖，圖17(b)係沿圖17(a)所示之切割線D-D之剖面圖。參照圖17(a)及圖17(b)，說明TFT400之構成。 Fig. 17 (a) is a plan view showing a configuration of a TFT 400 of a top gate structure according to a fourth embodiment of the present invention, and Fig. 17 (b) is a cross-sectional view taken along a cutting line D-D shown in Fig. 17 (a). The configuration of the TFT 400 will be described with reference to Figs. 17(a) and 17(b).
於玻璃基板等絕緣基板15上配置有島狀之通道層340。通道層340係含有包含銦(In)、鎵(Ga)、鋅(Zn)及氧(O)之IGZO層。於IGZO層之兩側分別形成高還原區域340a，且於高還原區域340a之內側分別形成低還原區域340b，並且由2個低還原區域340b夾持之區域係作為非還原區域340c殘留。再者，IGZO層之膜厚等係與TFT100之情形相同，故省略該等之說明。又，如圖17(b)所示，可將IGZO層直接形成於絕緣基板15上，但亦可形成於絕緣基板15上所形成之氮化矽膜或氧化矽膜上。又，亦可形成於在氮化矽膜上積層有氧化矽膜之積層絕緣膜上。 An island-shaped channel layer 340 is disposed on the insulating substrate 15 such as a glass substrate. The channel layer 340 contains an IGZO layer containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O). A high reduction region 340a is formed on both sides of the IGZO layer, and a low reduction region 340b is formed inside the high reduction region 340a, respectively, and a region sandwiched by the two low reduction regions 340b remains as the non-reduction region 340c. In addition, the film thickness of the IGZO layer is the same as that of the TFT 100, and the description thereof will be omitted. Further, as shown in FIG. 17(b), the IGZO layer may be formed directly on the insulating substrate 15, but may be formed on the tantalum nitride film or the hafnium oxide film formed on the insulating substrate 15. Further, it may be formed on a laminated insulating film in which a tantalum oxide film is laminated on a tantalum nitride film.
以覆蓋包含通道層340之絕緣基板15之整體之方式形成有閘極絕緣膜330。閘極絕緣膜330係包含氮化矽膜上積層有氧化矽膜之積層絕緣膜。閘極絕緣膜330之構成係與TFT100之情形相同，故省略其說明。再者，構成閘極絕緣膜330之氮化矽膜之膜厚為300 nm，氧化矽膜之膜厚為50 nm。 A gate insulating film 330 is formed to cover the entirety of the insulating substrate 15 including the channel layer 340. The gate insulating film 330 includes a laminated insulating film in which a tantalum oxide film is laminated on the tantalum nitride film. The configuration of the gate insulating film 330 is the same as that of the TFT 100, and the description thereof will be omitted. Further, the film thickness of the tantalum nitride film constituting the gate insulating film 330 was 300 nm, and the film thickness of the hafnium oxide film was 50 nm.
至少在與通道層340之低還原區域340b及非還原區域340c對向之閘極絕緣膜330上之位置配置有閘極電極320。閘極電極320之構成係與TFT100之情形相同，故省略其說明。以覆蓋包含閘極電極320之絕緣基板15之整體之方式，形成有包含氧化矽膜之層間絕緣膜350。再者，高還原區域340a之端部較佳為於俯視圖中進入至閘極電極320之內側為止，但亦可位於閘極電極320之外側。其原因在於，於該情形時，當對閘極電極320施加電壓時，在與閘極電極320相接之通道層340之表面上載子受到感應，形成高濃度層。 The gate electrode 320 is disposed at least at a position on the gate insulating film 330 opposed to the low reduction region 340b and the non-reduction region 340c of the channel layer 340. The configuration of the gate electrode 320 is the same as that of the TFT 100, and the description thereof will be omitted. An interlayer insulating film 350 including a hafnium oxide film is formed to cover the entirety of the insulating substrate 15 including the gate electrode 320. Further, the end portion of the high reduction region 340a preferably enters the inside of the gate electrode 320 in a plan view, but may be located on the outer side of the gate electrode 320. The reason for this is that, in this case, when a voltage is applied to the gate electrode 320, the surface of the channel layer 340 that is in contact with the gate electrode 320 is induced to form a high concentration layer.
於層間絕緣膜350及閘極絕緣膜330上分別形成有到達通道層340之兩側之高還原區域340a的接觸孔71a、71b。配置有經由接觸孔71a、71b而分別與兩側之高還原區域340a電性連接之源極電極360a及汲極電極360b。以覆蓋包含源極電極360a及汲極電極360b之絕緣基板15之整體之方式，形成有包含氧化矽膜之鈍化膜70。 Contact holes 71a and 71b which reach the high reduction region 340a on both sides of the channel layer 340 are formed on the interlayer insulating film 350 and the gate insulating film 330, respectively. A source electrode 360a and a drain electrode 360b that are electrically connected to the high-reduction regions 340a on both sides via the contact holes 71a and 71b are disposed. A passivation film 70 including a hafnium oxide film is formed so as to cover the entirety of the insulating substrate 15 including the source electrode 360a and the drain electrode 360b.
TFT之源極電極360a及汲極電極360b係於鈍化膜70之成膜時，曝露於包含自作為原料氣體之矽烷氣體或TEOS氣 體生成之氫的電漿中。此時，源極電極360a及汲極電極360b吸存電漿中之氫。繼而，當於鈍化膜70上形成接觸孔71a、71b之後，在大氣環境中進行溫度為300℃且時間為2小時之熱處理。藉由該熱處理，自源極電極360a及汲極電極360b之鈦層對IGZO層供給氫，且使氫於IGZO層內沿其長度方向進行擴散。藉此，於靠近源極電極360a及汲極電極360b之通道層340形成高還原區域340a，且於其等之內側分別形成低還原區域340b。於由2個低還原區域340b夾持之通道層340之中央殘留非還原區域340c。藉由該熱處理，而決定高還原區域340a之長度Lhigh、低還原區域340b之長度Llow及非還原區域40c之長度Lnon。又，可藉由該熱處理，而使於蝕刻接觸孔71a、71b時在源極電極360a及汲極電極360b中產生之損壞恢復。再者，熱處理之溫度較佳為300~350℃。又，用於還原IGZO膜之氫亦可為自氫氣中生成之氫電漿。於該情形時，源極電極360a及汲極電極360b可有效地進行吸氫。又，熱處理若為鈍化膜70之成膜後，則可於任何時候進行。 The source electrode 360a and the drain electrode 360b of the TFT are exposed to a decane gas or TEOS gas as a source gas when the film of the passivation film 70 is formed. The plasma of hydrogen produced by the body. At this time, the source electrode 360a and the drain electrode 360b absorb hydrogen in the plasma. Then, after the contact holes 71a and 71b were formed on the passivation film 70, heat treatment was performed in an atmosphere at a temperature of 300 ° C for 2 hours. By this heat treatment, hydrogen is supplied to the IGZO layer from the titanium layers of the source electrode 360a and the drain electrode 360b, and hydrogen is diffused in the IGZO layer along the longitudinal direction thereof. Thereby, the high reduction region 340a is formed in the channel layer 340 close to the source electrode 360a and the drain electrode 360b, and the low reduction region 340b is formed on the inner side thereof. The non-reduction region 340c remains in the center of the channel layer 340 sandwiched by the two low reduction regions 340b. By this heat treatment, the length Lhigh of the high reduction region 340a, the length Llow of the low reduction region 340b, and the length Lnon of the non-reduction region 40c are determined. Moreover, the damage generated in the source electrode 360a and the drain electrode 360b when the contact holes 71a and 71b are etched can be recovered by the heat treatment. Further, the temperature of the heat treatment is preferably from 300 to 350 °C. Further, the hydrogen used to reduce the IGZO film may also be a hydrogen plasma generated from hydrogen. In this case, the source electrode 360a and the drain electrode 360b can efficiently perform hydrogen absorption. Further, the heat treatment may be carried out at any time if it is formed by the passivation film 70.
又，亦於TFT400之情形時，可在形成通道層340之步驟至形成源極電極360a及汲極電極360b之步驟為止之任一步驟中進行例如溫度為350℃且時間為1小時之熱處理，以提昇TFT特性。 Further, in the case of the TFT 400, heat treatment such as a temperature of 350 ° C and a time of 1 hour may be performed in any step from the step of forming the channel layer 340 to the step of forming the source electrode 360a and the drain electrode 360b. To improve TFT characteristics.
<5.2效果> <5.2 effect>
根據本實施形態，與第1實施形態之TFT100之情形同樣地可獲得具有良好特性之TFT400。 According to the present embodiment, the TFT 400 having good characteristics can be obtained in the same manner as in the case of the TFT 100 of the first embodiment.
圖18係表示包含第1至第4實施形態之TFT100~400之任一者的液晶顯示裝置1之構成之方塊圖。圖18所示之液晶顯示裝置1係包含液晶面板2、顯示控制電路3、閘極驅動器4及源極驅動器5。於液晶面板2上形成有沿水平方向延伸之n條(n為1以上之整數)閘極配線G1~Gn、及沿與閘極配線G1~Gn交叉之方向延伸之m條(m為1以上之整數)源極配線S1~Sm。於第i條閘極配線Gi(i為1以上且n以下之整數)與第j條源極配線Sj(j為1以上且m以下之整數)之交點附近，分別配置有像素形成部Pij。 FIG. 18 is a block diagram showing the configuration of the liquid crystal display device 1 including any of the TFTs 100 to 400 of the first to fourth embodiments. The liquid crystal display device 1 shown in FIG. 18 includes a liquid crystal panel 2, a display control circuit 3, a gate driver 4, and a source driver 5. On the liquid crystal panel 2, n (n is an integer of 1 or more) gate wirings G1 to Gn extending in the horizontal direction and m (m is 1 or more) extending in a direction crossing the gate wirings G1 to Gn are formed. The integer is the source wiring S1~Sm. The pixel formation portion Pij is disposed in the vicinity of the intersection of the i-th gate wiring Gi (i is an integer of 1 or more and n or less) and the j-th source wiring Sj (j is an integer of 1 or more and m or less).
於顯示控制電路3中，自液晶顯示裝置1之外部供給水平同步信號或垂直同步信號等控制信號SC及圖像信號DT。顯示控制電路3係基於該等信號，對閘極驅動器4輸出控制信號SC1，且對源極驅動器5輸出控制信號SC2及圖像信號DT。 In the display control circuit 3, a control signal SC such as a horizontal synchronizing signal or a vertical synchronizing signal and an image signal DT are supplied from the outside of the liquid crystal display device 1. The display control circuit 3 outputs a control signal SC1 to the gate driver 4 based on the signals, and outputs a control signal SC2 and an image signal DT to the source driver 5.
閘極驅動器4係與閘極配線G1~Gn連接，源極驅動器5係與源極配線S1~Sm連接。閘極驅動器4係將表示選擇狀態之高位準信號依序供給至閘極配線G1~Gn。藉此，逐一地依序選擇閘極配線G1~Gn。例如，於選擇第i條閘極配線Gi時，一併選擇相當於1行之像素形成部Pi1~Pim。源極驅動器5係對各源極配線S1~Sm賦予與圖像信號DT相應之信號電壓。藉此，對選擇之相當於1行之像素形成部Pi1~Pim寫入與圖像信號DT相應之信號電壓。以此方式，液晶顯示裝置1於液晶面板2中顯示圖像。再者，存在將液晶面板2 稱為「顯示部」，且將閘極驅動器4及源極驅動器5統稱為驅動電路之情形。 The gate driver 4 is connected to the gate wirings G1 to Gn, and the source driver 5 is connected to the source wirings S1 to Sm. The gate driver 4 sequentially supplies the high level signals indicating the selected state to the gate wirings G1 to Gn. Thereby, the gate wirings G1 to Gn are sequentially selected one by one. For example, when the i-th gate wiring Gi is selected, the pixel formation portions Pi1 to Pim corresponding to one row are collectively selected. The source driver 5 applies a signal voltage corresponding to the image signal DT to each of the source lines S1 to Sm. Thereby, the signal voltage corresponding to the image signal DT is written to the pixel formation portions Pi1 to Pim corresponding to one row selected. In this way, the liquid crystal display device 1 displays an image in the liquid crystal panel 2. Furthermore, there will be a liquid crystal panel 2 It is called a "display part", and the gate driver 4 and the source driver 5 are collectively referred to as a drive circuit.
圖19係表示設於液晶面板2中之像素形成部Pij內之圖案配置的平面圖。如圖18所示，液晶面板2係包含沿水平方向延伸之第i條閘極配線Gi；沿與閘極配線Gi交叉之方向延伸之第j條源極配線Sj；及配置於由閘極配線Gi及源極配線Sj包圍之區域內之像素形成部Pij。像素形成部Pij包含圖7(a)及圖7(b)所示之TFT100，作為發揮開關元件之功能之TFT。TFT100之閘極電極20係與閘極配線Gi電性連接。於閘極電極20之上方形成有島狀之通道層40。通道層40之一端係與連接至源極配線Sj之源極電極電性連接，而通道層40之另一端係與汲極電極電性連接。進而，汲極電極經由接觸孔6而與像素電極7連接。像素電極7係與對向電極(未圖示)一併構成將與圖像信號DT相應之信號電壓保持特定時間之像素電容。 FIG. 19 is a plan view showing a pattern arrangement in the pixel formation portion Pij provided in the liquid crystal panel 2. As shown in FIG. 18, the liquid crystal panel 2 includes an i-th gate wiring Gi extending in the horizontal direction, a j-th source wiring Sj extending in a direction crossing the gate wiring Gi, and a gate wiring arranged in the gate wiring The pixel forming portion Pij in the region surrounded by Gi and the source wiring Sj. The pixel formation portion Pij includes the TFT 100 shown in FIGS. 7(a) and 7(b) as a TFT that functions as a switching element. The gate electrode 20 of the TFT 100 is electrically connected to the gate wiring Gi. An island-shaped channel layer 40 is formed above the gate electrode 20. One end of the channel layer 40 is electrically connected to the source electrode connected to the source wiring Sj, and the other end of the channel layer 40 is electrically connected to the drain electrode. Further, the drain electrode is connected to the pixel electrode 7 via the contact hole 6. The pixel electrode 7 is configured to form a pixel capacitance for maintaining a signal voltage corresponding to the image signal DT for a specific time together with a counter electrode (not shown).
可將具有良好TFT特性之TFT100用作設於液晶面板2中之各像素形成部Pij之開關元件，從而於截止時避免漏電流流動，或者避免接通電流因閾值電壓增高而降低。藉此，可將圖像信號之信號電壓於特定時間內保持於各像素形成部Pij，或者可確實地進行寫入，因此，可提昇顯示於液晶面板2中之圖像之顯示品質。 The TFT 100 having good TFT characteristics can be used as a switching element of each of the pixel formation portions Pij provided in the liquid crystal panel 2, thereby preventing leakage current from flowing at the time of turning off, or preventing the on-current from being lowered due to an increase in threshold voltage. Thereby, the signal voltage of the image signal can be held in each of the pixel formation portions Pij for a certain period of time, or the writing can be surely performed. Therefore, the display quality of the image displayed on the liquid crystal panel 2 can be improved.
再者，圖18及圖19係說明使用TFT100之情形，但亦可使用TFT200或300而取代TFT100。 18 and 19 illustrate the case of using the TFT 100, but the TFT 200 or 300 may be used instead of the TFT 100.
又，上述說明係說明將TFT210應用於液晶顯示裝置1中 之情形，但亦可應用於有機電致發光(Electro Luminescence，EL)顯示裝置中。 Moreover, the above description explains the application of the TFT 210 to the liquid crystal display device 1. However, it can also be applied to an organic electroluminescence (EL) display device.
本發明係適於主動矩陣型液晶顯示裝置等之類的顯示裝置，尤其適於構成形成於其像素部中之開關元件或用於驅動像素部之驅動電路的電晶體。 The present invention is suitable for a display device such as an active matrix type liquid crystal display device or the like, and is particularly suitable for forming a switching element formed in a pixel portion thereof or a transistor for driving a driving circuit of a pixel portion.
1‧‧‧液晶顯示裝置 1‧‧‧Liquid crystal display device
2‧‧‧液晶面板 2‧‧‧LCD panel
15‧‧‧絕緣基板 15‧‧‧Insert substrate
20‧‧‧閘極電極 20‧‧‧gate electrode
30‧‧‧閘極絕緣膜 30‧‧‧gate insulating film
40‧‧‧通道層(氧化物半導體層、IGZO層) 40‧‧‧channel layer (oxide semiconductor layer, IGZO layer)
40a‧‧‧高還原區域(第1區域) 40a‧‧‧High reduction area (1st area)
40b‧‧‧低還原區域(第2區域) 40b‧‧‧Low reduction area (2nd area)
40c‧‧‧非還原區域(第3區域) 40c‧‧‧Non-reduction area (3rd area)
60a‧‧‧源極電極 60a‧‧‧Source electrode
60b‧‧‧汲極電極 60b‧‧‧汲electrode
65‧‧‧鈦電極 65‧‧‧Titanium electrode
100‧‧‧薄膜電晶體(TFT) 100‧‧‧Thin Film Transistor (TFT)
150‧‧‧通道終止層 150‧‧‧channel termination layer
160a‧‧‧源極電極 160a‧‧‧Source electrode
160b‧‧‧汲極電極 160b‧‧‧汲electrode
165‧‧‧鈦電極 165‧‧‧Titanium electrode
200‧‧‧薄膜電晶體(TFT) 200‧‧‧Thin Film Transistor (TFT)
240‧‧‧通道層(氧化物半導體層、IGZO層) 240‧‧‧channel layer (oxide semiconductor layer, IGZO layer)
240a‧‧‧高還原區域(第1區域) 240a‧‧‧High reduction area (1st area)
240b‧‧‧低還原區域(第2區域) 240b‧‧‧Low reduction area (2nd area)
240c‧‧‧非還原區域(第3區域) 240c‧‧‧Non-reduction area (3rd area)
260a‧‧‧源極電極 260a‧‧‧Source electrode
260b‧‧‧汲極電極 260b‧‧‧汲electrode
265‧‧‧鈦電極 265‧‧‧Titanium electrode
267‧‧‧鈦電極 267‧‧‧Titanium electrode
300‧‧‧薄膜電晶體(TFT) 300‧‧‧Thin Film Transistor (TFT)
320‧‧‧閘極電極 320‧‧‧gate electrode
330‧‧‧閘極絕緣膜 330‧‧‧gate insulating film
340‧‧‧通道層(氧化物半導體層、IGZO層) 340‧‧‧channel layer (oxide semiconductor layer, IGZO layer)
340a‧‧‧高還原區域(第1區域) 340a‧‧‧High reduction area (1st area)
340b‧‧‧低還原區域(第2區域) 340b‧‧‧Low reduction area (2nd area)
340c‧‧‧非還原區域(第3區域) 340c‧‧‧Non-reduction area (3rd area)
360a‧‧‧源極電極 360a‧‧‧Source electrode
360b‧‧‧汲極電極 360b‧‧‧汲electrode
400‧‧‧薄膜電晶體(TFT) 400‧‧‧Thin Film Transistor (TFT)
Lch‧‧‧通道長度 Lch‧‧‧ channel length
Leff‧‧‧電通道長度 Leff‧‧‧Electrical channel length
△L/2‧‧‧單側之長度 △L/2‧‧‧One side length
圖1係表示基礎研究中使用之通道蝕刻結構之TFT之構成之剖面圖。 Fig. 1 is a cross-sectional view showing the constitution of a TFT of a channel etching structure used in the basic research.
圖2係表示於圖1所示之TFT中施加6 V之閘極電壓時求出電通道長度之方法之圖。 Fig. 2 is a view showing a method of determining the length of an electric path when a gate voltage of 6 V is applied to the TFT shown in Fig. 1.
圖3係表示圖1所示之TFT中之各區域之圖。 Fig. 3 is a view showing respective regions in the TFT shown in Fig. 1.
圖4係表示於圖1所示之TFT中，與源極電極之端部相距之距離和氧化物半導體層內之載子濃度之分佈的關係之圖。 Fig. 4 is a graph showing the relationship between the distance from the end portion of the source electrode and the distribution of the carrier concentration in the oxide semiconductor layer in the TFT shown in Fig. 1.
圖5係表示於圖1所示之TFT中閘極電壓與△區域之長度之關係之圖。 Fig. 5 is a view showing the relationship between the gate voltage and the length of the ? region in the TFT shown in Fig. 1.
圖6係表示於圖1所示之TFT中閘極電壓與△區域之平均片電阻之關係之圖。 Fig. 6 is a graph showing the relationship between the gate voltage and the average sheet resistance of the ? region in the TFT shown in Fig. 1.
圖7(a)係表示本發明第1實施形態之通道蝕刻結構之TFT之構成之平面圖，(b)係沿著(a)所示之切割線A-A之剖面圖。 Fig. 7 (a) is a plan view showing a configuration of a TFT of a channel etching structure according to a first embodiment of the present invention, and Fig. 7 (b) is a cross-sectional view taken along a cutting line A-A shown in (a).
圖8(a)係表示於圖7所示之TFT中，通道長度為3 μm時之TFT特性之圖，(b)係具有(a)所示之TFT特性之TFT之剖面 圖。 Fig. 8(a) is a view showing the characteristics of the TFT in the TFT shown in Fig. 7 with a channel length of 3 μm, and (b) a cross section of the TFT having the TFT characteristics shown in (a). Figure.
圖9(a)係表示於圖7所示之TFT中，通道長度為6 μm時之TFT特性之圖，(b)係具有(a)所示之TFT特性之TFT之剖面圖。 Fig. 9(a) is a view showing the characteristics of the TFT in the TFT shown in Fig. 7 with a channel length of 6 μm, and (b) a cross-sectional view of the TFT having the TFT characteristics shown in (a).
圖10(a)係表示於圖7所示之TFT中，通道長度為16 μm時之TFT特性之圖，(b)係具有(a)所示之TFT特性之TFT之剖面圖。 Fig. 10 (a) is a view showing the characteristics of the TFT in the TFT shown in Fig. 7 with a channel length of 16 μm, and (b) a cross-sectional view of the TFT having the TFT characteristics shown in (a).
圖11係表示於圖7所示之TFT中通道長度與汲極電流之關係之圖。 Figure 11 is a graph showing the relationship between the channel length and the drain current in the TFT shown in Figure 7.
圖12係表示於圖7所示之TFT中通道長度與閾值電壓之偏移量之關係之圖。 Fig. 12 is a view showing the relationship between the channel length and the threshold voltage in the TFT shown in Fig. 7.
圖13(a)-(c)係表示圖7所示之TFT之各製造步驟之步驟剖面圖。 Figures 13(a)-(c) are cross-sectional views showing the steps of the manufacturing steps of the TFT shown in Figure 7.
圖14(a)-(c)係表示圖7所示之TFT之各製造步驟之步驟剖面圖。 14(a)-(c) are cross-sectional views showing the steps of the respective manufacturing steps of the TFT shown in Fig. 7.
圖15(a)係表示本發明第2實施形態之蝕刻終止結構之TFT之構成之平面圖，(b)係(a)所示之TFT之沿B-B線之剖面圖。 Fig. 15 (a) is a plan view showing a configuration of a TFT of an etching termination structure according to a second embodiment of the present invention, and Fig. 15 (b) is a cross-sectional view taken along line B-B of the TFT shown in (a).
圖16(a)係表示本發明第3實施形態之底端接觸結構之TFT300之構成之平面圖，(b)係(a)所示之TFT之沿C-C線之剖面圖。 Fig. 16 (a) is a plan view showing a configuration of a TFT 300 of a bottom contact structure according to a third embodiment of the present invention, and (b) is a cross-sectional view taken along line C-C of the TFT shown in (a).
圖17(a)係表示本發明第4實施形態之頂閘極結構之TFT之構成之平面圖，(b)係沿(a)所示之切割線D-D之剖面圖。 Fig. 17 (a) is a plan view showing the configuration of a TFT of a top gate structure according to a fourth embodiment of the present invention, and Fig. 17 (b) is a cross-sectional view taken along line D-D shown in (a).
圖18係表示包含第1至第4實施形態之TFT之任一者的液 晶顯示裝置之構成之方塊圖。 Fig. 18 is a view showing a liquid including any of the TFTs of the first to fourth embodiments. A block diagram of the structure of a crystal display device.
圖19係表示圖18所示之液晶顯示裝置之液晶面板中設置之像素形成部內之圖案配置的平面圖。 Fig. 19 is a plan view showing a pattern arrangement in a pixel formation portion provided in a liquid crystal panel of the liquid crystal display device shown in Fig. 18.
20‧‧‧閘極電極 20‧‧‧gate electrode
30‧‧‧閘極絕緣膜 30‧‧‧gate insulating film
40‧‧‧通道層(氧化物半導體層、IGZO層) 40‧‧‧channel layer (oxide semiconductor layer, IGZO layer)
40a‧‧‧高還原區域(第1區域) 40a‧‧‧High reduction area (1st area)
40b‧‧‧低還原區域(第2區域) 40b‧‧‧Low reduction area (2nd area)
40c‧‧‧非還原區域(第3區域) 40c‧‧‧Non-reduction area (3rd area)
60a‧‧‧源極電極 60a‧‧‧Source electrode
60b‧‧‧汲極電極 60b‧‧‧汲electrode
Lch‧‧‧通道長度 Lch‧‧‧ channel length
Leff‧‧‧電通道長度 Leff‧‧‧Electrical channel length
△L/2‧‧‧單側之長度 △L/2‧‧‧One side length
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