TW201324831A

TW201324831A - Manufacturing method of solar cell

Info

Publication number: TW201324831A
Application number: TW100146480A
Authority: TW
Inventors: Jun-Cen Lu; Liang-Bin Chen
Original assignee: Motech Ind Inc
Priority date: 2011-12-15
Filing date: 2011-12-15
Publication date: 2013-06-16

Abstract

The present invention provides a manufacturing method of solar cell, which includes a preparation step for preparing a first type doping semiconductor substrate with a first surface and a second surface having opposite directions; a first diffusion layer forming step for forming a first diffusion layer with second type doping in the semiconductor substrate; and, an electrode unit forming step for forming an electrode unit electrically connected with the first diffusion layer. In which, the first diffusion layer forming step is first to form a first gel layer having the main component as silicon oxide on the first surface of the semiconductor substrate; thermally curing the first gel layer to form a first mask layer; next, conducting the second type doping on the semiconductor substrate to form the first diffusion layer; finally, removing the first mask layer to obtain the first diffusion layer.

Description

太陽能電池製造方法Solar cell manufacturing method

本發明是有關於一種太陽能電池的製造方法，特別是指一種利用熱硬化形成之氧化矽為擴散遮罩的太陽能電池製造方法。The invention relates to a method for manufacturing a solar cell, in particular to a method for manufacturing a solar cell using a cerium oxide formed by thermal hardening as a diffusion mask.

參閱圖1，習知的矽晶太陽能電池包含一矽晶基材11、一抗反射層12、一頂電極13，及一背電極14，該矽晶基材11具有一p型半導體層111、一與該p型半導體層111連接的n型半導體層112，及一形成於該n型半導體層112表面的凹凸結構113，該抗反射層12形成於該凹凸結構113表面，該頂電極13為穿過該抗反射層12與該n型半導體層112電連接，該背電極14與該p型半導體層111遠離該頂電極13的表面連接，且該n型半導體層112(也稱為射極層)具有凹凸結構113的表面即為該太陽能電池的收光面。當太陽光自該收光面入設至該矽晶基材11後，會藉由該抗反射層12與該凹凸結構113減低對入射光的反射，而該矽晶基材11照光後產生的電子會擴散至該n型半導體層112，再經由與該n型半導體層112電連接的頂電極13收集後，而與該背電極14配合向外輸出。Referring to FIG. 1 , a conventional silicon solar cell includes a twin crystal substrate 11 , an anti-reflection layer 12 , a top electrode 13 , and a back electrode 14 . The germanium substrate 11 has a p-type semiconductor layer 111 . An n-type semiconductor layer 112 connected to the p-type semiconductor layer 111, and a concave-convex structure 113 formed on the surface of the n-type semiconductor layer 112. The anti-reflection layer 12 is formed on the surface of the uneven structure 113, and the top electrode 13 is The anti-reflective layer 12 is electrically connected to the n-type semiconductor layer 112, the back electrode 14 is connected to the surface of the p-type semiconductor layer 111 away from the top electrode 13, and the n-type semiconductor layer 112 (also referred to as an emitter) The surface having the uneven structure 113 is the light-receiving surface of the solar cell. After the sunlight is introduced into the twinned substrate 11 from the light-receiving surface, the reflection of the incident light is reduced by the anti-reflective layer 12 and the concave-convex structure 113, and the twinned substrate 11 is illuminated. The electrons are diffused to the n-type semiconductor layer 112, collected by the top electrode 13 electrically connected to the n-type semiconductor layer 112, and then output to the back electrode 14 in cooperation with the back electrode 14.

前述該矽晶基材11之n型半導體層112，一般是將一p型矽晶片經由熱擴散製程，將高濃度的磷摻雜至該p型矽晶片之後而製得。然而，因為該n型半導體層112的摻雜濃度過高，因此容易導致太陽光被吸收後大多是以熱能形式消散，並無法有效產生光電流。The n-type semiconductor layer 112 of the twinned substrate 11 is generally prepared by doping a p-type germanium wafer with a high concentration of phosphorus to the p-type germanium wafer via a thermal diffusion process. However, since the doping concentration of the n-type semiconductor layer 112 is too high, it is likely that the sunlight is absorbed and mostly dissipated as heat energy, and the photocurrent cannot be efficiently generated.

而為了改善前述矽晶太陽能電池的缺點，則發展出具有選擇性射極(Selective Emitter)的矽晶太陽能電池，這種矽晶太陽能電池的n型半導體層112具有摻雜濃度較高的重摻雜區及摻雜濃度較低的輕摻雜區，而且頂電極13覆蓋於該重摻雜區所在區域的表面。藉由提高該矽晶基材11收光面與該頂電極13接觸區域的摻雜濃度且降低收光面有效收光區域(即未被該頂電極13覆蓋的區域)之摻雜濃度，達到降低電子傳遞阻抗的效果，以提高該太陽能電池的光電轉換效率。In order to improve the shortcomings of the foregoing twin solar cells, a twin crystal solar cell with selective emitter is developed, and the n-type semiconductor layer 112 of the twin solar cell has a high doping concentration. The impurity region and the lightly doped region having a lower doping concentration, and the top electrode 13 covers the surface of the region where the heavily doped region is located. By increasing the doping concentration of the region where the light-receiving surface of the twinned substrate 11 is in contact with the top electrode 13 and reducing the doping concentration of the effective light-receiving region of the light-receiving surface (ie, the region not covered by the top electrode 13) The effect of reducing the electron transfer impedance is improved to improve the photoelectric conversion efficiency of the solar cell.

前述該具有選擇性射極的矽晶太陽能電池一般是利用回蝕方式形成該輕、重摻雜區，即是將該具有凹凸結構113之p型矽晶片進行高濃度的磷摻雜，形成n型半導體層112後，於該n型半導體層112表面預定形成該頂電極13的位置，以網印或噴墨方式形成一層保護膜，接著再以蝕刻方式移除未被該保護膜保護的n型半導體層112，最後再將該保護層移除，即可得到該具有輕、重摻雜區的n型半導體層。The above-mentioned selective emitter-emitting silicon solar cell generally forms the light and heavily doped region by means of etch back, that is, the p-type germanium wafer having the uneven structure 113 is doped with a high concentration of phosphorus to form n. After the semiconductor layer 112 is formed, a position of the top electrode 13 is predetermined on the surface of the n-type semiconductor layer 112, a protective film is formed by screen printing or inkjet, and then the protective film is not removed by etching. The semiconductor layer 112 is finally removed by the protective layer to obtain the n-type semiconductor layer having light and heavily doped regions.

然而，前述無論是進行p型矽晶片摻雜而得到的該n型半導體層112，或是利用不同方式而得到具有不同摻雜濃度的n型半導體層112，其製程均較為繁瑣，而且都會有成本提升的問題，因此，如何提供一個更為簡便且可有效降低製程成本的方法，一直是此技術領域業者改善發展的方向。However, the n-type semiconductor layer 112 obtained by doping the p-type germanium wafer, or the n-type semiconductor layer 112 having different doping concentrations by different methods, is cumbersome in process and will have The problem of cost improvement, therefore, how to provide a more simple and effective way to reduce the cost of the process has been the direction of improvement in this technical field.

因此，本發明之目的，即在提供一種利用氧化矽構成之擴散阻擋遮罩製作太陽能電池的方法，不僅製程簡便且可降低製程成本。Accordingly, it is an object of the present invention to provide a method for fabricating a solar cell using a diffusion barrier mask composed of yttrium oxide, which is not only simple in process but also low in process cost.

於是，本發明太陽能電池的製造方法，包含一準備步驟、一第一擴散層形成步驟，及一電極單元形成步驟。Thus, the method of manufacturing a solar cell of the present invention comprises a preparation step, a first diffusion layer forming step, and an electrode unit forming step.

該準備步驟是先準備一具有第一型摻雜的半導體基板，該半導體基板具有方向相反的一第一表面及一第二表面。The preparation step is to first prepare a semiconductor substrate having a first type doping, the semiconductor substrate having a first surface and a second surface in opposite directions.

該第一擴散層形成步驟是於該半導體基板中形成一具有第二型摻雜的第一擴散層。The first diffusion layer forming step is to form a first diffusion layer having a second type doping in the semiconductor substrate.

該電極單元形成步驟是形成一與該第一擴散層電連接的電極單元。The electrode unit forming step is to form an electrode unit electrically connected to the first diffusion layer.

其中，該第一擴散層形成步驟是先於該半導體基板的第一表面形成一主成份為氧化矽的第一凝膠層，並將該第一凝膠層熱硬化形成一第一遮罩層，然後對該半導體基板進行第二型摻雜以形成該第一擴散層，最後將該第一遮罩層移除，而得到該第一擴散層。The first diffusion layer forming step is to form a first gel layer having a main component of cerium oxide before the first surface of the semiconductor substrate, and thermally harden the first gel layer to form a first mask layer. Then, the semiconductor substrate is doped with a second type to form the first diffusion layer, and finally the first mask layer is removed to obtain the first diffusion layer.

本發明之功效在於：利用主要由氧化矽構成的凝膠層熱硬化後形成之遮罩層作為擴散阻擋遮罩，不僅製程簡便，且利用單次熱擴散製程即可完成具有不同摻雜濃度的矽晶基材，此外，因氧化矽原料便宜容易取得，因此還可有效降低製程成本。The effect of the invention is that the mask layer formed by thermosetting the gel layer mainly composed of ruthenium oxide is used as a diffusion barrier mask, which is not only simple in process, but also can be completed by a single thermal diffusion process with different doping concentrations. The twin crystal substrate, in addition, is cheap and easy to obtain because of the cerium oxide raw material, so that the process cost can be effectively reduced.

有關本發明之前述及其他技術內容、特點與功效，在以下配合參考圖式之二個較佳實施例的詳細說明中，將可清楚的呈現。The above and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments of the invention.

參閱圖2，本發明太陽能電池製作方法的一第一較佳實施例是可用以製作如圖2所示的太陽能電池，該太陽能電池包含一半導體單元2、一抗反射層3，及一電極單元4。Referring to FIG. 2, a first preferred embodiment of the method for fabricating a solar cell of the present invention can be used to fabricate a solar cell as shown in FIG. 2, the solar cell comprising a semiconductor unit 2, an anti-reflection layer 3, and an electrode unit. 4.

該半導體單元2具有一第一表面21、一形成於該第一表面21的凹凸結構211、一第二表面22、一第一型摻雜的第一型半導體層23、一與該第一型半導體23連接並具有第二型摻雜的第一擴散層24，及一與該第一型半導體層23遠離該第一擴散層24的一側連接，具有第一型摻雜且摻雜濃度高於該第一型半導體層23的第二擴散層25；該第一擴散層24即為一般稱之射極層，且其表面即為該第一表面21，該第二擴散層25為一般稱之背電場(back-surface field，BSF)層，且其表面即為該第二表面22。The semiconductor unit 2 has a first surface 21, a concave-convex structure 211 formed on the first surface 21, a second surface 22, a first-type doped first-type semiconductor layer 23, and a first type. The semiconductor 23 is connected to and has a second type doped first diffusion layer 24, and is connected to a side of the first type semiconductor layer 23 away from the first diffusion layer 24, has a first type doping and a high doping concentration The second diffusion layer 25 of the first type semiconductor layer 23; the first diffusion layer 24 is generally referred to as an emitter layer, and the surface thereof is the first surface 21, and the second diffusion layer 25 is generally called A back-surface field (BSF) layer, and the surface thereof is the second surface 22.

要說明的是，該第一型摻雜與第二型摻雜的電性為彼此相反，例如當該第一型掺雜為p型摻雜時，則該第二型摻雜為n型摻雜，反之，當該第一型掺雜為n型摻雜時，則該第二型摻雜為p型摻雜，於本實施例中該第一型摻雜為p型摻雜，第二型摻雜為n型摻雜，且該第一表面21即為該太陽能電池的收光面。It should be noted that the electrical properties of the first type doping and the second type doping are opposite to each other. For example, when the first type doping is p-type doping, the second type doping is n-type doping. If the first type doping is n-type doping, then the second type doping is p-type doping. In this embodiment, the first type doping is p-type doping, and the second type is doped. The type doping is n-type doping, and the first surface 21 is the light-receiving surface of the solar cell.

該抗反射層3形成於該第一表面21，由透光材料構成，例如氮化矽(SiN_x)，可用以減少入射光的反射、降低載子在該第一擴散層24表面的復合率，並保護該半導體單元2。The anti-reflective layer 3 is formed on the first surface 21 and is made of a light-transmitting material, such as tantalum nitride (SiN _x ), which can reduce the reflection of incident light and reduce the recombination rate of the carrier on the surface of the first diffusion layer 24. And protecting the semiconductor unit 2.

該電極單元4用以將該半導體單元2吸收光線後產生之電流向外輸出，具有一頂電極41及一背電極42，該頂電極41穿過該抗反射層3與該第一擴散層24連接，具有一主電極(busbar)411及多數條自該主電極411向外延伸的指叉電極(finger)412，且該背電極42為形成該第二表面22並完全覆蓋該第二表面22。The electrode unit 4 is configured to output the current generated by the semiconductor unit 2 to absorb light, and has a top electrode 41 and a back electrode 42. The top electrode 41 passes through the anti-reflection layer 3 and the first diffusion layer 24. The connection has a main bus (busbar) 411 and a plurality of fingers 412 extending outward from the main electrode 411, and the back electrode 42 forms the second surface 22 and completely covers the second surface 22 .

參閱圖3，本發明該太陽能電池製作方法的第一較佳實施例，包含一準備步驟51、一第一擴散層形成步驟52、一抗反射層形成步驟53，及一電極單元形成步驟54。Referring to FIG. 3, a first preferred embodiment of the solar cell manufacturing method of the present invention comprises a preparation step 51, a first diffusion layer forming step 52, an anti-reflection layer forming step 53, and an electrode unit forming step 54.

該準備步驟51是準備一第一型摻雜的半導體基板，該半導體基材具有方向相反的一第一表面21及一第二表面22，且該第一表面21具有該凹凸結構211。於本實施例中該第一型摻雜為p型摻雜，該步驟51是利用濕式或乾式蝕刻方式蝕刻一p型矽晶基材的其中一表面，令該表面形成具有高低起伏的凹凸結構211而得到該具有p型摻雜的半導體基板。The preparation step 51 is to prepare a first type doped semiconductor substrate having a first surface 21 and a second surface 22 opposite to each other, and the first surface 21 has the uneven structure 211. In the embodiment, the first type doping is p-type doping, and the step 51 is to etch one surface of a p-type twin crystal substrate by wet or dry etching, so that the surface forms a bump with high and low undulations. The structure 211 is used to obtain the semiconductor substrate having p-type doping.

該第一擴散層形成步驟52是於該半導體基板鄰近該第一表面21的一側，形成一具有第二型摻雜的第一擴散層24，於本實施例中該第二型摻雜為n型摻雜。The first diffusion layer forming step 52 is formed on the side of the semiconductor substrate adjacent to the first surface 21 to form a first diffusion layer 24 having a second type doping. In this embodiment, the second type doping is N-type doping.

詳細的說，該步驟52是先於該第二表面22形成一主成份為氧化矽的第一凝膠層，並將該第一凝膠層熱硬化形成一第一遮罩層後，再自該半導體基板的第一表面21利用熱擴散製程進行第二型摻雜，於該半導體基板鄰近該第一表面21的一側形成該具有第二型摻雜的第一擴散層24，最後移除該第一遮罩層；較佳地，為了控制擴散阻擋效果，該第一遮罩層的厚度介於10-200nm。In detail, the step 52 is to form a first gel layer having a main component of cerium oxide before the second surface 22, and thermally harden the first gel layer to form a first mask layer, and then The first surface 21 of the semiconductor substrate is subjected to a second type doping by a thermal diffusion process, and the first diffusion layer 24 having the second type doping is formed on a side of the semiconductor substrate adjacent to the first surface 21, and finally removed. The first mask layer; preferably, the thickness of the first mask layer is between 10 and 200 nm in order to control the diffusion barrier effect.

於本實施例中，該步驟52是先將氧化矽溶於一溶劑中而製得一氧化矽溶液，該溶劑為選自高極性溶劑，例如水、甲醇、乙醇、正丁醇、乙酸乙酯等，用以調整該氧化矽溶液的黏度、固含量等特性。要說明的是該氧化矽溶液還可包括矽氧烷(siloxane)化合物，或是硼、磷、鋅等元素，以利後續熱硬化製程的交聯硬化，或是作為後續熱擴散過程的另一摻雜源；接著將該氧化矽溶液以超音波噴墨、網印、噴墨印刷等方式，於該半導體基板的第二表面22，形成一層由該氧化矽溶液構成之第一凝膠層，接著將該形成第一凝膠層的半導體基板進行熱處理：先在80~300℃、3分鐘的條件，讓該溶劑揮發，接著再於300~900℃、30分鐘的條件，令該第一凝膠層硬化，以形成該第一遮罩。接著，將該形成第一遮罩層的半導體基板置入一高溫爐管，爐管內的溫度約為750℃～800℃，並且在爐管內通入一反應氣體，於本實施例中該反應氣體為N₂-POCl₃(氮氣與三氯氧磷的混合)、O₂及N₂的混合氣體，但不限於此，於該半導體基板的第一表面沉積磷(P)。接著將爐管溫度升高到800℃～950℃並維持數十分鐘，使磷(P)自該第一表面21擴散進入該半導體基板的表層，最後再將該經熱擴散製程的半導體基板置入氫氟酸溶液約50~500秒，移除該第一遮罩層，即完成該步驟52。In this embodiment, the step 52 is to first dissolve cerium oxide in a solvent to prepare a cerium oxide solution selected from the group consisting of high polar solvents such as water, methanol, ethanol, n-butanol, and ethyl acetate. Etc., used to adjust the viscosity, solid content and other characteristics of the cerium oxide solution. It should be noted that the cerium oxide solution may further comprise a siloxane compound, or an element such as boron, phosphorus or zinc, to facilitate cross-linking hardening of the subsequent thermosetting process, or as another process of the subsequent thermal diffusion process. a doping source; then, the cerium oxide solution is formed by ultrasonic jetting, screen printing, inkjet printing or the like on the second surface 22 of the semiconductor substrate to form a first gel layer composed of the cerium oxide solution. Then, the semiconductor substrate forming the first gel layer is subjected to heat treatment: first, the solvent is volatilized at 80 to 300 ° C for 3 minutes, and then the first condensation is performed at 300 to 900 ° C for 30 minutes. The glue layer is hardened to form the first mask. Then, the semiconductor substrate forming the first mask layer is placed in a high temperature furnace tube, the temperature in the furnace tube is about 750 ° C to 800 ° C, and a reaction gas is introduced into the furnace tube. In this embodiment, The reaction gas is a mixed gas of N ₂ -POCl ₃ (mixing of nitrogen and phosphorus oxychloride), O ₂ and N ₂ , but is not limited thereto, and phosphorus (P) is deposited on the first surface of the semiconductor substrate. Then, the temperature of the furnace tube is raised to 800 ° C to 950 ° C and maintained for several tens of minutes to diffuse phosphorus (P) from the first surface 21 into the surface layer of the semiconductor substrate, and finally the semiconductor substrate subjected to the thermal diffusion process is placed. The step 52 is completed by removing the hydrofluoric acid solution for about 50 to 500 seconds and removing the first mask layer.

接著，進行該抗反射層形成步驟53，利用濺鍍(Sputtering)或電漿輔助化學氣相沉積(PECVD)等方式於該第一表面21形成由氮化矽(SiN_x)為材料構成之抗反射層3。Then, the anti-reflection layer forming step 53 is performed, and an anti-silicon (SiN _x )-based material is formed on the first surface 21 by sputtering or plasma-assisted chemical vapor deposition (PECVD). Reflective layer 3.

要說明的是，該抗反射層3並非太陽能電池的必要結構，也就是說太陽能電池也可以不包含該抗反射層3，因此，本發明該太陽能電池的製作方法也可以不包含該抗反射層形成步驟53。It should be noted that the anti-reflection layer 3 is not a necessary structure of the solar cell, that is, the solar cell may not include the anti-reflection layer 3. Therefore, the method for fabricating the solar cell of the present invention may not include the anti-reflection layer. Step 53 is formed.

最後，進行該電極單元形成步驟54，於該抗反射層3及該第二表面22形成該具有頂電極41及背電極42的電極單元4。Finally, the electrode unit forming step 54 is performed, and the electrode unit 4 having the top electrode 41 and the back electrode 42 is formed on the anti-reflective layer 3 and the second surface 22.

具體的說，該步驟54是將一第一導電銀漿以網印方式，於該抗反射層3的預定表面形成一第一導電層及多數條自該第一導電層延伸之導線，再利用一含鋁的第二導電銀漿以網印方式形成一覆蓋該第二表面212的第二導電層。接著將上述樣品置於高溫燒結爐中，令該第一導電層及該些導線於燒結後轉變成該主電極411，及該些指叉電極412；而該第二導電層於燒結後會轉變為該背電極42，且該第二導電層於燒結的過程中，該第二導電層的鋁會同時經由該第二表面22擴散進入該半導體基板100，而於形成該背電極42的同時，會在鄰近該第二表面22的一側形成該第二擴散層25，令該p型矽晶片轉變成該半導體單元2，即可完成太陽能電池的製作，得到如圖2所示的太陽能電池。Specifically, in the step 54, a first conductive silver paste is screen-printed, and a first conductive layer and a plurality of wires extending from the first conductive layer are formed on a predetermined surface of the anti-reflective layer 3, and then utilized. An aluminum-containing second conductive silver paste forms a second conductive layer covering the second surface 212 in a screen printing manner. Then, the sample is placed in a high-temperature sintering furnace, and the first conductive layer and the wires are converted into the main electrode 411 and the finger electrodes 412 after sintering; and the second conductive layer is transformed after sintering. For the back electrode 42 and the second conductive layer is sintered, the aluminum of the second conductive layer is simultaneously diffused into the semiconductor substrate 100 via the second surface 22, and while the back electrode 42 is formed, The second diffusion layer 25 is formed on the side adjacent to the second surface 22, and the p-type germanium wafer is converted into the semiconductor unit 2, thereby completing the fabrication of the solar cell, and the solar cell shown in FIG. 2 is obtained.

此外，要說明的是，當該半導體基板是選自n型矽晶基板且為使用傳統p-型矽晶基板製程的背面射極太陽能電池時，則可在形成鋁射極時同時形成該具有p型摻雜之第一擴散層24；而當該半導體基板是選自n型矽晶片且該太陽能電池為雙面結構(Bi-facial)電池時，由於該第二擴散層25通常無法利用形成該背電極42的過程同時形成，則該太陽能電池的製作方法還需進一步包含一第二擴散層形成步驟，該第二擴散層形成步驟可於該第一擴散層形成步驟52之前或之後實施，係利用與前述該第一凝膠層組成材料相同的第二凝膠層，於該第一表面21形成一第二凝膠層，並將該第二凝膠層熱硬化形成一第二遮罩層之後，再利用熱擴散製程自該第二表面212進行n型摻雜，而於該n型矽晶片鄰近該第二表面22的一側形成該第二擴散層25，再進行後續該步驟53、54即可。In addition, it is to be noted that when the semiconductor substrate is selected from an n-type twinned substrate and is a back-emitter solar cell using a conventional p-type twin-crystal substrate process, the aluminum emitter can be formed simultaneously. a p-type doped first diffusion layer 24; and when the semiconductor substrate is selected from an n-type germanium wafer and the solar cell is a bi-facial battery, since the second diffusion layer 25 is generally not formed The process of the back electrode 42 is simultaneously formed, and the method for fabricating the solar cell further includes a second diffusion layer forming step, which may be performed before or after the first diffusion layer forming step 52, And forming a second gel layer on the first surface 21 by using the same second gel layer as the first gel layer, and thermally hardening the second gel layer to form a second mask. After the layer, n-type doping is performed from the second surface 212 by using a thermal diffusion process, and the second diffusion layer 25 is formed on a side of the n-type germanium wafer adjacent to the second surface 22, and then the subsequent step 53 is performed. , 54 can be.

又要說明的是，該電極單元4的形態僅為示意而非限定，亦可為其他設計之態樣，例如，該背電極42的結構也可與該頂電極41相似，具有多條間隔設置的主電極。It should be noted that the shape of the electrode unit 4 is merely illustrative and not limited, and may be in other designs. For example, the structure of the back electrode 42 may be similar to the top electrode 41, and has multiple intervals. The main electrode.

習知係先利用PECVD形成以氧化矽為材料構成之遮罩層作為擴散阻擋層，再進行熱擴散製程以形成該第一、二擴散層24、25，然而，利用PECVD形成遮罩層的製程效果較差且有難以去除和背鍍問題，而為了要達到較佳的擴散阻擋效果而要將遮罩層的厚度提升時，其造成的背鍍問題也會隨著遮罩層的厚度變厚而更為嚴重；而本案利用噴墨或網印等方式於該半導體基板100表面形成由氧化矽構成之凝膠層，再直接利用熱硬化令凝膠層硬化成為遮罩層，不僅製程簡單，且該遮罩層的厚度不會受到製程限制，可輕易控制，除了可達到更佳的阻擋效果之外，也不會有習知因為遮罩層厚度增加時所產生的背鍍問題；此外，由於氧化矽凝膠原料便宜容易取得，因此，還可有效降低製程成本。Conventionally, PECVD is used to form a mask layer made of yttrium oxide as a diffusion barrier layer, and then a thermal diffusion process is performed to form the first and second diffusion layers 24 and 25. However, the process of forming a mask layer by PECVD is performed. The effect is poor and it is difficult to remove and back plating problems, and in order to achieve a better diffusion barrier effect, when the thickness of the mask layer is increased, the back plating problem caused by the thickness of the mask layer becomes thicker. More serious; in this case, a gel layer composed of ruthenium oxide is formed on the surface of the semiconductor substrate 100 by inkjet or screen printing, and the gel layer is hardened directly into a mask layer by thermal hardening, which is not only simple in process, but also The thickness of the mask layer is not limited by the process, and can be easily controlled. In addition to achieving a better barrier effect, there is no known problem of back plating caused by an increase in the thickness of the mask layer; The cerium oxide gel raw material is inexpensive and easy to obtain, and therefore, the process cost can be effectively reduced.

參閱圖4、圖5，圖4是利用本發明太陽能電池製作方法的一第二較佳實施例製得的具有選擇性射極的太陽能電池，圖5則是圖4的局部放大圖。該太陽能電池的結構與該第一較佳實施例大致相同，因此不再多加敘述，其不同處在於該半導體單元2的第一擴散層24具有一對應該些指叉電極412形成位置的重摻雜區241，及一未被該些指叉電極412遮覆的輕摻雜區242，其中，該重摻雜區241是指具有高濃度摻雜(heavy dopant)的區域，該輕摻雜區242則是指具有低濃度摻雜(light dopant)的區域。Referring to FIG. 4 and FIG. 5, FIG. 4 is a solar cell with a selective emitter prepared by using a second preferred embodiment of the solar cell manufacturing method of the present invention, and FIG. 5 is a partial enlarged view of FIG. The structure of the solar cell is substantially the same as that of the first preferred embodiment, and therefore will not be described again, except that the first diffusion layer 24 of the semiconductor unit 2 has a pair of heavily doped regions where the finger electrodes 412 are formed. a doped region 241, and a lightly doped region 242 that is not covered by the finger electrodes 412, wherein the heavily doped region 241 refers to a region having a high concentration of doping, the lightly doped region 242 refers to a region having a low concentration of light dopant.

參閱圖6，本發明太陽能電池製作方法的該第二較佳實施例包含一準備步驟61、一第一擴散層形成步驟62、一抗反射層形成步驟63，及一電極單元形成步驟64。Referring to FIG. 6, the second preferred embodiment of the solar cell manufacturing method of the present invention comprises a preparation step 61, a first diffusion layer forming step 62, an anti-reflection layer forming step 63, and an electrode unit forming step 64.

首先進行該準備步驟61，準備一具有凹凸結構211的半導體基板。First, the preparation step 61 is performed to prepare a semiconductor substrate having the uneven structure 211.

該半導體基板100是由具有第一型摻雜的半導體材料構成，具有方向相反的一第一表面21及一第二表面22，且該第一表面21具有該凹凸結構211。該第一型摻雜與後續製程的第二型摻雜的電性彼此相反，於本實施例中該第一型摻雜為p型摻雜，該半導體基板是以具有p型摻雜的p型矽晶片為例說明。The semiconductor substrate 100 is made of a semiconductor material having a first type doping, and has a first surface 21 and a second surface 22 opposite to each other, and the first surface 21 has the uneven structure 211. The electrical conductivity of the first type doping and the second type doping of the subsequent process are opposite to each other. In the embodiment, the first type doping is p-type doping, and the semiconductor substrate is p with p-type doping. The type of germanium wafer is taken as an example.

具體的說，該步驟61是先準備該半導體基板，接著利用濕式或乾式蝕刻方式蝕刻該半導體基板的第一表面21，令該第一表面21形成具有高低起伏的凹凸結構211。Specifically, in the step 61, the semiconductor substrate is prepared first, and then the first surface 21 of the semiconductor substrate is etched by wet or dry etching, so that the first surface 21 forms the uneven structure 211 having high and low undulations.

接著進行該第一擴散層形成步驟62，於該半導體基板鄰近該第一表面21的一側形成該具有重、輕摻雜區241、242的第一擴散層24。The first diffusion layer forming step 62 is then performed, and the first diffusion layer 24 having the heavy and lightly doped regions 241, 242 is formed on a side of the semiconductor substrate adjacent to the first surface 21.

具體的說，該步驟62是先以絲網印刷或噴墨印刷方式於該第一表面22預定不形成該指叉電極412的位置形成一主成份與前述該第一凝膠層相同之第三凝膠層，並令該第三凝膠層經過與該步驟52相同之熱硬化處理過程後形成一第三遮罩層，接著利用與該步驟52相同之熱擴散製程自該第一表面21及該第三遮罩層表面對該p型矽晶片進行第二型摻雜(n型摻雜)，於該p型矽晶片鄰近該第一表面21的一側形成該具有第二型摻雜的第一擴散層24，且該第一擴散層24在對應該第三遮罩層的區域會形成具有低摻雜濃度的輕摻雜區242，而在沒有該第三遮罩層阻擋的區域則形成具有高摻雜濃度的重摻雜區241，接著將該p型矽晶片置入氫氟酸溶液約50~500秒移除該第二遮罩層；而由於前述該p型矽晶片的側面及第二表面22也會在熱擴散製程中形成一層與該第一擴散層24相同材料的半導體層，因此，在熱擴散製程後須再利用溼式蝕刻方式將該半導體層移除，完成該步驟62。Specifically, the step 62 is to first form a third component having the same main component as the first gel layer at a position where the first surface 22 is not intended to form the finger electrode 412 by screen printing or inkjet printing. a gel layer, and subjecting the third gel layer to a third mask layer after the same thermal hardening process as in step 52, and then using the same thermal diffusion process as step 52 from the first surface 21 and Forming a second type doping (n-type doping) on the p-type germanium wafer on the surface of the third mask layer, and forming the second type doping on a side of the p-type germanium wafer adjacent to the first surface 21 a first diffusion layer 24, and the first diffusion layer 24 forms a lightly doped region 242 having a low doping concentration in a region corresponding to the third mask layer, and in a region not blocked by the third mask layer Forming a heavily doped region 241 having a high doping concentration, and then placing the p-type germanium wafer in a hydrofluoric acid solution for about 50 to 500 seconds to remove the second mask layer; and due to the aforementioned side of the p-type germanium wafer And the second surface 22 also forms a semiconductor layer of the same material as the first diffusion layer 24 in the thermal diffusion process. Thus, after the thermal diffusion process to be further removed by wet etching the semiconductor layer, the step 62 is completed.

藉由熱硬化後之氧化矽作為擴散遮罩(該第三遮罩層)，利用原子在不同材料的擴散速度差，而在有遮罩及沒有遮罩的位置形成摻雜濃度差，即可簡單利用一次重摻雜製程而得到該具有不同摻雜濃度之第一擴散層24(即所述之選擇性射極)。By thermally hardening the yttrium oxide as a diffusion mask (the third mask layer), the diffusion rate difference of the atoms in different materials is utilized, and the doping concentration difference is formed at a position where there is a mask and no mask. The first diffusion layer 24 (i.e., the selective emitter) having different doping concentrations is obtained by simply using a single heavily doping process.

另外，也可先利用膠帶將該第一表面21預定形成該些指叉電極412的位置遮覆，然後利用超音波噴霧或旋轉塗布方式將該氧化矽溶液噴印在該第一表面21後再將該膠帶撕除，即可在該第一半導體層21預定形成該指叉電極412的位置形成該第三凝膠層。In addition, the first surface 21 may be first covered with a tape to form a position of the finger electrodes 412, and then the cerium oxide solution is sprayed on the first surface 21 by ultrasonic spraying or spin coating. The tape is peeled off to form the third gel layer at a position where the first semiconductor layer 21 is intended to form the finger electrode 412.

接著，進行該抗反射層形成步驟63，及電極單元形成步驟64，即可完成該太陽能電池製作，得到如圖5所示之太陽能電池。由於該步驟63及步驟64與該第一較佳實施例之該步驟53及54相同，因此不再重複說明。Next, the anti-reflection layer forming step 63 and the electrode unit forming step 64 are performed to complete the solar cell fabrication, and a solar cell as shown in FIG. 5 is obtained. Since the steps 63 and 64 are the same as the steps 53 and 54 of the first preferred embodiment, the description will not be repeated.

參閱圖7，圖7是利用厚度為150nm之該第一遮罩層24作為摻雜遮罩對前述該p型半導體基材進行磷摻雜，所得的摻雜濃度對摻雜深度的結果。其摻雜條件是將表面形成該第一遮罩層的p型半導體基材放入高溫爐管中，通入N₂-POCl₃(氮氣與三氯氧磷的混合)、O₂及N₂的混合氣體，先以800℃持續25分鐘，再以868℃持續12.5分鐘。圖7中虛線(---)及實線(-)分別代表輕摻雜區242及重摻雜區241之摻雜濃度對摻雜深度的結果。Referring to FIG. 7, FIG. 7 is a result of phosphorus doping of the p-type semiconductor substrate using the first mask layer 24 having a thickness of 150 nm as a doping mask, and the resulting doping concentration versus doping depth. The doping condition is that a p-type semiconductor substrate having a surface forming the first mask layer is placed in a high temperature furnace tube, and N ₂ -POCl ₃ (mixing of nitrogen and phosphorus oxychloride), O ₂ and N _{2 are introduced.} The mixed gas was first held at 800 ° C for 25 minutes and then at 868 ° C for 12.5 minutes. The dotted line (---) and the solid line (-) in Fig. 7 represent the results of the doping concentration of the lightly doped region 242 and the heavily doped region 241, respectively, on the doping depth.

由圖7可知，輕摻雜區242因為有該第一遮罩層24阻擋所以摻雜原子的擴散速度較慢，因此摻雜濃度低且摻雜深度較淺，而重摻雜區241則因為沒有第一遮罩層的阻擋，因此摻雜濃度較高且摻雜深度較深，即，藉由本發明之摻雜遮罩，利用單次擴散製程就可將該重、輕摻雜區241、242的摻雜濃度有效區隔。As can be seen from FIG. 7, the lightly doped region 242 has a slower diffusion rate of dopant atoms because of the blocking of the first mask layer 24. Therefore, the doping concentration is low and the doping depth is shallow, and the heavily doped region 241 is because Without the barrier of the first mask layer, the doping concentration is higher and the doping depth is deeper, that is, by the doping mask of the present invention, the heavy and lightly doped regions 241 can be utilized by a single diffusion process. The doping concentration of 242 is effectively separated.

本發明利用熱硬化後之氧化矽作為擴散遮罩，利用原子在不同材料(擴散遮罩(SiO₂)及矽基材(Si))的擴散速度差，而在有遮罩及沒有遮罩的位置形成摻雜濃度差，如此即可利用硬化後之氧化矽作為矽晶片的摻雜擴散遮罩，或是作為製備選擇性射極用之摻雜擴散遮罩，而可以利用單一製程製得該具有重摻雜區241及輕摻雜區242的第一擴散層24，此外，由於氧化矽原料便宜容易取得，因此還可有效降低成本，故確實可達成本發明之目的。The invention utilizes the heat-hardened yttrium oxide as a diffusion mask, utilizing the difference in diffusion speed of atoms in different materials (diffusion mask (SiO ₂ ) and tantalum substrate (Si)), and in the presence of a mask and without a mask. The position is formed to have a doping concentration difference, so that the hardened yttrium oxide can be used as a doped diffusion mask of the germanium wafer or as a doped diffusion mask for preparing a selective emitter, and the single process can be used to obtain the The first diffusion layer 24 having the heavily doped region 241 and the lightly doped region 242, and the fact that the cerium oxide raw material is inexpensive and easy to obtain, can also effectively reduce the cost, so that it can be achieved for the purpose of the invention.

惟以上所述者，僅為本發明之較佳實施例而已，當不能以此限定本發明實施之範圍，即大凡依本發明申請專利範圍及發明說明內容所作之簡單的等效變化與修飾，皆仍屬本發明專利涵蓋之範圍內。The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent.

2．．．半導體單元2. . . Semiconductor unit

21．．．第一表面twenty one. . . First surface

211．．．凹凸結構211. . . Concave structure

22．．．第二表面twenty two. . . Second surface

23．．．第一型半導體層twenty three. . . First type semiconductor layer

24．．．第一擴散層twenty four. . . First diffusion layer

241．．．重摻雜區241. . . Heavily doped region

242．．．輕摻雜區242. . . Lightly doped area

25．．．第二擴散層25. . . Second diffusion layer

3．．．抗反射層3. . . Antireflection layer

4．．．電極單元4. . . Electrode unit

41．．．頂電極41. . . Top electrode

411．．．主電極411. . . Main electrode

412．．．指叉電極412. . . Finger electrode

42．．．背電極42. . . Back electrode

51．．．準備步驟51. . . Preparation step

52．．．第一擴散層形成步驟52. . . First diffusion layer forming step

53．．．抗反射層形成步驟53. . . Antireflection layer forming step

54．．．電極單元形成步驟54. . . Electrode unit forming step

61．．．準備步驟61. . . Preparation step

62．．．第一擴散層形成步驟62. . . First diffusion layer forming step

63．．．抗反射層形成步驟63. . . Antireflection layer forming step

64．．．電極單元形成步驟64. . . Electrode unit forming step

圖1是一示意圖，說明習知矽晶太陽能電池的結構；Figure 1 is a schematic view showing the structure of a conventional twin solar cell;

圖2是一示意圖，說明本發明第一較佳實施例製得的太陽能電池；Figure 2 is a schematic view showing a solar cell obtained by the first preferred embodiment of the present invention;

圖3是一流程圖，說明本發明該第一較佳實施例；Figure 3 is a flow chart illustrating the first preferred embodiment of the present invention;

圖4是一示意圖，說明本發明第二較佳實施例製得的的太陽能電池；Figure 4 is a schematic view showing a solar cell obtained by the second preferred embodiment of the present invention;

圖5是一局部放大圖，輔助說明圖4；Figure 5 is a partial enlarged view, which assists in explaining Figure 4;

圖6是一流程圖，說明本發明該第二較佳實施例；及Figure 6 is a flow chart illustrating the second preferred embodiment of the present invention; and

圖7是一摻雜濃度圖，說明重摻雜區及輕摻雜區的摻雜濃度對摻雜深度的結果。FIG. 7 is a doping concentration diagram illustrating the doping concentration of the heavily doped region and the lightly doped region versus the doping depth.

51．．．準備步驟51. . . Preparation step

53．．．抗反射層形成步驟53. . . Antireflection layer forming step

54．．．電極單元形成步驟54. . . Electrode unit forming step

Claims

一種太陽能電池製造方法，包含：一準備步驟，準備一具有第一型摻雜的半導體基板，該半導體基板具有方向相反的一第一表面及一第二表面；一第一擴散層形成步驟，於該半導體基板中形成一具有第二型摻雜的第一擴散層；及一電極單元形成步驟，形成一與該第一擴散層電連接的電極單元；其中，該第一擴散層形成步驟是先於該半導體基板的第一、二表面的其中任一表面，形成一主成份為氧化矽的第一凝膠層，並將該第一凝膠層熱硬化形成一第一遮罩層，然後對該半導體基板進行第二型摻雜以形成該第一擴散層，最後將該第一遮罩層移除，而得到該第一擴散層。A solar cell manufacturing method comprising: a preparation step of preparing a semiconductor substrate having a first type doping, the semiconductor substrate having a first surface and a second surface opposite to each other; and a first diffusion layer forming step Forming a first diffusion layer having a second type doping in the semiconductor substrate; and forming an electrode unit electrically connected to the first diffusion layer; wherein the first diffusion layer forming step is first Forming a first gel layer having a main component of cerium oxide on any one of the first and second surfaces of the semiconductor substrate, and thermally hardening the first gel layer to form a first mask layer, and then The semiconductor substrate is doped with a second type to form the first diffusion layer, and finally the first mask layer is removed to obtain the first diffusion layer.

依據申請專利範圍第1項所述之太陽能電池製造方法，其中該第一凝膠層為完全遮覆該第二表面，且該第一擴散層為靠近該第一表面的一側。The solar cell manufacturing method according to claim 1, wherein the first gel layer completely covers the second surface, and the first diffusion layer is on a side close to the first surface.

依據申請專利範圍第2項所述之太陽能電池製造方法，還包含一第二擴散層形成步驟，於該半導體基板中鄰近該第二表面的一側形成一第二擴散層，該第二擴散層形成步驟包括於該第一表面形成一主成份為氧化矽的第二凝膠層，並將該第一凝膠層熱硬化形成一第二遮罩層，接著自該第二表面對該半導體基板進行第一型雜質摻雜以形成一第二擴散層，最後移除該第二遮罩層。The method for manufacturing a solar cell according to claim 2, further comprising a second diffusion layer forming step, wherein a second diffusion layer is formed on a side of the semiconductor substrate adjacent to the second surface, the second diffusion layer The forming step includes forming a second gel layer having a main component of cerium oxide on the first surface, and thermally hardening the first gel layer to form a second mask layer, and then the semiconductor substrate from the second surface The first type impurity is doped to form a second diffusion layer, and finally the second mask layer is removed.

依據申請專利範圍第1項所述之太陽能電池製造方法，其中，該第一凝膠層為形成於該第一表面的部分區域，該第一擴散層位於該半導體基板位於靠近該第一表面的一側，並因為該第一遮罩層的阻擋效果使該第一擴散層具有一重摻雜區及一摻雜濃度低於該重摻雜區的輕摻雜區。The solar cell manufacturing method of claim 1, wherein the first gel layer is a partial region formed on the first surface, and the first diffusion layer is located on the semiconductor substrate adjacent to the first surface. One side, and because of the blocking effect of the first mask layer, the first diffusion layer has a heavily doped region and a lightly doped region having a lower doping concentration than the heavily doped region.

依據申請專利範圍第4項所述之太陽能電池製造方法，其中，該電極單元包含一覆蓋於該第一表面之主電極和複數條自該主電極向外延伸的指叉電極，且該重摻雜區被該些指叉電極遮覆。The method for manufacturing a solar cell according to claim 4, wherein the electrode unit comprises a main electrode covering the first surface and a plurality of finger electrodes extending outward from the main electrode, and the re-doping The miscellaneous area is covered by the interdigitated electrodes.

依據申請專利範圍第1項所述之太陽能電池製造方法，其中，該第一凝膠層是先在80~300℃的溫度條件進行第一階段熱處理，接著再於300~900℃的溫度條件進行第二階段熱處理，令該第一凝膠層熱硬化以形成該第一遮罩層。The method for manufacturing a solar cell according to claim 1, wherein the first gel layer is subjected to a first-stage heat treatment at a temperature of 80 to 300 ° C, and then at a temperature of 300 to 900 ° C. The second stage heat treatment causes the first gel layer to be thermally hardened to form the first mask layer.

依據申請專利範圍第1項所述之太陽能電池製造方法，其中，該第一凝膠層是以超音波噴霧、絲網印刷、噴墨印刷、或旋轉塗布方式形成於該第一表面。The solar cell manufacturing method according to claim 1, wherein the first gel layer is formed on the first surface by ultrasonic spraying, screen printing, inkjet printing, or spin coating.

依據申請專利範圍第3項所述之太陽能電池製造方法，其中，該第二凝膠層是先在80~300℃的溫度條件下進行第一階段熱處理，接著再於300~900℃的溫度條件下進行第二階段熱處理，令該第二凝膠層熱硬化以形成該第二遮罩層。The method for manufacturing a solar cell according to claim 3, wherein the second gel layer is first subjected to a first-stage heat treatment at a temperature of 80 to 300 ° C, and then at a temperature of 300 to 900 ° C. A second stage heat treatment is performed to thermally cure the second gel layer to form the second mask layer.

依據申請專利範圍第3項所述之太陽能電池製造方法，其中，該第一、二凝膠層是分別以超音波噴霧、絲網印刷、噴墨印刷、或旋轉塗布方式形成於該第一、二表面，且該第一、二遮罩層是利用氫氟酸溶液移除。The method for manufacturing a solar cell according to claim 3, wherein the first and second gel layers are respectively formed in the first by ultrasonic spraying, screen printing, inkjet printing, or spin coating. Two surfaces, and the first and second mask layers are removed using a hydrofluoric acid solution.

依據申請專利範圍第1項所述之太陽能電池製造方法，其中該第一遮罩厚度介於10-200nm。The solar cell manufacturing method according to claim 1, wherein the first mask has a thickness of 10 to 200 nm.