TW201318136A - 堆疊封裝結構 - Google Patents

堆疊封裝結構 Download PDF

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TW201318136A
TW201318136A TW101138027A TW101138027A TW201318136A TW 201318136 A TW201318136 A TW 201318136A TW 101138027 A TW101138027 A TW 101138027A TW 101138027 A TW101138027 A TW 101138027A TW 201318136 A TW201318136 A TW 201318136A
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substrate
wafer
package structure
stacked package
package
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TW101138027A
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TWI467726B (zh
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Tai-Yu Chen
Chun-Wei Chang
Chung-Hwa Wu
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Mediatek Inc
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Abstract

本發明揭示一種堆疊封裝結構。堆疊封裝結構包括：一上封裝體以及設置於其下方的一下封裝體。上封裝體包括一第一基底及裝設於第一基底上的一第一晶片。第一基底之熱導率大於70 W/(m×K)。下封裝體包括一第二基底及裝設於第二基底上的一第二晶片。第二晶片的一上表面與第一基底的一下表面熱接觸。

Description

堆疊封裝結構 相關申請之交叉引用
本申請的申請專利範圍要求2011年10月17日遞交的申請號為61/548,092的美國臨時案的優先權。在此合併參考该申請案的申請標的。
本發明係有關於一半導體封裝技術，特別是有關於一種三維(3D)堆疊封裝(package on package,PoP)結構。
隨著電子產業(例如，3C(電腦、通信及消費性電子)相關產業)的發展，已快速增加對於多功能、更具便利性及更小尺寸的裝置需求。上述需求進一步迫使增加積體電路(IC)密度。而增加積體電路密度造就了多重晶片封裝的發展，諸如封裝內封裝(package in package,PiP)及堆疊封裝(package on package,PoP)。在高效能及高積集度(integration)的需求下，將上封裝體堆疊於下封裝體上的三維堆疊封裝(3D PoP)已成為另一可接受的選擇。
PoP為一種封裝技術，可容許整合具有不同晶片功能的晶片(例如，微處理器、記憶體、邏輯或光學積體電路等)。然而，PoP相較於個別的單一晶片(chip/die)封裝來說需要更高的電源密度。因此，當電源密度增加且晶片內的半導體裝置尺寸縮小(即，IC密度增加)時，熱管理變得越來越重要。電源密度及IC密度的增加使得PoP結構 中晶片所產生的熱總量增加，而過量的熱通常會降低裝置效能，且裝置可能發生損害。
解決上述熱問題的方法之一包括提供一散熱片(heat spreader)，其與晶片進行熱接觸。然而，在PoP結構中，上封裝體的存在，妨礙了在上下封裝體之間放置散熱片，因而難以透過使用散熱片的方式來消散下封裝體所產生的熱。
因此，有必要尋求一種新的PoP結構，其能夠減輕或排除上述的問題。
有鑒於此，本發明之目的在於提供改良式的堆疊封裝結構，以改善上述堆疊封裝結構散熱的問題。
在本發明一實施例中，一種堆疊封裝結構，包括：一上封裝體，包括一第一基底及裝設於第一基底上的一第一晶片，其中第一基底之熱導率大於70 W/(m×K)；以及一下封裝體，設置於上封裝體下方，包括一第二基底及裝設於第二基底上的一第二晶片，其中第二晶片的一上表面與第一基底的一下表面熱接觸。
在本發明另一實施例中，一種堆疊封裝結構，包括：一上封裝體，包括一第一基底及裝設於第一基底上的一第一晶片，其中至少一電性浮接接墊設置於第一基底的一下表面；以及一下封裝體，設置於上封裝體下方，包括一第二基底及裝設於第二基底上的一第二晶片，其中第二晶片的一上表面與電性浮接接墊熱接觸。
本發明所提出之堆疊封裝結構，可以減輕或排除堆疊封裝結構散熱的問題。
以下說明包含了本發明實施例之製作過程與目的。然而，可輕易了解以下說明在於闡明本發明實施例之製做與使用，並非用於限定本發明的範圍。在圖式及內文中，相同或相似的部件係使用相同或相似的標號。再者，為了圖式的簡化與便利性，圖式中部件的外形及厚度得以放大。另外，未繪示或未揭露於圖式及內文中的部件係熟習技藝中慣用的部件。
請參照第1圖，其繪示根據本發明一實施例之堆疊封裝(PoP)結構剖面示意圖。在本實施例中，PoP結構包括一上封裝體150及設置於上封裝體150下方的一下封裝體250。上封裝體150包括一第一基底100及裝設於第一基底100上的一第一晶片(die)102。第一基底100係作為一封裝基底。特別的是，第一基底100也作為下封裝體250的一散熱板(heat dissipation plate)。在本實施例中，第一基底100之熱導率大於70 W/(m×K)，且可為一矽基底。複數接觸/接合墊100a及100b分別形成於第一基底100的上表面及下表面。上述接觸/接合墊100a及100b係用於第一晶片102與下封裝體250之間的電性連接。第一晶片102，例如一記憶體晶片，可包括形成於其下表面的複數接觸/接合墊102a。第一晶片102可透過習知覆晶(flip chip)方式而裝設於第一基底100上。舉例來說，第一晶片102透過 位於接觸/接合墊100a與接觸/接合墊102a之間的複數凸塊106而電性連接至第一基底100。一底膠材料104，例如環氧化物，填入於第一基底100與第一晶片102之間的空間，以保護上述凸塊106。
下封裝體250包括一第二基底200及裝設於第二基底200上的一第二晶片(die)202。在一實施例中，第二基底200可為一封裝基底。舉例來說，第二基底200可包括陶瓷基底或印刷電路板(printed circuit board,PCB)。在另一實施例中，第二基底200可包括相同於第一基底100的一基底。亦即，第二基底200之熱導率大於70 W/(m×K)，且可為一矽基底。複數接觸/接合墊200a及200b形成於第二基底200的一上表面。再者，複數接觸/接合墊200c形成於第二基底200的一下表面。上述接觸/接合墊200a及200b係用於第二晶片202與上封裝體150之間的電性連接。上述接觸/接合墊200c則連接至複數凸塊208，以將PoP結構電性連接至外部電路(未繪示)。第二晶片202可為一高功率晶片，例如一微處理器晶片。再者，第二晶片202可包括形成於其下表面的複數接觸/接合墊202a。第二晶片202可透過習知覆晶方式而裝設於第二基底200上。舉例來說，第二晶片202透過位於接觸/接合墊202a與接觸/接合墊200a之間的複數凸塊206而電性連接至第二基底200。一底膠材料204，例如環氧化物，填入於第二基底200與第二晶片202之間的空間，以保護上述凸塊206。
在本實施例中，PoP結構可更包括複數凸塊302，設置於第一基底100的接觸/接合墊100b與第二基底200的接 觸/接合墊200b之間，使第一基底100及位於其上的第一晶片102電性連接至第二基底200及位於第二基底200上的第二晶片202。
第二晶片202為高功率晶片，且在裝置操作期間可能會產生大量的熱，因此必須散除該處產生的熱。在本實施例中，第二晶片202的一上表面與第一基底100的下表面熱接觸，使散熱能夠透過第一基底100所構成的導熱路徑來完成。在一實施例中，第二晶片202可透過設置於第二晶片202與第一基底100之間的一導熱界面材料(thermal interface material,TIM)301而與第一基底100熱接觸。導熱界面材料(TIM)301可包括焊料凸塊或銅凸塊、熱脂(由填入金屬粉末的矽油所組成)、或微米銀或任何種類的相變化材料。在另一實施例中，第二晶片202可透過其與第一基底100之間的直接接觸而與第一基底100熱接觸。
請參照第2圖，其繪示根據本發明一實施例之堆疊封裝結構剖面示意圖，其中相同於第1圖的部件係使用與第1圖相同的標號並為求簡潔省略其說明。在本實施例中，第一晶片102透過一打線接合製程而裝設於第一基底100上。舉例來說，第一晶片102的下表面透過一黏著層108而貼附於第一基底100的上表面上。再者，複數接線112將第一晶片102的複數接觸/接合墊102b電性連接至第一基底100的複數接觸/接合墊100a’。在本實施例中，第一晶片102及上述接線112被一封膠材料110(例如，環氧化物)所覆蓋。
請參照第3圖，其繪示根據本發明一實施例之堆疊封 裝結構剖面示意圖，其中相同於第1圖的部件係使用與第1圖相同的標號並為求簡潔省略其說明。除了加入散熱片之外，本實施例的PoP結構相同於第1圖所示的PoP結構。上封裝體150更包括一散熱片114，其與第一晶片102的上表面熱接觸。舉例來說，散熱片114設置於第一基底100上，且覆蓋第一晶片102。散熱片114可消散第一晶片102所產生的熱。再者，散熱片114及第一基底100可構成一導熱路徑，以進一步消散第二晶片202所產生的熱。因此，相較於第1圖及第2圖所示的PoP結構，第3圖所示之PoP結構之散熱效率可進一步提升。
請參照第4圖，其繪示根據本發明一實施例之堆疊封裝結構剖面示意圖，其中相同於第1圖的部件係使用與第1圖相同的標號並為求簡潔省略其說明。本實施例中的PoP結構相似於第1圖所示的PoP結構。而不同於第1圖所示的PoP結構之處在於下封裝體250的第二晶片202內可包括複數貫穿基底之通孔(through substrate via,TSV)203。上述複數貫穿基底之通孔(TSV)203電性連接第一基底100的複數接觸/接合墊100c與第二基底200的複數接觸/接合墊200d，使第二晶片202透過複數貫穿基底之通孔203與第一基底100及/或第二基底200電性連接。在本實施例中，第二晶片202可透過位於其與第一基底100之間的導熱界面材料(未繪示)或透過其與第一基底100之間的直接接觸而與第一基底100熱接觸。
請參照第5圖，其繪示根據本發明一實施例之堆疊封裝結構剖面示意圖，其中相同於第2圖的部件係使用與第 2圖相同的標號並為求簡潔省略其說明。本實施例中的PoP結構相似於第2圖所示的PoP結構。而不同於第2圖所示的PoP結構之處在於下封裝體250的第二晶片202內可包括複數貫穿基底之通孔203。再者，複數貫穿基底之通孔203電性連接第一基底100的複數接觸/接合墊100c與第二基底200的複數接觸/接合墊200d，使第二晶片202透過複數貫穿基底之通孔203與第一基底100及/或第二基底200電性連接。同樣地，第二晶片202可透過位於其與第一基底100之間的導熱界面材料(未繪示)與第一基底100熱接觸，或透過與第一基底100直接接觸而與第一基底100熱接觸。
請參照第6圖，其繪示根據本發明一實施例之堆疊封裝結構剖面示意圖，其中相同於第3圖的部件係使用與第3圖相同的標號並為求簡潔省略其說明。本實施例中的PoP結構相似於第3圖所示的PoP結構。而不同於第3圖所示的PoP結構之處在於下封裝體250的第二晶片202內可包括複數貫穿基底之通孔203。再者，複數貫穿基底之通孔203電性連接第一基底100的複數接觸/接合墊100c與第二基底200的複數接觸/接合墊200d，使第二晶片202透過複數貫穿基底之通孔203與第一基底100及/或第二基底200電性連接。同樣地，第二晶片202可透過位於其與第一基底100之間的導熱界面材料(未繪示)或透過其與第一基底100之間的直接接觸而與第一基底100熱接觸。根據上述實施例，由於PoP結構的上封裝體中封裝基底可形成一導熱路徑，因此上封裝體與下封裝體之間可在未放置任何 散熱片的情形下，消散PoP結構的下封裝體所產生的熱。因此，可防止裝置效能降低並避免裝置發生損害。再者，由於可在PoP結構的上封裝體上設置一額外的散熱片，因此可透過散熱片進一步消散PoP結構中晶片所產生的熱，進而提升散熱效率。
請參照第7圖，其繪示根據本發明一實施例之堆疊封裝結構剖面示意圖，其中相同於第1圖的部件係使用與第1圖相同的標號並為求簡潔省略其說明。本實施例中的PoP結構其相似於第1圖所示的PoP結構，不同於第1圖所示的PoP結構之處在於上封裝體350的第一基底300可包括一印刷電路板(PCB)，且作為封裝基底，其中至少三銅層埋設於印刷電路板內的不同層位。在一實施例中，這些銅層包括複數接觸/接合墊300a、複數接觸/接合墊300b及一散熱板300c。一或多個電性浮接接墊304設置於第一基底300的下表面，其中電性浮接接墊304透過形成於第一基底300內的連接窗(Via)300d連接上述銅層的其中一者(例如，散熱板300c)。在一實施例中，第二晶片202的上表面與至少一電性浮接接墊304熱接觸，以透過由電性浮接接墊304、連接窗300d及散熱板300c所構成的導熱路徑進行散熱。在另一實施例中，第二晶片202可透過位於其與電性浮接接墊304之間的一導熱界面材料(未繪示)，例如焊料凸塊或銅凸塊、熱脂(由填入金屬粉末的矽油所組成)、或微米銀或任何種類的相變化材料，而與電性浮接接墊304熱接觸。在另一實施例中，第二晶片202可透過其與電性浮接接墊304之間的直接接觸而與電性浮 接接墊304熱接觸。
上述接觸/接合墊300a及300b係用於第二晶片202與上封裝體350之間的電性連接。再者，上述複數接觸/接合墊300a也用於第一晶片102與下封裝體250之間的電性連接。再者，PoP結構更包括複數凸塊302，設置於第一基底300的接觸/接合墊300b與第二基底200的接觸/接合墊200b之間，使第一基底300及位於其上的第一晶片102電性連接至第二基底200及位於第二基底200上的第二晶片202。
請參照第8圖，其繪示根據本發明一實施例之堆疊封裝結構剖面示意圖，其中分別相同於第2圖及第7圖的部件係使用分別與第2圖及第7圖相同的標號並為求簡潔省略其說明。不同於第2圖所示的PoP結構，第8圖中PoP結構的上封裝體350的第一基底300可為印刷電路板，且作為封裝基底，如第7圖所示的第一基底300。再者，複數接線112將第一晶片102的複數接觸/接合墊102b電性連接至第一基底300的複數接觸/接合墊300e。在本實施例中，第二晶片202的上表面與至少一電性浮接接墊304熱接觸，以透過由電性浮接接墊304、連接窗300d及散熱板300c所構成的導熱路徑進行散熱。
請參照第9圖，其繪示根據本發明一實施例之堆疊封裝結構剖面示意圖，其中分別相同於第3圖及第7圖的部件係使用分別與第3圖及第7圖相同的標號並為求簡潔省略其說明。不同於第3圖所示的PoP結構，第9圖中PoP結構的上封裝體350的第一基底300可為印刷電路板，且 作為封裝基底，如第7圖所示的第一基底300。在本實施例中，第二晶片202的上表面與至少一電性浮接接墊304熱接觸，以透過由電性浮接接墊304、連接窗300d、散熱板300c及散熱片114所構成的導熱路徑進行散熱。
另外，在一實施例中，第7、8及9圖所示的第二晶片202內可分別包括複數貫穿基底之通孔(未繪示)，如第4、5及6圖所示的第二晶片202，使第二晶片202透過複數貫穿基底之通孔而與第一基底300及/第二基底200電性連接。
根據上述實施例，由於PoP結構的上封裝體中散熱板及電性浮接接墊可形成一導熱路徑，因此上封裝體與下封裝體之間可在未放置任何散熱片的情形下，消散PoP結構的下封裝體所產生的熱。因此，可防止裝置效能降低並避免裝置發生損害。再者，由於可在PoP結構的上封裝體上設置一額外的散熱片，因此可透過散熱片進一步消散PoP結構中晶片所產生的熱，進而提升散熱效率。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100、300‧‧‧第一基底
100a、100a’、100b、100c、102a、102b、200a、200b、200c、200d、202a、300a、300b、300e‧‧‧接觸/接合墊
102‧‧‧第一晶片
104、204‧‧‧底膠材料
106、206、208、302‧‧‧凸塊
108‧‧‧黏著層
110‧‧‧封膠材料
112‧‧‧接線
114‧‧‧散熱片
150、350‧‧‧上封裝體
200‧‧‧第二基底
202‧‧‧第二晶片
203‧‧‧貫穿基底之通孔
250‧‧‧下封裝體
300c‧‧‧散熱板
300d‧‧‧連接窗
301‧‧‧導熱界面材料
304‧‧‧電性浮接接墊
第1至9圖係分別繪示根據本發明各個不同實施例之堆疊封裝結構剖面示意圖。
100‧‧‧第一基底
100a、100b、102a、200a、200b、200c、202a‧‧‧接觸/接合墊
102‧‧‧第一晶片
104、204‧‧‧底膠材料
106、206、208、302‧‧‧凸塊
150‧‧‧上封裝體
200‧‧‧第二基底
202‧‧‧第二晶片
250‧‧‧下封裝體
301‧‧‧導熱界面材料

Claims (19)

  1. 一種堆疊封裝結構，包括：一上封裝體，包括一第一基底及裝設於該第一基底上的一第一晶片，其中該第一基底之熱導率大於70 W/(m×K)；以及一下封裝體，設置於該上封裝體下方，包括一第二基底及裝設於該第二基底上的一第二晶片，其中該第二晶片的一上表面與該第一基底的一下表面熱接觸。
  2. 如申請專利範圍第1項所述之堆疊封裝結構，其中該上封裝體更包括一散熱片，該散熱片與該第一晶片的一上表面熱接觸。
  3. 如申請專利範圍第1項所述之堆疊封裝結構，其中該第一晶片透過複數凸塊或接線而電性連接至該第一基底。
  4. 如申請專利範圍第1項所述之堆疊封裝結構，其中該第一基底為矽基底。
  5. 如申請專利範圍第1項所述之堆疊封裝結構，其中該第二晶片內包括複數貫穿基底之通孔，使該第二晶片透過該等貫穿基底之通孔而與該第一基底及/或該第二基底電性連接。
  6. 如申請專利範圍第1項所述之堆疊封裝結構，其中該第二晶片透過該第二晶片與該第一基底之間的一導熱界面材料或透過該第二晶片與該第一基底之間的直接接觸而與該第一基底熱接觸。
  7. 如申請專利範圍第1項所述之堆疊封裝結構，其中 該第二晶片透過該第二晶片與該第一基底之間的一導熱界面材料而與該第一基底熱接觸，該導熱界面材料包括焊料凸塊、銅凸塊、熱脂或微米銀。
  8. 如申請專利範圍第1項所述之堆疊封裝結構，更包括複數凸塊，設置於該第一基底與該第二基底之間，使該第一基底電性連接至該第二基底。
  9. 如申請專利範圍第1項所述之堆疊封裝結構，其中該第二基底之熱導率大於70 W/(m×K)。
  10. 如申請專利範圍第1項所述之堆疊封裝結構，其中該第二基底為矽基底。
  11. 一種堆疊封裝結構，包括：一上封裝體，包括一第一基底及裝設於該第一基底上的一第一晶片，其中至少一電性浮接接墊設置於該第一基底的一下表面；以及一下封裝體，設置於該上封裝體下方，包括一第二基底及裝設於該第二基底上的一第二晶片，其中該第二晶片的一上表面與該電性浮接接墊熱接觸。
  12. 如申請專利範圍第11項所述之堆疊封裝結構，其中該上封裝體更包括一散熱片，其與該第一晶片的一上表面熱接觸。
  13. 如申請專利範圍第11項所述之堆疊封裝結構，其中該第一晶片透過複數凸塊或接線而電性連接至該第一基底。
  14. 如申請專利範圍第在11項所述之堆疊封裝結構，其中該第一基底為印刷電路板。
  15. 如申請專利範圍第14項所述之堆疊封裝結構，其中至少三銅層埋設於該印刷電路板內的不同層位，且其中該電性浮接接墊連接至該等銅層的其中一者。
  16. 如申請專利範圍第11項所述之堆疊封裝結構，其中該第二晶片內包括複數貫穿基底之通孔，使該第二晶片透過該等貫穿基底之通孔而與該第一基底及/或該第二基底電性連接。
  17. 如申請專利範圍第11項所述之堆疊封裝結構，其中該第二晶片透過該第二晶片與該電性浮接接墊之間的一導熱界面材料或透過該第二晶片與該電性浮接接墊之間的直接接觸而與該電性浮接接墊熱接觸。
  18. 如申請專利範圍第11項所述之堆疊封裝結構，其中該第二晶片透過該第二晶片與該電性浮接接墊之間的一導熱界面材料而與該電性浮接接墊熱接觸，該導熱界面材料包括焊料凸塊、銅凸塊、熱脂或微米銀。
  19. 如申請專利範圍第11項所述之堆疊封裝結構，更包括複數凸塊，設置於該第一基底與該第二基底之間，使該第一基底電性連接至該第二基底。
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