TW201314786A - Semiconductor process - Google Patents
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Description
本發明是有關於一種半導體製程，且特別是有關於一種鰭狀場效電晶體(fin-type field effect transistor,FinFET)的製造方法。The present invention relates to a semiconductor process, and more particularly to a method of fabricating a fin-type field effect transistor (FinFET).
隨著半導體製程技術的快速發展，為了增進元件的速度與效能，整個電路元件的尺寸必須不斷縮小，並持續不斷地提升元件的積集度(degree of integration)。一般而言，在半導體均趨向縮小電路元件的設計發展下，電晶體的通道區長度亦具有逐漸縮短的趨勢，以加快元件的操作速度。然而，如此容易造成電晶體產生嚴重漏電流(leakage current)、短通道效應(short channel effect)以及導通電流(turn-on current)下降等問題。With the rapid development of semiconductor process technology, in order to improve the speed and performance of components, the size of the entire circuit components must be continuously reduced, and the degree of integration of components is continuously improved. In general, in the development of semiconductors tending to reduce circuit components, the length of the channel region of the transistor has also been gradually shortened to speed up the operation speed of components. However, it is easy to cause problems such as a severe leakage current, a short channel effect, and a decrease in turn-on current of the transistor.
因此，為了克服上述問題，近年來業界提出多重閘極(multigate)結構，其係利用閘極將通道區包夾起來，使得整個通道區皆受到閘極電場之影響，而得以增加元件之導通電流，並減少漏電流。Therefore, in order to overcome the above problems, in recent years, the industry has proposed a multigate structure, which uses a gate to sandwich a channel region, so that the entire channel region is affected by the gate electric field, thereby increasing the conduction current of the device. And reduce leakage current.
本發明提供一種半導體製程，可縮小圖案線寬並同時確保圖案轉移的精確性。The present invention provides a semiconductor process that reduces the line width of a pattern while ensuring the accuracy of pattern transfer.
本發明提出一種半導體製程，其包括下列步驟。於基底上形成多個虛擬圖案(dummy pattern)。於基底上順應性地形成罩幕材料層，以覆蓋虛擬圖案，其中罩幕材料層與虛擬圖案具有不同的蝕刻率。移除部分罩幕材料層，以於各虛擬圖案的側壁上形成罩幕層，其中罩幕層的上表面與虛擬圖案的上表面實質上為共平面。移除虛擬圖案。以罩幕層作為罩幕，移除部分基底，以於基底中形成交替排列的多個鰭狀結構及多個溝渠。移除罩幕層。The present invention provides a semiconductor process that includes the following steps. A plurality of dummy patterns are formed on the substrate. A mask material layer is conformally formed on the substrate to cover the dummy pattern, wherein the mask material layer and the dummy pattern have different etch rates. A portion of the mask material layer is removed to form a mask layer on the sidewalls of each of the dummy patterns, wherein the upper surface of the mask layer is substantially coplanar with the upper surface of the dummy pattern. Remove the virtual pattern. A mask layer is used as a mask to remove a portion of the substrate to form a plurality of fin structures and a plurality of trenches alternately arranged in the substrate. Remove the mask layer.
在本發明之一實施例中，上述形成罩幕層的方法包括對罩幕材料層實質上平行於水平面的表面進行改質處理，使罩幕材料層具有改質部分及未改質部分；以及移除改質部分。In one embodiment of the invention, the method of forming a mask layer includes modifying a surface of the mask material layer substantially parallel to a horizontal plane such that the mask material layer has a modified portion and an unmodified portion; Remove the modified part.
在本發明之一實施例中，上述之改質處理包括垂直離子植入製程。垂直離子植入製程例如是於改質部分植入碳離子。In an embodiment of the invention, the upgrading process includes a vertical ion implantation process. The vertical ion implantation process is, for example, the implantation of carbon ions in the modified portion.
在本發明之一實施例中，上述形成罩幕層的方法包括下列步驟。於相鄰兩虛擬圖案之間的罩幕材料層上形成光阻層，至少暴露出位於虛擬圖案上的部分罩幕材料層。以光阻層作為罩幕，移除部分罩幕材料層，以暴露出虛擬圖案的頂表面。以光阻層作為罩幕，對暴露出的罩幕材料層表面進行改質處理，使罩幕材料層具有改質部分及未改質部分，其中改質部分及未改質部分具有不同的蝕刻率。以改質部分作為罩幕，移除光阻層及其下方之部分罩幕材料層。In an embodiment of the invention, the above method of forming a mask layer comprises the following steps. A photoresist layer is formed on the mask material layer between the adjacent two dummy patterns to expose at least a portion of the mask material layer on the dummy pattern. With the photoresist layer as a mask, a portion of the mask material layer is removed to expose the top surface of the dummy pattern. The photoresist layer is used as a mask to modify the surface of the exposed mask material layer, so that the mask material layer has a modified portion and an unmodified portion, wherein the modified portion and the unmodified portion have different etchings. rate. The modified portion is used as a mask to remove the photoresist layer and a portion of the mask material layer therebelow.
在本發明之一實施例中，上述之改質處理包括氧化處理。氧化處理例如是進行氧電漿製程或氧離子植入製程。In an embodiment of the invention, the upgrading process includes an oxidation treatment. The oxidation treatment is, for example, an oxygen plasma process or an oxygen ion implantation process.
在本發明之一實施例中，上述在形成罩幕材料層之前，更包括於虛擬圖案上分別形成硬罩幕層，且罩幕材料層覆蓋硬罩幕層。In an embodiment of the invention, before forming the mask material layer, the hard mask layer is further formed on the dummy pattern, and the mask material layer covers the hard mask layer.
在本發明之一實施例中，上述形成罩幕層的方法包括下列步驟。於相鄰兩虛擬圖案之間的罩幕材料層上形成介電層，介電層的頂面高度與位於虛擬圖案上的罩幕材料層的頂面高度實質上等高。移除位於虛擬圖案上之部分罩幕材料層及部分介電層，以暴露出虛擬圖案的頂表面。以剩餘的介電層作為罩幕，對暴露出的罩幕材料層表面進行改質處理，使罩幕材料層具有改質部分及未改質部分，其中改質部分及未改質部分具有不同的蝕刻率。以改質部分作為罩幕，移除介電層及其下方之部分罩幕材料層。In an embodiment of the invention, the above method of forming a mask layer comprises the following steps. A dielectric layer is formed on the mask material layer between the adjacent two dummy patterns, and the top surface height of the dielectric layer is substantially equal to the height of the top surface of the mask material layer on the dummy pattern. A portion of the mask material layer and a portion of the dielectric layer on the dummy pattern are removed to expose the top surface of the dummy pattern. The surface of the exposed mask material layer is modified by using the remaining dielectric layer as a mask, so that the mask material layer has a modified portion and an unmodified portion, wherein the modified portion and the unmodified portion have different Etching rate. The modified portion is used as a mask to remove the dielectric layer and a portion of the mask material layer therebelow.
在本發明之一實施例中，上述之改質處理包括氧化處理。氧化處理例如是進行氧電漿製程或氧離子植入製程。In an embodiment of the invention, the upgrading process includes an oxidation treatment. The oxidation treatment is, for example, an oxygen plasma process or an oxygen ion implantation process.
在本發明之一實施例中，上述在形成罩幕材料層之前，更包括於虛擬圖案上分別形成硬罩幕層，且罩幕材料層覆蓋硬罩幕層。In an embodiment of the invention, before forming the mask material layer, the hard mask layer is further formed on the dummy pattern, and the mask material layer covers the hard mask layer.
在本發明之一實施例中，上述之基底為塊狀(bulk)基底。半導體製程更包括於溝渠中形成多個隔離結構，且隔離結構的頂表面低於鰭狀結構的頂表面。In an embodiment of the invention, the substrate is a bulk substrate. The semiconductor process further includes forming a plurality of isolation structures in the trench, and the top surface of the isolation structure is lower than the top surface of the fin structure.
在本發明之一實施例中，上述之基底包括底層、絕緣層以及主體層，絕緣層配置於底層與主體層之間。形成鰭狀結構的方法包括以罩幕層作為罩幕，移除部分主體層，而暴露出部分絕緣層。In an embodiment of the invention, the substrate comprises a bottom layer, an insulating layer and a body layer, and the insulating layer is disposed between the bottom layer and the body layer. A method of forming a fin structure includes removing a portion of the body layer with a mask layer as a mask to expose a portion of the insulating layer.
在本發明之一實施例中，半導體製程更包括於基底上形成覆蓋鰭狀結構之閘極。In an embodiment of the invention, the semiconductor process further includes forming a gate covering the fin structure on the substrate.
在本發明之一實施例中，半導體製程於各鰭狀結構的末端分別形成源極及汲極。In one embodiment of the invention, the semiconductor process forms a source and a drain, respectively, at the ends of each fin structure.
基於上述，本發明之半導體製程在虛擬圖案的側壁上形成罩幕層，因此可藉由控制罩幕材料層的沈積膜厚，來縮小罩幕層的圖案線寬。再者，形成於虛擬圖案側壁上之罩幕層的上表面與虛擬圖案的上表面實質上共平面，因此罩幕層具有良好的圖案輪廓，而能夠確保利用此罩幕層轉移至鰭狀結構的圖案精確性。Based on the above, the semiconductor process of the present invention forms a mask layer on the sidewall of the dummy pattern, so that the pattern line width of the mask layer can be reduced by controlling the deposited film thickness of the mask material layer. Furthermore, the upper surface of the mask layer formed on the sidewall of the dummy pattern is substantially coplanar with the upper surface of the dummy pattern, so that the mask layer has a good pattern profile, and it is ensured that the mask layer is transferred to the fin structure. The accuracy of the pattern.
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.
本發明之半導體製程可用於形成鰭狀場效電晶體(FinFET)結構。鰭狀場效電晶體例如是使一個或多個鰭狀結構(fin)在電晶體的源極區與汲極區之間延伸，並使閘極跨越鰭狀結構而形成。而且，藉由鰭狀結構與閘極接觸的表面區域可決定鰭狀場效電晶體的有效通道(effective channel)。The semiconductor process of the present invention can be used to form a fin field effect transistor (FinFET) structure. The fin field effect transistor is formed, for example, by extending one or more fin structures between the source region and the drain region of the transistor and causing the gate to cross the fin structure. Moreover, the effective channel of the fin field effect transistor can be determined by the surface area of the fin structure in contact with the gate.
以三閘極(tri-gate)架構為例，鰭狀場效電晶體的通道除了位於鰭狀結構的頂表面部分之外，更包括位於鰭狀結構的側壁部分，因而能夠大幅增加通道寬度。一般而言，由於電晶體的驅動電流與通道寬度成正比，因此可提升鰭狀場效電晶體的驅動電流。如此一來，相較於平面電晶體，鰭狀場效電晶體具有增加的通道寬度，因而在積體電路中可利用較小的晶片區域並獲得更高的驅動電流。Taking a tri-gate architecture as an example, the fin field effect transistor has a channel portion in addition to the top surface portion of the fin structure, and further includes a sidewall portion of the fin structure, thereby greatly increasing the channel width. In general, since the driving current of the transistor is proportional to the channel width, the driving current of the fin field effect transistor can be improved. As a result, the fin field effect transistor has an increased channel width compared to a planar transistor, so that a smaller wafer area can be utilized in the integrated circuit and a higher drive current can be obtained.
接下來將以剖面圖的方式一一說明本發明之實施例。須注意的是，以下所述之流程主要是為了詳細說明本發明之半導體製程在實際應用於鰭狀場效電晶體中形成鰭狀結構(fin)的方法，以使熟習此項技術者能夠據以實施，但並非用以限定本發明之範圍。至於電晶體中的其它構件、配置位置及形成方式等，均可依所屬技術領域中具有通常知識者所知的技術製作，而不限於下述實施例所述。Next, an embodiment of the present invention will be described in a sectional view. It should be noted that the flow described below is mainly for explaining in detail the method for forming a fin structure (fin) in a semiconductor process of the present invention, which is practically applied to a fin field effect transistor, so that those skilled in the art can It is intended to be implemented, but not to limit the scope of the invention. Other members in the transistor, arrangement positions, formation manners, and the like can be made according to techniques known to those skilled in the art, and are not limited to the embodiments described below.
第一實施例First embodiment
圖1A至圖1F是依照本發明第一實施例之半導體製程的剖面示意圖。圖1G為圖1F所示之結構佈局上視的示意圖，為簡化圖式，其中僅繪示出鰭狀結構、閘極、源極、汲極等主要構件。1A through 1F are schematic cross-sectional views showing a semiconductor process in accordance with a first embodiment of the present invention. 1G is a schematic view of the structure of the structure shown in FIG. 1F. In order to simplify the drawing, only the main components such as a fin structure, a gate, a source, and a drain are shown.
請參照圖1A，提供基底100，其例如是塊狀(bulk)晶圓。須注意的是，雖然圖1A是以塊狀晶圓為例來進行說明，但在其他實施例中，基底100亦可置換為絕緣層上覆矽(silicon on insulator,SOI)晶圓。構成基底100的材料可選自於由矽、摻雜鍺的矽(Ge-doped Si)、摻雜碳的矽(C-doped Si)、矽化鍺(SiGe)、鍺(Ge)以及三五族半導體(如砷化鎵(GaAs)、砷化銦鎵(InGaAs)、銻化銦(InSb)、砷化銦(InAs)、銻化鎵(GaSb)、磷化銦(InP))所組成之群組。接著，選擇性地於基底100上形成墊層102，用以增加隨後形成之虛擬圖案104的附著力。墊層102的材料例如是氧化矽，其形成方法可採用熱氧化法或化學氣相沈積。Referring to FIG. 1A, a substrate 100 is provided, which is, for example, a bulk wafer. It should be noted that although FIG. 1A is illustrated by taking a bulk wafer as an example, in other embodiments, the substrate 100 may be replaced by a silicon on insulator (SOI) wafer. The material constituting the substrate 100 may be selected from ruthenium, Ge-doped Si, C-doped Si, SiGe, Ge (Ge), and San 5 A group of semiconductors such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium antimonide (InSb), indium arsenide (InAs), gallium antimonide (GaSb), and indium phosphide (InP) group. Next, a pad layer 102 is selectively formed on the substrate 100 to increase the adhesion of the subsequently formed dummy pattern 104. The material of the underlayer 102 is, for example, ruthenium oxide, and the formation method thereof may be thermal oxidation or chemical vapor deposition.
之後，於墊層102上形成多個虛擬圖案104。虛擬圖案104例如是彼此平行排列且沿著垂直於圖面的方向D1延伸之條狀圖案。虛擬圖案104的材料可選用未經摻雜或經摻雜的多晶矽、氧化矽、氮化矽、氮氧化矽、碳化矽、碳氮化矽(SiCN)、氮化硼(BN)、低介電常數材料(low K)、超低介電常數材料(ultra low-K,ULK)或其他的含碳材料等。虛擬圖案104的形成方法可以是先在墊層102上形成上述材料膜層後，再利用微影、蝕刻製程以圖案化光阻層為罩幕來圖案化上述材料膜層。Thereafter, a plurality of dummy patterns 104 are formed on the underlayer 102. The dummy patterns 104 are, for example, strip patterns that are arranged in parallel to each other and extend in a direction D1 perpendicular to the plane of the drawing. The material of the dummy pattern 104 may be selected from undoped or doped polycrystalline germanium, cerium oxide, tantalum nitride, hafnium oxynitride, tantalum carbide, niobium carbonitride (SiCN), boron nitride (BN), low dielectric. Constant material (low K), ultra low dielectric constant material (ultra low-K, ULK) or other carbonaceous materials. The dummy pattern 104 may be formed by first forming the material film layer on the underlayer 102, and then patterning the material film layer by using a lithography and etching process to pattern the photoresist layer as a mask.
接著，於基底100上順應性地形成罩幕材料層106，以覆蓋虛擬圖案104、墊層102及基底100。罩幕材料層106的材料例如是未經摻雜或經摻雜的多晶矽、氧化矽、氮化矽、氮氧化矽、碳化矽、碳氮化矽(SiCN)、氮化硼(BN)、低介電常數材料(low K)、超低介電常數材料(ultra low-K,ULK)或其他的含碳材料等。在此說明的是，罩幕材料層106與虛擬圖案104具有不同的蝕刻率，即兩者間具有蝕刻高選擇比。舉例而言，當虛擬圖案104的材料為多晶矽時，則可以選擇以原子層沈積法(atomic layer deposition,ALD)所形成之氮化矽層作為罩幕材料層106，但本發明並不以此為限。Next, a mask material layer 106 is conformally formed on the substrate 100 to cover the dummy pattern 104, the pad layer 102, and the substrate 100. The material of the mask material layer 106 is, for example, undoped or doped polycrystalline germanium, cerium oxide, tantalum nitride, hafnium oxynitride, tantalum carbide, niobium carbonitride (SiCN), boron nitride (BN), low. Dielectric constant material (low K), ultra low dielectric constant material (ultra low-K, ULK) or other carbonaceous materials. It is noted herein that the mask material layer 106 and the dummy pattern 104 have different etch rates, i.e., have an etch high selection ratio therebetween. For example, when the material of the dummy pattern 104 is polysilicon, the layer of tantalum nitride formed by atomic layer deposition (ALD) may be selected as the mask material layer 106, but the present invention does not Limited.
請參照圖1B，對罩幕材料層106實質上平行於水平面的表面進行改質處理T1，而使罩幕材料層106具有改質部分106a與未改質部分106b。改質處理T1可以採用離子植入製程來進行，所植入之離子例如是碳(C)。此外，離子植入製程例如是以0°傾斜角來進行的垂直植入，且至少能夠使位於虛擬圖案104上的部分罩幕材料層106進行改質即可。Referring to FIG. 1B, the surface of the mask material layer 106 substantially parallel to the horizontal surface is subjected to a reforming process T1, and the mask material layer 106 has a modified portion 106a and an unmodified portion 106b. The upgrading treatment T1 can be carried out using an ion implantation process, such as carbon (C). In addition, the ion implantation process is, for example, vertical implantation at an inclination angle of 0°, and at least a portion of the mask material layer 106 located on the dummy pattern 104 can be modified.
請參照圖1C，移除罩幕材料層106的改質部分106a，而剩餘的未改質部分106b則形成罩幕層108。罩幕層108例如是以條狀結構的形式形成於每個虛擬圖案104的兩側壁上，且暴露出虛擬圖案104的頂表面。在一實施例中，罩幕層108的上表面會與虛擬圖案104的上表面實質上為共平面。移除改質部分106a的方法例如是進行非等向性乾式蝕刻製程。Referring to FIG. 1C, the modified portion 106a of the mask material layer 106 is removed, and the remaining unmodified portion 106b forms the mask layer 108. The mask layer 108 is formed, for example, in the form of a strip structure on both sidewalls of each of the dummy patterns 104, and exposes the top surface of the dummy pattern 104. In an embodiment, the upper surface of the mask layer 108 may be substantially coplanar with the upper surface of the dummy pattern 104. The method of removing the modified portion 106a is, for example, an anisotropic dry etching process.
特別說明的是，當利用離子植入製程對罩幕材料層106進行改質處理T1時，由於垂直植入的離子會轟擊到實質上平行於水平面的罩幕材料層106頂部，因而使其結構變得較鬆散。如此一來，在進行乾式蝕刻時，經離子轟擊或經植入碳(C)之改質部分106a的移除速率會遠高於未經離子轟擊之未改質部分106b。因此，在進行乾式蝕刻製程期間，幾乎僅會移除改質部分106a而留下虛擬圖案104兩側壁上的罩幕層108(未改質部分106b)。In particular, when the masking material layer 106 is subjected to the reforming process T1 by the ion implantation process, the vertically implanted ions are bombarded to the top of the masking material layer 106 substantially parallel to the horizontal plane, thereby structuring the structure. Become looser. As a result, the rate of removal of the modified portion 106a by ion bombardment or implantation of carbon (C) during the dry etching is much higher than that of the unmodified portion 106b which is not ion bombarded. Therefore, during the dry etching process, only the modified portion 106a is removed leaving the mask layer 108 (unmodified portion 106b) on both sidewalls of the dummy pattern 104.
請參照圖1D，移除虛擬圖案104，而使墊層102上僅殘留罩幕層108。移除虛擬圖案104的方法例如是進行濕式蝕刻製程，其可以使用包含經稀釋的氫氟酸(DHF)、氨水或氫氧化四甲基銨(TMAH)等的蝕刻液。之後，以罩幕層108作為罩幕，移除暴露的墊層102及部分基底100，而於基底100中形成多個交替排列的鰭狀結構110及溝渠112。在此實施例中，鰭狀結構110及溝渠112例如是彼此平行排列且沿著垂直於圖面的方向D1延伸。移除未被罩幕層108所遮蔽之墊層102及部分基底100的方法例如是進行非等向性之乾式蝕刻法。Referring to FIG. 1D, the dummy pattern 104 is removed, leaving only the mask layer 108 on the pad layer 102. The method of removing the dummy pattern 104 is, for example, a wet etching process using an etching solution containing diluted hydrofluoric acid (DHF), ammonia water or tetramethylammonium hydroxide (TMAH). Thereafter, the exposed pad layer 102 and a portion of the substrate 100 are removed by using the mask layer 108 as a mask, and a plurality of alternately arranged fin structures 110 and trenches 112 are formed in the substrate 100. In this embodiment, the fin structure 110 and the trench 112 are, for example, arranged in parallel with each other and extending in a direction D1 perpendicular to the plane of the drawing. The method of removing the underlayer 102 and a portion of the substrate 100 that is not covered by the mask layer 108 is, for example, an anisotropic dry etching method.
請參照圖1E，於溝渠112中形成隔離結構114，且隔離結構114的頂表面低於鰭狀結構110的頂表面。隔離結構114的材料例如是氧化矽。在一實施例中，隔離結構114的形成方法可以先利用化學氣相沈積法形成覆蓋罩幕層108且填滿溝渠112之氧化矽層，接著移除部分氧化矽層直到暴露出鰭狀結構110的上部側壁，其中移除部分氧化矽層例如是依序採用化學機械研磨法(CMP)及乾式回蝕刻法來進行。Referring to FIG. 1E , an isolation structure 114 is formed in the trench 112 , and a top surface of the isolation structure 114 is lower than a top surface of the fin structure 110 . The material of the isolation structure 114 is, for example, ruthenium oxide. In an embodiment, the isolation structure 114 may be formed by first forming a cap layer 108 by chemical vapor deposition and filling the hafnium oxide layer of the trench 112, and then removing a portion of the hafnium oxide layer until the fin structure 110 is exposed. The upper sidewall, wherein the portion of the ruthenium oxide layer is removed, for example, is sequentially subjected to chemical mechanical polishing (CMP) and dry etchback.
請參照圖1F及圖1G，移除罩幕層108及墊層102，而暴露出鰭狀結構110的頂表面。之後，在基底100上形成閘極116。閘極116例如是具有沿著方向D2延伸之條狀圖案，而覆蓋部分鰭狀結構110及隔離結構114。在此實施例中，閘極116的延伸方向D2與鰭狀結構110的延伸方向D1不同，其例如是彼此垂直。閘極116的材料例如是多晶矽、金屬、合金、矽化金屬等導體或上述材料之組合。此外，在閘極116與鰭狀結構110之間更包括形成有閘介電層(未繪示)，且閘介電層的配置及形成方式可依照實際的製程需求加以變化。接著，在鰭狀結構110的兩末端分別形成源極118S及汲極118D，而大致完成鰭狀場效電晶體結構的製作。在一實施例中，為了進一步增加鰭狀場效電晶體的通道寬度，也可以使多個鰭狀結構110的兩末端連結至同一源極及同一汲極。Referring to FIGS. 1F and 1G, the mask layer 108 and the pad layer 102 are removed to expose the top surface of the fin structure 110. Thereafter, a gate 116 is formed on the substrate 100. The gate 116 is, for example, a stripe pattern extending along the direction D2 to cover a portion of the fin structure 110 and the isolation structure 114. In this embodiment, the extending direction D2 of the gate 116 is different from the extending direction D1 of the fin structure 110, which are, for example, perpendicular to each other. The material of the gate 116 is, for example, a conductor such as polysilicon, a metal, an alloy, a metal halide, or a combination thereof. In addition, a gate dielectric layer (not shown) is further formed between the gate 116 and the fin structure 110, and the configuration and formation manner of the gate dielectric layer can be changed according to actual process requirements. Next, a source electrode 118S and a drain electrode 118D are respectively formed at both ends of the fin structure 110, and the fabrication of the fin field effect transistor structure is substantially completed. In an embodiment, in order to further increase the channel width of the fin field effect transistor, both ends of the plurality of fin structures 110 may be connected to the same source and the same drain.
由於罩幕層108(罩幕材料層106的未改質部分106b)是形成在各虛擬圖案104兩側壁上，因此可藉由控制罩幕材料層106的沈積膜厚，來決定罩幕層108的圖案線寬。換言之，控制罩幕材料層106的沈積條件而減少其膜厚，可以獲得圖案線寬較小的罩幕層108，而利用罩幕層108所定義之鰭狀結構110的線寬也會隨之減小。舉例而言，如圖1C及圖1D所示，當微影製程的極限是30 nm時，利用微影製程來定義各虛擬圖案104的圖案線寬W1則約為30 nm。此時，將罩幕材料層106的沈積膜厚控制在約為20 nm，則可以使形成在虛擬圖案104側壁上的罩幕層108具有約20 nm的圖案線寬W2，因此即可獲得圖案線寬小於光學極限的罩幕層108。如此一來，以罩幕層108作為罩幕所定義的鰭狀結構110也會具有約20 nm的圖案線寬W3，因而可進一步提高元件積集度。Since the mask layer 108 (the unmodified portion 106b of the mask material layer 106) is formed on both sidewalls of each of the dummy patterns 104, the mask layer 108 can be determined by controlling the deposited film thickness of the mask material layer 106. The pattern line width. In other words, by controlling the deposition conditions of the mask material layer 106 to reduce the film thickness thereof, the mask layer 108 having a smaller pattern line width can be obtained, and the line width of the fin structure 110 defined by the mask layer 108 is also followed. Reduced. For example, as shown in FIG. 1C and FIG. 1D, when the limit of the lithography process is 30 nm, the pattern line width W1 of each dummy pattern 104 is defined by the lithography process to be about 30 nm. At this time, by controlling the deposited film thickness of the mask material layer 106 to about 20 nm, the mask layer 108 formed on the sidewall of the dummy pattern 104 can have a pattern line width W2 of about 20 nm, so that a pattern can be obtained. The mask layer 108 has a line width that is less than the optical limit. As a result, the fin structure 110 defined by the mask layer 108 as a mask also has a pattern line width W3 of about 20 nm, so that the component integration can be further improved.
值得一提的是，一般而言，即使是對材料層進行非等向性蝕刻製程，其亦會在其他方向上對材料層造成些許損耗，而影響剩餘材料層的輪廓。因此，若是直接對未經改質處理的罩幕材料層106進行非等向性蝕刻製程，則殘留於虛擬圖案104側壁上的剩餘罩幕材料層則容易形成上部具有圓化現象(rounding)之間隙壁(spacer)結構。後續利用個別圖案線寬不均勻之間隙壁結構作為罩幕層來定義鰭狀結構，通常會導致所形成之鰭狀結構的圖案線寬有顯著變動而影響製程裕度(process window)。然而，在此實施例中，用來定義鰭狀結構110之罩幕層108是預先對罩幕材料層106頂部進行改質處理T1再移除改質部分106a而形成，因此罩幕層108的上部並不會產生類似間隙壁之圓化現象而具有良好的圖案輪廓，可有助於改善轉移至鰭狀結構110的圖案精確性。It is worth mentioning that, in general, even if the material layer is anisotropically etched, it will cause some loss to the material layer in other directions, and affect the contour of the remaining material layer. Therefore, if the mask material layer 106 that has not been modified is directly subjected to an anisotropic etching process, the remaining mask material layer remaining on the sidewall of the dummy pattern 104 is likely to form an upper portion having a rounding effect. Spacer structure. Subsequent use of the spacer pattern with uneven line width of individual patterns as the mask layer to define the fin structure generally results in a significant variation in the pattern line width of the formed fin structure and affects the process window. However, in this embodiment, the mask layer 108 for defining the fin structure 110 is formed by previously modifying the top portion of the mask material layer 106 and then removing the modified portion 106a, so that the mask layer 108 is The upper portion does not produce a rounding phenomenon like the gap wall and has a good pattern profile, which can contribute to improving the pattern accuracy of the transfer to the fin structure 110.
第二實施例Second embodiment
圖2A至圖2D是依照本發明第二實施例之半導體製程的剖面示意圖。圖2A主要是繪示接續上述實施例圖1A之後的步驟，且相同的構件則使用相同的標號並省略其說明。2A through 2D are schematic cross-sectional views showing a semiconductor process in accordance with a second embodiment of the present invention. FIG. 2A mainly illustrates the steps subsequent to FIG. 1A of the above embodiment, and the same components are denoted by the same reference numerals and the description thereof will be omitted.
請參照圖2A，於基底100上順應性地形成罩幕材料層106之後，罩幕材料層106會在相鄰虛擬圖案104之間形成有凹陷202。接著，於相鄰兩虛擬圖案104之間的罩幕材料層106上形成光阻層204，且光阻層204至少使位於虛擬圖案104上的罩幕材料層106被暴露出來。詳言之，光阻層204填入罩幕材料層106的凹陷202，且光阻層204的頂面高度與虛擬圖案104的頂面高度例如是約略等高，而使罩幕材料層106實質上平行於水平面的表面被暴露出來。光阻層204的形成方法例如是先於罩幕材料層106上塗佈光阻材料並使光阻材料填滿凹陷202，然後進行回蝕刻製程移除位於凹陷202以外的光阻材料，並控制所形成之光阻層204的頂面高度位置。Referring to FIG. 2A, after the mask material layer 106 is conformally formed on the substrate 100, the mask material layer 106 is formed with a recess 202 between the adjacent dummy patterns 104. Next, a photoresist layer 204 is formed on the mask material layer 106 between the adjacent two dummy patterns 104, and the photoresist layer 204 exposes at least the mask material layer 106 on the dummy pattern 104. In detail, the photoresist layer 204 fills the recess 202 of the mask material layer 106, and the top surface height of the photoresist layer 204 and the top surface height of the dummy pattern 104 are, for example, approximately equal, and the mask material layer 106 is substantially The surface parallel to the horizontal plane is exposed. The photoresist layer 204 is formed by, for example, coating a photoresist material on the mask material layer 106 and filling the photoresist material with the recess 202, and then performing an etch back process to remove the photoresist material located outside the recess 202 and controlling The top surface height position of the formed photoresist layer 204.
請參照圖2B，以光阻層204作為罩幕，移除被暴露出的部分罩幕材料層106。而剩餘的罩幕材料層206暴露出虛擬圖案104的頂表面。在一實施例中，剩餘的罩幕材料層206的上表面會與虛擬圖案104的上表面實質上為共平面。移除部分罩幕材料層106的方法例如是進行乾式或濕式蝕刻製程。Referring to FIG. 2B, the photoresist layer 204 is used as a mask to remove the exposed portion of the mask material layer 106. The remaining mask material layer 206 exposes the top surface of the dummy pattern 104. In an embodiment, the upper surface of the remaining mask material layer 206 may be substantially coplanar with the upper surface of the dummy pattern 104. The method of removing a portion of the mask material layer 106 is, for example, a dry or wet etch process.
之後，以光阻層204作為罩幕，對暴露出的罩幕材料層206表面進行改質處理T2，而使罩幕材料層206具有改質部分206a與未改質部分206b。值得一提的是，罩幕材料層206的改質部分206a及未改質部分206b具有不同的蝕刻率。在對罩幕材料層206進行改質處理T2的同時，由於光阻層204也會使虛擬圖案104暴露出來，因此虛擬圖案104例如是亦會形成改質部分104a與未改質部分104b。Thereafter, the surface of the exposed mask material layer 206 is subjected to a reforming process T2 using the photoresist layer 204 as a mask, and the mask material layer 206 has a modified portion 206a and an unmodified portion 206b. It is worth mentioning that the modified portion 206a and the unmodified portion 206b of the mask material layer 206 have different etching rates. While the masking material layer 206 is subjected to the reforming process T2, since the photoresist layer 204 also exposes the dummy pattern 104, the dummy pattern 104, for example, also forms the modified portion 104a and the unmodified portion 104b.
上述之改質處理T2例如是氧化處理，其可採用氧電漿或氧離子植入來進行。舉例而言，當虛擬圖案104的材料為多晶矽且罩幕材料層206的材料為氮化矽時，則改質部分104a會成為氧化矽且改質部分206a會成為氮氧化矽，但本發明並不以此為限。在一實施例中，對暴露出的罩幕材料層206表面進行改質處理T2可以使用含氧電漿進行氧化處理。在另一實施例中，對暴露出的罩幕材料層206表面進行改質處理T2可以進行垂直式氧離子植入。The above-described upgrading treatment T2 is, for example, an oxidation treatment, which can be carried out by using oxygen plasma or oxygen ion implantation. For example, when the material of the dummy pattern 104 is polysilicon and the material of the mask material layer 206 is tantalum nitride, the modified portion 104a becomes yttrium oxide and the modified portion 206a becomes yttrium oxynitride, but the present invention Not limited to this. In one embodiment, the surface of the exposed mask material layer 206 is subjected to a modification process T2 which may be oxidized using an oxygen-containing plasma. In another embodiment, the surface of the exposed mask material layer 206 is subjected to a modification process T2 for vertical oxygen ion implantation.
請參照圖2C，移除光阻層204，且移除位於光阻層204下方之部分罩幕材料層206(未改質部分206b)。位於各虛擬圖案104兩側壁上之改質部分206a及剩餘的未改質部分206b則形成罩幕層208。罩幕層208的形成方法例如是以改質部分104a及改質部分206a作為罩幕來對暴露出的罩幕材料層206進行乾式蝕刻製程，以移除光阻層204下方之未改質部分206b而暴露出墊層102。Referring to FIG. 2C, the photoresist layer 204 is removed, and a portion of the mask material layer 206 (unmodified portion 206b) under the photoresist layer 204 is removed. The modified portion 206a and the remaining unmodified portion 206b on both sidewalls of each of the dummy patterns 104 form a mask layer 208. The mask layer 208 is formed by performing a dry etching process on the exposed mask material layer 206 by using the modified portion 104a and the modified portion 206a as a mask to remove the unmodified portion under the photoresist layer 204. The mat 102 is exposed to 206b.
請參照圖2D，移除虛擬圖案104，而使墊層102上僅殘留罩幕層208。移除虛擬圖案104的方法可以使用包含經稀釋的氫氟酸(DHF)、氨水或氫氧化四甲基銨(TMAH)等蝕刻液進行濕式蝕刻製程，且虛擬圖案104的改質部分104a及未改質部分104b例如是在同一步驟中被移除。接著，以罩幕層208作為罩幕，移除暴露的墊層102及部分基底100，而於基底100中形成多個交替排列的鰭狀結構210及溝渠212。然後，於溝渠212中形成隔離結構214，且隔離結構214的頂表面低於鰭狀結構210的頂表面。Referring to FIG. 2D, the dummy pattern 104 is removed, leaving only the mask layer 208 on the pad layer 102. The method of removing the dummy pattern 104 may be performed by a wet etching process using an etching solution containing diluted hydrofluoric acid (DHF), ammonia water or tetramethylammonium hydroxide (TMAH), and the modified portion 104a of the dummy pattern 104 and The unmodified portion 104b is removed, for example, in the same step. Next, the exposed pad layer 102 and a portion of the substrate 100 are removed by using the mask layer 208 as a mask, and a plurality of alternately arranged fin structures 210 and trenches 212 are formed in the substrate 100. An isolation structure 214 is then formed in the trench 212, and the top surface of the isolation structure 214 is lower than the top surface of the fin structure 210.
在完成圖2D所示之結構之後，移除鰭狀結構210上方之罩幕層208及墊層102，並形成閘極、源極及汲極，即可獲得如圖1F及圖1G所示之鰭狀場效電晶體結構。這些步驟的細節為此領域具有通常知識者可依前述實施例知其應用及變化，故於此不再贅述。After the structure shown in FIG. 2D is completed, the mask layer 208 and the pad layer 102 above the fin structure 210 are removed, and the gate, the source, and the drain are formed, as shown in FIG. 1F and FIG. 1G. Fin field effect transistor structure. The details of these steps are generally applicable to those skilled in the art, and their applications and variations are known in the foregoing embodiments, and thus will not be described again.
第三實施例Third embodiment
圖3A至圖3D是依照本發明第三實施例之半導體製程的剖面示意圖。圖3A至圖3D所示之製程步驟及順序與圖2A至圖2D所示之方法大致相似，因此相同的構件則使用相同的標號並省略其說明。3A through 3D are schematic cross-sectional views showing a semiconductor process in accordance with a third embodiment of the present invention. The process steps and the sequence shown in FIGS. 3A to 3D are substantially similar to those of the method shown in FIGS. 2A to 2D, and therefore the same members are denoted by the same reference numerals and the description thereof will be omitted.
請參照圖3A，此實施例所述之方法與第二實施例所述之方法兩者之間的差異主要是在於：在形成罩幕材料層106之前，先於虛擬圖案104上方分別形成多個硬罩幕層302。因此，後續形成之罩幕材料層106例如是覆蓋硬罩幕層302、墊層102及基底100。硬罩幕層302的材料例如是氮化矽或氧化矽。虛擬圖案104及硬罩幕層302的形成方法可以是藉由在墊層102上依序沈積虛擬圖案104的材料及硬罩幕層302的材料之後，再利用微影、蝕刻製程來圖案化上述材料膜層。之後，於相鄰虛擬圖案104之間的罩幕材料層106上形成光阻層204，以至少使位於虛擬圖案104上的罩幕材料層106被暴露出來。Referring to FIG. 3A, the difference between the method described in this embodiment and the method described in the second embodiment is mainly: forming a plurality of layers above the dummy pattern 104 before forming the mask material layer 106. Hard mask layer 302. Thus, the subsequently formed mask material layer 106 covers, for example, the hard mask layer 302, the pad layer 102, and the substrate 100. The material of the hard mask layer 302 is, for example, tantalum nitride or tantalum oxide. The dummy pattern 104 and the hard mask layer 302 may be formed by sequentially depositing the material of the dummy pattern 104 and the material of the hard mask layer 302 on the pad layer 102, and then patterning the above by using a lithography or etching process. Material film layer. Thereafter, a photoresist layer 204 is formed over the mask material layer 106 between adjacent dummy patterns 104 to expose at least the mask material layer 106 on the dummy pattern 104.
請參照圖3B，以光阻層204作為罩幕，移除被暴露出的部分罩幕材料層106，使剩餘的罩幕材料層306暴露出硬罩幕層302的頂表面。在一實施例中，剩餘的罩幕材料層306的上表面會與硬罩幕層302的上表面實質上為共平面。Referring to FIG. 3B, with the photoresist layer 204 as a mask, the exposed portion of the mask material layer 106 is removed, exposing the remaining mask material layer 306 to the top surface of the hard mask layer 302. In an embodiment, the upper surface of the remaining mask material layer 306 may be substantially coplanar with the upper surface of the hard mask layer 302.
之後，以光阻層204作為罩幕，對暴露出的罩幕材料層306表面及硬罩幕層302進行改質處理T2。在經過改質處理T2後，罩幕材料層306會形成改質部分306a與未改質部分306b。在一實施例中，若罩幕材料層306的材料為氮化矽，則改質部分306a則會形成氮氧化矽，因而使得改質部分306a及未改質部分306b是具有不同的蝕刻率。此時，當硬罩幕層302的材料為氮化矽時，經改質的硬罩幕層302a則例如是氮氧化矽；當硬罩幕層302的材料為氧化矽時，經改質的硬罩幕層302a則例如是氧化矽。Thereafter, the surface of the exposed mask material layer 306 and the hard mask layer 302 are subjected to a reforming process T2 using the photoresist layer 204 as a mask. After the reforming process T2, the mask material layer 306 forms the modified portion 306a and the unmodified portion 306b. In one embodiment, if the material of the mask material layer 306 is tantalum nitride, the modified portion 306a forms niobium oxynitride, thus causing the modified portion 306a and the unmodified portion 306b to have different etching rates. At this time, when the material of the hard mask layer 302 is tantalum nitride, the modified hard mask layer 302a is, for example, niobium oxynitride; when the material of the hard mask layer 302 is tantalum oxide, the modified The hard mask layer 302a is, for example, tantalum oxide.
請參照圖3C，以改質部分206a及經改質的硬罩幕層302a作為罩幕，移除光阻層204以及位於光阻層204下方之部分罩幕材料層306(未改質部分306b)，而暴露出墊層102。因此，經改質的硬罩幕層302a側壁上之改質部分306a及殘留於虛擬圖案104側壁上之未改質部分306b則形成罩幕層308。Referring to FIG. 3C, the modified portion 206a and the modified hard mask layer 302a are used as masks to remove the photoresist layer 204 and a portion of the mask material layer 306 under the photoresist layer 204 (unmodified portion 306b). ), while the mat 102 is exposed. Therefore, the modified portion 306a on the sidewall of the modified hard mask layer 302a and the unmodified portion 306b remaining on the sidewall of the dummy pattern 104 form the mask layer 308.
請參照圖3D，移除經改質的硬罩幕層302a及虛擬圖案104，而使墊層102上僅殘留罩幕層308。移除經改質的硬罩幕層302a及虛擬圖案104的方法例如是濕式蝕刻製程，且可在同一步驟中同時移除經改質的硬罩幕層302a及虛擬圖案104。在一實施例中，由於罩幕層308中的改質部分306a與經改質的硬罩幕層302a例如是具有相近的蝕刻率，因此在濕式蝕刻步驟中也可以一併移除改質部分306a，而使墊層102上僅殘留未改質部分306b。Referring to FIG. 3D, the modified hard mask layer 302a and the dummy pattern 104 are removed, leaving only the mask layer 308 on the mat layer 102. The method of removing the modified hard mask layer 302a and the dummy pattern 104 is, for example, a wet etching process, and the modified hard mask layer 302a and the dummy pattern 104 can be simultaneously removed in the same step. In an embodiment, since the modified portion 306a in the mask layer 308 has a similar etching rate to the modified hard mask layer 302a, the modification may be removed in the wet etching step. Portion 306a leaves only unmodified portion 306b on mat layer 102.
接著，以剩餘的未改質部分306b作為罩幕，移除暴露的墊層102及部分基底100，而於基底100中形成多個交替排列的鰭狀結構310及溝渠312。然後，於溝渠312中形成隔離結構314，且隔離結構314的頂表面低於鰭狀結構310的頂表面。之後，以類似上述方法移除鰭狀結構310上方之剩餘的未改質部分306b及墊層102並形成閘極、源極及汲極，從而獲得鰭狀場效電晶體結構。Next, with the remaining unmodified portion 306b as a mask, the exposed pad layer 102 and a portion of the substrate 100 are removed, and a plurality of alternately arranged fin structures 310 and trenches 312 are formed in the substrate 100. An isolation structure 314 is then formed in the trench 312, and the top surface of the isolation structure 314 is lower than the top surface of the fin structure 310. Thereafter, the remaining unmodified portion 306b and the pad layer 102 over the fin structure 310 are removed and a gate, a source, and a drain are formed in a manner similar to that described above, thereby obtaining a fin field effect transistor structure.
第四實施例Fourth embodiment
圖4A至圖4D是依照本發明第四實施例之半導體製程的剖面示意圖。圖4A至圖4D所示之製程步驟及順序與圖2A至圖2D所示之方法相似，因此相同的構件則使用相同的標號並省略其說明。4A through 4D are schematic cross-sectional views showing a semiconductor process in accordance with a fourth embodiment of the present invention. The process steps and the sequence shown in FIGS. 4A to 4D are similar to those of the processes shown in FIGS. 2A to 2D, and therefore the same members are denoted by the same reference numerals and the description thereof will be omitted.
請參照圖4A，此實施例所述之方法與第二實施例所述之方法兩者之間的差異主要是在於：本實施例於相鄰虛擬圖案104之間的罩幕材料層106上形成介電層404來取代圖2A之光阻層204。詳言之，介電層404填入罩幕材料層106的凹陷202，且介電層404的頂面高度與位於虛擬圖案104上之罩幕材料層106的頂面高度例如是約略等高，而暴露出罩幕材料層106的頂表面。介電層404的材料例如是氧化矽或其他合適之材料。介電層404的形成方法可先於罩幕材料層106上沈積氧化矽材料並使其填滿凹陷202，然後進行化學機械研磨製程來移除位於凹陷202以外的氧化矽材料，在研磨過程中並以位於虛擬圖案104上之罩幕材料層106的頂面作為研磨中止層。Referring to FIG. 4A, the difference between the method described in this embodiment and the method described in the second embodiment is mainly that the present embodiment is formed on the mask material layer 106 between the adjacent dummy patterns 104. A dielectric layer 404 is substituted for the photoresist layer 204 of FIG. 2A. In detail, the dielectric layer 404 fills the recess 202 of the mask material layer 106, and the top surface height of the dielectric layer 404 is approximately equal to the height of the top surface of the mask material layer 106 on the dummy pattern 104, for example. The top surface of the masking material layer 106 is exposed. The material of the dielectric layer 404 is, for example, ruthenium oxide or other suitable material. The dielectric layer 404 can be formed by depositing a yttria material on the mask material layer 106 and filling the recess 202, and then performing a chemical mechanical polishing process to remove the yttrium oxide material outside the recess 202 during the grinding process. The top surface of the mask material layer 106 on the dummy pattern 104 is used as a polishing stop layer.
請參照圖4B，至少移除位於虛擬圖案104上之部分罩幕材料層106，使剩餘的罩幕材料層406暴露出虛擬圖案104的頂表面。移除位於虛擬圖案104上之部分罩幕材料層106的方法例如是以虛擬圖案104的頂面作為研磨中止層進行化學機械研磨製程。在一實施例中，在移除位於虛擬圖案104上之部分罩幕材料層106的期間，部分介電層404亦會同時被移除，因而使得剩餘的罩幕材料層406、介電層404的上表面會與虛擬圖案104的上表面實質上為共平面。Referring to FIG. 4B, at least a portion of the mask material layer 106 on the dummy pattern 104 is removed such that the remaining mask material layer 406 exposes the top surface of the dummy pattern 104. The method of removing a portion of the mask material layer 106 on the dummy pattern 104 is performed, for example, by a chemical mechanical polishing process using the top surface of the dummy pattern 104 as a polishing stop layer. In an embodiment, during removal of a portion of the mask material layer 106 on the dummy pattern 104, portions of the dielectric layer 404 are also removed simultaneously, thereby allowing the remaining mask material layer 406, dielectric layer 404. The upper surface will be substantially coplanar with the upper surface of the dummy pattern 104.
之後，以剩餘的介電層404作為罩幕，對暴露出的罩幕材料層406及虛擬圖案104表面進行改質處理T2。在經過改質處理T2之後，罩幕材料層406會形成改質部分406a與未改質部分406b，虛擬圖案104會形成改質部分104a與未改質部分104b。值得一提的是，當罩幕材料層406的材料為氮化矽時，則改質部分406a會成為氮氧化矽，因而與未改質部分406b具有不同的蝕刻率。此外，當虛擬圖案104的材料為多晶矽時，則改質部分104a會成為氧化矽。Thereafter, the exposed mask layer 406 and the surface of the dummy pattern 104 are subjected to a modification process T2 using the remaining dielectric layer 404 as a mask. After the reforming process T2, the mask material layer 406 forms the modified portion 406a and the unmodified portion 406b, and the dummy pattern 104 forms the modified portion 104a and the unmodified portion 104b. It is worth mentioning that when the material of the mask material layer 406 is tantalum nitride, the modified portion 406a becomes yttrium oxynitride and thus has a different etching rate from the unmodified portion 406b. Further, when the material of the dummy pattern 104 is polysilicon, the modified portion 104a becomes yttrium oxide.
請參照圖4C，以改質部分406a作為罩幕，移除介電層404及其下方之部分罩幕材料層406(未改質部分406b)，而暴露出墊層102。在一實施例中，由於介電層404與虛擬圖案104中的改質部分104a例如是具有相近的蝕刻率，因此在移除介電層404及其下方之部分罩幕材料層406也會一併移除改質部分104a，而暴露出未改質部分104b的頂表面。而殘留於未改質部分104b側壁上之未改質部分406b及改質部分406a則形成罩幕層408。Referring to FIG. 4C, with the modified portion 406a as a mask, the dielectric layer 404 and a portion of the mask material layer 406 (unmodified portion 406b) below it are removed to expose the pad layer 102. In an embodiment, since the dielectric layer 404 and the modified portion 104a in the dummy pattern 104 have similar etching rates, for example, the dielectric layer 404 and a portion of the mask material layer 406 below it are also removed. The modified portion 104a is removed to expose the top surface of the unmodified portion 104b. The unmodified portion 406b and the modified portion 406a remaining on the sidewall of the unmodified portion 104b form a mask layer 408.
請參照圖4D，移除虛擬圖案104的未改質部分104b，而使墊層102上僅殘留罩幕層408。之後，以罩幕層408作為罩幕，移除暴露的墊層102及部分基底100，而於基底100中形成多個交替排列的鰭狀結構410及溝渠412。然後，於溝渠412中形成隔離結構414，且隔離結構414的頂表面低於鰭狀結構410的頂表面。接著，以類似前述實施例所述之方法移除鰭狀結構410上方之罩幕層408及墊層102並形成閘極、源極及汲極，從而獲得鰭狀場效電晶體結構。Referring to FIG. 4D, the unmodified portion 104b of the dummy pattern 104 is removed, leaving only the mask layer 408 on the pad layer 102. Thereafter, the exposed pad layer 102 and a portion of the substrate 100 are removed by using the mask layer 408 as a mask, and a plurality of alternately arranged fin structures 410 and trenches 412 are formed in the substrate 100. An isolation structure 414 is then formed in the trench 412, and the top surface of the isolation structure 414 is lower than the top surface of the fin structure 410. Next, the mask layer 408 and the pad layer 102 over the fin structure 410 are removed and the gate, source and drain are formed in a manner similar to that described in the previous embodiment, thereby obtaining a fin field effect transistor structure.
第五實施例Fifth embodiment
圖5A至圖5D是依照本發明第五實施例之半導體製程的剖面示意圖。圖5A至圖5D所示之製程步驟及順序與圖2A至圖2D所示之方法相似，因此相同的構件則使用相同的標號並省略其說明。5A through 5D are schematic cross-sectional views showing a semiconductor process in accordance with a fifth embodiment of the present invention. The process steps and the sequence shown in FIGS. 5A to 5D are similar to those of the processes shown in FIGS. 2A to 2D, and therefore the same members are denoted by the same reference numerals and the description thereof will be omitted.
請參照圖5A，此實施例所述之方法與第二實施例所述之方法兩者之間的差異主要是在於：本實施例是採用絕緣層上覆矽(SOI)基底500來取代圖2A之塊狀基底100。詳言之，基底500例如是主要由底層500a、絕緣層500b以及用以製作元件的主體層500c所構成。絕緣層500b配置於底層500a與主體層500c之間，以減少耗電並提高元件效能。底層500a以及主體層500c的材料例如是相同或不同的半導體材料，其可選自矽、摻雜鍺的矽(Ge-doped Si)、摻雜碳的矽(C-doped Si)、矽化鍺(SiGe)、鍺(Ge)或砷化鎵(GaAs)、砷化銦鎵(InGaAs)、銻化銦(InSb)、砷化銦(InAs)、銻化鎵(GaSb)、磷化銦(InP)等三五族半導體。絕緣層500b例如是埋入式氧化層(buried oxide,BOX)，其材料可為氧化矽或是其他絕緣材料。之後，以類似圖2A所述之方式，於主體層500c上依序形成墊層102、虛擬圖案104、罩幕材料層106以及光阻層204。Referring to FIG. 5A, the difference between the method described in this embodiment and the method described in the second embodiment is mainly: this embodiment uses an insulating layer overlying cerium (SOI) substrate 500 instead of FIG. 2A. The block substrate 100. In detail, the substrate 500 is mainly composed of, for example, a bottom layer 500a, an insulating layer 500b, and a body layer 500c for fabricating components. The insulating layer 500b is disposed between the underlayer 500a and the body layer 500c to reduce power consumption and improve device performance. The material of the bottom layer 500a and the body layer 500c is, for example, the same or different semiconductor material, which may be selected from the group consisting of germanium, germanium-doped germanium (Ge-doped Si), carbon-doped germanium (C-doped Si), germanium telluride ( SiGe), germanium (Ge) or gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium antimonide (InSb), indium arsenide (InAs), gallium antimonide (GaSb), indium phosphide (InP) Waiting for three or five semiconductors. The insulating layer 500b is, for example, a buried oxide (BOX), and the material thereof may be yttrium oxide or other insulating material. Thereafter, the pad layer 102, the dummy pattern 104, the mask material layer 106, and the photoresist layer 204 are sequentially formed on the body layer 500c in a manner similar to that described in FIG. 2A.
請參照圖5B，以光阻層204作為罩幕，移除位於虛擬圖案104上之部分罩幕材料層106，並對剩餘的罩幕材料層206表面進行改質處理T2，而形成改質部分206a與未改質部分206b。Referring to FIG. 5B, the photoresist layer 204 is used as a mask to remove a portion of the mask material layer 106 on the dummy pattern 104, and the surface of the remaining mask material layer 206 is subjected to a modification process T2 to form a modified portion. 206a and unmodified portion 206b.
請參照圖5C，以改質部分104a及改質部分206a作為罩幕，移除光阻層204及其下方之部分未改質部分206b，而於虛擬圖案104兩側壁上形成罩幕層208。Referring to FIG. 5C, the modified portion 104a and the modified portion 206a are used as masks to remove the photoresist layer 204 and a portion of the unmodified portion 206b below it, and a mask layer 208 is formed on both sidewalls of the dummy pattern 104.
請參照圖5D，在移除虛擬圖案104之後，以罩幕層208作為罩幕，移除暴露的墊層102及部分主體層500c，而於基底500中形成多個溝渠512並暴露出部分絕緣層500b。經圖案化之主體層500c因而形成與溝渠512交替排列之鰭狀結構510。之後，移除罩幕層208及墊層102，而暴露出鰭狀結構510的頂表面。Referring to FIG. 5D, after the dummy pattern 104 is removed, the exposed pad layer 102 and a portion of the body layer 500c are removed by using the mask layer 208 as a mask, and a plurality of trenches 512 are formed in the substrate 500 to expose partial insulation. Layer 500b. The patterned body layer 500c thus forms a fin structure 510 that is alternately arranged with the trenches 512. Thereafter, the mask layer 208 and the pad layer 102 are removed to expose the top surface of the fin structure 510.
特別說明的是，由於在此實施例中是採用絕緣層上覆矽(SOI)基底500，因此在圖案化主體層500c以形成鰭狀結構510之後，不需要在溝渠512中另行形成隔離結構。換言之，如圖5D所示，位於鰭狀結構510下方之絕緣層500b即可作為隔離結構之用。然後，以類似前述實施例所述之方法形成閘極、源極及汲極，而完成鰭狀場效電晶體結構的製作。In particular, since the insulating layer overlying cerium (SOI) substrate 500 is employed in this embodiment, after the patterned body layer 500c is formed to form the fin structure 510, it is not necessary to separately form the isolation structure in the trench 512. In other words, as shown in FIG. 5D, the insulating layer 500b under the fin structure 510 can be used as an isolation structure. Then, the gate, the source and the drain are formed in a manner similar to that described in the foregoing embodiments, and the fabrication of the fin field effect transistor structure is completed.
須注意的是，雖然第三實施例是以在虛擬圖案上形成硬罩幕層為例且第五實施例是以絕緣層上覆矽(SOI)基底為例來進行說明，但本發明並不限於此。在其他可行之實施例中，也可以進一步在虛擬圖案上形成硬罩幕層，或是將塊狀基底置換成絕緣層上覆矽(SOI)基底。換言之，本發明並未對上述各實施例之間的部分置換或結合加以限制，因而於此技術領域具有通常知識者當可由前述實施例知其變化及應用，故於此不再贅述。It should be noted that although the third embodiment is exemplified by forming a hard mask layer on a dummy pattern and the fifth embodiment is described by taking an insulating layer overlying (SOI) substrate as an example, the present invention does not. Limited to this. In other possible embodiments, the hard mask layer may be further formed on the dummy pattern, or the bulk substrate may be replaced by an insulating layer overlying (SOI) substrate. In other words, the present invention does not limit the partial replacement or combination between the above embodiments. Therefore, those skilled in the art can change and apply the above embodiments, and thus will not be described again.
綜上所述，本發明實施例之半導體製程藉由對罩幕材料層表面進行改質處理，而在虛擬圖案的側壁上形成與虛擬圖案上表面共平面之罩幕層。因此，罩幕層的上部並不會產生類似間隙壁之圓化現象，而具有良好的圖案輪廓。如此一來，利用此罩幕層來定義鰭狀結構可獲得較小圖案線寬且不易產生差異，而能夠提升轉移至鰭狀結構的圖案精確性。In summary, the semiconductor process of the embodiment of the present invention forms a mask layer coplanar with the upper surface of the dummy pattern on the sidewall of the dummy pattern by modifying the surface of the mask material layer. Therefore, the upper portion of the mask layer does not have a rounding phenomenon like the gap wall, but has a good pattern outline. In this way, the use of the mask layer to define the fin structure can obtain a smaller pattern line width and is less likely to cause a difference, and can improve the pattern accuracy of the transfer to the fin structure.
此外，本發明之半導體製程能夠輕易地與現有的鰭狀場效電晶體製程相整合，製程簡單且可大幅提升後續形成之元件效能。In addition, the semiconductor process of the present invention can be easily integrated with existing fin field effect transistor processes, and the process is simple and can greatly improve the performance of subsequently formed components.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
100、500．．．基底100, 500. . . Base
102．．．墊層102. . . Cushion
104．．．虛擬圖案104. . . Virtual pattern
104a、106a、206a、306a、406a．．．改質部分104a, 106a, 206a, 306a, 406a. . . Modified part
104b、106b、206b、306b、406b．．．未改質部分104b, 106b, 206b, 306b, 406b. . . Unmodified part
106、206、306、406．．．罩幕材料層106, 206, 306, 406. . . Mask material layer
108、208、308、408．．．罩幕層108, 208, 308, 408. . . Mask layer
110、210、310、410、510．．．鰭狀結構110, 210, 310, 410, 510. . . Fin structure
112、212、312、412、512．．．溝渠112, 212, 312, 412, 512. . . ditch
114、214、314、414．．．隔離結構114, 214, 314, 414. . . Isolation structure
116．．．閘極116. . . Gate
118D．．．汲極118D. . . Bungee
118S．．．源極118S. . . Source
202．．．凹陷202. . . Depression
204．．．光阻層204. . . Photoresist layer
302．．．硬罩幕層302. . . Hard mask layer
404．．．介電層404. . . Dielectric layer
500a．．．底層500a. . . Bottom layer
500b．．．絕緣層500b. . . Insulation
500c．．．主體層500c. . . Main layer
D1、D2．．．方向D1, D2. . . direction
T1、T2．．．改質處理T1, T2. . . Modification
W1、W2、W3．．．圖案線寬W1, W2, W3. . . Pattern line width
圖1A至圖1F是依照本發明第一實施例之半導體製程的剖面示意圖。1A through 1F are schematic cross-sectional views showing a semiconductor process in accordance with a first embodiment of the present invention.
圖1G為圖1F所示之結構佈局的上視示意圖。1G is a top plan view of the structural layout shown in FIG. 1F.
圖2A至圖2D是依照本發明第二實施例之半導體製程的剖面示意圖。2A through 2D are schematic cross-sectional views showing a semiconductor process in accordance with a second embodiment of the present invention.
圖3A至圖3D是依照本發明第三實施例之半導體製程的剖面示意圖。3A through 3D are schematic cross-sectional views showing a semiconductor process in accordance with a third embodiment of the present invention.
圖4A至圖4D是依照本發明第四實施例之半導體製程的剖面示意圖。4A through 4D are schematic cross-sectional views showing a semiconductor process in accordance with a fourth embodiment of the present invention.
圖5A至圖5D是依照本發明第五實施例之半導體製程的剖面示意圖。5A through 5D are schematic cross-sectional views showing a semiconductor process in accordance with a fifth embodiment of the present invention.
100．．．基底100. . . Base
102．．．墊層102. . . Cushion
104．．．虛擬圖案104. . . Virtual pattern
106．．．罩幕材料層106. . . Mask material layer
106a．．．改質部分106a. . . Modified part
106b．．．未改質部分106b. . . Unmodified part
T1．．．改質處理T1. . . Modification
Claims (18)
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| TW100134603A TWI518792B (en) | 2011-09-26 | 2011-09-26 | Semiconductor process |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI575564B (en) * | 2013-04-10 | 2017-03-21 | 聯華電子股份有限公司 | Method for manufacturing semiconductor structures |
| TWI700745B (en) * | 2016-03-13 | 2020-08-01 | 美商應用材料股份有限公司 | Methods and apparatus for selective dry etch |
-
2011
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI575564B (en) * | 2013-04-10 | 2017-03-21 | 聯華電子股份有限公司 | Method for manufacturing semiconductor structures |
| TWI700745B (en) * | 2016-03-13 | 2020-08-01 | 美商應用材料股份有限公司 | Methods and apparatus for selective dry etch |
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| Publication number | Publication date |
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| TWI518792B (en) | 2016-01-21 |
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