TW201304414A - Sub-threshold voltage circuit with multiple channel lengths - Google Patents

Abstract

The present invention provides a sub-threshold voltage circuit with multiple channel lengths, which comprises a plurality of logic gates electrically connected with each other in a predetermined manner. These logic gates are composed of a plurality of PMOS transistors and a plurality of NMOS transistors for forming a plurality of signal paths. These signal paths are respectively used to define at least one critical signal path and a plurality of general signal paths. The channel length of the logic gates located on the plurality of general signal paths is the minimum channel length in the transistor manufacturing process. The logic gate located on the at least one critical signal path is a transistor (PMOS or NMOS) with anti-short-channel effect, and has a channel length larger than the minimum channel length in the transistor manufacturing process, and thus defined as a large channel length. Accordingly, the present invention can have the advantages of both good performance and not-too-large current leakage, and also maintain the circuit area within a suitable level during the integrated circuit layout process.

Description

多通道長度之次臨界電壓電路Multi-channel length sub-threshold voltage circuit

本發明係與電子電路有關，特別是指一種多通道長度之次臨界電壓電路。The present invention relates to electronic circuits, and more particularly to a multi-channel length sub-threshold voltage circuit.

當數位電路操作在次臨界(sub-threshold)電壓區域時，電晶體臨界電壓(V_T)和電晶體通道長度(L)有特殊的反短通道效應(Reverse-Short-Channel-Effect;RSCE)關係。反短通道效應指的是當通道變長時，電晶體臨界電壓會反而下降而產生使汲極電流(I_D)增加的現象。此現象之所以發生，是由於電晶體之通道區域會使用非均勻濃度參雜(non-uniform doping)以解決汲極引發的屏障降低效應(drain-included-barrier-lowering;DIBL)，並降低漏電流-此即所謂的靠近源極/汲極區域的高低參雜(halo doping)分佈。When the digital circuit operates in the sub-threshold voltage region, the transistor threshold voltage (V _T ) and the transistor channel length (L) have a special reverse-channel-Effect (RSCE). relationship. The anti-short channel effect means that when the channel becomes longer, the threshold voltage of the transistor will fall instead and the drain current (I _D ) will increase. This phenomenon occurs because the channel region of the transistor uses non-uniform doping to solve the drain-included-barrier-lowering (DIBL) and reduce leakage. Current - This is the so-called halo doping distribution close to the source/drain region.

在傳統的積體電路(IC)的電路設計中，所有的邏輯閘均擁有製程所允許的最小通道長度(L_min)，以減少電路的使用面積。另一方面，部分的邏輯閘之通道寬度(W)會有不同的放大程度，以提供不同的負載驅動能力。第五圖所示的電路80是傳統利用製程所允許的最小通道長度L_min之邏輯閘的電路設計，其所有的邏輯閘均擁有最小通道長度L_min，然而每一邏輯閘都可以有不同大小的推動力。若需要愈大的推動力，則須使用愈大寬度的電晶體。例如反向器101,102,103就是具有不同驅動能力的邏輯閘，反向器101具有一個單位的推動力，反向器102具有二個單位的推動力，而反向器103則具有三個單位的推動力。In the circuit design of a conventional integrated circuit (IC), all logic gates have the minimum channel length (L _min ) allowed by the process to reduce the circuit area. On the other hand, the channel width (W) of some of the logic gates will have different amplification levels to provide different load drive capabilities. The circuit 80 shown in the fifth figure is a circuit design of a logic gate that uses the minimum channel length L _min allowed by the process. All of the logic gates have a minimum channel length L _min , but each logic gate can have a different size. The driving force. If a larger driving force is required, a larger width transistor must be used. For example, the inverters 101, 102, 103 are logic gates having different driving capabilities, the inverter 101 has a unit of driving force, the inverter 102 has two units of driving force, and the inverter 103 has three units of driving force. .

在第六圖中顯示上述三個不同推動力的反向器101,102,103的積體電路佈局圖例，圖號201,202,203之元件分別代表反向器101,102,103的電路佈局。其中，假設製程允許的最小通道長度是L_min，一個單位的PMOS電晶體的通道寬度為W_p，一個單位的NMOS電晶的通道寬度為W_n，則反向器202的PMOS電晶體的通道寬度為二倍的W_p，反向器203的PMOS電晶體的通道寬度為三倍的W_p；同理，反向器202的NMOS電晶的通道寬度為二倍的W_n，反向器203的NMOS電晶的通道寬度為三倍的W_n。In the sixth figure, the integrated circuit layout illustration of the inverters 101, 102, 103 of the above three different driving forces is shown, and the elements of the numbers 201, 202, 203 represent the circuit layouts of the inverters 101, 102, 103, respectively. Wherein, assuming that the minimum channel length allowed by the process is L _min , the channel width of one unit of the PMOS transistor is W _p , the channel width of one unit of the NMOS transistor is W _n , and the channel of the PMOS transistor of the inverter 202 twice the width W _p, the channel width of the PMOS transistor of the inverter 203 is three times the W _p; Similarly, the channel width of the NMOS inverter electric crystal 202 is twice the W _n, reverser The channel width of the NMOS transistor of 203 is three times W _n .

上述電路中的邏輯閘均為最小通道長度的架構，因此其效能較差但漏電流的問題較小。但是，若將所有的邏輯閘改使用大通道長度的架構，則雖然改善了效能，卻又有漏電流增加的問題，此外，所有邏輯閘都使用大通道長度的架構的話，還會有積體電路佈局時其電路面積需求變大的缺點。The logic gates in the above circuits are all architectures with a minimum channel length, so their performance is poor but the leakage current problem is small. However, if all logic gates are changed to use a large channel length architecture, although the performance is improved, there is a problem of increased leakage current. In addition, if all logic gates use a large channel length architecture, there will be an integrated body. The disadvantage of increasing the circuit area requirement when the circuit is laid out.

本發明之主要目的在於提供一種多通道長度之次臨界電壓電路，其可兼具效能以及漏電流不會過大的優點，且還具有保持積體電路佈局時其電路面積維持於適當程度的優點。SUMMARY OF THE INVENTION A primary object of the present invention is to provide a multi-channel length sub-threshold voltage circuit which has the advantages of both performance and leakage current not being excessive, and also has the advantage that the circuit area is maintained at an appropriate level when the integrated circuit layout is maintained.

為了達成前述目的，依據本發明所提供之一種多通道長度之次臨界電壓電路，係成形於一積體電路(IC)上，該多通道長度之次臨界電壓電路包含有：複數邏輯閘，彼此間依預定方式電性連接，該等邏輯閘係由複數PMOS電晶體與複數NMOS電晶體組合而成；該等邏輯閘係形成複數訊號路徑，該等訊號路徑分別定義為至少一個關鍵訊號路徑以及複數一般訊號路徑；位於該複數一般訊號路徑上的該等邏輯閘之通道長度係為電晶體製程上之最小通道長度，位於該至少一個關鍵訊號路徑上的該等邏輯閘係為反短通道效應之電晶體(PMOS或NMOS)，其通道長度係大於電晶體製程上之最小通道長度，並定義為一大通道長度。藉此，可兼具效能以及漏電流不會過大的優點，並能使積體電路佈局時其電路面積維持於適當程度。In order to achieve the foregoing object, a multi-channel length sub-threshold voltage circuit according to the present invention is formed on an integrated circuit (IC), the multi-channel length sub-threshold voltage circuit includes: a complex logic gate, each other Electrically connected in a predetermined manner, the logic gates are formed by combining a plurality of PMOS transistors and a plurality of NMOS transistors; the logic gates form a complex signal path, and the signal paths are respectively defined as at least one critical signal path and a plurality of general signal paths; a channel length of the logic gates on the plurality of general signal paths is a minimum channel length on the transistor process, and the logic gates on the at least one critical signal path are anti-short channel effects The transistor (PMOS or NMOS) has a channel length that is greater than the minimum channel length on the transistor process and is defined as a large channel length. Thereby, the efficiency and the leakage current are not excessively large, and the circuit area can be maintained at an appropriate level in the layout of the integrated circuit.

為了詳細說明本發明之技術特點所在，茲舉以下之較佳實施例並配合圖式說明如後，其中：如第一圖至第二圖所示，本發明第一較佳實施例所提供之一種多通道長度之次臨界電壓電路10，係成形成一積體電路(IC)上，該多通道長度之次臨界電壓電路10具有：複數邏輯閘111,112，彼此間依預定方式電性連接，該等邏輯閘係由複數PMOS電晶體與複數NMOS電晶體所組成。In order to explain the technical features of the present invention in detail, the following preferred embodiments are described below with reference to the accompanying drawings, wherein, as shown in the first to second drawings, the first preferred embodiment of the present invention provides A multi-channel length sub-threshold voltage circuit 10 is formed to form an integrated circuit (IC) having a plurality of logic gates 111, 112 electrically connected to each other in a predetermined manner. The equal logic gate is composed of a plurality of PMOS transistors and a plurality of NMOS transistors.

該等邏輯閘111,112係形成複數訊號路徑P1,P2，該等訊號路徑P1,P2係依據實體電路的特性或需求來分別定義為至少一個關鍵訊號路徑P1以及複數個一般訊號路徑P2，該至少一個關鍵訊號路徑P1係指需要增加推動力之訊號路徑，於本實施例中，係以一個關鍵訊號路徑P1為例說明。其中，位於該複數一般訊號路徑P2上的該等邏輯閘112之通道長度係為電晶體製程上之最小通道長度L_min，位於該關鍵訊號路徑P1上的該等邏輯閘111係為反短通道效應之電晶體(PMOS或NMOS)，其通道長度係大於電晶體製程上之最小通道長度L_min，並定義為一大通道長度L_RSCE。The logic gates 111, 112 form a complex signal path P1, P2, and the signal paths P1, P2 are respectively defined as at least one key signal path P1 and a plurality of general signal paths P2 according to characteristics or requirements of the physical circuit, the at least one The key signal path P1 is a signal path that needs to increase the driving force. In this embodiment, a key signal path P1 is taken as an example. The length of the channel of the logic gates 112 on the plurality of general signal paths P2 is the minimum channel length L _min on the transistor process, and the logic gates 111 located on the key signal path P1 are anti-short channels. The effect transistor (PMOS or NMOS) has a channel length greater than the minimum channel length L _min on the transistor process and is defined as a large channel length L _RSCE .

接下來說明本第一實施例之動作方式。Next, the mode of operation of the first embodiment will be described.

請再度參閱第一圖及第二圖，由於該等邏輯閘111,112所形成的複數訊號路徑P1,P2中，該關鍵訊號路徑P1是需要增加推動力的，因此在該關鍵訊號路徑P1上的邏輯閘111是為大通道長度L_RSCE的邏輯閘(在圖中係以NMOS的部分為例)，在工作時由於推動力增加了因此可以改善電路性能；而在該複數一般訊號路徑P2上的邏輯閘112由於不需要特別的去增加推動力，因此使用最小通道長度L_min的邏輯閘即可應付推動力的需求。藉此，雖然在關鍵訊號路徑P1上有漏電流增加、電路面積增加、以及功率消耗增加的問題，但僅佔局部而已，並不會全面性的造成影響；反觀一般訊號路徑P2，由於未使用到大通道長度L_RSCE的邏輯閘，因此不會有電路面積、漏電流以及功率消耗增加的問題。Please refer to the first figure and the second figure again. Since the complex signal paths P1 and P2 formed by the logic gates 111 and 112 are required to increase the driving force, the logic on the key signal path P1 is required. The gate 111 is a logic gate for a large channel length L _RSCE (for example, an NMOS portion in the figure), which can improve circuit performance due to an increase in driving force during operation; and logic on the complex general signal path P2 Since the gate 112 does not need to specifically increase the driving force, the logic gate with the minimum channel length L _min can cope with the driving force requirement. Therefore, although there is a problem of increased leakage current, increased circuit area, and increased power consumption on the key signal path P1, it is only partial and does not have a comprehensive impact; in contrast, the general signal path P2 is not used. The logic gate to the large channel length L _RSCE , so there is no problem of increased circuit area, leakage current and power consumption.

由此可知，本第一實施例整體而言，可一方面改善電路性能，又可有效的控制電路面積、漏電流以及功率消耗的問題，改善了習知技術之缺點。Therefore, the first embodiment can improve the circuit performance on the one hand, and effectively control the circuit area, leakage current, and power consumption, and improve the shortcomings of the prior art.

請再參閱第三圖至第四圖，本發明第二較佳實施例所提供之一種多通道長度之次臨界電壓電路20，主要概同於前揭第一實施例，不同之處在於：該等訊號路徑P1,P2,P3中，除了定義為至少一個關鍵訊號路徑P1以及複數一般訊號路徑P2之外，還定義了至少一個次關鍵訊號路徑P3。Referring to the third to fourth embodiments, a multi-channel length sub-threshold voltage circuit 20 according to the second preferred embodiment of the present invention is mainly similar to the first embodiment described above, except that: The equal signal paths P1, P2, and P3 define at least one secondary key signal path P3 in addition to the at least one key signal path P1 and the complex general signal path P2.

此外，位於該至少一個次關鍵訊號路徑P3上的該等邏輯閘113，其通道長度係介於該最小通道長度L_min與該大通道長度L_RSCE之間，並定義其通道長度為一個次通道長度L_sub。In addition, those located at least one secondary key logic 113 on signal path P3, which is the length of the channel system between the channel length L _min of a minimum of the large channel length L _RSCE, and to define a channel length of a secondary channel Length L _sub .

本第二實施例的動作方式亦概同於第一實施例，差異在於，除了關鍵訊號路徑P1以及一般訊號路徑P2的動作方式之外，還有次關鍵訊號路徑P3上的邏輯閘113的動作方式。藉由次關鍵訊號路徑P3上的邏輯閘113的次通道長度L_sub大於最小通道長度L_min的關係，可達到優於最小通道長度L_min的邏輯閘112的電路特性；而藉由次關鍵訊號路徑P3上的邏輯閘113的次通道長度L_sub小於前述之大通道長度L_RSCE的關係，可達到電路面積、漏電流以及功率消耗均小於大通道長度L_RSCE的邏輯閘111的效果。進而可讓電路設計者藉由選擇不同通道長度的邏輯閘來符合其設計需求，而使得電路特性、電路面積、漏電流以及功率消耗均達到最佳狀態。The operation mode of the second embodiment is also similar to that of the first embodiment. The difference is that, besides the operation mode of the key signal path P1 and the general signal path P2, the action of the logic gate 113 on the secondary key signal path P3 is also performed. the way. By the relationship between the _sub -channel length L _sub of the logic gate 113 on the sub-critical signal path P3 being greater than the minimum channel length L _min , the circuit characteristics of the logic gate 112 superior to the minimum channel length L _min can be achieved; and by the sub-critical signal The secondary channel length L _sub of the logic gate 113 on the path P3 is smaller than the relationship of the large channel length L _RSCE described above, and the effect of the circuit gate, the leakage current, and the logic gate 111 whose power consumption is smaller than the large channel length L _RSCE can be achieved. In turn, the circuit designer can meet the design requirements by selecting logic gates with different channel lengths, so that the circuit characteristics, circuit area, leakage current and power consumption are optimized.

本第二實施例之其餘結構及所能達成之功效係概同於前揭第一實施例，容不贅述。The remaining structure of the second embodiment and the achievable functions are the same as those of the first embodiment, and are not described here.

須補充說明的是，前述之第一實施例所對應的第一圖以及第二實施例所對應之第三圖，主要是用來說明各種訊號路徑，並非限制此二實施例必須是此二圖中的電路結構，其他種電路結構亦會有依其實際狀態之訊號路徑，而不一定會與上述二實施例之電路結構相同。It should be noted that the first diagram corresponding to the first embodiment and the third diagram corresponding to the second embodiment are mainly used to describe various signal paths, and are not limited to the two embodiments. In the circuit structure, other kinds of circuit structures also have signal paths according to their actual states, and are not necessarily the same as the circuit structures of the above two embodiments.

由上可知，本發明係依需求而選用適當通道長度的邏輯閘，藉以兼具電路特性的良好效能以及漏電流不會過大的優點，且還具有保持積體電路佈局時其電路面積維持於適當程度的優點。As can be seen from the above, the present invention selects a logic gate of an appropriate channel length according to requirements, thereby having the advantages of good circuit characteristics and excessive leakage current, and also maintaining a proper circuit area when the integrated circuit layout is maintained. The advantage of the degree.

10．．．多通道長度之次臨界電壓電路10. . . Multi-channel length sub-threshold voltage circuit

111,112,113．．．邏輯閘111,112,113. . . Logic gate

20．．．多通道長度之次臨界電壓電路20. . . Multi-channel length sub-threshold voltage circuit

L_min．．．最小通道長度L _min . . . Minimum channel length

L_RSCE．．．大通道長度L _RSCE . . . Large channel length

L_sub．．．次通道長度L _sub . . . Secondary channel length

P1．．．關鍵訊號路徑P1. . . Key signal path

P2．．．一般訊號路徑P2. . . General signal path

P3．．．次關鍵訊號路徑P3. . . Secondary key signal path

第一圖係本發明第一較佳實施例之電路示意圖，顯示邏輯電路的連接狀態。The first figure is a circuit diagram of a first preferred embodiment of the present invention, showing the connection state of the logic circuit.

第二圖係本發明第一較佳實施例之積體電路電路佈局示意圖，主要顯示通道長度。The second figure is a schematic diagram of the circuit layout of the integrated circuit of the first preferred embodiment of the present invention, mainly showing the channel length.

第三圖係本發明第二較佳實施例之電路示意圖，顯示邏輯電路的連接狀態。The third figure is a circuit diagram of a second preferred embodiment of the present invention, showing the connection state of the logic circuit.

第四圖係本發明第二較佳實施例之積體電路電路佈局示意圖，主要顯示通道長度。The fourth figure is a schematic diagram of the circuit layout of the integrated circuit of the second preferred embodiment of the present invention, mainly showing the channel length.

第五圖係習知次臨界電壓電路之電路示意圖，顯示邏輯電路的連接狀態。The fifth figure is a schematic circuit diagram of a conventional sub-threshold voltage circuit, showing the connection state of the logic circuit.

第六圖係習知次臨界電壓電路之積體電路電路佈局示意圖，主要顯示通道長度。The sixth figure is a schematic diagram of the circuit layout of the integrated circuit of the conventional sub-critical voltage circuit, mainly showing the channel length.

10．．．多通道長度之次臨界電壓電路10. . . Multi-channel length sub-threshold voltage circuit

111,112．．．邏輯閘111,112. . . Logic gate

P1．．．關鍵訊號路徑P1. . . Key signal path

P2．．．一般訊號路徑P2. . . General signal path

Claims (3)

一種多通道長度之次臨界電壓電路，係成形於一積體電路(IC)上，該多通道長度之次臨界電壓電路包含有：複數邏輯閘，彼此間依預定方式電性連接，該等邏輯閘係由複數PMOS電晶體與複數NMOS電晶體組合而成；其特徵在於：該等邏輯閘係形成複數訊號路徑，該等訊號路徑分別定義為至少一個關鍵訊號路徑以及複數一般訊號路徑；位於該複數一般訊號路徑上的該等邏輯閘之通道長度係為電晶體製程上之最小通道長度，位於該至少一個關鍵訊號路徑上的該等邏輯閘係為反短通道效應之電晶體(PMOS或NMOS)，其通道長度係大於電晶體製程上之最小通道長度，並定義為一大通道長度。A multi-channel length sub-threshold voltage circuit is formed on an integrated circuit (IC), and the multi-channel length sub-threshold voltage circuit includes: a plurality of logic gates electrically connected to each other in a predetermined manner, the logic The gate system is composed of a plurality of PMOS transistors and a plurality of NMOS transistors; wherein the logic gates form a complex signal path, and the signal paths are respectively defined as at least one key signal path and a plurality of general signal paths; The channel length of the logic gates on the plurality of general signal paths is the minimum channel length on the transistor process, and the logic gates on the at least one critical signal path are anti-short channel effect transistors (PMOS or NMOS) The channel length is greater than the minimum channel length on the transistor process and is defined as a large channel length. 依據申請專利範圍第1項所述之多通道長度之次臨界電壓電路，其中：該等訊號路徑除了定義為至少一個關鍵訊號路徑以及複數一般訊號路徑之外，還定義了至少一個次關鍵訊號路徑，位於該至少一個次關鍵訊號路徑上的該等邏輯閘之通道長度係介於該最小通道長度與該大通道長度之間，並定義為一個次通道長度。According to the multi-channel length sub-threshold voltage circuit described in claim 1, wherein the signal path defines at least one sub-critical signal path in addition to at least one key signal path and a plurality of general signal paths. The channel length of the logic gates located on the at least one secondary critical signal path is between the minimum channel length and the large channel length, and is defined as a secondary channel length. 依據申請專利範圍第1項所述之多通道長度之次臨界電壓電路，其中：該至少一個關鍵訊號路徑係指需要增加推動力之訊號路徑。The multi-channel length sub-threshold voltage circuit according to claim 1, wherein: the at least one key signal path refers to a signal path that needs to increase driving force.