TW201304113A - 半導體感測裝置及其封裝方法 - Google Patents

半導體感測裝置及其封裝方法 Download PDF

Info

Publication number
TW201304113A
TW201304113A TW101119009A TW101119009A TW201304113A TW 201304113 A TW201304113 A TW 201304113A TW 101119009 A TW101119009 A TW 101119009A TW 101119009 A TW101119009 A TW 101119009A TW 201304113 A TW201304113 A TW 201304113A
Authority
TW
Taiwan
Prior art keywords
die
substrate
prt
semiconductor
electrical connection
Prior art date
Application number
TW101119009A
Other languages
English (en)
Inventor
Wai Yew Lo
Lan Chu Tan
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of TW201304113A publication Critical patent/TW201304113A/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01LMEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L19/00Details of, or accessories for, apparatus for measuring steady or quasi-steady pressure of a fluent medium insofar as such details or accessories are not special to particular types of pressure gauges
    • G01L19/06Means for preventing overload or deleterious influence of the measured medium on the measuring device or vice versa
    • G01L19/0627Protection against aggressive medium in general
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01LMEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L19/00Details of, or accessories for, apparatus for measuring steady or quasi-steady pressure of a fluent medium insofar as such details or accessories are not special to particular types of pressure gauges
    • G01L19/14Housings
    • G01L19/142Multiple part housings
    • G01L19/143Two part housings
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01LMEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L19/00Details of, or accessories for, apparatus for measuring steady or quasi-steady pressure of a fluent medium insofar as such details or accessories are not special to particular types of pressure gauges
    • G01L19/14Housings
    • G01L19/147Details about the mounting of the sensor to support or covering means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/16Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201Structure
    • H01L2224/32012Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32013Structure relative to the bonding area, e.g. bond pad the layer connector being larger than the bonding area, e.g. bond pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832Applying energy for connecting
    • H01L2224/8321Applying energy for connecting using a reflow oven
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862Heat curing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83871Visible light curing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009Pre-treatment of the connector or the bonding area
    • H01L2224/8501Cleaning, e.g. oxide removal step, desmearing
    • H01L2224/85013Plasma cleaning
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Dispersion Chemistry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本發明揭示一種封裝有一高腳罩之半導體感測器晶粒,該高腳罩具有若干側壁及帶有一中心孔之一頂部部分。在附接該罩頂部部分之前將凝膠材料施塗至由該等側壁形成之一腔中,使其覆蓋該晶粒。

Description

半導體感測裝置及其封裝方法
本發明大體而言係關於半導體裝置之封裝,且更特定而言,係關於一種組裝半導體感測器裝置之方法。
諸如壓力感測器裝置之半導體感測器裝置係眾所習知的。壓力感測器晶粒在搬運及封裝期間易受機械損壞。出於此原因,通常將此等感測器晶粒安裝於預模製封裝中且然後使用一單獨之蓋/罩密封於該等封裝中。
一種封裝半導體晶粒之方式係將該等晶粒安裝至一預模製引線框架並藉助一模製化合物囊封晶粒與預模製引線框架。舉例而言,當前之腔式QFN(四邊扁平無引線)封裝需要預模製引線框架以形成用於覆蓋感測器之一凝膠塗層之一腔。然而,預模製製程並不穩健、通常係低良率的,且可能導致模製相關缺陷。
此外,諸如壓阻式傳感器(PRT)、參數化佈局單元(Pcell)及陀螺儀之晶粒並不允許完全囊封,此乃因此將阻礙其功能性。因此,預模製引線框架需要在模具壁上放置一金屬罩或帽以保護晶粒免受外部環境之影響。然而,預模製引線框架相對昂貴,此使得總體封裝成本不具吸引力。若使用一預模製基板來代替一預模製引線框架,則上述情形同樣適用。
帶有預模製引線框架或預模製基板之封裝具有其他相關聯問題,諸如模具飛邊及空隙、模具-晶粒槳形座(paddle) 共面性及腔高度不一致。
因此,能夠高效地封裝半導體晶粒將係有利的,其中在減小總體封裝成本之同時實質上減小或消除對晶粒之環境損壞之危險。
本發明係以實例方式加以圖解說明且不受附圖限制,在附圖中相似參考編號指示類似元件。圖中之元件係為簡單及清晰起見而圖解說明,且未必按照比例繪製。舉例而言,可能為清晰起見而放大層及區之厚度。
本文中揭示本發明之詳細說明性實施例。然而,出於闡述本發明之實例性實施例之目的,本文中所揭示之特定結構性及功能性細節僅僅為代表性的。本發明可以諸多替代形式體現且不應解釋為僅限於本文中所闡明之實施例。此外,本文中所使用之術語係僅出於闡述特定實施例之目的且不意欲限制本發明之實例性實施例。
如本文中所使用,單數形式「一(a、an)」及「該(the)」亦意欲包含複數形式,除非上下文另有明確指示。將進一步理解,術語「包括(comprise、comprising)」、「包含(include and/or including)」規定所陳述之特徵、步驟或組件之存在,但並不排除一或多個其他特徵、步驟或組件之存在或添加。亦應注意,在某些替代實施方案中,所提及之功能/動作可不按圖中所提及之次序發生。舉例而言,連續展示之兩個圖事實上可實質上同時執行或有時可以相反次序執行,此取決於所涉及之功能性/動作。
在一項實施例中,本發明提供一種封裝一半導體晶粒之方法。該方法包含提供複數個引線框架或一基板(印刷佈線板)。該複數個引線框架中之每一者包含一晶粒墊及複數個引線指狀物。將一膠帶附接至該複數個引線框架之一第一側,且將半導體晶粒附接至該等引線框架之該等晶粒墊中之各別晶粒墊。將該等各別半導體晶粒之接合墊電連接至該等引線框架之該等引線指狀物。然後將一高腳罩之側壁附接至該等引線框架中之每一者以在該等引線框架中之每一者之一第二側上形成一腔。在該等腔中之每一者內施塗一凝膠材料,以使得該凝膠材料覆蓋該半導體晶粒且實質上填充該晶粒墊與每一引線框架之該等引線指狀物之間的間隙。然後將一頂部蓋附接至該高腳罩之該等側壁。
在另一實施例中,本發明係一種根據上述方法形成之封裝式半導體裝置。
現在參考圖1,其展示根據本發明之一實施例之一封裝式半導體裝置10之一剖面視圖。封裝式半導體裝置10包含具有一晶粒墊14及若干引線指狀物16之一引線框架12。引線框架12可由銅、一銅合金、一鍍銅鐵/鎳合金、鍍鋁或類似物形成。在本發明之此示範性實施例中,晶粒墊14及引線指狀物16之端部係半蝕刻的。
可使用如此項技術中已知的鋸割、衝壓及/或蝕刻製程處理一金屬薄片以形成具有晶粒墊14及引線指狀物16之引線框架12。另一選擇係,可自一單獨之供應商獲得一預製作之引線框架板,其中引線框架已形成有呈一所期望組態 之晶粒墊及引線指狀物。
一半導體晶粒18附接且電耦合至引線框架12。在本發明之此示範性實施例中,半導體晶粒18包含一壓阻式傳感器(PRT)晶粒。半導體晶粒18可係使用一晶粒附接黏合劑附接至引線框架12。半導體晶粒18及引線框架12係半導體裝置之眾所習知之組件,且因此對本發明之一完全理解無需對該等組件之詳細闡述。
在本發明之此示範性實施例中,半導體晶粒18附接且經由導線22電耦合至引線框架12之引線指狀物16。導線22使用一眾所習知的線接合製程及已知的線接合設備接合至半導體晶粒18之一作用表面24上之墊及引線框架12上之對應接觸墊。導線22由諸如鋁或金之一導電材料形成。
將半導體晶粒18電連接至引線框架12之另一方式係藉助附接至半導體晶粒18之一底側之倒裝晶片凸塊(未展示)將半導體晶粒18之接合墊連接至引線指狀物16。該等倒裝晶片凸塊可包含焊料凸塊、金球、模製之螺柱或其組合。
封裝式半導體裝置10包含具有側壁28及30之一高腳罩26。側壁28、30附接至引線框架12以便形成一腔32。在本發明之此示範性實施例中,側壁28、30藉助像不導電環氧樹脂那樣的一罩附接黏合劑34附接至各別引線指狀物16。在本發明之一項示範性實施例中,側壁28、30附接至自晶粒墊14向外延伸之導流條(未展示)。側壁28、30由一耐久且剛性材料形成,以使得PRT晶粒18受到保護且因此由側 壁28、30形成之腔32內之環境係穩定的。在一較佳實施例中,側壁28、30由諸如不銹鋼、鍍金屬或聚合物之材料形成。
在腔32內置入諸如一基於矽之凝膠之一凝膠材料36,凝膠材料36覆蓋半導體晶粒18且實質上填充晶粒墊14與引線指狀物16之間的間隙38及40。然後將一頂部蓋42附接至高腳罩26之側壁28及30。較佳地,頂部蓋42係由金屬形成且藉助一黏合劑附接至側壁28、30。然而,可設想出其他附接機制。頂部蓋42包含在頂部蓋42之一頂部表面上之一通氣孔44。通氣孔44用於促進空氣壓力量測。在一項實施例中,通氣孔44位於頂部蓋42之一中心區域處。可藉由鑽孔、壓製、沖孔等在頂部蓋42中形成通氣孔44。圖1之封裝式半導體裝置10之實例性組態可用於諸如一個四邊扁平無引線(QFN)封裝之一扁平無引線封裝中。
在某些示範性實施例中,裝置10之半導體晶粒18附接至諸如一撓性基板或一層壓基板之一基板而非引線框架12,如下文更詳細地論述。一撓性基板或層壓基板之使用可防止凝膠材料36自裝置10洩漏。
PRT裝置通常使用預模製引線框架,亦即,其上形成有一模製化合物之金屬引線框架,該模製化合物形成其中安置PRT晶粒之一腔。然而,預模製引線框架係昂貴的。因此,本發明提供一種不使用一預模製引線框架之組裝一PRT裝置之方法。而是,連同一引線框架或一基板(例如,印刷佈線板)一起使用具有形成用於一凝膠塗層之一腔之 側壁之一高腳罩。
現在參考圖2至圖9,將闡述根據本發明之一實施例之組裝一PRT裝置之一方法。圖2係展示複數個引線框架12之一剖面側視圖,其中一膠帶50附接至引線框架12之一第一側52。如所圖解說明,每一引線框架12包含一晶粒墊14及若干引線指狀物16。
複數個引線框架12可以具有毗鄰個別分段式框架之一單個條帶之形式或以一陣列格式來使用。
圖3係將一半導體PRT晶粒18附接至引線框架12之晶粒墊14中之各別晶粒墊之一步驟之一圖解。藉助諸如晶粒接合環氧樹脂之晶粒附接黏合劑20將PRT晶粒18附接至引線框架12之各別晶粒墊14。使用一已知的施塗裝置將晶粒附接黏合劑20施塗於引線框架12之一頂部表面54上,且將半導體晶粒18放置於晶粒附接黏合劑20上以將晶粒18附接至各別晶粒墊14。隨後,可在一烘箱中或經由光波使晶粒附接黏合劑20固化以使晶粒附接黏合劑20變硬。
圖4展示將PRT晶粒18電連接至各別引線框架12之步驟。在本發明之此示範性實施例中,使用眾所習知的線接合製程及已知的線接合設備藉助導線22將半導體晶粒18之接合墊電連接至引線框架12之引線指狀物16。在此示範性實施例中,在將各別半導體晶粒18之接合墊電連接至引線指狀物16之前使用一電漿處理製程清潔該等接合墊。
將半導體晶粒18連接至引線框架12之另一方式係經由附接至半導體晶粒18之一底側之倒裝晶片凸塊(未展示)。該 等倒裝晶片凸塊可包含焊料凸塊、金球、模製之螺柱或其組合。可使用諸如蒸鍍、電鍍、印刷、噴射以及螺柱凸塊形成及直接放置之已知技術在半導體晶粒18上形成或放置凸塊。倒裝每一半導體晶粒18,且使該等凸塊與引線指狀物16之接觸墊(未展示)對準。
對於其中使用諸如一基板或撓性基板之一印刷佈線板組裝PRT裝置之情形,使用如此項技術中已知的諸如環氧樹脂之一晶粒附接黏合劑將PRT晶粒在預定位置處附接至基板。晶粒附接步驟包含諸如藉助一烘箱使環氧樹脂固化。在固化之後,該基板經歷電漿清潔,然後使用此項技術中亦已知的市售線接合設備經由一線接合製程將晶粒電連接至基板。亦即,使用導線來互連半導體晶粒之接合墊與基板上之電連接墊。在線接合之後,使用諸如環氧樹脂之一黏合劑將罩之側壁附接至基板,且使環氧樹脂固化,可同樣使用一烘箱來使環氧樹脂固化。用於形成組裝有一基板之一PRT裝置之剩餘步驟係如下文針對基於引線框架之裝置所闡述,唯若不將一膠帶附接至基板之底部,則不包含去膠帶步驟。
圖5展示將高腳罩26之側壁28及30附接至引線框架12中之每一者之步驟。在本發明之此示範性實施例中,使用一罩附接黏合劑34將側壁28及30附接至引線框架12中之每一者之各別引線指狀物16以在每一引線框架12之一第二側56上形成一腔32。使用一已知的施塗裝置在引線指狀物16之一頂部表面上施塗罩附接黏合劑,然後將側壁放置於罩附 接黏合劑34上以將側壁28及30附接至各別引線指狀物16。隨後,在一烘箱中使罩附接黏合劑34固化。
圖6展示在每一腔32內施塗一凝膠材料36之步驟。可施塗諸如一基於矽之凝膠之凝膠材料36以覆蓋半導體晶粒18且實質上填充每一引線框架12之晶粒墊14與引線指狀物16之間的間隙38及40。可藉助如此項技術中已知的一習用施塗機器之一噴嘴施塗凝膠材料36。隨後,在一烘箱中使凝膠材料36固化。在本發明之此示範性實施例中,在於腔32內施塗凝膠材料36之前,使每一引線框架12經受電漿清潔。
圖7係展示一頂部蓋42附接至高腳罩26之側壁28及30之一側視剖面圖。在本發明之此示範性實施例中,頂部蓋42包含使用一黏合劑附接至側壁28及30之一金屬蓋。隨後,在一習用烘箱中使黏合劑34固化,後續接著將膠帶50自引線框架12移除,如圖8中所展示。如可見,在移除膠帶50之後,旋即曝露晶粒墊14與引線指狀物16之間的凝膠材料36。
圖9展示藉由一分割製程將個別封裝式半導體裝置10彼此分離。分割製程係眾所習知的且可包含藉助一鋸或一雷射進行切割。如所圖解說明,對複數個引線框架12進行分割以形成個別封裝式半導體裝置10。
如上文所闡述,本發明允許在不需要預模製引線框架來封裝一半導體晶粒之情形下封裝該晶粒。將一半導體晶粒附接至引線框架之晶粒墊。此外,將一高腳罩附接至引線 框架,其中該高腳罩之側壁附接至引線指狀物以形成一腔。在該腔內置入一凝膠材料以覆蓋半導體晶粒且實質上填充晶粒墊與引線指狀物之間的間隙。隨後,在不需要一預模製引線框架之情形下,將該罩之一頂部蓋附接至封裝。
因此,本發明提供一種封裝諸如一壓力感測器晶粒之半導體晶粒以形成具有一較低封裝輪廓之QFN封裝之方法,該方法不需要用於促進罩附接之一預模製引線框架,藉此減小此等封裝之製造成本。此外,上文所闡述之封裝技術防止此等半導體裝置封裝之諸如模具毛刺、模具飛邊、模具平面性及腔壁不一致之問題。
至今,應瞭解,已提供一種改良之封裝式半導體裝置及一種形成該封裝式半導體裝置之方法。由於對本發明之一完全理解不需要電路細節之知識,因此未揭示該等電路細節。雖然已在本說明及申請專利範圍中使用諸如術語「前部」、「後部」、「頂部」、「底部」、「在...上方」、「在...下方」及類似術語之相對術語闡述了本發明,但此等術語用於闡述性目的而未必用於闡述永久相對位置。應理解,如此使用之術語在適當情形下可互換,以使得本文中所闡述之本發明實施例(舉例而言)能夠以本文中所圖解說明或以其他方式闡述之彼等定向之定向來操作。
除非另有說明,否則,使用諸如「第一」及「第二」等術語來任意地區分此等術語所闡述之元件。因此,此等術語未必意欲指示此等元件之時間順序或其他優先順序。此 外,在申請專利範圍中使用諸如「至少一個」及「一或多個」等介紹性片語不應解釋為暗指通過不定冠詞「一」(「a」或「an」)來介紹另一請求項元素會將含有此所介紹之請求項元素之任何特定請求項限制為僅含有一個此元素之發明,甚至當同一請求項包含介紹性片語「一或多個」或「至少一個」及諸如「一」(「a」或「an」)等不定冠詞時亦係如此。此對於定冠詞之使用亦成立。
雖然本文中參考特定實施例闡述了本發明,但可在不背離下文申請專利範圍中所闡明之本發明範疇之情形下做出各種修改及改變。因此,應在一說明性意義而非一限制性意義上考量說明書及圖,且意欲將所有此等修改包含在本發明之範疇內。本文中關於特定實施例所闡述之任何益處、優點或問題之解決方案均不意欲解釋為任何或所有請求項之一關鍵、必需或基本特徵或元件。
10‧‧‧封裝式半導體裝置/裝置
12‧‧‧引線框架
14‧‧‧晶粒墊
16‧‧‧引線指狀物
18‧‧‧半導體晶粒/半導體壓阻式傳感器晶粒/壓阻式傳感器晶粒/晶粒
20‧‧‧晶粒附接黏合劑
22‧‧‧導線
24‧‧‧作用表面
26‧‧‧高腳罩
28‧‧‧側壁
30‧‧‧側壁
32‧‧‧腔
34‧‧‧罩附接黏合劑/黏合劑
36‧‧‧凝膠材料
38‧‧‧間隙
40‧‧‧間隙
42‧‧‧頂部蓋
44‧‧‧通氣孔
50‧‧‧膠帶
52‧‧‧第一側
54‧‧‧頂部表面
56‧‧‧第二側
圖1係根據本發明之一項實施例之一半導體裝置封裝之一剖面視圖;圖2係展示複數個引線框架之一剖面側視圖,其中一膠帶附接至該等引線框架;圖3係將半導體晶粒附接至引線框架之晶粒墊中之各別晶粒墊之一步驟之一圖解;圖4展示將半導體晶粒電連接至各別引線框架之步驟;圖5展示將一高腳罩之側壁附接至引線框架中之每一者之步驟; 圖6展示在由高腳罩形成之腔中之每一者內施塗一凝膠材料之步驟;圖7係展示一頂部蓋附接至高腳罩之側壁之一剖面側視圖;圖8展示將膠帶自引線框架移除之步驟;且圖9圖解說明將封裝式半導體裝置陣列分離成個別封裝式半導體裝置之一步驟。
10‧‧‧封裝式半導體裝置/裝置
12‧‧‧引線框架
14‧‧‧晶粒墊
16‧‧‧引線指狀物
18‧‧‧半導體晶粒/半導體壓阻式傳感器晶粒/壓阻式傳感器晶粒/晶粒
20‧‧‧晶粒附接黏合劑
22‧‧‧導線
24‧‧‧作用表面
26‧‧‧高腳罩
28‧‧‧側壁
30‧‧‧側壁
32‧‧‧腔
34‧‧‧罩附接黏合劑/黏合劑
36‧‧‧凝膠材料
38‧‧‧間隙
40‧‧‧間隙
42‧‧‧頂部蓋
44‧‧‧通氣孔

Claims (20)

  1. 一種封裝一半導體感測器晶粒之方法,其包括以下步驟:提供一基板,該基板具有包含一晶粒附接區域及若干基板電連接墊之一第一側;將一壓阻式傳感器(PRT)型半導體晶粒附接至該晶粒附接區域;將該PRT型半導體晶粒之接合墊電連接至該等基板電連接墊;將一高腳罩之側壁附接至該基板之該第一側,以使得該等側壁形成一腔且環繞該PRT型半導體晶粒及該晶粒與該基板之間的電連接;在該腔內施塗一凝膠材料,以使得該凝膠材料覆蓋該PRT型半導體晶粒且實質上填充該晶粒附接區域與該等基板電連接墊之間的間隙;及將一頂部蓋附接至該高腳罩之該等側壁。
  2. 如請求項1之封裝一半導體感測器晶粒之方法,其中該基板包括一撓性印刷佈線板。
  3. 如請求項1之封裝一半導體感測器晶粒之方法,其中該基板包括一引線框架,該晶粒附接區域包括一引線框架旗標,且該等基板電連接墊包括引線指狀物。
  4. 如請求項3之封裝一半導體感測器晶粒之方法,其中將該高腳罩之側壁附接至該等引線框架中之每一者包括藉助一罩附接黏合劑將該高腳罩之該等側壁附接至該引線 框架之各別引線指狀物並使該罩附接黏合劑固化。
  5. 如請求項3之封裝一半導體感測器晶粒之方法,其中對晶粒墊及該等引線指狀物之至少一端進行半蝕刻。
  6. 如請求項3之封裝一半導體感測器晶粒之方法,其進一步包括在將該PRT型半導體晶粒附接至該晶粒墊之前將該引線框架之一第二側附接至一膠帶並在將該凝膠材料施塗至該腔中之後移除該膠帶。
  7. 如請求項6之封裝一半導體感測器晶粒之方法,其中該凝膠材料填充該等引線指狀物與該晶粒墊之間的空間,且其中在移除該膠帶之後曝露該空間中之該凝膠材料之外表面。
  8. 如請求項1之封裝一半導體感測器晶粒之方法,其中附接該頂部蓋包括藉助一黏合劑材料將該蓋附接至該高腳罩之該等側壁並使該黏合劑材料固化。
  9. 如請求項1之封裝一半導體感測器晶粒之方法,其進一步包括在附接該頂部蓋之前使該凝膠材料固化。
  10. 如請求項1之封裝一半導體感測器晶粒之方法,其中該電連接步驟包括使用一線接合製程藉助導線將該PRT型半導體晶粒之該等接合墊連接至該等基板電連接墊。
  11. 如請求項1之封裝一半導體感測器晶粒之方法,其進一步包括在於該腔內施塗該凝膠材料之前對該基板進行電漿清潔。
  12. 如請求項1之封裝一半導體感測器晶粒之方法,其中該頂部蓋包含一通氣孔。
  13. 一種封裝式半導體感測器裝置,其包括:一基板,其包含一晶粒附接區域及複數個電連接墊;一壓阻式傳感器(PRT)半導體晶粒,其在該晶粒附接區域處附接至該基板且藉助於該複數個電連接墊電耦合至該基板;一高腳罩,其具有若干側壁,其中該等側壁附接至該基板且環繞該PRT半導體晶粒,以便形成一腔且使該PRT半導體晶粒位於該腔內;一凝膠材料,其置入於該腔內,覆蓋該PRT半導體晶粒及該PRT半導體晶粒與該等基板電連接墊之間的電連接;及一頂部蓋,其附接至該高腳罩之該等側壁。
  14. 如請求項13之封裝式半導體感測器裝置,其中該頂部蓋包含一通氣孔。
  15. 如請求項13之封裝式半導體感測器裝置,其中晶粒接合墊係藉助接合線電耦合至基板電連接墊。
  16. 如請求項13之封裝式半導體感測器裝置,其中該凝膠材料包括基於矽之凝膠。
  17. 如請求項13之封裝式半導體感測器裝置,其中該基板包括一撓性印刷佈線板。
  18. 如請求項13之封裝式半導體感測器裝置,其中該基板包括一引線框架,該晶粒附接區域包括該引線框架之一晶粒墊,且該等基板電連接墊包括引線指狀物。
  19. 一種封裝一半導體感測器晶粒之方法,其包括以下步 驟:提供一基板,該基板包含複數個晶粒附接區域及複數組電連接墊,其中使一組電連接墊與每一晶粒附接區域相關聯;藉助一晶粒附接黏合劑將若干壓阻式傳感器(PRT)型半導體晶粒附接至該基板之各別晶粒附接區域並使該晶粒附接黏合劑固化;將該等PRT型半導體晶粒之接合墊電連接至各別組之該等電連接墊;藉助一罩附接黏合劑將高腳罩之側壁附接至該基板,以使得該等側壁中之各別側壁環繞該等PRT型半導體晶粒中之對應半導體晶粒,其中該等側壁形成腔且該等PRT型半導體晶粒位於該等腔中之各別腔中;將一凝膠材料施塗至該等腔中,以使得該凝膠材料覆蓋該等PRT型半導體晶粒;藉助一黏合劑材料將一頂部蓋附接至該高腳罩之該等側壁,其中該頂部蓋包含一通氣孔;及對該基板進行分割以形成個別封裝式半導體感測器裝置。
  20. 如請求項19之方法,其中該基板包括一撓性印刷佈線板。
TW101119009A 2011-05-31 2012-05-28 半導體感測裝置及其封裝方法 TW201304113A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/118,596 US20120306031A1 (en) 2011-05-31 2011-05-31 Semiconductor sensor device and method of packaging same

Publications (1)

Publication Number Publication Date
TW201304113A true TW201304113A (zh) 2013-01-16

Family

ID=47234166

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101119009A TW201304113A (zh) 2011-05-31 2012-05-28 半導體感測裝置及其封裝方法

Country Status (3)

Country Link
US (1) US20120306031A1 (zh)
CN (1) CN102810488A (zh)
TW (1) TW201304113A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI642160B (zh) * 2014-02-07 2018-11-21 東琳精密股份有限公司 用於四方平面無引腳封裝的導線架結構、四方平面無引腳封裝及形成導線架結構的方法

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102589753B (zh) * 2011-01-05 2016-05-04 飞思卡尔半导体公司 压力传感器及其封装方法
US9029999B2 (en) * 2011-11-23 2015-05-12 Freescale Semiconductor, Inc. Semiconductor sensor device with footed lid
US9510495B2 (en) * 2012-11-27 2016-11-29 Freescale Semiconductor, Inc. Electronic devices with cavity-type, permeable material filled packages, and methods of their manufacture
CN103094132B (zh) * 2012-12-15 2017-12-26 华天科技(西安)有限公司 一种采用加宽模具假型腔优化二次塑封封装件的制作工艺
US9824924B2 (en) 2013-03-29 2017-11-21 Stmicroelectronics Pte Ltd. Semiconductor packages having an electric device with a recess
EP2985785B1 (en) * 2013-04-10 2023-12-20 Mitsubishi Electric Corporation Method of manufacturing a semiconductor device with prevention of adhesive climbing up and corresponding semiconductor device
CN103599893B (zh) * 2013-09-12 2015-07-15 宁波康强电子股份有限公司 功率集成电路引线框架原材料的清刷方法
US9040335B2 (en) * 2013-09-17 2015-05-26 Freescale Semiconductor, Inc. Side vented pressure sensor device
US9136399B2 (en) 2013-11-21 2015-09-15 Freescale Semiconductor, Inc. Semiconductor package with gel filled cavity
JP6180902B2 (ja) * 2013-11-25 2017-08-16 新日本無線株式会社 センサ装置の製造方法
CN103674399B (zh) * 2013-12-25 2016-04-27 北京必创科技有限公司 一种应力分散mems塑封压力传感器及其制备方法
US9297713B2 (en) 2014-03-19 2016-03-29 Freescale Semiconductor,Inc. Pressure sensor device with through silicon via
US9476788B2 (en) 2014-04-22 2016-10-25 Freescale Semiconductor, Inc. Semiconductor sensor with gel filled cavity
US9362479B2 (en) 2014-07-22 2016-06-07 Freescale Semiconductor, Inc. Package-in-package semiconductor sensor device
CN105300593B (zh) * 2014-07-28 2018-12-28 恩智浦美国有限公司 具有盖的封装的半导体传感器装置
CN106876342A (zh) * 2016-12-19 2017-06-20 杰群电子科技(东莞)有限公司 一种双面散热半导体元件的制造方法
DE102017200162A1 (de) * 2017-01-09 2018-07-12 Robert Bosch Gmbh Verfahren zum Herstellen eines mikroelektromechanischen Bauteils und Wafer-Anordnung
JP6922244B2 (ja) * 2017-02-17 2021-08-18 富士電機株式会社 半導体物理量センサ装置の製造方法および半導体物理量センサ装置の試験方法
US10679929B2 (en) * 2017-07-28 2020-06-09 Advanced Semiconductor Engineering Korea, Inc. Semiconductor package device and method of manufacturing the same
CN107588889A (zh) * 2017-09-05 2018-01-16 武汉飞恩微电子有限公司 一种耐流体冰冻的介质隔离封装压力传感器
DE102017222393A1 (de) * 2017-12-11 2019-06-13 Robert Bosch Gmbh Sensorbaugruppe und Verfahren zur Herstellung einer Sensorbaugruppe
DE102019201228B4 (de) * 2019-01-31 2023-10-05 Robert Bosch Gmbh Verfahren zum Herstellen einer Mehrzahl von Sensoreinrichtungen und Sensoreinrichtung
CN110429075B (zh) * 2019-07-19 2020-07-14 广东气派科技有限公司 高密度多侧面引脚外露的封装结构及其生产方法
US12033960B1 (en) * 2021-12-10 2024-07-09 Amazon Technologies, Inc. Semiconductor package with stiffener ring having elevated opening

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10335374A (ja) * 1997-06-04 1998-12-18 Fujitsu Ltd 半導体装置及び半導体装置モジュール
US6266197B1 (en) * 1999-12-08 2001-07-24 Amkor Technology, Inc. Molded window array for image sensor packages
US6900531B2 (en) * 2002-10-25 2005-05-31 Freescale Semiconductor, Inc. Image sensor device
TWI285415B (en) * 2005-08-01 2007-08-11 Advanced Semiconductor Eng Package structure having recession portion on the surface thereof and method of making the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI642160B (zh) * 2014-02-07 2018-11-21 東琳精密股份有限公司 用於四方平面無引腳封裝的導線架結構、四方平面無引腳封裝及形成導線架結構的方法

Also Published As

Publication number Publication date
CN102810488A (zh) 2012-12-05
US20120306031A1 (en) 2012-12-06

Similar Documents

Publication Publication Date Title
TW201304113A (zh) 半導體感測裝置及其封裝方法
US9029999B2 (en) Semiconductor sensor device with footed lid
US8802474B1 (en) Pressure sensor and method of packaging same
US8501517B1 (en) Method of assembling pressure sensor device
US9297713B2 (en) Pressure sensor device with through silicon via
JP5707902B2 (ja) 半導体装置及びその製造方法
US20140374848A1 (en) Semiconductor sensor device with metal lid
US20160056097A1 (en) Semiconductor device with inspectable solder joints
US20120139067A1 (en) Pressure sensor and method of packaging same
US20150069537A1 (en) Package-on-package semiconductor sensor device
US9362479B2 (en) Package-in-package semiconductor sensor device
KR102223245B1 (ko) 패키징된 반도체 디바이스
US8643158B2 (en) Semiconductor package and lead frame therefor
US9890034B2 (en) Cavity type pressure sensor device
JP5278037B2 (ja) 樹脂封止型半導体装置
CN104425426A (zh) 压力传感器装置及装配方法
CN112750804A (zh) 半导体设备封装和其制造方法
US20170081178A1 (en) Semiconductor device package with seal structure
US8941194B1 (en) Pressure sensor device having bump chip carrier (BCC)
US9099363B1 (en) Substrate with corner cut-outs and semiconductor device assembled therewith
US9638596B2 (en) Cavity-down pressure sensor device
US9293395B2 (en) Lead frame with mold lock structure
TWI845784B (zh) 半導體裝置封裝及其製造方法
JP2011014606A (ja) 半導体装置の製造方法
JP5910950B2 (ja) 樹脂封止型半導体装置、多面付樹脂封止型半導体装置、リードフレーム、および樹脂封止型半導体装置の製造方法