TW201300567A - 藉由紫外線輔助之光化學沉積而介電回復電漿損壞之低介電常數薄膜 - Google Patents

藉由紫外線輔助之光化學沉積而介電回復電漿損壞之低介電常數薄膜 Download PDF

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TW201300567A
TW201300567A TW101117401A TW101117401A TW201300567A TW 201300567 A TW201300567 A TW 201300567A TW 101117401 A TW101117401 A TW 101117401A TW 101117401 A TW101117401 A TW 101117401A TW 201300567 A TW201300567 A TW 201300567A
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dielectric film
carbon
film
radiation
low
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Kang-Sub Yim
Thomas Nowak
Xie Bo
Alexandros T Demos
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Applied Materials Inc
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Abstract

在此提供用於修復損壞的低k膜的方法。低k膜的損壞發生在處理膜期間,諸如蝕刻、灰化,與平坦化期間。處理低k膜引發水儲存在膜的孔隙中,且處理低k膜進一步引發親水性化合物形成在低k膜結構中。結合了紫外線(UV)輻射與含碳化合物的修復製程從孔隙移除了水,並且該等修復製程進一步從低k膜結構中移除了親水性化合物。

Description

藉由紫外線輔助之光化學沉積而介電回復電漿損壞之低介電常數薄膜
本發明的實施例大體而言係關於用於修復與降低半導體製造中的低k膜之介電常數的方法。
隨著元件規模持續調整,半導體製造中的介電膜之介電常數(k)持續減少。對於能夠持續減少特徵結構尺寸而言,盡量減少低介電常數(低k)膜上的整合損壞是相當重要的。然而,隨著特徵結構尺寸縮小,在介電膜的電阻電容與可靠度上的改良變成一項嚴峻的挑戰。
當前用於蝕刻或灰化介電膜的技術涉及生成水(H2O)的製程化學條件(process chemistries),水為副產物。水副產物可能導入沉積的介電膜中,因而增加介電膜的k值。同樣,當前用於移除氧化銅(CuO)與化學機械平坦化(CMP)殘餘物的技術涉及使用氨(NH3)電漿或氫(H2)電漿。為了改良金屬化結構的電遷移(electromigration(EM))以及ILD膜的時間相依介電質崩潰性(time dependent dielectric breakdown(TDDB)),必須移除氧化銅以及CMP殘餘物。然而,將低k膜暴露至NH3與H2電漿修飾了膜結構並且增加了k值。現存的修復技術涉及液相矽烷化或使用超臨界CO2。然而,該等技術尚未被證實對修復膜中凹陷的特徵結構之側壁損 壞有效。
因此,需要一種修復介電膜以降低k值的方法,以改良效能並且得以用於更小的元件尺寸。
本發明的實施例大體而言係關於用於修復與降低半導體製造中的低k膜之介電常數的方法。
一個實施例中,提供一種修復損壞的低k介電膜的方法。該方法通常包含以下步驟:將介電膜定位在處理腔室中,加熱該處理腔室,將含碳前驅物流進該處理腔室,將該含碳前驅物與該介電膜暴露至紫外線(UV)輻射,分解該含碳前驅物,以及將含碳化合物沉積至介電膜的孔隙中。
本發明的實施例大體而言係關於用於修復與降低半導體製造中的低k膜之介電常數(k值)的方法。
第1A圖繪示沉積在結構101上的介電膜100。該結構101可以是基材(例如矽晶圓)或先前形成的層(例如金屬化或互連層)。介電膜100可以是多孔含矽低k膜,諸如例如SiO2、Si+O+C、Si+O+N、Si+C+O+H、Si+O+C+N,或其他相關膜。介電膜100可具有形成在該膜中的孔隙102。
第1B圖繪示平坦化且蝕刻後的介電膜100,該平坦化及蝕刻用於形成特徵結構104至介電膜100中。介電膜100可透過例如化學機械平坦化(CMP)製程平坦化。介電膜100可例如透過以下方式蝕刻:遮蔽介電膜100的一部分,將介電膜100未受遮蔽的該部分接觸由氫氟酸(HF)蒸氣所形成的電漿,以及使用由氧(O2)氣或CO2氣體形成的電漿將該遮罩灰化而移除。
介電膜100的平坦化、灰化,與蝕刻將氫及/或水導進介電膜100,而使Si-OH基形成,該Si-OH基例如會使介電膜100親水。介電膜100的親水性質使孔隙102被水填充,而生成損壞的孔隙103。Si-OH基與損壞的孔隙103二者皆增加了介電膜100的k值。來自平坦化與蝕刻的損壞通常是侷限在介電膜100的上部以及侷限在特徵結構104的側壁,如第1B圖所示。
第1C圖繪示修復製程修復後的介電膜100,下文中將描述該修復製程。舉例而言,該修復製程透過將水從損壞的孔隙103移除(因而生成被修復的孔隙105)而減少介電膜100的k值,並且該修復製程也透過將介電膜100中的SiOH基轉換成疏水的Si-O-Si(CH3)3基而減少介電膜100的k值。該疏水的Si-O-Si(CH3)3基有助於將水從介電膜100的損壞孔隙103汲引出來。
一個實施例中,可透過紫外線(UV)輔助的化學氣相沉積(CVD)製程修復介電膜100。UV-CVD製程包含在UV輻射的存在下以含碳化合物接觸介電膜100而在介 電膜100中生成前文所述的Si-O-Si(CH3)3基。
例如,UV-CVD製程可透過以下方式實施:將介電膜100放入處理腔室中,加熱該處理腔室,將氣相含碳前驅物流進該處理腔室,將UV輻射源接合以使該含碳前驅物與該介電膜100接觸UV輻射,以UV輻射分解該含碳前驅物,以及將含碳化合物沉積至介電膜100的損壞孔隙103中。一個實施例中,同時供應UV輻射與含碳前驅物。在修復製程期間,薄的含碳膜201可沉積至修復的介電膜100上,如第2A圖中所見。該薄的含碳膜201可以高達10Å厚。如第1C圖所示,可視情況移除該薄的含碳膜201,此舉是透過昇華或透過使該薄的含碳膜201擴散至介電膜100中而實現。
適合的含碳前驅物包括,乙烯、乙炔、1,3-丁二烯,與異戊二烯,但不以此為限。其他適合的含碳前驅物包括含有碳碳雙鍵(C=C)及/或碳碳三鍵(CΞC)的化合物。可調整該UV輻射以含有特定波長,該等特定波長可被所用的特定含碳前驅物吸收,以在修復製程期間有效分解該含碳前驅物。例如,1,3-丁二烯對波長為介於200 nm至220 nm的UV輻射具高度吸收性,而乙炔對波長為介於120 nm至180 nm的UV輻射具高度吸收性。UV輻射可具有10 nm至400 nm之間的波長,例如介於20 nm至230 nm之間的波長。也可加熱處理腔室至一溫度,該溫度有益於含碳前驅物的分解。
一項使用氣相前驅物的優點在於該氣相前驅物的分子 能夠比液相前驅物更深入地滲入膜中。同樣,使用UV輻射是有益的,因為UV輻射助於將介電膜100中的Si-OH基轉換成疏水的Si-O-Si(CH3)3基。
可在以下條件下施行UV-CVD製程:處理腔室壓力介於1 Torr至100 Torr之間(諸如10 Torr)、介電膜溫度介於0℃至400℃之間(諸如200℃)、含碳前驅物流速介於10 sccm至5000 sccm之間(諸如500 sccm),以及處理時間介於5秒至300秒之間,諸如30秒。
介電膜100已修復後,可執行後續的製程以繼續製造半導體元件。例如,可沉積擴散阻障層106至介電膜100的特徵結構104中,且可沉積金屬材料107(例如銅或銅合金)至特徵結構104中,如第1D圖所示。可能必須平坦化金屬材料107,且從金屬材料107移除在平坦化期間可能形成的任何氧化物。常見的金屬氧化物移除技術涉及使用氫電漿或氨電漿。該平坦化及/或金屬氧化物移除製程可能再度損壞介電膜100的表面,如第1E圖所見。可藉由使用前文所述的修復製程修復介電膜100。修復製程期間可沉積薄的含碳膜202(類似含碳膜201)至修復過的介電膜100上,如第2B圖所見。該薄的含碳膜202可高達10Å厚。如第1F圖所示,可視情況移除該薄的含碳膜202,此舉是透過昇華或透過使該薄的含碳膜202擴散至介電膜100中而實現。
所述的修復製程有效地降低損壞的介電膜的k值,因而使半導體元件特徵結構能夠持續在規模上有所調整。
前述內容是涉及本發明之實施例,可不背離本發明之基本範疇而設計其他及進一步之實施例,而本發明之範疇由隨後的申請專利範圍所決定。
100‧‧‧介電膜
101‧‧‧結構
102‧‧‧孔隙
103‧‧‧損壞的孔隙
104‧‧‧特徵結構
105‧‧‧修復的孔隙
106‧‧‧擴散阻障物
107‧‧‧金屬材料
201、202‧‧‧薄的含碳膜
藉由參考實施例(該等實施例中之一些實施例圖示於附圖中),可獲得於【發明內容】中簡要總結的本發明之更特定的說明,而能詳細瞭解於【發明內容】記載的本發明之特徵。然而應注意附圖僅圖示此發明的典型實施例,因而不應將該等附圖視為限制本發明之範疇,因為本發明可容許其他等效實施例。
第1A圖至第1F圖繪示處理的各階段期間的介電層。
第2A圖至第2B圖繪示處理的各階段期間具有薄碳膜的介電層。
100‧‧‧介電膜
101‧‧‧結構
102‧‧‧孔隙
104‧‧‧特徵結構
105‧‧‧修復的孔隙

Claims (10)

  1. 一種修復一損壞的低k介電膜的方法,該方法包含以下步驟:將一介電膜定位在一處理腔室中;加熱該處理腔室;將一含碳前驅物流進該處理腔室;將該含碳前驅物與該介電膜暴露至紫外線(UV)輻射;分解該含碳前驅物;以及將一含碳化合物沉積至該介電膜的孔隙中。
  2. 如請求項1所述的方法,其中該含碳前驅物包含1,3-丁二烯與異戊二烯之至少一者。
  3. 如請求項2所述的方法,其中該UV輻射具有介於200 nm至220 nm之間的波長。
  4. 如請求項1所述的方法,其中該UV輻射具有介於20 nm至230 nm之間的波長。
  5. 如請求項1所述的方法,其中該分解該含碳前驅物之步驟包含以下步驟:用該UV輻射分解該含碳前驅物。
  6. 如請求項1所述的方法,其中該處理腔室處於介於1 Torr至100 Torr之間的一壓力下,該介電膜處於介於0℃至400℃之間的一溫度下,該含碳前驅物以介於10 sccm至5000 sccm之間的一流速流進該處理腔室,且該介電膜受到處理達介於5秒至300秒之間的一處理時間。
  7. 如請求項1所述的方法,進一步包含以下步驟:沉積一含碳膜至該介電膜上。
  8. 如請求項7所述的方法,其中該含碳膜被沉積達不超過10Å的一厚度。
  9. 如請求項7所述的方法,進一步包含以下步驟:從該介電膜移除該含碳膜。
  10. 如請求項9所述的方法,其中該從該介電膜移除該含碳膜之步驟包含以下步驟之至少一者:昇華該含碳膜,以及使該含碳膜擴散進入該介電膜。
TW101117401A 2011-06-28 2012-05-16 藉由紫外線輔助之光化學沉積而介電回復電漿損壞之低介電常數薄膜 TW201300567A (zh)

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Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201403711A (zh) 2012-07-02 2014-01-16 Applied Materials Inc 利用氣相化學暴露之低k介電質損傷修復
TWI581331B (zh) 2012-07-13 2017-05-01 應用材料股份有限公司 降低多孔低k膜的介電常數之方法
CN104143524A (zh) * 2013-05-07 2014-11-12 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
WO2015100292A1 (en) 2013-12-26 2015-07-02 Applied Materials, Inc. Photo-assisted deposition of flowable films
CN105336663B (zh) * 2014-05-30 2018-11-16 中芯国际集成电路制造(上海)有限公司 金属互连结构的形成方法
US10113234B2 (en) * 2014-07-21 2018-10-30 Applied Materials, Inc. UV assisted silylation for porous low-k film sealing
CN105702619A (zh) * 2014-11-27 2016-06-22 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
US9793108B2 (en) * 2015-06-25 2017-10-17 Applied Material, Inc. Interconnect integration for sidewall pore seal and via cleanliness
US9887128B2 (en) * 2015-12-29 2018-02-06 Taiwan Semiconductor Manufacturing Co., Ltd. Method and structure for interconnection
KR20180030280A (ko) 2016-09-12 2018-03-22 삼성전자주식회사 배선 구조체를 갖는 반도체 소자
CN110129769B (zh) * 2019-05-17 2021-05-14 江苏菲沃泰纳米科技股份有限公司 疏水性的低介电常数膜及其制备方法
CN110158052B (zh) 2019-05-17 2021-05-14 江苏菲沃泰纳米科技股份有限公司 低介电常数膜及其制备方法
CN110306226B (zh) * 2019-07-25 2020-12-25 常州大学 超临界二氧化碳中电沉积碳膜的方法
US11348784B2 (en) 2019-08-12 2022-05-31 Beijing E-Town Semiconductor Technology Co., Ltd Enhanced ignition in inductively coupled plasmas for workpiece processing

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7404990B2 (en) * 2002-11-14 2008-07-29 Air Products And Chemicals, Inc. Non-thermal process for forming porous low dielectric constant films
JP4666200B2 (ja) * 2004-06-09 2011-04-06 パナソニック株式会社 SiC半導体装置の製造方法
JP5019714B2 (ja) * 2005-01-31 2012-09-05 大陽日酸株式会社 低誘電率膜のダメージ回復法
US7135402B2 (en) * 2005-02-01 2006-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Sealing pores of low-k dielectrics using CxHy
US8187678B2 (en) * 2006-02-13 2012-05-29 Stc.Unm Ultra-thin microporous/hybrid materials
JP2007317817A (ja) * 2006-05-25 2007-12-06 Sony Corp 半導体装置の製造方法
JP5548332B2 (ja) * 2006-08-24 2014-07-16 富士通セミコンダクター株式会社 半導体デバイスの製造方法
US7851232B2 (en) * 2006-10-30 2010-12-14 Novellus Systems, Inc. UV treatment for carbon-containing low-k dielectric repair in semiconductor processing
US7500397B2 (en) * 2007-02-15 2009-03-10 Air Products And Chemicals, Inc. Activated chemical process for enhancing material properties of dielectric films
JP2009164198A (ja) * 2007-12-28 2009-07-23 Panasonic Corp 半導体装置の製造方法
US20110151590A1 (en) * 2009-08-05 2011-06-23 Applied Materials, Inc. Apparatus and method for low-k dielectric repair
JP2010245562A (ja) * 2010-07-15 2010-10-28 Tokyo Electron Ltd 低誘電率絶縁膜のダメージ回復方法及び半導体装置の製造方法

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