201248747 六、發明說明： 【發明所屬之技術領域】 本案是有關於一種封展結構及其製造方法，且特別是 有關於一種晶片内埋式封裝結構及其製造方法。 【先前技術】 隨著科技的進步，各式電子產品不斷推陳出新。尤其 是在科技技術發展的過程中，半導體封裝技術扮演著極重 要的角色。 在半導體封裝製程中，晶圓先經過切割，而形成一顆 顆的晶粒。晶粒再透過打線、覆晶等製程將其内部走線引 導至外部’並透過封膠等方式來保護晶粒。 在產品微小化與精密化的趨勢下，半導體封裝技術不 斷地在追求如何在有限空間下，提高線路的精密度及構裝 密集度。此外’除了提高線路的精密度及構裝密集度外’ 如何在新技術下維持製程良率、品質與成本也同樣是研究 發展之一重要目標。 【發明内容】 本案係有關於一種封裝結構其製造方法，其利用通孔 之設計與製程，提高線路的精密度及構裝密集度，並維持 製程良率、品質與成本。 根據本案之一方面，提出一種封裝結構之製造方法。 封裝結構之製造方法包括以下步驟。提供一封膠件及一晶 片。封膠件具有一第一表面及一第二表面。晶片埋入於封 4 201248747 膠件。晶片之一主動表面暴露於第一表面。形成一第一重 佈線路層（Redistribution Layer，RDL)於第一表面。 餘刻封膠件及第一重佈線路層，以形成一封膠通孔及一線 路通孔。於封膠通孔及線路通孔形成一導電柱。形成一第 二重佈線路層（Redistribution Layer，RDL)於第二表 面。導電柱電性連接第一重佈線路層及第二重佈線路層。 根據本案之另一方面，提出一種封裝結構之製造方 法。封裝結構之製造方法包括以下步驟。提供一封膠件及 一晶片。封膠件具有一第一表面及一第二表面。晶片埋入 於封膠件。晶片之一主動表面暴露於第一表面。姓刻封膠 件，以形成一封膠通孔。於封膠通孔形成一導電柱。形成 一第一重佈線路層（Redistribution Layer，RDL)於第 一表面。第一重佈線路層電性連接導電柱^形成一第二重 佈線路層（Redistribution Layer，RDL)於第二表面， 第二重佈線路層電性連接導電柱。 根據本案之再一方面，提出一種封裝結構。封裝結構 包括一封膠件、一晶片、一第一重佈線路層、一電鍵種子 層及一導電層。封膠件具有一第一表面、一第二表面及一 封膠通孔。封膠通孔從第一表面至第二表面穿透封膠件。 晶片埋入於封膠件。晶片之一主動表面暴露於第一表面。 第重佈線路層具有一線路通孔。第一重佈線路層設置於 第一表面。線路通孔連通於封膠通孔。電鍍種子層設置於 封膠通孔之孔壁及線路通孔之孔壁。導電柱設置於封膠通 孔及線路通孔内。 為了對本案之上述及其他方面更瞭解，下文特舉實施 201248747 例’並配合所附圖式，作詳細說明如下： 【實施方式】 ，凊參照第1A〜1F圖’其繪示一實施例之封裝結構1〇〇 之製造方法。透過第1A〜1F圖之步驟，可以形成雙面具 有重佈線路層之晶圓級晶片内埋式封装結構丨〇〇。 如第1A圖所示，提供一封膠件及一晶片12〇。 封膠件110之材質例如是環氧樹脂材料、有機矽樹脂材料 或聚氨酯材料。晶片120係為内含邏輯電路或記憶胞之裸 晶片。封膠件110具有一第一表面11〇a及一第二表面 ll〇b。晶片120具有一主動表面i2〇a、一非主動表面12〇b 及至少一接墊120c。接墊120c設置於主動表面12〇a。晶 片120埋入於封膠件11〇,晶片120之主動表面12〇a暴露 於第一表面110a。封膠件110可以覆蓋晶片ι2〇之非主動 表面120b或者暴露出晶片120之非主動表面12〇b，端看 設計需求而定。 如第1B圖所示’形成一第一重佈線路層 (Redistribution Layer’RDL) 130 於第一表面 ii〇a。 第一重佈線路層130包括一第一介電層131、一第一導線 層132及一第二介電層133。第一介電層131覆蓋於主動 表面120a上’並暴露出晶片120之接墊i2〇c 第一導線 層132覆蓋於接墊120c及第一介電層131，第一導電層 132會與晶片之接塾120c電性連接。第二介電層133覆蓋 於第一導線層132及第一介電層131，並暴露出部份之第 一導線層132，以形成一第一銲墊134。。 6 201248747 為了不受限於晶片120上之接塾120c的大小和主動 表面120a空間太小的限制’第一重佈線路層13〇可以採 用扇出（Fan-out )之方式來配置，第一重佈線路層130 不僅配置於晶片120之主動表面120a上，一部份會分佈 在封膠件110上。 如第1 c圖所示，钱刻封膠件11 〇及第一重佈線路層 130 ’以分別形成一封膠通孔110h及一線路通孔I30h。在 此步驟中’封膠通孔ll〇h位於晶片120所設置之範圍之 外，以避免破壞晶片120内部之電路。 封膠通孔11 Oh及線路通孔130h係在同一製程動作中 完成’而形成兩端開放之通孔。在一實施例中，可以一雷 射線蝕刻出封膠通孔11 〇h及線路通孔130h。在一實施例 中，亦可以微影製程蝕刻出封膠通孔ll〇h及線路通孔 130h。在一實施例中，亦可以機械鑽孔之方式姓刻出封膠 通孔110h及線路通孔130h。 在此步驟中，係採用兩端皆開放之通孔製程，而不是 採用盲孔製程（只有一端開放）。相較於盲孔製程，通孔 製程在製程良率、品質與成本上，均優於盲孔製程。 如第1D圖所示’貼附一保護膜160於第一表面11 〇a， 以覆蓋第一重佈線路層130。保護膜160具有絕緣性、容 易貼附且容易移除之特性，其材質例如是聚醢亞胺 (Polyimide ’ PI)、聚丙烯（polypropylene，pp)或聚 氨酯（Polyurethane，PU)之高分子聚合物。保護膜16〇 用以在後續電鍍製程中，保護第一重佈線路層13〇，以避 免第一重佈線路層13 0遭到破壞。另外此保護膜16 〇也可 201248747 為一保S蒦載具，此載具可放置於第一表面11 〇a上，同樣 可達到保護第一重佈線路層1 30之功能。 如第1E圖所示’於封膠通孔11 〇h及線路通孔13〇h 形成一導電柱170。在此步驟中，係先形成一電鍍種子層 180於封膠通孔ll〇h之孔壁、線路通孔13〇h之孔壁及保 護膜160之表面。電鍍種子層18〇之材質係為鈦（Ti)、 紹（A1)、鎳（Ni)、釩（V)、銅（Cu)、金（AU)、鎢（w)、 錯（Pd)或銀（Ag)及其合金。形成電鍍種子層18〇之方 式一般係採用無電電鍍。電鍍種子層18〇主要是作為後續 電鍍製程的種子，使電鍍製程能夠施加電流於電鍍種子層 180，並於其上累積導電材料。 鈦（Ti)'銅（㈤、1呂（A1)、銀（Ag)、金（Au)、鎳（Ni) 再以電鍍種子層180為基礎，電鍍導電材料於電鍍種 子層180上，以形成導電柱17〇。導電柱17〇之材質係為 或錫（Sn)及其合金。 如第1F圖所示，形 (Redistribution Layer > RJ)T 如第IF ’ RDL)190於第二表面201248747 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a sealing structure and a method of manufacturing the same, and more particularly to a wafer-embedded package structure and a method of fabricating the same. [Prior Art] With the advancement of technology, various electronic products continue to evolve. Especially in the process of technological development, semiconductor packaging technology plays an extremely important role. In a semiconductor packaging process, wafers are first diced to form individual dies. The grain is then passed through a process such as wire bonding and flip chip to direct its internal trace to the outside and protect the die through a sealant or the like. Under the trend of miniaturization and precision of products, semiconductor packaging technology is constantly pursuing how to improve the precision and compactness of the circuit in a limited space. In addition to 'improving the precision and complexity of the line', how to maintain process yield, quality and cost under new technologies is also an important goal of research and development. SUMMARY OF THE INVENTION The present invention relates to a package structure manufacturing method that utilizes the design and process of through-holes to improve the precision and construction density of the circuit and maintain process yield, quality, and cost. According to one aspect of the present invention, a method of fabricating a package structure is proposed. The manufacturing method of the package structure includes the following steps. Provide a piece of plastic and a wafer. The sealant has a first surface and a second surface. The wafer is embedded in the seal 4 201248747. One of the active surfaces of the wafer is exposed to the first surface. A first redistribution layer (RDL) is formed on the first surface. The encapsulating component and the first re-wiring circuit layer form a glue through hole and a through hole. A conductive pillar is formed on the through hole of the sealant and the through hole of the line. A second redistribution layer (RDL) is formed on the second surface. The conductive pillar is electrically connected to the first redistribution circuit layer and the second redistribution circuit layer. According to another aspect of the present invention, a method of fabricating a package structure is presented. The manufacturing method of the package structure includes the following steps. A piece of plastic and a wafer are provided. The sealant has a first surface and a second surface. The wafer is embedded in the sealant. One of the active surfaces of the wafer is exposed to the first surface. The surname is engraved to form a glue through hole. Forming a conductive pillar in the through hole of the sealant. A first redistribution layer (RDL) is formed on the first surface. The first redistribution circuit layer is electrically connected to the conductive pillars to form a second redistribution layer (RDL) on the second surface, and the second redistribution wiring layer is electrically connected to the conductive pillars. According to still another aspect of the present invention, a package structure is proposed. The package structure includes a glue member, a wafer, a first redistribution circuit layer, a key seed layer and a conductive layer. The sealant has a first surface, a second surface and a glue through hole. The seal through hole penetrates the seal member from the first surface to the second surface. The wafer is embedded in the sealant. One of the active surfaces of the wafer is exposed to the first surface. The first redistribution circuit layer has a line through hole. The first redistribution circuit layer is disposed on the first surface. The through hole of the line is connected to the through hole of the seal. The electroplating seed layer is disposed on the hole wall of the seal through hole and the hole wall of the line through hole. The conductive pillars are disposed in the seal through holes and the through holes of the wires. In order to better understand the above and other aspects of the present application, the following is a detailed description of the example of 201248747, which is described in detail with reference to the accompanying drawings. [Embodiment] Referring to Figures 1A to 1F, an embodiment is illustrated. A manufacturing method of the package structure. Through the steps of FIGS. 1A to 1F, it is possible to form a wafer-level wafer embedded package structure with a double mask and a redistributed wiring layer. As shown in Figure 1A, a piece of plastic and a wafer 12 are provided. The material of the sealant 110 is, for example, an epoxy resin material, an organic resin material or a polyurethane material. The wafer 120 is a bare wafer containing logic or memory cells. The sealant 110 has a first surface 11A and a second surface 11b. The wafer 120 has an active surface i2〇a, an inactive surface 12〇b, and at least one pad 120c. The pad 120c is disposed on the active surface 12〇a. The wafer 120 is embedded in the seal member 11A, and the active surface 12A of the wafer 120 is exposed to the first surface 110a. The encapsulant 110 can cover the inactive surface 120b of the wafer 或者2 or expose the inactive surface 12〇b of the wafer 120, depending on the design requirements. As shown in Fig. 1B, a first redistribution layer (RDL) 130 is formed on the first surface ii 〇 a. The first redistribution circuit layer 130 includes a first dielectric layer 131, a first wiring layer 132, and a second dielectric layer 133. The first dielectric layer 131 covers the active surface 120a and exposes the pad of the wafer 120. The first wire layer 132 covers the pad 120c and the first dielectric layer 131. The first conductive layer 132 and the wafer The connection 120c is electrically connected. The second dielectric layer 133 covers the first wiring layer 132 and the first dielectric layer 131, and exposes a portion of the first wiring layer 132 to form a first bonding pad 134. . 6 201248747 In order not to be limited to the size of the interface 120c on the wafer 120 and the space of the active surface 120a is too small, the first redistribution layer 13 can be configured in a fan-out manner, first The redistribution wiring layer 130 is disposed not only on the active surface 120a of the wafer 120 but also on a portion of the sealing member 110. As shown in Fig. 1c, the engraving member 11 and the first re-wiring layer 130' respectively form a glue through hole 110h and a line through hole I30h. In this step, the sealant vias 11h are outside the range set by the wafer 120 to avoid damaging the circuitry inside the wafer 120. The seal through hole 11 Oh and the line through hole 130h are completed in the same process operation to form a through hole open at both ends. In one embodiment, the via through holes 11 〇h and the line vias 130h may be etched by a laser beam. In one embodiment, the via through hole 〇h and the line via 130h may also be etched by the lithography process. In an embodiment, the seal through hole 110h and the line through hole 130h may be engraved by mechanical drilling. In this step, a through-hole process with open ends is used instead of a blind hole process (only one end is open). Compared with the blind hole process, the through hole process is superior to the blind hole process in process yield, quality and cost. A protective film 160 is attached to the first surface 11 〇a as shown in FIG. 1D to cover the first redistribution wiring layer 130. The protective film 160 has the characteristics of being insulative, easy to attach, and easy to remove, and is made of, for example, a polymer of Polyimide 'PI, polypropylene (PP), or Polyurethane (PU). . The protective film 16 is used to protect the first redistribution wiring layer 13 在 in the subsequent plating process to prevent the first redistribution wiring layer 130 from being damaged. In addition, the protective film 16 can also be used as a protective device. The carrier can be placed on the first surface 11 〇a, and the function of protecting the first redistribution layer 1 30 can also be achieved. As shown in FIG. 1E, a conductive pillar 170 is formed in the seal through hole 11 〇h and the line through hole 13〇h. In this step, a plating seed layer 180 is formed on the hole wall of the sealing through hole 〇h, the hole wall of the line through hole 13〇h, and the surface of the protective film 160. The plating seed layer 18〇 is made of titanium (Ti), sho (A1), nickel (Ni), vanadium (V), copper (Cu), gold (AU), tungsten (w), erroneous (Pd) or silver. (Ag) and its alloys. The method of forming the electroplated seed layer 18 is generally electroless plating. The electroplated seed layer 18 is primarily used as a seed for subsequent electroplating processes to enable the electroplating process to apply an electrical current to the electroplated seed layer 180 and build up a conductive material thereon. Titanium (Ti) 'copper ((5), 1 Lu (A1), silver (Ag), gold (Au), nickel (Ni) based on the electroplated seed layer 180, electroplating a conductive material on the electroplated seed layer 180 to form The conductive pillar 17〇. The material of the conductive pillar 17〇 is either tin (Sn) and its alloy. As shown in Fig. 1F, the shape (Redistribution Layer > RJ)T is IF 'RDL 190 on the second surface.
，形成一第二重佈線路層 其他封裝結構之锡 ，以進行封裝結構 8 201248747 之堆疊。 為了不受限於晶片120之接墊120c的大小和主動表 面120a空間太小的限制’第二重佈線路層19〇可以採用 扇出（Fan-out)之方式來配置，第二重佈線路層19〇不 僅配置於晶片120之主動表面120a上，一部份會分佈在 封膠件110上。 第二重佈線路層190形成後，導電柱17〇電性連接第 一重佈線路層130及第二重佈線路層190,而使得晶片12〇 之内部電路可以在第一表面ll〇a或第二表面u〇b擴展。 透過上述步驟’即可完成封裝結構100。如第1F圖 下方放大部分所示’在線路通孔13〇h與封膠通孔11〇h之 連通處，線路通孔130h之孔徑實質上等於封膠通孔n〇h 之孔徑，而填充於封膠通孔ll〇h及線路通孔13〇h之導電 柱170係為一體成型之結構。並且，請同時參照附圖i及 第1F圖，附圖1為封膠通孔11〇h與線路通孔13〇h之連 通處之SEM圖。附圖1之矩形框線處相當於第1F圖之封 膠通孔中間區域A。經過EDX分析後，研究人員證實中間 區域A並不存在電鍍種子層18〇。 並且，導電桎17〇凸出於第一表面u〇a，而不是實 質上與第一表面11〇a齊平。再者，導電柱17〇之長度 士於封膠件110之厚度L110。事實上，導電柱17〇之長度 貫質上等於封♦件11Q之厚度L11Q與第—重佈線路層130 之厚度L13 0之加總。 在一實施例中，第一重佈線路層130亦可以在導電柱 no形成之步驟之後再形成。請參照第2a〜2m圖，其繪示 201248747 貫知例之封裝結構10 0之製造方法。 士第2Α圖所示，提供封膠件110及晶片120。封膠 件no具有第一表面110a及第二表面u〇b。晶片12〇埋 入於封膠件11()’晶片120之主動表面12Ga暴露於第-表 面 110a。 〜如第2B圖所示，放置封膠件11〇於一機台平台上並 ㈣此封膠件1m刻封膠件11G’以形成封膠通孔 在此步驟中，係採用兩端皆開放之通孔製程，而不 是，用盲孔製程（只有一端開放）。相較於盲孔製程，通 孔製程在製程良率、品質與成本上，均優於盲孔製程。 如第2C圖所示’形成電鍍種子層18〇於封膠通孔11〇h 之孔壁及封膠件11〇之第一表面u〇a、第二表面u〇b。 電鍍種子層1刖之材質例如是鈦（Ti)、鋁（A1)、鎳（Ni)、 飢（V)、銅（Cu)、金（Au)、鎢（W)、錯（Pb)、銀（Ag) 或其組合。 如第2D圖所示’電鍍一金屬材料181於封膠通孔n〇h 内及第一表面ll〇a、第二表面ii〇b上，以形成導電柱 170。金屬材料181例如是鈦（Ti)、銅（Cu)、ls (A1)、 銀（Ag)、金（Au)、鎳（Ni)、錫（Sn)、或其組合。 如第2E圖所示，以蝕刻或化學機械研磨之方式移除 第二表面ll〇b側之金屬材料181及電鍍種子層180。 如第2F圖所示，以蝕刻或化學機械研磨之方式移除 第一表面110a側之金屬材料181及電鍍種子層180,而在 封膠通孔110h内留下導電材料181及電鍍種子層180。 如第2G圖所示，分別形成第一介電層131及第三介 201248747 電層191於第一表面11 〇a及第二表面i1〇b。第一介電層 131至少暴露出接墊i2〇c及導電柱Π0之一端。第三介電 層191至少暴露出導電柱no之另一端。 如第2H圖所示’形成電鍍種子層182於第一表面11〇a 侧及第二表面ll〇b側，以覆蓋第一介電層131、第三介電 層191及暴露之接塾i20c與導電柱之170之兩端。 如第21圖所示，分別形成第一光阻層135及第二光 阻層195於第一表面n〇a側及第二表面ii〇b側。第一光 阻層135及第二光阻層195暴露出部份之電鍍種子層 182，第一光阻層135之開口 135a至少對應於接墊i20c 及導電柱170之一端，第二光阻層195之開口 195a至少 對應於導電柱170之另一端。 如第2J圖所示，分別電鍍第一導線層132及第二導 線層192於第一光阻層135之開口 135a及第二光阻層195 之開口 195a。其中，第一導線層132及第二導線層195之 材質例如是銅（Cu)。 如第2K圖所示，移除第一光阻層135及第二光阻層 195 ’而留下第一導線層132及第二導線層192。 如第2L所不’以雷射或勉刻之方式移除第一導線層 132及第—導線層192所暴露出之電鍵種子層M2。 如第2M圖所示，分別形成第二介電層133及第四介 層193於第-表面11Qa側及第二表面側。第二介 電層133之開口 133a及第四介電層193之開口胸對應 於接墊12Gc或導電柱17Q之兩端。如此—來，第一介電 曰131帛4線層132及第二介電層133即形成第一重 201248747 佈線路層（Redistribution Layer，RDL) 130，而第一重 佈線路層130電性連接導電柱170。此外第三介電層19卜 第二導線層192及第四介電層193即形成第二重佈線路層 (Redistribution Layer，RDL) 190，而第二重佈線路層 190電性連接導電柱170。如此即形成雙面具有重佈線路 層之晶圓級晶片内埋式封裝結構100。 綜上所述，雖然本案已以實施例揭露如上，然其並非 用以限定本案。本案所屬技術領域中具有通常知識者，在 不脫離本案之精神和範圍内，當可作各種之更動與潤飾。 因此，本案之保護範圍當視後附之申請專利範圍所界定者 為準。 【圖式簡單說明】 第1A〜1F圖繪示一實施例之封裝結構之製造方法。 第2A〜2M圖繪示一實施例之封裝結構之製造方法。 附圖1為封膠通孔與線路通孔之連通處之SEM圖。 【主要元件符號說明】 100 :封裝結構 110 :封膠件 110a :第一表面 110b :第二表面 110h :封膠通孔 120 .晶片 120a :主動表面 201248747 120b :非主動表面 120c :接墊 130 :第一重佈線路層 130h :線路通孔 131 :第一介電層 132 :第一導線層 133 :第二介電層 133a、135a、193a、195a ··開口 134 :第一銲墊 135 :第一光阻層 15 0 :錫球 160 :保護膜 170 :導電柱 180、182 :電鍍種子層 181 :金屬材料 190 :第二重佈線路層 191 :第三介電層 192 :第二導線層 193 :第四介電層 194 :第二銲墊 195 :第二光阻層 A :中間區域 L110 :封膠件之厚度 L130:第一重佈線路層之厚度 L170 :導電柱之長度 13Forming a second redistribution layer of tin of other package structures for stacking of package structures 8 201248747. In order not to be limited to the size of the pad 120c of the wafer 120 and the space of the active surface 120a is too small, the second redistribution layer 19 can be configured in a fan-out manner, and the second redistribution line The layer 19 is disposed not only on the active surface 120a of the wafer 120 but also on a portion of the encapsulant 110. After the second redistribution circuit layer 190 is formed, the conductive pillars 17 are electrically connected to the first redistribution wiring layer 130 and the second redistribution wiring layer 190, so that the internal circuit of the wafer 12 can be on the first surface 〇a or The second surface u〇b expands. The package structure 100 can be completed through the above steps. As shown in the enlarged portion at the bottom of FIG. 1F, at the intersection of the line through hole 13〇h and the seal through hole 11〇h, the hole diameter of the line through hole 130h is substantially equal to the aperture of the seal through hole n〇h, and is filled. The conductive pillars 170 in the seal through hole 〇 〇 h and the line through holes 13 〇 h are integrally formed. Further, please refer to FIG. 1 and FIG. 1F at the same time. FIG. 1 is an SEM diagram of the connection between the sealing through hole 11〇h and the line through hole 13〇h. The rectangular frame line of Fig. 1 corresponds to the intermediate area A of the seal through hole of Fig. 1F. After EDX analysis, the researchers confirmed that there was no plating seed layer 18 in the middle region A. Also, the conductive turns 17 are protruded from the first surface u〇a instead of being substantially flush with the first surface 11A. Furthermore, the length of the conductive post 17〇 is the thickness L110 of the sealant 110. In fact, the length of the conductive post 17〇 is substantially equal to the sum of the thickness L11Q of the sealing member 11Q and the thickness L13 0 of the first repeating wiring layer 130. In an embodiment, the first redistribution wiring layer 130 may also be formed after the step of forming the conductive pillar no. Please refer to FIG. 2a to FIG. 2m, which illustrate a manufacturing method of the package structure 100 of the example of 201248747. As shown in Figure 2, the encapsulant 110 and the wafer 120 are provided. The sealant no has a first surface 110a and a second surface u〇b. The active surface 12Ga of the wafer 12, which is buried in the encapsulant 11 ()' wafer 120, is exposed to the first surface 110a. ~ As shown in Fig. 2B, the sealing member 11 is placed on a platform platform and (4) the sealing member 1m is engraved with the sealing member 11G' to form a sealing through hole. In this step, both ends are open. Through-hole process, instead of blind hole process (only one end is open). Compared with the blind hole process, the through hole process is superior to the blind hole process in process yield, quality and cost. As shown in Fig. 2C, the electroplated seed layer 18 is formed on the hole wall of the seal through hole 11〇h and the first surface u〇a and the second surface u〇b of the sealant 11〇. The material of the plating seed layer 1 is, for example, titanium (Ti), aluminum (A1), nickel (Ni), hunger (V), copper (Cu), gold (Au), tungsten (W), erbium (Pb), silver. (Ag) or a combination thereof. As shown in Fig. 2D, a plating metal material 181 is formed in the sealing via hole n〇h and on the first surface 11a and the second surface ii〇b to form a conductive pillar 170. The metal material 181 is, for example, titanium (Ti), copper (Cu), ls (A1), silver (Ag), gold (Au), nickel (Ni), tin (Sn), or a combination thereof. As shown in Fig. 2E, the metal material 181 on the second surface 11b side and the plating seed layer 180 are removed by etching or chemical mechanical polishing. As shown in FIG. 2F, the metal material 181 on the side of the first surface 110a and the plating seed layer 180 are removed by etching or chemical mechanical polishing, and the conductive material 181 and the plating seed layer 180 are left in the via hole 110h. . As shown in FIG. 2G, the first dielectric layer 131 and the third dielectric layer 20748 are formed on the first surface 11a and the second surface i1b, respectively. The first dielectric layer 131 exposes at least one of the pads i2〇c and the conductive pillars. The third dielectric layer 191 exposes at least the other end of the conductive pillar no. As shown in FIG. 2H, a plating seed layer 182 is formed on the first surface 11a side and the second surface 11b side to cover the first dielectric layer 131, the third dielectric layer 191, and the exposed interface i20c. And the ends of the conductive column 170. As shown in Fig. 21, the first photoresist layer 135 and the second photoresist layer 195 are formed on the first surface n〇a side and the second surface ii〇b side, respectively. The first photoresist layer 135 and the second photoresist layer 195 expose a portion of the plating seed layer 182. The opening 135a of the first photoresist layer 135 corresponds to at least one of the pad i20c and the conductive post 170, and the second photoresist layer The opening 195a of 195 corresponds at least to the other end of the conductive post 170. As shown in Fig. 2J, the first wiring layer 132 and the second wiring layer 192 are respectively plated to the opening 135a of the first photoresist layer 135 and the opening 195a of the second photoresist layer 195. The material of the first wire layer 132 and the second wire layer 195 is, for example, copper (Cu). As shown in Fig. 2K, the first photoresist layer 135 and the second photoresist layer 195' are removed leaving the first wiring layer 132 and the second wiring layer 192. The first wire layer 132 and the electric wire seed layer M2 exposed by the first wire layer 192 are removed by laser or engraving as in 2L. As shown in Fig. 2M, the second dielectric layer 133 and the fourth dielectric layer 193 are formed on the first surface 11Qa side and the second surface side, respectively. The opening 133a of the second dielectric layer 133 and the opening chest of the fourth dielectric layer 193 correspond to both ends of the pad 12Gc or the conductive post 17Q. In this way, the first dielectric layer 131 帛 4 line layer 132 and the second dielectric layer 133 form a first heavy 201248747 Redistribution Layer (RDL) 130, and the first redistribution circuit layer 130 is electrically connected. Conductive post 170. In addition, the third dielectric layer 19 and the second dielectric layer 193 form a second redistribution layer (RDL) 190, and the second redistribution layer 190 is electrically connected to the conductive pillars 170. . Thus, a wafer level wafer embedded package structure 100 having a double-sided wiring layer is formed. In summary, although the present invention has been disclosed above by way of example, it is not intended to limit the present invention. Those who have ordinary knowledge in the technical field of the present invention can make various changes and refinements without departing from the spirit and scope of the case. Therefore, the scope of protection in this case is subject to the definition of the scope of the patent application attached. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1F are views showing a method of manufacturing a package structure according to an embodiment. 2A to 2M are diagrams showing a method of manufacturing a package structure of an embodiment. Figure 1 is an SEM image of the junction of the seal through hole and the line through hole. [Main component symbol description] 100: package structure 110: sealant 110a: first surface 110b: second surface 110h: seal through hole 120. wafer 120a: active surface 201248747 120b: inactive surface 120c: pad 130: First redistribution circuit layer 130h: line via hole 131: first dielectric layer 132: first wire layer 133: second dielectric layer 133a, 135a, 193a, 195a · opening 134: first pad 135: A photoresist layer 150: solder ball 160: protective film 170: conductive pillars 180, 182: plating seed layer 181: metal material 190: second redistribution wiring layer 191: third dielectric layer 192: second wiring layer 193 : Fourth dielectric layer 194 : second bonding pad 195 : second photoresist layer A : intermediate region L110 : thickness of the sealing member L130 : thickness of the first redistribution wiring layer L170 : length of the conductive pillar 13