TW201246520A - Semiconductor device, manufacturing method thereof, and electronic apparatus - Google Patents
Semiconductor device, manufacturing method thereof, and electronic apparatus Download PDFInfo
- Publication number
- TW201246520A TW201246520A TW100141094A TW100141094A TW201246520A TW 201246520 A TW201246520 A TW 201246520A TW 100141094 A TW100141094 A TW 100141094A TW 100141094 A TW100141094 A TW 100141094A TW 201246520 A TW201246520 A TW 201246520A
- Authority
- TW
- Taiwan
- Prior art keywords
- connection
- semiconductor
- semiconductor wafer
- wiring
- wafer unit
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 778
- 238000004519 manufacturing process Methods 0.000 title claims description 55
- 238000003384 imaging method Methods 0.000 claims abstract description 224
- 235000012431 wafers Nutrition 0.000 claims description 358
- 239000004020 conductor Substances 0.000 claims description 295
- 239000000758 substrate Substances 0.000 claims description 160
- 229910052751 metal Inorganic materials 0.000 claims description 125
- 239000002184 metal Substances 0.000 claims description 125
- 238000012545 processing Methods 0.000 claims description 47
- 238000000034 method Methods 0.000 claims description 40
- 239000007787 solid Substances 0.000 claims description 30
- 230000008569 process Effects 0.000 claims description 26
- 230000001681 protective effect Effects 0.000 claims description 25
- 238000003491 array Methods 0.000 claims description 14
- 230000000149 penetrating effect Effects 0.000 claims description 11
- 230000003287 optical effect Effects 0.000 claims description 9
- 239000010410 layer Substances 0.000 description 177
- 238000010586 diagram Methods 0.000 description 38
- 230000008878 coupling Effects 0.000 description 24
- 238000010168 coupling process Methods 0.000 description 24
- 238000005859 coupling reaction Methods 0.000 description 24
- 230000003071 parasitic effect Effects 0.000 description 23
- 239000011229 interlayer Substances 0.000 description 18
- 229910044991 metal oxide Inorganic materials 0.000 description 17
- 150000004706 metal oxides Chemical class 0.000 description 17
- 238000004364 calculation method Methods 0.000 description 14
- 238000002955 isolation Methods 0.000 description 14
- 239000000470 constituent Substances 0.000 description 13
- 239000010949 copper Substances 0.000 description 12
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 11
- 238000006243 chemical reaction Methods 0.000 description 10
- 230000008901 benefit Effects 0.000 description 9
- 239000003990 capacitor Substances 0.000 description 9
- 238000005286 illumination Methods 0.000 description 9
- 239000012535 impurity Substances 0.000 description 8
- 239000000047 product Substances 0.000 description 8
- 238000009751 slip forming Methods 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 7
- 230000006870 function Effects 0.000 description 7
- 239000010931 gold Substances 0.000 description 7
- 239000012790 adhesive layer Substances 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 210000004027 cell Anatomy 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 238000003466 welding Methods 0.000 description 4
- 238000007667 floating Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000000376 reactant Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000007767 bonding agent Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000011265 semifinished product Substances 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 239000007858 starting material Substances 0.000 description 2
- 239000010959 steel Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000872 buffer Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 210000002858 crystal cell Anatomy 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
201246520 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種諸如一固態成像元件之半導體元件、 製造該半導體元件之一種方法及包括該固態成像元件之一 種電子裝置，諸如一相機。 【先前技術】 作為一固態成像元件，已知一放大型固態成像元件，諸 如一 MOS，諸如一 CMOS(互補金屬氧化物半導體）、影像 感測器。此外，已知一電荷轉移型固態成像元件，諸如/ CCD(電荷耦合元件）影像感測器。此等固態成像元件廣泛 地用於數位靜態相機、數位視頻攝影機或諸如此類中。於 最近數年中，就低電力電壓及電力消耗而言，M〇s影像感 測器已廣泛地用作裝配於行動裝置（諸如具有一相機或 PDA(個人數位助理）之一可攜式電話）中之固態成像元件。 在MOS固態成像元件中，一單元像素包括充當一光電轉 換單元之一光電二極體及複數個像素電晶體。M〇s固態成 像元件包括配置成二維陣列形狀之複數個單元像素之一像 素陣列（像素區）及-周邊電路區。該複數個像素電晶體形 成為MOS電晶體，且包括為—傳輸電晶體、—重設電晶 體、-放大電晶體之三個電晶體，或包括另外包括一選擇 電晶體之四個電晶體。 迄今，就一 MOS固態成像元侔士 几仔之本身而論，已建議各種 固態成像元件，其中包括其中西？番、包如 ^ . γ配置複數個像素之一像素陣 列之一半導體晶片與包括執行作歌♦ 琥處理之一邏輯電路之一 157964.doc 201246520 半導體晶片彼等電連接且因此組態為一單個元件。舉例而 言’日本未經審查之專利申請公開案第2006-49361號揭示 一種半導體模組，其中藉由微凸塊將其中在每一像素胞中 包括一微墊之一背側照明式影像感測器晶片與包括其中形 成一信號處理電路之若干微墊之一信號處理晶片彼此連 接。 國際公開案第WO 2006/129762號揭示一種半導體影像感 測器模組’其中堆疊包括一影像感測器之一第一半導體晶 片、包括一類比/數位轉換器陣列之一第二半導體晶片、 及包括一記憶體器件陣列之一第三半導體晶片。該第一半 導體晶片與該第二半導體晶片經由一凸塊彼此連接，該凸 塊係一導電連接導體。該第二半導體晶片與該第三半導體 晶片藉由穿透該第二半導體晶片之一貫通觸點彼此連接。 如曰本未經審查之專利申請公開案第2〇〇6_49361號中所 揭示，已建議用於合併不同電路晶片（諸如影像感測器晶 片及執行信號處理之邏輯電路）之各種技術。在相關技術 中’實質已完成之功能晶片經由所形成之貫通連接孔彼此 連接。另-選擇係’該等晶片經由凸塊彼此連接。 【發明内容】 本申請案已建議-固態成像元件，其中包括—像素陣列 之半導體晶片單元與包括一邏輯電路之一半導體晶片單 7C彼此接合’以使得該等各別半導體晶片發揮充分效能且 匕達成大量生產及低成本。該固態成像元件係藉由如下 來形成字包括—半完成像素陣列之一第一半導體晶片單 157964.doc 201246520 / 元與包括一半完成邏輯電路之一第二半導體晶片單元接 合；薄化該第一半導體晶片單元；及然後連接該像素陣列 與該邏輯電路。該像素陣列與該邏輯電路係藉由如下來連 接：形成連接至該第一半導體晶片單元之一佈線之—連接 • 導體、穿透該第一半導體晶片單元且連接至該第二半導體 晶片單元之一佈線之一貫通連接導體及形成為將該兩個連 接導體彼此連接之一連接導體之一連接佈線。此後，將該 成品劃分成右干晶片，且因此將該固態成像元件級態為— 背側照明式固態成像元件。 在該固態成像元件中’該連接導體與該貫通連接導體經 形成以隱埋於其之間間置有一絕緣膜之穿透該第一半導體 晶片單元之一矽基板之貫通孔中。連接導體之剖面面積與 貫通連接導體之剖面面積係相對較大的。出於此原因，當 不忽略矽基板與連接導體及貫通連接導體之間所致的寄生 電容時’已證明該寄生電容可使一電路之一驅動速度惡化 且因此可致使固態成像元件之高效能之惡化。 在具有其中經接合之半導體晶片單元係藉由連接導體及 貫通連接導體彼此連接之一組態之固態成像元件中，一對 . 導體（連接導體及貫通連接導體）係連接至對應於每一垂直 - 信號線之每一佈線（亦即，敷設佈線）。此時，出現作為寄 生電容之接地電容及毗鄰耦合電容。舉例而言，接地電容 係在一佈線與具有—接地電位之一半導體基板之間的寄生 電容。相鄰耦合電容係在毗鄰敷設佈線或一對毗鄰導體之 間的寄生電容。當增強功率或提供一缓衝電路流動電流時 157964.doc -9- 201246520 可使接地電容分解。然而，毗鄰耦 線干擾而不可被分解。 由於與1鄰 寄生電容之問題甚至可出現於其中各自包括—半導體 體電路之半導體晶片單元彼此接合且該等半導體晶片單元 藉由一連接導體及一貫通連接導體彼此連接之一=疋 件中。 媸疋 期望提供-種半導體元件’諸如能夠減小寄生電容且達 成高效能之-固態成像元件’及其—製造方法。此外，期 望提供一種包含該固態成像元件之電子裝置，諸如—相 機。 根據本發明之一實施例，提供一半導體元件，其包括一 經堆疊半導體晶片，該經堆疊半導體晶片係藉由將兩個或 兩個以上半導體晶片單元彼此接合來形成，且其中至少— 像素陣列及一多層佈線層係形成於一第一半導體晶片單元 中且一邏輯電路及一多層佈線層係形成於一第二半導體晶 片單元中。該第一半導體晶片單元包括其中該第一半導2 晶片單元之一部分之一半導體區段經完全移除之—半導體 移除區。根據本發明之該實施例之半導體元件包括形成於 該半導體移除區中且將該第一半導體晶片單元與該第二半 導體晶片單元彼此連接之複數個連接佈線。因此，該半導 體元件經組態為一背側照明式固態成像元件。 在根據本發明之實施例之半導體元件中，該半導體移除 區經形成以使得完全移除具有一像素陣列之該第—半導體 晶片之一部分之半導體區段。連接該第一半導體晶片單元 157964.doc 201246520 與該第一半導體晶片單元之連接佈線係形成於該半導體移 于'區中因此’可減小連接佈線與半導體之間的寄生電 容。 根據本發明之另一實施例，提供製造一半導體元件之一 方法。该方法包括接合至少包括—第一半導體晶圓及一第 一半導體晶圓之兩個或兩個以上半導體晶圓。在該第一半 導體晶圓巾，—像素陣列及—多層佈線層係形成於充當一 第半導體晶片單元之一區中。在該第二半導體晶圓中， 一邏輯電路及一多層佈線層係形成於充當一第二半導體晶 片單7L之一區中。該方法進一步包括藉由完全移除充當該 第一半導體晶圓中之第一半導體晶片單元之該區之一部分 之一半導體區段來形成一半導體移除區。該方法進一步包 括在《亥半導體移除區中形成連接該第一半導體晶片單元與 該第二半導體晶片單元之複數個連接佈線且將形成為一最 終產品之半導體晶圓劃分成若干晶片。因此，製造背側照 明式固態成像元件。 在根據本發明之實施例之製造半導體元件之方法中，將 兩個或更夕個半導體晶圓彼此接合，完全移除充當具有像 素陣列之第一半導體晶片單元之區之一部分之半導體區 段，在該半導體移除區中形成將該第一半導體晶片單元與 肩第一半導體晶片單元彼此連接之連接佈線。因此，可製 造能夠減小連接佈線與+導體之間㈣纟電容之背侧照明 式固態成像元件。 根據本發明之又一實施例，提供一電子裝置，其包括. 157964.doc -11 - 201246520 一固態成像元件；將入射光引導至該固態成像元件之一光 電轉換單元之一光學系統；處理自該固態成像元件輪出之 一信號之一信號處理電路《該固態成像元件包括一經堆疊 半導體晶片’該經堆疊半導體晶片係藉由將兩個或兩個以 上半導體晶片單元彼此接合來形成，且其中一像素陣列及 一多層佈線層至少形成於一第一半導體晶片單元中且一邏 輯電路及一多層佈線層至少形成於一第二半導體晶片單元 中。該第一半導體晶片單元包括其中該第一半導體晶片單 元之一部分之一半導體區段經完全移除之一半導體移除 區。根據本發明之該實施例之固態成像元件進一步包括形 成於該半導體移除區中且將該第一半導體晶片單元與該第 一半導體晶片單元彼此連接之複數個連接佈線。該固態成 像元件經組態為背側照明式固態成像元件。 根據本發明之實施例之電子裝置將具有上文所闡述組態 之背側照明式固態成像元件包括為固態成像元件。因此， 該固態成像元件能夠減小半導體與連接該第一半導體晶片 單元與第二半導體晶片單元之連接佈線之間的寄生電容。 根據本發明之又一實施例，提供一半導體元件，該半導 體疋件包括一經堆疊半導體晶片，該經堆疊半導體晶片係 藉由將兩個或兩個以上半導體晶片單元彼此接合來形成， 且其中至少一第一半導體積體電路及一多層佈線層係形成 於一第一半導體晶片單元中且一第二半導體積體電路及一 多層佈線層係形成於一第二半導體晶片單元中。該第一半 導體晶片單元包括其中該第一半導體晶片單元之一部分之 157964.doc -12·201246520 VI. Description of the Invention: The present invention relates to a semiconductor element such as a solid-state imaging element, a method of manufacturing the same, and an electronic device including the solid-state imaging element, such as a camera. [Prior Art] As a solid-state imaging element, an amplifying type solid-state imaging element such as a MOS such as a CMOS (Complementary Metal Oxide Semiconductor) or an image sensor is known. Further, a charge transfer type solid-state imaging element such as a /CCD (Charge Coupled Device) image sensor is known. These solid-state imaging elements are widely used in digital still cameras, digital video cameras, or the like. In recent years, M〇s image sensors have been widely used as mobile devices (such as portable phones with a camera or PDA (personal digital assistant)) in terms of low power voltage and power consumption. Solid state imaging element. In the MOS solid-state imaging element, a unit pixel includes a photodiode serving as one photoelectric conversion unit and a plurality of pixel transistors. The M〇s solid-state imaging element includes a pixel array (pixel region) and a peripheral circuit region of a plurality of unit pixels arranged in a two-dimensional array shape. The plurality of pixel transistors are formed into MOS transistors and include three transistors which are - a transmission transistor, a reset transistor, an amplifying transistor, or a fourth transistor additionally including a selection transistor. So far, as far as a MOS solid-state imaging element gentleman is concerned, various solid-state imaging components have been proposed, including West? 、,包如^. γ Configuring one of a plurality of pixels, one of the pixel arrays, the semiconductor wafer and one of the logic circuits including the one of the logic circuits 157964.doc 201246520 are electrically connected and thus configured as a single component . For example, the Japanese Unexamined Patent Application Publication No. 2006-49361 discloses a semiconductor module in which a micro-bump is used to include a backside illuminated image in one of the pixel cells. The tester wafer is connected to one another with a signal processing wafer including a plurality of micropads in which a signal processing circuit is formed. International Publication No. WO 2006/129762 discloses a semiconductor image sensor module in which a first semiconductor wafer including one image sensor, a second semiconductor wafer including an array of analog/digital converters, and A third semiconductor wafer comprising one of the memory device arrays. The first semiconductor wafer and the second semiconductor wafer are connected to each other via a bump, and the bump is a conductive connecting conductor. The second semiconductor wafer and the third semiconductor wafer are connected to each other by a through contact penetrating through the second semiconductor wafer. Various techniques for combining different circuit chips, such as image sensor wafers and logic circuits for performing signal processing, have been proposed as disclosed in Japanese Unexamined Patent Application Publication No. Hei No. Hei. In the related art, the substantially completed functional wafers are connected to each other via the formed through-connection holes. Alternatively - the selection of the wafers is connected to each other via bumps. SUMMARY OF THE INVENTION The present application has proposed a solid-state imaging device in which a semiconductor wafer unit including a pixel array and a semiconductor wafer unit 7C including a logic circuit are bonded to each other 'to enable the respective semiconductor wafers to perform sufficiently and 匕Achieve mass production and low cost. The solid-state imaging element is formed by forming a word including a semi-finished pixel array, a first semiconductor wafer, a single semiconductor wafer, 157964.doc 201246520, and a second semiconductor wafer unit including one of the half-completed logic circuits; thinning the first a semiconductor wafer unit; and then connecting the pixel array to the logic circuit. The pixel array and the logic circuit are connected by forming a connection conductor connected to one of the first semiconductor wafer units, penetrating the first semiconductor wafer unit, and connecting to the second semiconductor wafer unit. One of the wirings is connected to the connecting conductor and one of the connecting conductors that connects the two connecting conductors to each other. Thereafter, the finished product is divided into right-handed wafers, and thus the solid-state imaging element is graded as a backside illuminated solid-state imaging element. In the solid-state imaging element, the connecting conductor and the through-connecting conductor are formed to be buried between the through-holes of the one of the first semiconductor wafer units with an insulating film interposed therebetween. The cross-sectional area of the connecting conductor and the cross-sectional area of the through-connecting conductor are relatively large. For this reason, when the parasitic capacitance between the 矽 substrate and the connection conductor and the through-connection conductor is not neglected, 'the parasitic capacitance has been proven to deteriorate the driving speed of one of the circuits and thus the high performance of the solid-state imaging element. Deterioration. In a solid-state imaging element having a configuration in which a bonded semiconductor wafer unit is connected to each other by a connection conductor and a through-connection conductor, a pair of conductors (connection conductors and through-connection conductors) are connected to correspond to each vertical - Each wiring of the signal line (ie, laying wiring). At this time, a grounding capacitor as a parasitic capacitor and an adjacent coupling capacitor appear. For example, the ground capacitance is a parasitic capacitance between a wiring and a semiconductor substrate having a ground potential. Adjacent coupling capacitors are parasitic capacitances between adjacent routing wires or a pair of adjacent conductors. When boosting power or providing a snubber circuit current, 157964.doc -9- 201246520 can decompose the grounding capacitor. However, adjacent coupling interference cannot be broken down. The problems with the parasitic capacitance of 1 may occur even in the case where the semiconductor wafer units each including the semiconductor circuit are bonded to each other and the semiconductor wafer units are connected to each other by a connecting conductor and a through connecting conductor.期望 It is desirable to provide a semiconductor element such as a solid-state imaging element' capable of reducing parasitic capacitance and achieving high performance, and a manufacturing method thereof. Furthermore, it is desirable to provide an electronic device including the solid-state imaging element, such as a camera. According to an embodiment of the present invention, there is provided a semiconductor device including a stacked semiconductor wafer formed by bonding two or more semiconductor wafer units to each other, and wherein at least - a pixel array and A multilayer wiring layer is formed in a first semiconductor wafer unit and a logic circuit and a multilayer wiring layer are formed in a second semiconductor wafer unit. The first semiconductor wafer unit includes a semiconductor removal region in which one of the semiconductor portions of one of the first semiconductor wafer units is completely removed. A semiconductor device according to this embodiment of the present invention includes a plurality of connection wirings formed in the semiconductor removal region and connecting the first semiconductor wafer unit and the second semiconductor wafer unit to each other. Thus, the semiconductor component is configured as a backside illuminated solid state imaging element. In the semiconductor device according to an embodiment of the present invention, the semiconductor removal region is formed such that the semiconductor portion of a portion of the first semiconductor wafer having a pixel array is completely removed. Connecting the first semiconductor wafer unit 157964.doc 201246520 and the connection wiring of the first semiconductor wafer unit are formed in the semiconductor to be moved in the 'region so that the parasitic capacitance between the connection wiring and the semiconductor can be reduced. According to another embodiment of the present invention, a method of fabricating a semiconductor component is provided. The method includes bonding two or more semiconductor wafers including at least a first semiconductor wafer and a first semiconductor wafer. The first semiconductor wafer, the pixel array and the multi-layer wiring layer are formed in a region serving as a first semiconductor wafer unit. In the second semiconductor wafer, a logic circuit and a multilayer wiring layer are formed in a region serving as a second semiconductor wafer sheet 7L. The method further includes forming a semiconductor removal region by completely removing a semiconductor segment that is part of the region of the first semiconductor wafer unit in the first semiconductor wafer. The method further includes forming a plurality of connection wirings connecting the first semiconductor wafer unit and the second semiconductor wafer unit in the semiconductor removal region and dividing the semiconductor wafer formed into a final product into a plurality of wafers. Therefore, a back side illumination type solid state imaging element is manufactured. In a method of fabricating a semiconductor device according to an embodiment of the present invention, two or more semiconductor wafers are bonded to each other to completely remove a semiconductor segment serving as a portion of a region of the first semiconductor wafer unit having the pixel array, A connection wiring connecting the first semiconductor wafer unit and the shoulder first semiconductor wafer unit to each other is formed in the semiconductor removal region. Therefore, it is possible to manufacture a back side illumination type solid-state imaging element capable of reducing the (four) tantalum capacitance between the connection wiring and the + conductor. According to still another embodiment of the present invention, there is provided an electronic device comprising: 157964.doc -11 - 201246520 a solid-state imaging element; directing incident light to an optical system of one of the photoelectric conversion units of the solid-state imaging element; a signal processing circuit of one of the signals of the solid-state imaging device; the solid-state imaging device includes a stacked semiconductor wafer; the stacked semiconductor wafer is formed by bonding two or more semiconductor wafer units to each other, and wherein A pixel array and a multilayer wiring layer are formed at least in a first semiconductor wafer unit, and a logic circuit and a multilayer wiring layer are formed in at least a second semiconductor wafer unit. The first semiconductor wafer unit includes a semiconductor removal region in which one of the semiconductor segments of one of the first semiconductor wafer units is completely removed. The solid-state imaging element according to this embodiment of the invention further includes a plurality of connection wirings formed in the semiconductor removal region and connecting the first semiconductor wafer unit and the first semiconductor wafer unit to each other. The solid state imaging element is configured as a backside illuminated solid state imaging element. An electronic device according to an embodiment of the present invention includes a back side illumination type solid state imaging element having the configuration set forth above as a solid state imaging element. Therefore, the solid-state imaging element can reduce the parasitic capacitance between the semiconductor and the connection wiring connecting the first semiconductor wafer unit and the second semiconductor wafer unit. According to still another embodiment of the present invention, a semiconductor device is provided, the semiconductor device including a stacked semiconductor wafer formed by bonding two or more semiconductor wafer units to each other, and wherein at least A first semiconductor integrated circuit and a multilayer wiring layer are formed in a first semiconductor wafer unit, and a second semiconductor integrated circuit and a multilayer wiring layer are formed in a second semiconductor wafer unit. The first semiconductor wafer unit includes a portion of the first semiconductor wafer unit 157964.doc -12
S 201246520 一半導體區段經完全移除之一半導體移除區。根據本發明 之该實施例之半導體元件進—步包括形成於該半導體移除 區中且將該第一半導體晶片單元與該第二半導體晶片單元 彼此連接之複數個連接佈線。 在根據本發明之該實施例之半導體元件中，形成其中完 全移除該第一半導體晶片單元之一部分之半導體區段之半 導體移除區且形成將其中一半導體積體電路形成於該半導 體移除區中之第一半導體晶片單元與第二半導體晶片單元 彼此連接之連接佈線。因此，可減小連接佈線與 間的寄生電容。 根據本發明之實施例之半導體元件，可減少半導體與將 該第一半導體晶片單元與該第二半導體晶片單元彼此連接 之連接佈線之間的寄生電容。因此，可實現具有高效能之 由接合之晶片形成之背側照明式固態成像元件。 根據本發明之該實施例製造該半導體元件之方法，可減 少半導體與將該第一半導體晶片單元與該第二半導體晶片 單元彼此連接之連接佈線之間的寄生電容。因此，可實現 具有尚效能之由接合之晶片形成之背側照明式固態成像元 件。 根據本發明之該實施例之電子裝置，可減少寄生電容且 提供由該等經接合晶片形成之具有高效能之背側照明式固 態成像元件。因此，可提供一電子裝置，諸如一高品質相 機。 根據根據本發明之該實施例之半導體元件，可減小半導 157964.doc •13- 201246520 體與將該第一半導體晶片單元與該第二半導體晶片單元彼 此連接之連接佈線之間的寄生電容。因此，可實現具有高 效能之由經接合之晶片形成之半導體積體電路元件。 【實施方式】 在下文中’將闡述用於貫行本發明之模式（在下文中稱 作實施例）。將按以下次序進行說明。 1. MOS固態成像元件之整體組態之實例 2. 第一實施例（固態成像元件之組態之實例及其製造方 法之實例） 3 ·第二實施例（固態成像元件之組態之實例及其製造方 法之實例） 4 ·第三實施例（固態成像元件之組態之實例及其製造方 法之實例） 5. 第四實施例（固態成像元件之組態之實例） 6. 第五實施例（固態成像元件之組態之實例） 7. 第六實施例（固態成像元件之組態之實例） 8. 第七實施例（固態成像元件之組態之實例） 9. 第八實施例（半導體元件之組態之實例） 10. 第九實施例（半導體元件之組態之實例） 11. 第十實施例（半導體元件之組態之實例） 12. 第十一實施例（半導體元件之組態之實例） 1 · MOS固態成像元件之整體組態之實例 圖1係根據本發明之實施例應用於一半導體元件之一 MOS固態成像元件之整體組態之一圖示。該MOS固態成像S 201246520 A semiconductor segment is completely removed by one of the semiconductor removal regions. The semiconductor device according to this embodiment of the present invention further includes a plurality of connection wirings formed in the semiconductor removal region and connecting the first semiconductor wafer unit and the second semiconductor wafer unit to each other. In the semiconductor device according to this embodiment of the invention, a semiconductor removal region in which a semiconductor portion of a portion of the first semiconductor wafer unit is completely removed is formed and a semiconductor integrated circuit is formed in the semiconductor removal A connection wiring in which the first semiconductor wafer unit and the second semiconductor wafer unit in the region are connected to each other. Therefore, the parasitic capacitance between the connection wiring and between can be reduced. According to the semiconductor element of the embodiment of the invention, the parasitic capacitance between the semiconductor and the connection wiring connecting the first semiconductor wafer unit and the second semiconductor wafer unit to each other can be reduced. Therefore, a back side illumination type solid state imaging element formed of a bonded wafer having high performance can be realized. According to this embodiment of the invention, the method of manufacturing the semiconductor element can reduce the parasitic capacitance between the semiconductor and the connection wiring connecting the first semiconductor wafer unit and the second semiconductor wafer unit to each other. Therefore, a backside illuminated solid-state imaging element formed of a bonded wafer having an effective performance can be realized. According to the electronic device of this embodiment of the present invention, parasitic capacitance can be reduced and a high-performance backside illumination type solid-state imaging element formed of the bonded wafers can be provided. Therefore, an electronic device such as a high quality camera can be provided. According to the semiconductor element according to the embodiment of the present invention, the parasitic capacitance between the semiconductor 157964.doc • 13-201246520 body and the connection wiring connecting the first semiconductor wafer unit and the second semiconductor wafer unit to each other can be reduced. . Therefore, a semiconductor integrated circuit element formed of a bonded wafer having high efficiency can be realized. [Embodiment] Hereinafter, a mode for carrying out the invention (hereinafter referred to as an embodiment) will be explained. The explanation will be made in the following order. 1. Example of Overall Configuration of MOS Solid-State Imaging Element 2. First Embodiment (Example of Configuration of Solid-State Imaging Element and Example of Manufacturing Method) 3 · Second Embodiment (Example of Configuration of Solid-State Imaging Element and Example of the manufacturing method thereof) 4. Third Embodiment (Example of Configuration of Solid-State Imaging Element and Example of Manufacturing Method) 5. Fourth Embodiment (Example of Configuration of Solid-State Imaging Element) 6. Fifth Embodiment (Example of Configuration of Solid-State Imaging Element) 7. Sixth Embodiment (Example of Configuration of Solid-State Imaging Element) 8. Seventh Embodiment (Example of Configuration of Solid-State Imaging Element) 9. Eighth Embodiment (Semiconductor Example of Configuration of Components) 10. Ninth Embodiment (Example of Configuration of Semiconductor Element) 11. Tenth Embodiment (Example of Configuration of Semiconductor Element) 12. Eleventh Embodiment (Configuration of Semiconductor Element) EXAMPLES 1] Example of Overall Configuration of MOS Solid-State Imaging Element FIG. 1 is a diagram showing an overall configuration of a MOS solid-state imaging element applied to a semiconductor element according to an embodiment of the present invention. The MOS solid state imaging
157964.doc •14· S 201246520 元件根據各別實施例應用於_固態成像元件。如在圖 斤展示 貫例性固態成像元件1包括一像素陣列（所謂的 像素區)3及一周邊電路區段’在該像素陣列中包括複數個 光電轉換單元之像素2以二維陣列形式規則地配置於一半 ， ^體基板U(諸如一石夕基板）上。像素2包括光電轉換單元 (諸如光電二極體）及複數個像素電晶體（所謂的M〇s電晶 體）該複數個像素電晶體可包括（舉例而言）三個電晶體： -傳輸電晶體、—重設電晶體及一放大電晶體。該複數個 像素電晶體可藉由進一步提供一選擇電晶體而包括四個電 a日體 I元像素之一等效電路具有一常規組態且因此將 不作詳細說明。像素2可組態為一個單元像素。此外，像 素2具有像素共用結構。該像素共用結構係由複數個光 電二極體、複數個傳輸電晶體、一個共用浮動擴散及一個 共用像素電晶體形成。亦即，在該像素共用結構中，形成 該複數個單元像素之光電二極體及傳輸電晶體各自共用不 同像素電晶體。 周邊電路區段包括-垂直驅動電路4、行信號處理電路 5、一水平驅動電路6、一輸出電路7及一控制電路8。 • 控制電路8接收關於一輸入時脈、-操作模式或諸如此 ' 冑之一指令之資料並輸出關於固態成像元件之内部資訊或 諸如此類之資料。亦即，控制電路8產生充當分別根據一 垂直同步仏號、一水平同步信號及一主時脈之垂直驅動電 路4、行信號處理電路5、水平驅動電路6及諸如此類之操 作之參考之時脈信號或控制信號。此等信號係輸入至垂直 157964.doc -15- 201246520 驅動電路4、行信號處理電路5、水平驅動電路认諸如此 類。 垂直驅動電路4包括（舉例而言）移位暫存器，其選擇像 素驅動線、供應脈衝用於驅動該等選定像素驅動線之像素 並以-列單元驅動像素。亦即’垂直驅動電路4沿一垂直 方向以-列為單位依序選擇及择描像素陣⑴之像素2,並 經由垂直信號線9向行信號處理電路5供應基於根據（舉例 而言）充當各別像素2之光電轉換單元之光電二極體中所接 收之光量所產生之信號電荷之像素信號。 由於像素係以每—行炎西p番 rp 仃术配置’因而行信號處理電路5儀 2置於（舉例而言）每—像素2行中，且對自對應於每一像素 行中之-條線之像素2輸出之信號執行信號處理，諸如一 ^移除過程°亦即’行信號處理電路5執行信號處理， 諸如移除在像素2中係唯一之固定圖案雜訊之cm =及AD轉換。水平選擇„(未展示财裝於行信號處 ^電路5之輸出級中以連接於該輸出級與水平信號線 間0 =區動電路6包括(舉例而言)—移位暫存器，其藉由 ,序輸出水平掃描脈衝來依序選擇行信號處理電路卜且 將來自行信號處理電路5 線丨〇。 〃 k娩为別輸出至水平信號 輸出電路7對經由水平信號線1〇自行信號處理電路5依序 ::之信號執行信號處理且輪出經處理信號。舉例而言， 月電路7有時緩衝該等信號或有時執行各種數位信號處 J57964.doc157964.doc • 14· S 201246520 The components are applied to the solid-state imaging element according to various embodiments. As shown in the figure, the solid-state imaging element 1 includes a pixel array (so-called pixel region) 3 and a peripheral circuit segment 'in which a plurality of pixels 2 including a plurality of photoelectric conversion units are arranged in a two-dimensional array. It is disposed on half of the body substrate U (such as a stone substrate). The pixel 2 includes a photoelectric conversion unit such as a photodiode and a plurality of pixel transistors (so-called M〇s transistors). The plurality of pixel transistors may include, for example, three transistors: - a transmission transistor , - reset the transistor and a magnifying transistor. The plurality of pixel transistors can have a conventional configuration by further providing a selection transistor to include one of the four electrical a-body I-element pixels and thus will not be described in detail. Pixel 2 can be configured as one unit pixel. Further, the pixel 2 has a pixel sharing structure. The pixel sharing structure is formed by a plurality of photodiodes, a plurality of transmission transistors, a common floating diffusion, and a common pixel transistor. That is, in the pixel sharing structure, the photodiode and the transmission transistor forming the plurality of unit pixels each share a different pixel transistor. The peripheral circuit section includes a vertical drive circuit 4, a row signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. • The control circuit 8 receives information about an input clock, an operation mode, or a command such as this one and outputs internal information about the solid state imaging element or the like. That is, the control circuit 8 generates a clock which serves as a reference for the operation of the vertical drive circuit 4, the line signal processing circuit 5, the horizontal drive circuit 6, and the like according to a vertical sync signal, a horizontal sync signal, and a main clock, respectively. Signal or control signal. These signals are input to the vertical 157964.doc -15- 201246520 drive circuit 4, line signal processing circuit 5, horizontal drive circuit such as this. The vertical drive circuit 4 includes, for example, a shift register that selects pixel drive lines, supply pulses for driving the pixels of the selected pixel drive lines, and drives the pixels in - column units. That is, the 'vertical drive circuit 4 sequentially selects and selects the pixel 2 of the pixel array (1) in units of - column in a vertical direction, and supplies the line signal processing circuit 5 via the vertical signal line 9 based on, for example, acting as A pixel signal of a signal charge generated by the amount of light received in the photodiode of the photoelectric conversion unit of each pixel 2. Since the pixel system is configured in every line, the line signal processing circuit 5 is placed in, for example, every 2 pixels, and the pair corresponds to each pixel row. The signal output from the pixel 2 of the line performs signal processing, such as a removal process, that is, the 'line signal processing circuit 5 performs signal processing, such as removing the fixed pattern noise in the pixel 2, cm = and AD. Conversion. Horizontal selection „ (not shown in the output stage of the circuit signal circuit 5 to be connected between the output stage and the horizontal signal line 0 = the zone circuit 6 includes, for example, a shift register, By sequentially outputting the horizontal scanning pulse to sequentially select the row signal processing circuit and in the future, the self-processing signal processing circuit 5 is 丨〇. 〃 k delivery is output to the horizontal signal output circuit 7 to the horizontal signal line 1 〇 self-signal processing The circuit 5 sequentially performs signal processing on the signal and rotates the processed signal. For example, the monthly circuit 7 sometimes buffers the signals or sometimes performs various digital signals at J57964.doc
S -16· 201246520 理，諸如黑標準調整及行變化校正。一輸入/輸出端子12 傳輸並接收來往於外部之信號。 圖2A至圖2C係根據本發明實施例之m〇S固態成像元件 之基本總體組態之圖示。在根據相關技術之一 MOS固態成 像元件151中，一像素陣列153、一控制電路154及執行信 號處理之一邏輯電路155係裝配於一個半導體晶片152中， 如在圖2A中所展示。一般而言’像素陣列153及控制電路 15 4形成一衫像感測器15 6。另一方面，在根據本發明之一 貫施例之一 MOS固態成像元件2 〇中，一像素陣列2 3及一控 制電路24係裝配於一第一半導體晶片單元22中，且包括執 行信號處理之一信號處理電路之一邏輯電路25係裝配於一 第二半導體晶片單元26中，如在圖2B中所展示。第一半導 體曰曰片單元22與第二半導體晶片單元26彼此電連接以形成 MOS固態成像元件20之一單個半導體晶片。在根據本發明 之另一實施例之一 MOS固態成像元件21中，一像素陣列23 係裝配於一第一半導體晶片單元22中，且一控制電路以及 包括一信號處理電路之一邏輯電路25係裝配於一第二半導 體晶片單元26中，如在圖2C中所展示。第一半導體晶片單 TC22與第二半導體晶片單元26彼此f連接以形成m〇s0態 成像元件21之一單個半導體晶片。 雖然未圖解說明，但端視MOS固態成像元件之組態，兩 個或兩個以上半導體晶片可係彼此接合的。舉例而言，除 上文所闡述之第-半導體晶片單元與第二半導體晶片單元 之外，可添加包括一記憶體器件陣列之一半導體晶片單元 157964.doc •17· 201246520 及包括另一電路器件之一半導體晶片單元，且三個或三個 以上半導體晶片單元可彼此接合以形成MOS固態成像元件 之—單個晶片。 2·第—實施例 固態成像元件之組態之實例 圖3係根據本發明之一第一實施例之一半導體元件（亦 即，一MOS固態成像元件）之一圖示。根據該第一實施例 之固態成像元件28包括一經堆疊半導體晶片27，其中包 括一像素陣列2 3及一控制電路2 4之一第一半導體晶片單元 22與包括一邏輯電路25之一第二半導體晶片單元26彼此接 。。第一半導體晶片單元22與第二半導體晶片單元26彼此 接合以使得多層佈線層41與55彼此面對。可藉由一黏合劑 層57將該等半導體晶片單元彼此接合，其中保護膜42及56 係間置其之間。可藉由電漿焊接將該等半導體晶片單元彼 此接合。 在本實施例中，完全移除第一半導體晶片單元22之一部 分之一半導體區段以形成一半導體移除區52。在該半導體 移除區52中，形成一連接佈線67以將第一半導體晶片單元 22連接至第二半導體晶片單元26。半導體移除區52係一整 個區，其包括其中形成連接至對應於像素陣列23之每一垂 直仏號線之一敷設佈線40d之每—連接佈線67之一部分。 半導體移除區52係在像素陣列23之外形成，如在圖丨5 A中 所展示。半導體移除區52對應於一所謂之電極墊區。在圖 15A中，半導體移除區52係在像素陣列23之外垂直地形S -16· 201246520, such as black standard adjustment and line change correction. An input/output terminal 12 transmits and receives signals to and from the outside. 2A through 2C are diagrams showing a basic overall configuration of a m〇S solid-state imaging element according to an embodiment of the present invention. In the MOS solid-state imaging element 151 according to one of the related art, a pixel array 153, a control circuit 154, and a logic circuit 155 for performing signal processing are mounted in a semiconductor wafer 152, as shown in Fig. 2A. In general, the pixel array 153 and the control circuit 154 form a shirt image sensor 156. On the other hand, in a MOS solid-state imaging device 2 according to a consistent embodiment of the present invention, a pixel array 23 and a control circuit 24 are mounted in a first semiconductor wafer unit 22, and include performing signal processing. A logic circuit 25, one of the signal processing circuits, is mounted in a second semiconductor wafer unit 26, as shown in Figure 2B. The first semiconductor wafer unit 22 and the second semiconductor wafer unit 26 are electrically connected to each other to form a single semiconductor wafer of one of the MOS solid-state imaging elements 20. In a MOS solid-state imaging device 21 according to another embodiment of the present invention, a pixel array 23 is mounted in a first semiconductor wafer unit 22, and a control circuit and a logic circuit 25 including a signal processing circuit are provided. Mounted in a second semiconductor wafer unit 26, as shown in Figure 2C. The first semiconductor wafer unit TC22 and the second semiconductor wafer unit 26 are connected to each other f to form a single semiconductor wafer of the m〇s0 state imaging element 21. Although not illustrated, two or more semiconductor wafers may be bonded to each other, depending on the configuration of the MOS solid-state imaging device. For example, in addition to the first-semiconductor wafer unit and the second semiconductor wafer unit as set forth above, one semiconductor wafer unit including a memory device array 157964.doc • 17· 201246520 may be added and include another circuit device. One of the semiconductor wafer units, and three or more semiconductor wafer units can be bonded to each other to form a single wafer of MOS solid state imaging elements. 2. First Embodiment Example of Configuration of Solid-State Imaging Element Fig. 3 is a diagram showing one of semiconductor elements (i.e., a MOS solid-state imaging element) according to a first embodiment of the present invention. The solid-state imaging device 28 according to the first embodiment includes a stacked semiconductor wafer 27 including a pixel array 23 and a control circuit 24, a first semiconductor wafer unit 22 and a second semiconductor including a logic circuit 25. The wafer units 26 are connected to each other. . The first semiconductor wafer unit 22 and the second semiconductor wafer unit 26 are bonded to each other such that the multilayer wiring layers 41 and 55 face each other. The semiconductor wafer units can be bonded to each other by an adhesive layer 57 with the protective films 42 and 56 interposed therebetween. The semiconductor wafer units can be bonded to each other by plasma welding. In the present embodiment, one of the semiconductor segments of one of the first semiconductor wafer units 22 is completely removed to form a semiconductor removal region 52. In the semiconductor removal region 52, a connection wiring 67 is formed to connect the first semiconductor wafer unit 22 to the second semiconductor wafer unit 26. The semiconductor removal region 52 is an entire region including a portion in which each of the connection wirings 67 connected to one of the vertical alignment lines corresponding to the pixel array 23 is formed. Semiconductor removal region 52 is formed outside of pixel array 23, as shown in Figure 5A. The semiconductor removal region 52 corresponds to a so-called electrode pad region. In FIG. 15A, the semiconductor removal region 52 is vertically topographically outside the pixel array 23.
157964.doc -18· S 201246520 成。 在第一半導體晶片單元22中’在一經薄化第一半導體基 板31中形成充當光電轉換單元之光電二極體（pD)、包括複 數個像素電晶體Trl及Tr2之像素陣列23及包括MOS電晶體 Tr3及Tr4之控制電路24。該圖圖解說明代表性像素電晶體 Trl及Tr2及代表性MOS電晶體Tr3及Tr4。在本實施例中， 在半導體基板31之一表面3 la上，形成一多層佈線層41， 在該多層佈線層中沈積由其之間間置有一層間絕緣膜39之 三層金屬Ml至M3形成之佈線40[40a、40b及40c]。下文當 闡述製造像素電晶體Trl及Tr2及MOS電晶體Tr3及Tr4之一 方法時’詳細闡述像素電晶體Trl及Tr2及控制電路24之 MOS電晶體Tr3及Tr4。 在第二半導體晶片單元26中，在一第二半導體基板仏上 形成包括MOS電晶體Tr6至Tr8之邏輯電路25。在本實施例 中，在半導體基板45之一表面45a上，形成一多層佈線層 55，在該多層佈線層中沈積由其之間間置有一層間絕緣膜 49之二層金屬M11至M13形成之佈線53[53a、53b及幻。 下文當闡述製造MOS電晶體Tr6及Tr8之一方法時，詳細闡 • 述M〇S電晶體Tr6及Tr8。 • 在第一半導體晶片單元22之半導體移除區52中，藉由 (舉例而言）蝕刻來移除整個第一半導體基板31。由（舉例而 吕）氧化矽（SiOJ膜58及氮化矽（SiN)膜59形成之一經堆疊 絕緣膜61係藉由自半導體移除區52之底表面及側表面延伸 至半導體基板之表面來形成。經堆疊絕緣膜61充當一保護 157964.doc -19- 201246520 絕緣膜’其保護朝向半導體移除區52之一凹陷部分之側表 面曝露之半導體基板31,且亦充當像素之一抗反射膜。 在半導體移除區52中，形成一連接孔64,以自氮化矽膜 59延伸至電連接至第一半導體晶片單元22中之多層佈線層 41之一佈線（在此實例中’由第三層金屬M3形成之敷設佈 線40d)之一第一連接墊65。此外，形成一貫通連接孔62以 穿透第一半導體晶片單元22之多層佈線層41且延伸至電連 接至第一半導體晶片單元26中之多層佈線層55之一佈線 (在此實例中，由第三層金屬M13形成之一敷設佈線53d)之 一第二連接墊63。 連接佈線67包括隱埋於連接孔64及62中且電連接至第一 連接墊65之一連接導體68、電連接至第二連接墊63之一貫 通連接導體69及電連接連接導體68之上部端與貫通連接導 體69之上部端之一連接導體71 » 在充當第一半導體晶片單元22之光電二極體34之一光入 射表面之一後表面31b上形成覆蓋需要遮蔽光之一區之一 光遮蔽膜72。此外，形成一經平坦化膜73，以使得覆蓋光 遮蔽膜72，在經平坦化膜73上形成晶片上濾色器74以對應 於各別像素，且在晶片上濾色器74上形成晶片上微透鏡 75，以使得形成背側照明式固態成像元件28。曝露在連接 佈線67之外之連接導體71充當連接至一外部佈線其之間間 置有一接合線之一電極墊。 製造固態成像元件之方法實例 圖4至圖14係根據第一實施例製造固態成像元件28之一 157964.doc •20- 201246520 方法之圖示。 如在圖4中所展示，一半完成影像感測器，亦即，在第 半導體BB圓（在下文中，亦稱作一半導體基板）3丨之各別 晶片單元之區中形成像素陣列23及控制電路24。亦即，在 其中形成有半導體基板（舉例而言，一矽基板）3 1之每一晶 片單元之區中形成充當每一像素之光電轉換單元之一光電 二極體（PD)。在一半導體井區32中形成每一像素電晶體之 源極/汲極區33。半導體井區32係藉由引入第一導電型雜 質（舉例而言，p型雜質）而形成，且源極/汲極區33係藉由 引入第二導電型雜質（舉例而言’ η型雜質）而形成。光電二 極體（PD)及每一像素電晶體之源極/汲極區33係藉由自半 導體基板之前表面植入離子而形成。 光電二極體（PD)經形成以在基板之表面之側上包括一 η 型半導體區34及一 ρ型半導體區35〇藉由在該基板之表面 上其之間間置有一閘極絕緣膜地形成閘極電極36(其形成 一像素），由閘極電極36及一對源極/汲極區33形成像素電 晶體Trl及Tr2。在圖4中，將兩個像素電晶體Trl及Tr2圖解 說明為複數個像素電晶體之代表性像素電晶體。此鄰光電 一極體（PD)之像素電晶體Trl對應於一傳輸電晶體，且其 源極/汲極區對應於一浮動擴散部（FD)。各別單元像素3〇 係藉由-器件隔離區38彼此隔離。舉例而言，藉由在形成 於該基板中之-溝#中隱埋一絕緣膜（諸如叫膜）來以一 STI(淺溝道隔鵡）結構形成器件隔離區38。 另-方面，在控制電路24之側上，在半導體基板31上形 I57964.doc •21 · 201246520 成形成控制電路之MOS電晶體。在圖4中，MOS電晶體Tr3 及Tr4係圖解說明為形成控制電路23之代表性m〇s電晶 體* MOS電晶體Tr3及Tr4係由在其之間間置有閘極絕緣膜 之η型源極/汲極區33與閘極電極36形成。 接下來，在半導體基板31之表面上形成第一層層間絕緣 膜39，且然後在層間絕緣膜39中形成連接孔以形成連接至 各別電晶體之連接導體44。在形成具有不同高度之連接導 體44時，在包括電晶體之上部表面之整個表面上層壓充當 一蝕刻停止層之一第一絕緣薄膜43a(諸如氧化矽膜）及一第 二絕緣薄膜43b(諸如氮化矽膜）。第一層層間絕緣膜％係形 成於第二絕緣薄膜43b上。具有不同深度之連接孔係選擇 性地形成於第一層間絕緣膜39中直到充當蝕刻停止層之第 二絕緣薄膜43b。隨後，連接孔經形成以便與藉由在各別 單元中以相同膜厚度來選擇性地蝕刻第一絕緣薄膜43a及 第二絕緣薄膜43b而形成之連接孔連續。然後，將連接導 體44隱埋於各別連接孔中。 接下來，藉由形成佈線40[40a、40b及40c]來形成多層佈 線層41，在本實施例中，佈線4〇係藉由其之間間置有層間 絕緣膜39之三層金屬M1至M3來形成以連接至各別連接導 體44。佈線40係由銅（Cu)形成。一般而言，以防止cu擴散 之一障壁金屬膜覆蓋各別鋼佈線。因此，在該多層佈線層 41上形成鋼佈線40之一頂蓋膜，一所謂之保護膜42。藉由 先前所執行之製程形成作為半完成產品之包括像素陣列23 及控制電路24之第一半導體基板31。157964.doc -18· S 201246520 成. Forming, in the first semiconductor wafer unit 22, a photodiode (pD) serving as a photoelectric conversion unit, a pixel array 23 including a plurality of pixel transistors Tr1 and Tr2, and a MOS device in a thinned first semiconductor substrate 31 Control circuit 24 of crystals Tr3 and Tr4. The figure illustrates representative pixel transistors Trl and Tr2 and representative MOS transistors Tr3 and Tr4. In the present embodiment, a multilayer wiring layer 41 is formed on one surface 3 la of the semiconductor substrate 31, and three layers of metal M1 to M3 with an interlayer insulating film 39 interposed therebetween are deposited in the multilayer wiring layer. The wirings 40 [40a, 40b, and 40c] are formed. Hereinafter, the pixel transistors Tr1 and Tr2 and the MOS transistors Tr3 and Tr4 of the control circuit 24 will be described in detail when a method of manufacturing the pixel transistors Tr1 and Tr2 and the MOS transistors Tr3 and Tr4 is explained. In the second semiconductor wafer unit 26, a logic circuit 25 including MOS transistors Tr6 to Tr8 is formed on a second semiconductor substrate. In the present embodiment, on one surface 45a of the semiconductor substrate 45, a multilayer wiring layer 55 is formed in which two layers of metal M11 to M13 having an interlayer insulating film 49 interposed therebetween are formed. Wiring 53 [53a, 53b and magic. The M〇S transistors Tr6 and Tr8 are explained in detail below when describing a method of manufacturing the MOS transistors Tr6 and Tr8. • In the semiconductor removal region 52 of the first semiconductor wafer unit 22, the entire first semiconductor substrate 31 is removed by, for example, etching. One of the stacked insulating films 61 formed by (for example, ruthenium oxide) (SiOJ film 58 and tantalum nitride (SiN) film 59 is extended from the bottom surface and the side surface of the semiconductor removal region 52 to the surface of the semiconductor substrate. The stacked insulating film 61 serves as a protective 157964.doc -19-201246520 insulating film which protects the semiconductor substrate 31 exposed toward the side surface of the recessed portion of one of the semiconductor removing regions 52, and also functions as an anti-reflection film for the pixel In the semiconductor removal region 52, a connection hole 64 is formed to extend from the tantalum nitride film 59 to one of the plurality of wiring layers 41 electrically connected to the first semiconductor wafer unit 22 (in this example, by the first The first connection pad 65 is formed by one of the laying wires 40d) formed by the three-layer metal M3. Further, a through-connection hole 62 is formed to penetrate the multilayer wiring layer 41 of the first semiconductor wafer unit 22 and extend to be electrically connected to the first semiconductor wafer. One of the plurality of wiring layers 55 in the unit 26 is wired (in this example, one of the wirings 53d is formed by the third layer of metal M13). The connection wiring 67 is buried in the connection holes 64 and 62. Medium and electrical connection One of the first connection pads 65 is connected to the conductor 68, electrically connected to one of the second connection pads 63, and is connected to the upper end of the electrical connection connection conductor 68 and one of the upper ends of the through connection conductor 69. A light shielding film 72 covering one of the areas of the light-receiving surface is formed on one of the light incident surfaces of the photodiode 34 of the first semiconductor wafer unit 22. Further, a planarization film 73 is formed to cover The light shielding film 72 forms a wafer-on-color filter 74 on the planarization film 73 to correspond to the respective pixels, and a wafer-on-microlens 75 is formed on the wafer-on-color filter 74 to form a back-side illuminated solid state. The imaging element 28. The connection conductor 71 exposed outside the connection wiring 67 serves as an electrode pad which is connected to an external wiring with a bonding wire interposed therebetween. Example of Manufacturing Method of Solid-State Imaging Element FIG. 4 to FIG. EXAMPLES One of the Solid State Imaging Elements 28 is fabricated 157964.doc • 20- 201246520 Illustration of the method. As shown in Figure 4, half of the image sensor is completed, that is, at the semiconductor BB circle (below a pixel array 23 and a control circuit 24 are formed in a region of each of the respective wafer units, that is, a semiconductor substrate, that is, each of a semiconductor substrate (for example, a substrate) 31 is formed therein. A photodiode (PD) serving as a photoelectric conversion unit of each pixel is formed in a region of the wafer unit. A source/drain region 33 of each pixel transistor is formed in a semiconductor well region 32. The semiconductor well region 32 The formation is performed by introducing a first conductivity type impurity (for example, a p type impurity), and the source/drain region 33 is formed by introducing a second conductivity type impurity (for example, 'n type impurity). The photodiode (PD) and the source/drain regions 33 of each of the pixel transistors are formed by implanting ions from the front surface of the semiconductor substrate. The photodiode (PD) is formed to include an n-type semiconductor region 34 and a p-type semiconductor region 35 on the side of the surface of the substrate by providing a gate insulating film between the surfaces of the substrate A gate electrode 36 (which forms a pixel) is formed, and pixel transistors Tr1 and Tr2 are formed by the gate electrode 36 and the pair of source/drain regions 33. In Fig. 4, two pixel transistors Tr1 and Tr2 are illustrated as representative pixel transistors of a plurality of pixel transistors. The pixel transistor Tr1 of the adjacent photodiode (PD) corresponds to a transfer transistor, and its source/drain region corresponds to a floating diffusion (FD). The individual unit pixels 3 are isolated from each other by a device isolation region 38. For example, the device isolation region 38 is formed in an STI (shallow trench isolation) structure by embedding an insulating film (such as a film) in the trench # formed in the substrate. On the other hand, on the side of the control circuit 24, I57964.doc • 21 · 201246520 is formed on the semiconductor substrate 31 to form a MOS transistor of the control circuit. In FIG. 4, MOS transistors Tr3 and Tr4 are diagrams for forming a representative m〇s transistor of the control circuit 23* MOS transistors Tr3 and Tr4 are of an n-type with a gate insulating film interposed therebetween. The source/drain region 33 is formed with the gate electrode 36. Next, a first interlayer insulating film 39 is formed on the surface of the semiconductor substrate 31, and then connection holes are formed in the interlayer insulating film 39 to form connection conductors 44 connected to the respective transistors. When forming the connection conductors 44 having different heights, a first insulating film 43a (such as a hafnium oxide film) and a second insulating film 43b (for example, one of an etch stop layer) are laminated on the entire surface including the upper surface of the transistor. Tantalum nitride film). The first interlayer insulating film % is formed on the second insulating film 43b. Connection holes having different depths are selectively formed in the first interlayer insulating film 39 up to the second insulating film 43b serving as an etch stop layer. Subsequently, the connection holes are formed so as to be continuous with the connection holes formed by selectively etching the first insulating film 43a and the second insulating film 43b with the same film thickness in the respective cells. Then, the connecting conductors 44 are buried in the respective connecting holes. Next, the multilayer wiring layer 41 is formed by forming the wirings 40 [40a, 40b, and 40c]. In the present embodiment, the wiring 4 is made of the three layers of metal M1 with the interlayer insulating film 39 interposed therebetween. M3 is formed to be connected to the respective connection conductors 44. The wiring 40 is formed of copper (Cu). In general, a barrier metal film is used to prevent the cu diffusion from covering the respective steel wiring. Therefore, a top film of the steel wiring 40, a so-called protective film 42, is formed on the multilayer wiring layer 41. The first semiconductor substrate 31 including the pixel array 23 and the control circuit 24 as a semi-finished product is formed by a previously executed process.
157964.doc -22· S 201246520 另一方面，如圖5中展示，在其中形成有第二半導體基 板（半導體晶圓）45之每一晶片單元之區中形成包括執行作 號處理之信號處理電路之半完成邏輯電路25。亦即，在半 導體基板（舉例而言，一矽基板）45之表面上之p型半導體井 區46中，形成形成一邏輯電路之複數個1^〇8電晶體以藉由 器件隔離區50來隔離。此處，m〇S電晶體Tr6、Tr7及Tr8 係複數個MOS電晶體之代表性m〇s電晶體。m〇S電晶體157964.doc -22·S 201246520 On the other hand, as shown in FIG. 5, a signal processing circuit including performing number processing is formed in a region in which each of the wafer units of the second semiconductor substrate (semiconductor wafer) 45 is formed. The logic circuit 25 is completed in half. That is, in the p-type semiconductor well region 46 on the surface of the semiconductor substrate (for example, a germanium substrate) 45, a plurality of transistors forming a logic circuit are formed by the device isolation region 50. isolation. Here, the m〇S transistors Tr6, Tr7, and Tr8 are representative m〇s transistors of a plurality of MOS transistors. m〇S transistor
Tr6、1V7及Tr8各自包括其之間間置有一閘極絕緣膜之一 對η型源極/汲極區47與一閘極電極48 ^邏輯電路25可係以 CMOS電晶體來組態。藉由在形成於基板中之一溝槽中隱 埋一絕緣膜（諸如Si〇2膜）來以一 STI結構形成器件隔離區 50 ° 接下來，在半導體基板45之表面上形成第一層層間絕緣 膜49，且然後在層間絕緣膜49中形成連接孔以形成連接至 各別電晶體之連接導體54。在形成具有不同高度之連接導 體54時，在包括電晶體之上部表面之整個表面上層壓充當 餘刻停止層之一第一絕緣薄膜43a(諸如氧化矽膜）及一第 二絕緣薄膜43b(諸如氮化矽膜），如上文所闡述。第一層層 間絕緣膜49係形成於第二絕緣薄膜43}5上。具有不同深度 之連接孔係選擇性地形成於第一層間絕緣膜39中直至充當 蝕刻停止層之第二絕緣薄膜43b。隨後，連接孔經形成以 便與藉由在各別單元中以相同膜厚度來選擇性地蝕刻第一 絕緣薄膜43&及第二絕緣薄膜43b而形成之連接孔連續。然 後，將連接導體44隱埋於各別連接孔中。 157964.doc -23· 201246520 接下來，藉由形成佈線53[53a、53b及53c]來形成多層佈 線層5 5，在本實施例中，佈線5 3係藉由其之間間置有層間 絕緣膜49之三層金屬肘丨至M3來形成以連接至各別連接導 體54。佈線53係由銅（Cu)形成。如上文所論述，在該多層 佈線層49上形成銅佈線53之一頂蓋膜，一所謂之保護膜 56。藉由先前所執行之製程形成作為半完成產品之包括邏 輯電路25之第二半導體基板45。 接下來，如圖6中展示，使第一半導體基板31與第二半 導體基板45彼此接合以使得多層佈線層41與45彼此面對。 舉例而言，藉由電漿焊接或一黏合劑來使半導體基板彼此 接合。在此實例中，藉由一黏合劑來使該等半導體基板彼 此接合。在使用一黏合劑時，如圖7中展示，在第一半導 體基板31及第二半導體基板45之黏合表面中之一者上形成 一黏合劑層58，且然後將兩個半導體基板疊置且藉助間置 於其之間的黏合劑層58將其彼此黏合。亦即，使第一半導 體基板31與第二半導體基板45彼此接合。 當藉由電漿焊接使該兩個半導體基板彼此接合時，雖然 未圖解說明，但在第一半導體晶圓31及第二半導體晶圓Μ 之接合表面中之每-者上形成—電漿ΤΕ〇_、—電聚_ 膜、一SiON膜（阻擋膜）、一 Sic膜或類似物。使於其上形 成此膜之接合表面經受電聚處理、將其疊置且然後經受退 火處理，以使得將該兩個+導體基板彼此接合。車交佳地藉 由在等於或低於彻t之—溫度下之—低溫製程執行該接 合，等於或低於400。(：之一溫度對佈線或類似物無影響。 157964.doc •24· 201246520 接下來，如在圖8中所展示，藉由自第一半導體基板31 之後表面31b研磨或拋光將第一半導體基板31薄化。執行 該薄化以面對光電二極體（PD)0在該薄化之後，在光電二 極體（PD)之後表面上形成防止暗電流之一p型半導體層。 半導體基板31之厚度係（舉例而言）約6〇〇 μπι，但經薄化直 至（舉例而言）約3 μπι至約5 μηι。根據相關技術，藉由接合 一經分別製備之支撐基板來執行該薄化。然而，在本實施 例中’藉由使用包括邏輯電路25之第二半導體基板45作為 一支撑基板來薄化第一半導體基板31。當將該固態成像元 件組態為背側照明式固態成像元件時，第一半導體基板3 1 之後表面31b充當一光入射表面。 然後’如在圖9中所展示，在將第一半導體基板31與第 二半導體基板45彼此接合中，藉由完全移除充當已完成第 一半導體晶片單元（亦即，部分半導體基板3丨）之區之一部 分之一半導體區段來形成半導體移除區52。半導體移除區 52係一整個區，其包括其中每一連接佈線連接至對應於像 素陣列之每一垂直信號線之敷設佈線4〇d之一部分且在像 素陣列23之外形成，如在圖15A中所展示。在圖15A中， 半導體移除區52係在像素陣列23之外垂直地形成。 接下來’如在圖10中所展示，自半導體移除區52之内表 面起跨越控制電路24之後表面（光入射表面）及像素陣列23 沈積氧化矽（Si〇2)膜58及氮化矽（SiN)膜59之一經堆疊絕緣 膜61。經堆疊絕緣膜61不僅充當半導體移除區52之半導體 側表面之一保護膜且亦充當像素陣列23之一抗反射膜。 157964.doc -25- 201246520 接下來，如在圖11中所展示，在半導體移除區52中，到 達連接至第二半導體基板45之多層佈線層55之一佈線53連 接墊63之貫通連接孔62自經堆疊絕緣膜61穿透第一半導體 基板3 1之多層佈線層41。此實例之貫通連接孔62到達電連 接至多層佈線層之最上層（亦即’由第三層金屬M13形成之 佈線53d)之第二連接塾63。該複數個貫通連接孔62經形成 以在數目上對應於像素陣列23之垂直信號線之數目。連接 至第一連接墊63之由第三層金屬M13形成之佈線53d充當 對應於垂直信號線之一敷設佈線。在此實例中，第二連接 墊63係由第三層金屬M13形成且係連續地形成於對應於垂 直信號線之敷設佈線53d中。 接下來，如在圖12中所展示，在半導體移除區52中形成 自經堆疊絕緣膜61到達連接至第一半導體基板31之多層佈 線層4 1之佈線40之第一連接墊65之連接孔64。在此實例 中，連接孔64經形成以到達電連接至由多層佈線層41之第 二層金屬M3形成之佈線40d之第一連接墊65。複數個連接 孔64經形成而在數目上對應於像素陣列23之垂直信號線之 數目。連接至第一連接墊65之由第三層金屬M3b成之佈 線40d充當對應於垂直信號線之一敷設佈線。在此實例 中，第一連接墊65係連續地形成於由第三層金屬M3形成 且對應於垂直信號之敷設佈線40d中。 接下來，如在圖13中所展示，形成連接佈線67以將第二 連接墊63電連接至第一連接墊65。亦即，在第一半導體基 板31之整個後表面上形成一導電膜以隱埋於連接孔62及連Each of Tr6, 1V7 and Tr8 includes a gate insulating film interposed therebetween. The n-type source/drain region 47 and a gate electrode 48 ^ logic circuit 25 can be configured with a CMOS transistor. The device isolation region 50 is formed in an STI structure by embedding an insulating film (such as a Si〇2 film) in one of the trenches formed in the substrate. Next, a first interlayer is formed on the surface of the semiconductor substrate 45. The insulating film 49 is formed, and then a connection hole is formed in the interlayer insulating film 49 to form a connection conductor 54 connected to the respective transistors. When forming the connection conductors 54 having different heights, a first insulating film 43a (such as a hafnium oxide film) and a second insulating film 43b (such as one of the remaining stop layers) are laminated on the entire surface including the upper surface of the transistor. Tantalum nitride film) as explained above. The first interlayer insulating film 49 is formed on the second insulating film 43}5. Connection holes having different depths are selectively formed in the first interlayer insulating film 39 up to the second insulating film 43b serving as an etch stop layer. Subsequently, the connection holes are formed to be continuous with the connection holes formed by selectively etching the first insulating film 43 & and the second insulating film 43b in the respective film thicknesses in the respective cells. Then, the connecting conductors 44 are buried in the respective connecting holes. 157964.doc -23· 201246520 Next, the multilayer wiring layer 5 5 is formed by forming the wirings 53 [53a, 53b, and 53c]. In the present embodiment, the wiring 53 is interposed with interlayer insulation therebetween. Three layers of metal elbows of film 49 are formed to M3 to connect to respective connecting conductors 54. The wiring 53 is formed of copper (Cu). As discussed above, a cap film of a copper wiring 53, a so-called protective film 56, is formed on the multilayer wiring layer 49. The second semiconductor substrate 45 including the logic circuit 25 is formed as a semi-finished product by a previously executed process. Next, as shown in Fig. 6, the first semiconductor substrate 31 and the second semiconductor substrate 45 are bonded to each other such that the multilayer wiring layers 41 and 45 face each other. For example, the semiconductor substrates are bonded to each other by plasma welding or a bonding agent. In this example, the semiconductor substrates are bonded to each other by a bonding agent. When an adhesive is used, as shown in FIG. 7, an adhesive layer 58 is formed on one of the bonding surfaces of the first semiconductor substrate 31 and the second semiconductor substrate 45, and then the two semiconductor substrates are stacked and They are bonded to each other by means of an adhesive layer 58 interposed therebetween. That is, the first semiconductor substrate 31 and the second semiconductor substrate 45 are bonded to each other. When the two semiconductor substrates are bonded to each other by plasma welding, although not illustrated, a plasma is formed on each of the bonding surfaces of the first semiconductor wafer 31 and the second semiconductor wafer Μ 〇_, - Electropolymer _ film, a SiON film (barrier film), a Sic film or the like. The bonding surface on which the film is formed is subjected to electropolymerization treatment, stacked, and then subjected to annealing treatment so that the two + conductor substrates are bonded to each other. The junction is performed by a low temperature process at a temperature equal to or lower than - t, which is equal to or lower than 400. (: One of the temperatures has no effect on wiring or the like. 157964.doc • 24· 201246520 Next, as shown in FIG. 8, the first semiconductor substrate is ground or polished by the rear surface 31b from the first semiconductor substrate 31. The thinning is performed to face the photodiode (PD) 0. After the thinning, a p-type semiconductor layer which prevents dark current is formed on the surface after the photodiode (PD). The thickness is, for example, about 6 μm, but thinned up to, for example, about 3 μm to about 5 μm. According to the related art, the thinning is performed by bonding a separately prepared support substrate. However, in the present embodiment, the first semiconductor substrate 31 is thinned by using the second semiconductor substrate 45 including the logic circuit 25 as a supporting substrate. When the solid-state imaging element is configured as a back side illumination type solid-state imaging In the case of the element, the rear surface 31b of the first semiconductor substrate 3 1 serves as a light incident surface. Then, as shown in FIG. 9, in joining the first semiconductor substrate 31 and the second semiconductor substrate 45 to each other, by completely The semiconductor removal region 52 is formed by forming a semiconductor removal region 52 as one of a portion of a region in which the first semiconductor wafer unit (ie, a portion of the semiconductor substrate 3A) has been completed. The semiconductor removal region 52 is an entire region including each of A connection wiring is connected to a portion of the routing wiring 4?d corresponding to each vertical signal line of the pixel array and formed outside the pixel array 23, as shown in Fig. 15A. In Fig. 15A, the semiconductor removal region 52 It is formed vertically outside the pixel array 23. Next, as shown in Fig. 10, yttrium oxide is deposited from the inner surface of the semiconductor removal region 52 across the rear surface of the control circuit 24 (light incident surface) and the pixel array 23 One of the (Si〇2) film 58 and the tantalum nitride (SiN) film 59 is laminated with the insulating film 61. The stacked insulating film 61 serves not only as a protective film of the semiconductor side surface of the semiconductor removal region 52 but also as the pixel array 23 An anti-reflection film. 157964.doc -25- 201246520 Next, as shown in FIG. 11, in the semiconductor removal region 52, one of the wiring layers 55 of the multilayer wiring layer 55 connected to the second semiconductor substrate 45 is reached. The through-connection hole 62 of the pad 63 penetrates the multilayer wiring layer 41 of the first semiconductor substrate 31 from the stacked insulating film 61. The through-connection hole 62 of this example reaches the uppermost layer electrically connected to the multilayer wiring layer (ie, 'by The second connection layer 63 of the third layer metal M13 is formed by the second connection port 63. The plurality of through connection holes 62 are formed to correspond in number to the number of vertical signal lines of the pixel array 23. The first connection pad 63 is connected to the first connection pad 63. The wiring 53d formed of the third layer metal M13 serves as a wiring corresponding to one of the vertical signal lines. In this example, the second connection pad 63 is formed of the third layer metal M13 and is continuously formed corresponding to the vertical signal line. It is laid in the wiring 53d. Next, as shown in FIG. 12, the connection of the first connection pad 65 from the stacked insulating film 61 to the wiring 40 connected to the multilayer wiring layer 41 of the first semiconductor substrate 31 is formed in the semiconductor removal region 52. Hole 64. In this example, the connection hole 64 is formed to reach the first connection pad 65 electrically connected to the wiring 40d formed of the second layer metal M3 of the multilayer wiring layer 41. A plurality of connection holes 64 are formed to correspond in number to the number of vertical signal lines of the pixel array 23. The wiring 40d formed of the third layer metal M3b connected to the first connection pad 65 serves as a wiring corresponding to one of the vertical signal lines. In this example, the first connection pads 65 are continuously formed in the laying wiring 40d formed of the third layer metal M3 and corresponding to the vertical signal. Next, as shown in Fig. 13, a connection wiring 67 is formed to electrically connect the second connection pad 63 to the first connection pad 65. That is, a conductive film is formed on the entire rear surface of the first semiconductor substrate 31 to be buried in the connection hole 62 and connected
157964.doc -26- S 201246520 接孔64兩者中，且然後藉由回蝕或圖案化來形成連接佈線 67 ^連接佈線67包括連接導體68及貫通連接導體69，連接 導體68係隱埋於連接孔64中且連接至第一連接墊65，貫通 連接導體69係隱埋於貫通連接孔62中且連接至第二連接 墊。連接佈線67進一步包括連接導體71，連接導體71在半 導體移除區之曝露底表面上將連接導體68電連接至貫通連 接導體69。連接導體68、貫通連接導體69及連接導體71係 由同一金屬整體地形成。連接佈線67可由可經由障壁金屬 (TiN或諸如此類）予以圖案化之金屬形成，諸如鎢（w)、鋁 (A1)或金（Au)。 接下來，如在圖14中所展示，在其中需要遮蔽光之一區 上形成光遮蔽膜72。如在該圖式中所示意性地圖解說明， 在控制電路24上形成光遮蔽臈72，但亦可在像素電晶體上 形成光遮蔽膜72。光遮蔽膜72可由諸如鎢（W)之金屬形 成。跨越像素陣列23形成經平坦化膜73以覆蓋光遮蔽膜 72 ^在經平坦化膜73上形成（舉例而言）紅色（R)、綠色 及藍色（B)之晶片上濾色器74以對應於各別像素，且在晶 片上濾色器74上形成晶片上微透鏡75。在第一半導體基板 31中，像素陣列23及控制電路25係形成為成品。連接佈線 67之連接導體71充當曝露在外之一電極墊。在第二半導體 基板45中，邏輯電路25形成為成品。 接下來，將該等半導體基板劃分成若干晶片，且因此獲 得背側照明式固態成像裝置28之一目標，如在圖3中所展 不。藉由線接合將固態成像裝置28之連接佈線67之連接導 157964.doc •27- 201246520 體71所形成之電極墊連接至一外部佈線。 根據第-實施例之固態成像元件及其製造方法，在第一 半導體晶片單元22中形成像素陣肋及控制電路％且在第 二半導體晶片單元26令形成執行信號處理之邏輯電路乃。 以此方式，由於在不同晶月單元中實現像素陣列功能與邏 輯功能，因而可針對像素陣列23及邏輯電路25使用最佳處 理技術。因此，由於可充分地達成像素陣列23及邏輯電路 25之各別功能，因而可提供具有高效能之固態成像元件。 特疋而§，在本實施例中，完全移除第一半導體晶片單 元22之一部分，亦即其中形成有連接導體及貫通連接導體 之區之半導體區段。由於連接導體68及貫通連接導體69係 形成於其中已移除半導體區段之半導體移除區52中，因此 可減少半導體基板31與連接導體68及貫通連接導體69之間 的寄生電容，藉此提供具有較高效能之固態成像元件。 當利用圖2C中所展不之組態時，可在第一半導體晶片單 元22中僅形成接收光之像素陣列23，且控制電路24及邏輯 電路25可分離地形成且形成於第二半導體晶片單元26中。 因此’在製造半導體晶片單元22與26中可獨立地選擇最佳 處理技術且可減小一產品模組之面積。 在第一實施例中’使包括像素陣列23及控制電路24之半 完成之第一半導體基板31與包括邏輯電路25之半完成之第 二半導體基板45彼此接合，且然後薄化第一半導體基板 31。亦即，將第二半導體基板45用作在薄化第一半導體其 板3 1時之第一半導體基板3 1之支撐基板《因此，可節約構 157964.doc • 28 - 201246520 件且可減少製造步驟。 在本實施例中，由於將第一半導體基板31薄化且將貫通 連接孔62及連接孔64形成於其中移除半導體區段之半導體 移除區52中，因而減小了孔之縱橫比且可以高精度形成連 接孔62及64。因此，可以高精度製造具有高效能之固態成 像裝置。 3.第二實施例 固態成像元件之組態之實例 圖16係根據本發明之一第二實施例之一半導體元件（亦 即，一MOS固態成像裝置）之一圖示。根據第二實施例之 一固態成像裝置78具有如下組態，其申經堆疊半導體晶片 27經形成以使得將包括像素陣列23及控制電路24之第一半 導體晶片單元22與包括邏輯電路25之第二半導體晶片單元 %彼此接合。將第-半導體晶片單元22與第二半導體晶片 單兀26彼此接合以使得多層佈線層“與”彼此面對。 在本實轭例中，形成其中完全移除第一半導體晶片單元 22之一部分之半導體區段之半導體移除區且形成自半 導體移除區52之内表面延伸至半導體基板”之後表面川 之，士堆疊絕緣膜6 i。在半導體移除區52中形成與半導體基 板3 1上之&堆疊絕緣膜6 i之表面齊平之一經平坦化絕緣膜 呈平i一化絕緣膜77之蝕刻速率不同於在經堆疊絕緣膜 61之表面上之氮切膜59之㈣速率。舉例而言，經平坦 化絕緣膜77係形成為一絕緣膜，諸如氧化矽膜。 穿經經平坦化絕緣膜77形成到達第-連接⑽及第二連 157964.doc •29- 201246520 接墊63之連接孔64及貫通連接孔62 ^連接第一連接墊65與 第二連接墊63之連接佈線67係穿經連接孔64及62兩者而形 成。連接佈線67包括隱埋於連接孔64及62中且電連接至第 一連接墊65之連接導體68、電連接至第二連接墊63之貫通 連接導體69、及電連接連接導體68之上部端與貫通連接導 體69之上部端之連接導體71。連接導體68、貫通連接導體 69及連接導體71係由金屬整體地形成。連接導體71係形成 於經平坦化絕緣膜77上。 其他組態與第一實施例中所闡述之組態相同。給對應於 圖3之組成器件之組成器件賦予相同參考編號，且將不重 複對其之說明。 製造固態成像元件之方法實例 圖17至圖24係根據第二實施例製造固態成像元件78之一 方法之圖示。 在圖17中，固態成像元件78之組態與在參考圖1〇根據上 文所闡述之第一實施例製造固態成像元件28之方法中所闡 述之組態相同。由於直至圖17之步驟與自圖4至圖1〇之步 驟相同，因而將不重複詳細說明。 在圖17之步驟中，自半導體移除區52之内表面起跨越控 制電路24之後表面（光入射表面）及像素陣列23沈積氧化石夕 (Si〇2)膜58氮化矽（SiN)膜59之經堆疊絕緣膜61。 接下來’如在圖18中所展示，在半導體基板31之整個後 表面上堆疊諸如氧化石夕膜之絕緣膜7 7以隱埋於半導體移除 區5 2中。 157964.doc • 30- & 201246520 接下來，如在圖19中所展示157964.doc -26- S 201246520 Both of the holes 64, and then the connection wiring 67 is formed by etch back or patterning. The connection wiring 67 includes the connection conductor 68 and the through connection conductor 69, and the connection conductor 68 is buried in The connection hole 64 is connected to the first connection pad 65, and the through connection conductor 69 is buried in the through connection hole 62 and connected to the second connection pad. The connection wiring 67 further includes a connection conductor 71 electrically connecting the connection conductor 68 to the through-connection conductor 69 on the exposed bottom surface of the semiconductor removal region. The connecting conductor 68, the through connecting conductor 69, and the connecting conductor 71 are integrally formed of the same metal. The connection wiring 67 may be formed of a metal that can be patterned via a barrier metal (TiN or the like) such as tungsten (w), aluminum (A1) or gold (Au). Next, as shown in Fig. 14, a light shielding film 72 is formed on a region where shadowing is required. As illustrated in the schematic diagram of the figure, a light shielding aperture 72 is formed on the control circuit 24, but a light shielding film 72 may also be formed on the pixel transistor. The light shielding film 72 may be formed of a metal such as tungsten (W). A planarization film 73 is formed across the pixel array 23 to cover the light shielding film 72. On the wafer (for example, red (R), green, and blue (B), a color filter 74 is formed on the planarization film 73. On-wafer microlenses 75 are formed on the on-wafer color filters 74 corresponding to the respective pixels. In the first semiconductor substrate 31, the pixel array 23 and the control circuit 25 are formed as a finished product. The connection conductor 71 of the connection wiring 67 serves as an electrode pad exposed to the outside. In the second semiconductor substrate 45, the logic circuit 25 is formed as a finished product. Next, the semiconductor substrates are divided into a plurality of wafers, and thus one of the targets of the back side illumination type solid-state imaging device 28 is obtained, as shown in Fig. 3. The electrode pads formed by the connection wires 67 of the solid-state imaging device 28 are connected to an external wiring by wire bonding. According to the solid-state imaging element of the first embodiment and the method of manufacturing the same, the pixel array rib and the control circuit % are formed in the first semiconductor wafer unit 22 and the logic circuit for performing signal processing is formed in the second semiconductor wafer unit 26. In this manner, the optimum processing techniques can be used for pixel array 23 and logic circuit 25 since pixel array functions and logic functions are implemented in different crystal cell units. Therefore, since the respective functions of the pixel array 23 and the logic circuit 25 can be sufficiently achieved, a solid-state imaging element having high performance can be provided. Specifically, in the present embodiment, a portion of the first semiconductor wafer unit 22, that is, a semiconductor portion in which a connection conductor and a region penetrating the connection conductor are formed, is completely removed. Since the connection conductor 68 and the through connection conductor 69 are formed in the semiconductor removal region 52 in which the semiconductor segment has been removed, the parasitic capacitance between the semiconductor substrate 31 and the connection conductor 68 and the through connection conductor 69 can be reduced, whereby the parasitic capacitance between the semiconductor substrate 31 and the connection conductor 68 and the through connection conductor 69 can be reduced. A solid-state imaging element with higher performance is provided. When the configuration shown in FIG. 2C is utilized, only the pixel array 23 for receiving light may be formed in the first semiconductor wafer unit 22, and the control circuit 24 and the logic circuit 25 may be separately formed and formed on the second semiconductor wafer. In unit 26. Thus, the optimum processing technique can be independently selected in the fabrication of semiconductor wafer units 22 and 26 and the area of a product module can be reduced. In the first embodiment, the first semiconductor substrate 31 including the pixel array 23 and the control circuit 24 and the second semiconductor substrate 45 including the logic circuit 25 are bonded to each other, and then the first semiconductor substrate is thinned. 31. That is, the second semiconductor substrate 45 is used as a supporting substrate for the first semiconductor substrate 31 when the first semiconductor 31 thereof is thinned. Therefore, the 157964.doc • 28 - 201246520 can be saved and the manufacturing can be reduced. step. In the present embodiment, since the first semiconductor substrate 31 is thinned and the through-connection holes 62 and the connection holes 64 are formed in the semiconductor removal region 52 in which the semiconductor segments are removed, the aspect ratio of the holes is reduced and The connection holes 62 and 64 can be formed with high precision. Therefore, it is possible to manufacture a high-performance solid-state imaging device with high precision. 3. Second Embodiment Example of Configuration of Solid-State Imaging Element Fig. 16 is a view showing one of semiconductor elements (i.e., a MOS solid-state imaging device) according to a second embodiment of the present invention. The solid-state imaging device 78 according to the second embodiment has a configuration in which the stacked semiconductor wafer 27 is formed such that the first semiconductor wafer unit 22 including the pixel array 23 and the control circuit 24 and the logic circuit 25 are included The two semiconductor wafer units % are bonded to each other. The first semiconductor wafer unit 22 and the second semiconductor wafer unit 26 are bonded to each other such that the multilayer wiring layers "AND" face each other. In the present embodiment, a semiconductor removal region in which a semiconductor portion of a portion of the first semiconductor wafer unit 22 is completely removed and formed from the inner surface of the semiconductor removal region 52 to the surface of the semiconductor substrate is formed, The stacking insulating film 6 i is formed in the semiconductor removing region 52 to be flush with the surface of the stacked insulating film 6 i on the semiconductor substrate 31, and the etching rate of the insulating film 77 is flattened by the planarizing insulating film 77. Unlike the (four) rate of the nitrogen cut film 59 on the surface of the stacked insulating film 61. For example, the planarized insulating film 77 is formed as an insulating film such as a hafnium oxide film. Forming the connection hole 64 and the through connection hole 62 of the pad 63 reaching the first connection (10) and the second connection 157964.doc • 29-201246520, and connecting the connection wiring 67 of the first connection pad 65 and the second connection pad 63 through the connection The connection wiring 67 includes a connection conductor 68 buried in the connection holes 64 and 62 and electrically connected to the first connection pad 65, and a through connection conductor 69 electrically connected to the second connection pad 63, And electrical connection connecting conductor 68 The upper end and the connecting conductor 71 that penetrates the upper end of the connecting conductor 69. The connecting conductor 68, the through connecting conductor 69, and the connecting conductor 71 are integrally formed of a metal. The connecting conductor 71 is formed on the planarized insulating film 77. The configuration is the same as that explained in the first embodiment. The constituent elements corresponding to the constituent devices of Fig. 3 are given the same reference numerals, and the description thereof will not be repeated. Example of the method of manufacturing the solid-state imaging element Fig. 17 to Fig. Figure 24 is a diagram showing a method of manufacturing a solid-state imaging element 78 according to the second embodiment. In Figure 17, the configuration of the solid-state imaging element 78 and the solid-state imaging according to the first embodiment set forth above with reference to Figure 1 The configuration described in the method of component 28 is the same. Since the steps up to Figure 17 are the same as those from Figure 4 to Figure 1, the detailed description will not be repeated. In the step of Figure 17, the semiconductor removal region 52 is removed. The inner surface thereof is a stacked insulating film 61 of a tantalum nitride (SiN) film 59 which is deposited on the surface (light incident surface) of the control circuit 24 and the pixel array 23 by a oxidized oxide (Si〇2) film 58. As shown in Fig. 18, an insulating film 77 such as an oxidized oxide film is stacked on the entire rear surface of the semiconductor substrate 31 to be buried in the semiconductor removal region 52. 157964.doc • 30- & 201246520 Next As shown in Figure 19
(CMP)方法將絕緣膜77拋光直至一定厚度。 化學機械拋光 接下來，如在圖20中所展示’使用氫氟酸以一濕式钮刻 方法蝕刻絕緣膜77直至氮化矽膜59，且將絕緣膜77平坦化 以與氮化石夕膜59齊平。此時，t化石夕膜59充當一钱刻停止 層。 接下來，如在圖21中所展示，在半導體移除區52中形成 穿透絕緣膜77及多層佈線層41且到達連接至第二半導體基 板45之多層佈線層55之佈線53d之第二連接墊63之連接孔 62。在此實例中，如上文所闡述，連接孔以經形成以到達 電連接至多層佈線層55之最上層之（亦即，由第三層金屬 M13形成之佈線53d)第二連接墊63。該複數個連接孔“經 形成以在數目上對應於像素陣列23之垂直信號線之數目。 連接至第二連接墊63之由第三層金屬M1 3形成之佈線53d 充當對應於垂直信號線之一敷設佈線。在此實例中，第二 連接墊63係連續地形成於由第三層金屬M13形成且對應於 垂直信號線之敷設佈線53d中。 接下來’如在圖22中所展示，在半導體移除區52中形成 自絕緣膜77到達第一連接墊65之連接孔64。在此實例中， 連接孔64經形成以到達電連接至由多層佈線層41之第三層 金屬M3形成之佈線4〇d之第一連接墊65。複數個連接孔“ 經形成而在數目上對應於像素陣列23之垂直信號線之數 目。連接至第一連接墊65之由第三層金屬M3形成之佈線 40d充當對應於垂直信號線之一敷設佈線。在此實例中， 157964.doc • 31 - 201246520 第一連接墊65係連續地形成於由第三層金屬河3形成且對 應於垂直信號之敷設佈線40d中。 接下來，如在圖23中所展示，形成連接佈線67以將第二 連接塾63電連接至第一連接墊65 »亦即，在絕緣薄膜77及 第一半導體基板31之整個後表面上形成一導電膜以隱埋於 連接孔62及連接孔64兩者中，且然後藉由回蝕或圖案化來 形成連接佈線67。連接佈線67包括連接導體68及貫通連接 導體69 ’連接導體68係隱埋於連接孔64中且連接至第一連 接墊65 ’貫通連接導體69係隱埋於貫通連接孔62中且連接 至第二連接墊。連接佈線67進一步包括在經平坦化絕緣膜 77上將連接導體68電連接至貫通連接導體69之連接導體 71。 連接導體68、貫通連接導體69及連接導體71係由同一 金屬整體地形成以充當一導電膜。連接佈線67可由可經由 障壁金屬（TiN或諸如此類）予以圖案化之金屬形成，諸如 鑛（W)、銘（A1)或金（Au)。 接下來，如在圖24中所展示’在其中需要遮蔽光之一區 上形成光遮蔽膜72。如在該圖式中所示意性地圖解說明， 在控制電路24上形成光遮蔽膜72，但亦可在像素電晶體上 形成光遮蔽膜72。光遮蔽膜72可由諸如鎢（W)之金屬形 成。跨越像素陣列23形成經平坦化膜73以覆蓋光遮蔽膜 72。 在經平坦化膜73上形成（舉例而言）紅色（R)、綠色（G) 及藍色（B)之晶片上濾色器74以對應於各別像素，且在晶 片上濾色器74上形成晶片上微透鏡75 »在第一半導體基板 31中，像素陣列23及控制電路25係形成為成品。連接佈線 -32- 157964.docThe (CMP) method polishes the insulating film 77 to a certain thickness. Chemical Mechanical Polishing Next, as shown in FIG. 20, the insulating film 77 is etched by a wet button method using hydrofluoric acid until the tantalum nitride film 59, and the insulating film 77 is planarized to be nitrided with the nitride film 59. Qi Ping. At this time, the t fossil film 59 acts as a stop layer. Next, as shown in FIG. 21, a second connection is formed in the semiconductor removal region 52 through the insulating film 77 and the multilayer wiring layer 41 and reaching the wiring 53d connected to the multilayer wiring layer 55 of the second semiconductor substrate 45. The connection hole 62 of the pad 63. In this example, as explained above, the connection holes are formed to reach the second connection pads 63 electrically connected to the uppermost layer of the multilayer wiring layer 55 (i.e., the wiring 53d formed of the third layer metal M13). The plurality of connection holes "are formed to correspond in number to the number of vertical signal lines of the pixel array 23. The wiring 53d formed of the third layer metal M1 3 connected to the second connection pad 63 serves as a line corresponding to the vertical signal line A wiring is laid. In this example, the second connection pads 63 are continuously formed in the laying wiring 53d formed of the third layer metal M13 and corresponding to the vertical signal lines. Next 'as shown in Fig. 22, A connection hole 64 is formed in the semiconductor removal region 52 from the insulating film 77 to the first connection pad 65. In this example, the connection hole 64 is formed to reach an electrical connection to the third layer metal M3 formed by the multilayer wiring layer 41. The first connection pad 65 of the wiring 4〇d. The plurality of connection holes are formed to correspond in number to the number of vertical signal lines of the pixel array 23. The wiring 40d formed of the third layer metal M3 connected to the first connection pad 65 serves as a wiring corresponding to one of the vertical signal lines. In this example, 157964.doc • 31 - 201246520 The first connection pads 65 are continuously formed in the laying wiring 40d formed by the third layer metal river 3 and corresponding to the vertical signals. Next, as shown in FIG. 23, a connection wiring 67 is formed to electrically connect the second connection pad 63 to the first connection pad 65 » that is, formed on the entire rear surface of the insulating film 77 and the first semiconductor substrate 31. A conductive film is buried in both the connection hole 62 and the connection hole 64, and then the connection wiring 67 is formed by etch back or patterning. The connection wiring 67 includes a connection conductor 68 and a through connection conductor 69. The connection conductor 68 is buried in the connection hole 64 and connected to the first connection pad 65. The through connection conductor 69 is buried in the through connection hole 62 and connected to the Two connection pads. The connection wiring 67 further includes a connection conductor 71 electrically connecting the connection conductor 68 to the through connection conductor 69 via the planarization insulating film 77. The connecting conductor 68, the through connecting conductor 69, and the connecting conductor 71 are integrally formed of the same metal to serve as a conductive film. The connection wiring 67 may be formed of a metal which can be patterned via a barrier metal (TiN or the like) such as mine (W), Ming (A1) or gold (Au). Next, a light shielding film 72 is formed on a region in which light is to be shielded as shown in Fig. 24. As illustrated in the diagram, the light shielding film 72 is formed on the control circuit 24, but the light shielding film 72 may be formed on the pixel transistor. The light shielding film 72 may be formed of a metal such as tungsten (W). A planarization film 73 is formed across the pixel array 23 to cover the light shielding film 72. A color filter 74 on a wafer (for example) of red (R), green (G), and blue (B) is formed on the planarization film 73 to correspond to respective pixels, and a color filter 74 is on the wafer. The on-wafer microlens 75 is formed. » In the first semiconductor substrate 31, the pixel array 23 and the control circuit 25 are formed as a finished product. Connection wiring -32- 157964.doc
S 201246520 67之連接導體71充當曝露在外之一電極墊。在第二半導體 基板45中，邏輯電路25形成為成品。 接下來’將該等半導體基板劃分成若干晶片，且因此獲 得背側照明式DU成縣置78之〜目#，如在圖16中所展 示。 根據第二實施例之固態成像元件78及其製造方法，完全 移除第一半導體晶片單元22之-部分(亦即其中形成連接 導體68及貫通連接冑體69之區之+導體區段），且將絕緣 膜77隱埋於經移除之半導體移除區52中。由於連接導體“ 及貫通連接導體69係隱埋於形成於絕緣膜77中之連接孔64 及貫通連接孔62中，因而連接導體68及69因絕緣膜77而遠 離半導體基板31之側表面。因此減少了半導體基板31與連 接導體68及69之間的寄生電容。此外，由於半導體移除區 52之内側係隱埋於絕緣膜77中，因此可與經堆疊絕緣膜6ι 合作以機械方式可靠地保護半導體基板31之與半導體移除 區52之側壁面對之表面。因此，可提供具有較高效能之固 態成像元件》 在本實施例中，由於將第一半導體基板3 1薄化且形成貫 通連接孔62及連接孔64，因而減小了孔之縱橫比且可以高 精度形成連接孔62及64。因此，可以高精度製造具有高效 能之固態成像裝置。 雖然未作其他說明，但可獲得與第一實施例之優點相同 之優點。 4.第三實施例 157964.doc -33· 201246520 固態成像元件之組態之實例 圖25係根據本發明之一第三實施例之一半導體元件（亦 即，一 MOS固態成像裝置）之一圖示。根據第三實施例之 一固態成像裝置82具有如下組態，其中經堆疊半導體晶片 27經形成以使得將包括像素陣列23及控制電路24之第一半 導體晶片單元22與包括邏輯電路25之第二半導體晶片單元 26彼此接合。將第一半導體晶片單元22與第二半導體晶片 單元26彼此接合以使得多層佈線層41與55彼此面對。 在本實施例中，形成其中完全移除第一半導體晶片單元 22之一部分之半導體區段之半導體移除區52，且形成自半 導體移除區52之内表面延伸至半導體基板31之後表面之經 堆疊絕緣膜61。在半導體移除區52中形成與半導體基板31 上之經堆疊絕緣膜6 1之表面齊平之經平坦化絕緣膜77，且 在對應於絕緣膜77之連接佈線67之一部分中形成自該表面 起具有一定深度之一凹陷部分8 1。經平坦化絕緣膜77之蝕 刻速率不同於在經堆疊絕緣膜61之表面上之氮化矽膜59之 触刻速率。舉例而言，經平坦化絕緣膜77係形成為一絕緣 膜，諸如氧化碎膜。 連接孔64及貫通連接孔62經形成以穿經凹陷部分8 1下方 之絕緣膜77到達第一連接墊65及第二連接墊63。連接第一 連接墊65與第二連接墊63之連接佈線67係穿經連接孔64及 62兩者而形成。連接佈線67包括隱埋於連接孔64及62中且 電連接至第一連接墊65之連接導體68、電連接至第二連接 塾63之貫通連接導體69、及電連接連接導體68之上部端與 157964.doc •34- 201246520 貝通連接導體69之上部端之連接導體71。連接導體68、貫 通連接導體69及連接導體71係由金屬整體地形成。連接導 體71係S埋於絕緣膜77之凹陷部分8工中且連接導體71之表 面經形成以與經平坦化絕緣膜77之表面齊平。 其他組態與第-實施例中所鬧述之組態相同。給對應於 圖3之組成器件之組成器件賦予相同參考編號，且將不重 複對其之說明。 製造固態成像元件之方法實例 圖26至圖30係根據第三實施例製造固態成像元件82之一 方法之圖不。在圖26中，固態成像元件82之組態與在參考 圖20根據上文所闡述之第二實施例製造固態成像元件冗之 方法中所闡述之組態相同。由於直至圖26之步驟與自圖4 至圖10及自圖17至圖20之步驟相同，因而將不重複詳細說 明。 在圖26之一步驟中，絕緣膜77經堆疊以隱埋於半導體移 除區52中，且然後藉由化學機械拋光（CMp)及濕式蝕刻將 絕緣膜77之表面平坦化以與經堆疊絕緣膜6丨之表面齊平。 接下來，如在圖27中所展示，在絕緣膜77之表面中形成 自該表面起具有一定深度之凹陷部分81以對應於其中形成 連接佈線67之區。 接下來’如在圖28中所展示，貫通連接孔62穿透凹陷部 分81下方之絕緣膜77及多層佈線層41以到達第二連接塾 63。在此實例中’如上文所闡述，連接孔62經形成以到達 電連接至第二半導體晶片單元26之多層佈線層55之最上層 157964.doc -35- 201246520 金屬（亦即，第三層金屬M13之佈線53d)之第二連接墊63。 該複數個連接孔62經形成以在數目上對應於像素陣列23之 垂直信號線之數目。連接至第二連接墊63之佈線53d充當 對應於垂直信號線之一敷設佈線》在此實例中，第二連接 墊63係連續地形成於由第三層金屬M13形成且對應於垂直 信號線之敷設佈線53d中。 此外，在半導體移除區52中形成自凹陷部分81下方之絕 緣膜7 7到達第一連接塾6 5之連接孔6 4。在此實例中，連接 孔64經形成以到達電連接至由第一半導體晶片單元22之多 層佈線層41之第三層金屬M3形成之佈線40d之第一連接塾 6 5。複數個連接孔6 4經形成而在數目上對應於像素陣列2 3 之垂直信號線之數目。連接至第一連接塾65之第三層金屬 之佈線40c充當對應於垂直信號線之一敷設佈線。在此實 例中，第一連接墊65係連續地形成於由第三層金屬M13形 成且對應於垂直信號之敷設佈線40d中。 接下來，如在圖29中所展示，形成連接佈線67以將第二 連接墊63電連接至第一連接墊65。亦即，在絕緣薄膜”及 第一半導體基板31之整個後表面上形成一導電膜以隱埋於 凹陷部分81與連接孔62及連接孔64兩者中，且然後藉由回 蝕或圖案化來形成連接佈線67 ^連接佈線67包括連接導體 68及貫通連接導體69，連接導體68係隱埋於連接孔以中且 連接至第一連接墊65,貫通連接導體69係隱埋於貫通連接 孔62中且連接至第二連接墊。連接佈線67進一步包括將連 接導體68電連接至貫通連接導體69之連接導體71。連接導 157964.docThe connection conductor 71 of S 201246520 67 serves as an electrode pad exposed to the outside. In the second semiconductor substrate 45, the logic circuit 25 is formed as a finished product. Next, the semiconductor substrates are divided into a plurality of wafers, and thus the backside illumination type DU is set to 78, which is shown in Fig. 16. According to the solid-state imaging element 78 of the second embodiment and the method of manufacturing the same, the portion of the first semiconductor wafer unit 22 is completely removed (that is, the + conductor portion in which the connection conductor 68 and the region connecting the connection body 69 are formed), The insulating film 77 is buried in the removed semiconductor removal region 52. Since the connection conductors " and the through-connection conductors 69 are buried in the connection holes 64 and the through-connection holes 62 formed in the insulating film 77, the connection conductors 68 and 69 are separated from the side surface of the semiconductor substrate 31 by the insulating film 77. The parasitic capacitance between the semiconductor substrate 31 and the connection conductors 68 and 69 is reduced. Further, since the inner side of the semiconductor removal region 52 is buried in the insulating film 77, it can be mechanically and reliably cooperative with the stacked insulating film 6ι. The surface of the semiconductor substrate 31 facing the side wall of the semiconductor removal region 52 is protected. Therefore, a solid-state imaging element having higher performance can be provided. In this embodiment, since the first semiconductor substrate 31 is thinned and formed through The connection hole 62 and the connection hole 64 are formed, thereby reducing the aspect ratio of the hole and forming the connection holes 62 and 64 with high precision. Therefore, it is possible to manufacture a high-performance solid-state imaging device with high precision. The same advantages as those of the first embodiment. 4. Third embodiment 157964.doc -33·201246520 Example of configuration of solid-state imaging element FIG. 25 is according to the present invention One of the semiconductor elements (i.e., a MOS solid-state imaging device) of a third embodiment is illustrated. According to the third embodiment, the solid-state imaging device 82 has a configuration in which the stacked semiconductor wafer 27 is formed such that The first semiconductor wafer unit 22 including the pixel array 23 and the control circuit 24 and the second semiconductor wafer unit 26 including the logic circuit 25 are bonded to each other. The first semiconductor wafer unit 22 and the second semiconductor wafer unit 26 are bonded to each other to be multi-layered The wiring layers 41 and 55 face each other. In the present embodiment, the semiconductor removal region 52 in which the semiconductor portion of a portion of the first semiconductor wafer unit 22 is completely removed is formed, and is formed from the inner surface of the semiconductor removal region 52. The stacked insulating film 61 is extended to the rear surface of the semiconductor substrate 31. A planarization insulating film 77 is formed in the semiconductor removal region 52 flush with the surface of the stacked insulating film 61 on the semiconductor substrate 31, and corresponds to A recessed portion 81 having a certain depth from the surface is formed in a portion of the connection wiring 67 of the insulating film 77. The planarized insulating film 77 is formed. The engraving rate is different from the etch rate of the tantalum nitride film 59 on the surface of the stacked insulating film 61. For example, the planarization insulating film 77 is formed as an insulating film such as an oxide film. The through-connection hole 62 is formed to pass through the insulating film 77 under the recessed portion 81 to the first connection pad 65 and the second connection pad 63. The connection wiring 67 connecting the first connection pad 65 and the second connection pad 63 is passed through. The connection wirings 67 are formed by the connection holes 64 and 62. The connection wiring 67 includes a connection conductor 68 buried in the connection holes 64 and 62 and electrically connected to the first connection pad 65, and a through connection conductor 69 electrically connected to the second connection port 63. And the connecting conductor 71 of the upper end of the connecting conductor 68 and the upper end of the 157964.doc • 34-201246520 beton connecting conductor 69. The connecting conductor 68, the through connecting conductor 69, and the connecting conductor 71 are integrally formed of a metal. The connection conductor 71 is buried in the recessed portion 8 of the insulating film 77 and the surface of the connection conductor 71 is formed to be flush with the surface of the planarization insulating film 77. The other configuration is the same as the configuration described in the first embodiment. The constituent elements corresponding to the constituent elements of Fig. 3 are given the same reference numerals, and the description thereof will not be repeated. Method of Manufacturing Solid-State Imaging Element FIG. 26 to FIG. 30 are diagrams showing a method of manufacturing the solid-state imaging element 82 according to the third embodiment. In Fig. 26, the configuration of the solid-state imaging element 82 is the same as that explained in the method of manufacturing the solid-state imaging element redundancy according to the second embodiment explained above with reference to Fig. 20. Since the steps up to Fig. 26 are the same as those from Figs. 4 to 10 and from Fig. 17 to Fig. 20, detailed description will not be repeated. In one step of FIG. 26, the insulating film 77 is stacked to be buried in the semiconductor removal region 52, and then the surface of the insulating film 77 is planarized by chemical mechanical polishing (CMp) and wet etching to be stacked. The surface of the insulating film 6 is flush. Next, as shown in Fig. 27, a recessed portion 81 having a certain depth from the surface is formed in the surface of the insulating film 77 to correspond to a region in which the connection wiring 67 is formed. Next, as shown in Fig. 28, the through-connection hole 62 penetrates the insulating film 77 and the multilayer wiring layer 41 under the recessed portion 81 to reach the second connection port 63. In this example, as explained above, the connection hole 62 is formed to reach the uppermost layer 157964.doc -35 - 201246520 metal electrically connected to the multilayer wiring layer 55 of the second semiconductor wafer unit 26 (ie, the third layer metal The second connection pad 63 of the wiring 53d) of M13. The plurality of connection holes 62 are formed to correspond in number to the number of vertical signal lines of the pixel array 23. The wiring 53d connected to the second connection pad 63 serves as a wiring corresponding to one of the vertical signal lines. In this example, the second connection pad 63 is continuously formed in the third layer metal M13 and corresponds to the vertical signal line. The wiring 53d is laid. Further, an insulating film 7 7 formed under the recessed portion 81 is formed in the semiconductor removing region 52 to reach the connecting hole 614 of the first connecting port 65. In this example, the connection hole 64 is formed to reach the first connection port 65 electrically connected to the wiring 40d formed of the third layer metal M3 of the plurality of wiring layers 41 of the first semiconductor wafer unit 22. A plurality of connection holes 64 are formed to correspond in number to the number of vertical signal lines of the pixel array 2 3 . The wiring 40c of the third layer metal connected to the first connection port 65 serves as a wiring corresponding to one of the vertical signal lines. In this example, the first connection pads 65 are continuously formed in the laying wiring 40d formed of the third layer metal M13 and corresponding to the vertical signal. Next, as shown in Fig. 29, a connection wiring 67 is formed to electrically connect the second connection pad 63 to the first connection pad 65. That is, a conductive film is formed on the entire rear surface of the insulating film ” and the first semiconductor substrate 31 to be buried in the recessed portion 81 and the connection hole 62 and the connection hole 64, and then etched back or patterned. The connection wiring 67 is formed. The connection wiring 67 includes a connection conductor 68 and a through connection conductor 69. The connection conductor 68 is buried in the connection hole and connected to the first connection pad 65. The through connection conductor 69 is buried in the through connection hole. And connected to the second connection pad 62. The connection wiring 67 further includes a connection conductor 71 electrically connecting the connection conductor 68 to the through connection conductor 69. The connection guide 157964.doc
S •36· 201246520 體71係隱埋於凹陷部分81中且經平坦化以與絕緣膜77之表 面齊平。連接導體68、貫通連接導體69及連接導體71係由 同一金屬整體地形成以充當一導電膜。由於連接佈線67係 藉由回蝕而形成’因而連接佈線67可係由銅（Cu)形成。連 接佈線67可經由障壁金屬（TiN或諸如此類）由金屬形成， 諸如鶴（W)、銘（A1)或金（Au)。 接下來’如在圖30中所展示，在其中需要遮蔽光之一區 上形成光遮蔽膜72。如在該圖式中所示意性地圖解說明， 在控制電路24上形成光遮蔽膜72，但亦可在像素電晶體上 形成光遮蔽膜72。光遮蔽膜72可由諸如鎢（w)之金屬形 成。跨越像素陣列23形成經平坦化膜73以覆蓋光遮蔽膜 72。在經平坦化膜73上形成（舉例而言）紅色（R)、綠色（g) 及藍色（B)之晶片上遽色器74以對應於各別像素，且在晶 片上滤.色器74上形成晶片上微透鏡75。在第一半導體基板 31中，像素陣列23及控制電路25係形成為成品。連接佈線 67之連接導體71充當曝露在外之一電極墊。在第二半導體 基板45中，邏輯電路25形成為成品。 接下來，將該等半導體基板劃分成若干晶片，且因此獲 得背側照明式固態成像元件裝置82之一目標，如在圖乃中 所展示。 根據第三實施例之固態成像元件及其製造方法，完全移 除第一半導體晶片單元22之-部分（亦即其中形成連接導 體68及貫通連接導體69之區之半導體區段），且將絕緣膜 77隱埋於經移除之半導體移除區52中。凹陷部分81係形成 157964.doc •37· 201246520 於絕緣膜77中且連接導體68及貫通連接導體69係隱埋於形 成於凹陷部分81下方之絕緣膜77中之連接孔64及貫通連接 孔62中。由於連接導體68及69因絕緣膜77而遠離半導體基 板3 1之側表面，因而減少了半導體基板3〗與連接導體68及 69之間的寄生電容。此外，半導體移除區52之内側係隱埋 於絕緣膜77中，因此可與經堆疊絕緣膜61合作以機械方式 可葬地保護半導體基板3 1之與半導體移除區52之側壁面對 之表面。因此，可提供具有較高效能之固態成像元件。 由於連接導體71係隱埋於絕緣膜77之凹面部分81中，且 連接導體71經平坦化以與絕緣膜77之表面齊平，因此，可 形成具有較小表面步差之固態成像裝置。 在第三實施例中，由於將第一半導體基板3 1薄化，凹陷 部分81另外地形成於絕緣膜77中，且形成貫通連接孔62及 連接孔64，因而減小了孔之縱橫比且可以高精度形成連接 孔62及64。因此，可以高精度製造具有高效能之固態成像 裝置。 雖然未作其他說明，但可獲得與第一實施例之優點相同 之優點。 在上文所闡述之第二及第三實施例中，可利用圖2C中所 展示之組態。 根據上文所闡述之實施例’將兩個半導體晶片22與26彼 此接合。此外，根據本發明之實施例之固態成像元件，可 將兩個或兩個以上半導體晶片單元彼此接合。即使在彼此 接合之兩個或兩個以上半導體晶片單元中，仍可應用上文 157964.docS • 36· 201246520 The body 71 is buried in the recessed portion 81 and planarized to be flush with the surface of the insulating film 77. The connecting conductor 68, the through connecting conductor 69, and the connecting conductor 71 are integrally formed of the same metal to serve as a conductive film. Since the connection wiring 67 is formed by etch back, the connection wiring 67 can be formed of copper (Cu). The connection wiring 67 may be formed of metal via a barrier metal (TiN or the like) such as crane (W), Ming (A1) or gold (Au). Next, as shown in Fig. 30, a light shielding film 72 is formed on a region in which light is to be shielded. As illustrated in the diagram, the light shielding film 72 is formed on the control circuit 24, but the light shielding film 72 may be formed on the pixel transistor. The light shielding film 72 may be formed of a metal such as tungsten (w). A planarization film 73 is formed across the pixel array 23 to cover the light shielding film 72. On the wafer (for example) red (R), green (g), and blue (B) on the planarization film 73, a color filter 74 is formed on the wafer to correspond to the respective pixels, and the color filter is filtered on the wafer. A wafer upper microlens 75 is formed on 74. In the first semiconductor substrate 31, the pixel array 23 and the control circuit 25 are formed as a finished product. The connection conductor 71 of the connection wiring 67 serves as an electrode pad exposed to the outside. In the second semiconductor substrate 45, the logic circuit 25 is formed as a finished product. Next, the semiconductor substrates are divided into a plurality of wafers, and thus an object of the back side illumination type solid state imaging device device 82 is obtained, as shown in the figure. According to the solid-state imaging element of the third embodiment and the method of manufacturing the same, the portion of the first semiconductor wafer unit 22 (that is, the semiconductor portion in which the connection conductor 68 and the through-connection conductor 69 are formed) are completely removed, and the insulation is to be insulated. The film 77 is buried in the removed semiconductor removal region 52. The recessed portion 81 is formed in the insulating film 77, and the connecting conductor 68 and the through connecting conductor 69 are buried in the connecting hole 64 and the through connecting hole 62 formed in the insulating film 77 under the recessed portion 81. in. Since the connection conductors 68 and 69 are away from the side surface of the semiconductor substrate 31 by the insulating film 77, the parasitic capacitance between the semiconductor substrate 3 and the connection conductors 68 and 69 is reduced. In addition, the inner side of the semiconductor removal region 52 is buried in the insulating film 77, so that the semiconductor substrate 31 can be mechanically buried in cooperation with the stacked insulating film 61 to face the sidewall of the semiconductor removal region 52. surface. Therefore, a solid-state imaging element having higher performance can be provided. Since the connection conductor 71 is buried in the concave portion 81 of the insulating film 77, and the connection conductor 71 is planarized to be flush with the surface of the insulating film 77, a solid-state imaging device having a small surface step can be formed. In the third embodiment, since the first semiconductor substrate 31 is thinned, the recessed portion 81 is additionally formed in the insulating film 77, and the through-connection hole 62 and the connection hole 64 are formed, thereby reducing the aspect ratio of the hole and The connection holes 62 and 64 can be formed with high precision. Therefore, it is possible to manufacture a high-performance solid-state imaging device with high precision. Although not otherwise illustrated, the same advantages as those of the first embodiment can be obtained. In the second and third embodiments set forth above, the configuration shown in Figure 2C can be utilized. The two semiconductor wafers 22 and 26 are bonded to each other in accordance with the embodiment set forth above. Further, according to the solid-state imaging element of the embodiment of the present invention, two or more semiconductor wafer units can be bonded to each other. Even in two or more semiconductor wafer units bonded to each other, the above 157964.doc can be applied.
S -38 - 201246520 所闡述之組態，其中完全移除在包括像素陣列23之第一半 導體晶片單元22與包括邏輯電路25之第二半導體晶片單元 26之間的連接部分中之半導體區段。 在其中使上文所闡述之半導體晶片單元彼此接合之組態 中，出現諸如接地電容毗鄰耦合電容之寄生電容。特定而 言，由於連接導體68及貫通連接導體69之表面面積大，因 而較佳地在毗鄰行之連接導體之間的間隙中或在毗鄰行之 敷設佈線之間的間隙中減少毗鄰耦合電容。此處，連接導 體之間的間隙係指當將連接導體68及貫通連接導體69設定 為一對連接導體時一對毗鄰連接導體之間的間隙。另一方 面，由於第一連接墊65之面積及間鉅與第二連接墊63之面 積及間距大於一像素面積及一像素間距，因此一實際可用 佈置係較佳的。 接下來’將根據本發明之一實施例闡述該對之毗鄰耦合 電容之減小與實際可用佈置。 5.第四實施例 固態成像元件之組態之實例 圖3 1至圖3 5係根據一第四實施例之一半導體元件（亦 • 即’一MOS固態成像元件）之圖示。特定而言，圖31至圖 . 35僅展示包括將第一半導體晶片單元與第二半導體晶片單 元彼此電連接之連接塾之一佈線連接部分之佈置。圖3 1係 一連接塾陣列之一平面圖。圖32係沿圖31之線χχχιι_ XXXII截取之一剖面圖。圖33係沿圖3 1之線χχχιιι_ XXXIII截取之一剖面圖。圖34及圖35係圖31之分解平面 157964.doc -39- 201246520 圖。 在根據第四實施例之一固態成像元件84中，如上文所闡 述，將兩個半導體晶片單元22與26彼此接合，移除第一半 導體晶片單元22之一部分之半導體區段’且經由半導體移 除區52中之連接佈線67使兩個半導體晶片單元22與26彼此 連接。在本實施例中，由於將上文所闡述之實施例之數個 組態應用於除佈線連接區段之佈置外的其他組態，因此將 不重複對其之詳細說明。 在第四實施例中，第一半導體晶片單元22中之多層佈線 41之佈線40[40a、40b、40c、及40d]係形成為複數個層， 在此實例中四層金屬Ml至M4。第一連接墊65係由第一層 金屬Ml形成’且對應於垂直信號線之敷設佈線4〇d係由在 第二層之後的一金屬形成。在本實施例中，對應於垂直信 號線之敷設佈線40d係由第四層金屬M4形成。第二半導體 晶片單元26中之多層佈線層55之佈線53 [53a、53b、53 c及 53d]係由複數個層形成，在此實例中，四層金屬mi 1至 M14。第二連接墊63係由在第二層金屬之後的層（諸如第三 層金屬或第四層金屬）形成，在本實施例中，係最上層之 第四層金屬M14。對應於垂直信號線之敷設佈線53d係由 連接墊63之金屬M14下方之一金屬（在此實例中，第一層金 屬Mil)形成。在第一半導體晶片單元22中，由第一層金屬 形成之第一連接墊65經由由第二層金屬及第三層金屬形成 之導通導體86及連接部分85電連接至由第四層金屬形成之 敷設佈線40d。在第二半導體晶片單元26中，由第四層金 -40- 157964.docThe configuration described in S-38 - 201246520, in which the semiconductor segments in the connection portion between the first semiconductor wafer unit 22 including the pixel array 23 and the second semiconductor wafer unit 26 including the logic circuit 25 are completely removed. In a configuration in which the above-described semiconductor wafer units are bonded to each other, a parasitic capacitance such as a grounding capacitor adjacent to the coupling capacitor occurs. In particular, since the surface area of the connecting conductor 68 and the through connecting conductor 69 is large, it is preferable to reduce the adjacent coupling capacitance in the gap between the connecting conductors adjacent to the row or in the gap between the adjacent wirings. Here, the gap between the connection conductors means a gap between a pair of adjacent connection conductors when the connection conductor 68 and the through connection conductor 69 are set as a pair of connection conductors. On the other hand, since the area of the first connection pad 65 and the area and spacing between the giant connection pad and the second connection pad 63 are larger than a pixel area and a pixel pitch, a practically usable arrangement is preferred. Next, a reduction in the adjacent coupling capacitance of the pair and an actual usable arrangement will be described in accordance with an embodiment of the present invention. 5. Fourth Embodiment Example of Configuration of Solid-State Imaging Element FIG. 3 to FIG. 3 are diagrams showing a semiconductor element (also referred to as a 'MOS solid-state imaging element) according to a fourth embodiment. In particular, Figures 31 to 35 show only the arrangement of one of the wiring connections including the connection ports for electrically connecting the first semiconductor wafer unit and the second semiconductor wafer unit to each other. Figure 3 is a plan view of a connection stack. Figure 32 is a cross-sectional view taken along line χχχιι_XXXII of Figure 31. Figure 33 is a cross-sectional view taken along line χχχιιι XXXIII of Figure 31. Figures 34 and 35 are diagrams of the exploded plane 157964.doc -39-201246520 of Figure 31. In the solid-state imaging element 84 according to the fourth embodiment, as explained above, the two semiconductor wafer units 22 and 26 are bonded to each other, the semiconductor segment of a portion of the first semiconductor wafer unit 22 is removed and moved via the semiconductor The connection wiring 67 in the division area 52 connects the two semiconductor wafer units 22 and 26 to each other. In the present embodiment, since a plurality of configurations of the above-described embodiments are applied to other configurations than the arrangement of the wiring connection sections, detailed description thereof will not be repeated. In the fourth embodiment, the wirings 40 [40a, 40b, 40c, and 40d] of the multilayer wiring 41 in the first semiconductor wafer unit 22 are formed in a plurality of layers, in this example, four layers of metal M1 to M4. The first connection pad 65 is formed of the first layer metal M1' and the laying wiring 4〇d corresponding to the vertical signal line is formed of a metal after the second layer. In the present embodiment, the laying wiring 40d corresponding to the vertical signal line is formed of the fourth layer metal M4. The wirings 53 [53a, 53b, 53c, and 53d] of the multilayer wiring layer 55 in the second semiconductor wafer unit 26 are formed of a plurality of layers, in this example, four layers of metal mi 1 to M14. The second connection pad 63 is formed of a layer (such as a third layer metal or a fourth layer metal) behind the second layer of metal, and in this embodiment, the fourth layer of metal M14 of the uppermost layer. The laying wiring 53d corresponding to the vertical signal line is formed by one metal (in this example, the first layer of metal Mil) under the metal M14 of the connection pad 63. In the first semiconductor wafer unit 22, the first connection pad 65 formed of the first layer of metal is electrically connected to the fourth layer metal via the via conductor 86 and the connection portion 85 formed of the second layer metal and the third layer metal. The wiring 40d is laid. In the second semiconductor wafer unit 26, by the fourth layer of gold -40-157964.doc
S 201246520 屬形成之第二連接墊63經由由第三層金屬及第二層金屬形 成之導通導體88及連接部分87電連接至由第一層金屬形成 之敷設佈線53d。 考量第一半導體晶片單元22與第二半導體晶片單元％之 接合之位置偏離，第二連接墊63具有大於第一連接墊65之 面積之一面積。將一第一連接墊65與一第二連接墊63之一 對統稱為一連接墊對89。 一般而言，垂直信號線係以每一像素間距來安置。然 而’當像素間距係微小的時’該連接墊對89之間距比像素 間距相對較大且因此難以安置佈線。而且，由於垂直信號 線係密集地安置，因而垂直信號線之間的毗鄰耦合電容增 加且因此出現一缺點。在本實施例中，實現連接佈線與垂 直k號線之一佈置以防止此問題。在一個垂直信號線、一 個連接導體或一個貫通連接導體中接地電容較佳地係2〇 fF 或更少。此外’毗鄰耦合電容較佳地係接地電容之約1/1〇 或更少’亦即2 fF或更少以避免一拖尾現象。 在一平面圖中，第一連接墊65及第二連接墊63在一平面 圖中具有一八邊形形狀，且較佳地具有一正八邊形形狀。 形成一連接墊對89之第一連接墊及第二連接墊係沿一水平 方向配置。在各別行之敷設佈線4〇d及53d配置所沿之水平 方向上配置複數個連接塾對8 9。在此實例中，在一垂直方 向上配置連接墊89之四個級。亦即，具有正八邊形形狀之 第一連接墊65及第二連接墊63在水平方向及垂直方向上交 替配置於半導體晶片單元22與26之間的佈線連接部分中。 157964.doc -41· 201246520 此處，一連接墊陣列91經形成以使得在水平方向上配置複 數個連接墊對89且在垂直方向上配置連接墊89之四個級。 在下文中’將界定八邊形形狀。在某些情形甲，八邊形第 一連接墊65整體地具有部分地突出之一連接突出部分65& 以供應與敷設佈線40d之連接（參見圖32)。在此情形中，由 於該突出部之程度在考量整個八邊形形狀之情形中係小 的，因此該突出部納入八邊形之類別中。 舉例而言，在一平面圖中，在連接墊陣列91中，第一連 接墊65與第二連接墊63緊密地配置。第一連接墊65與第二 連接墊63可彼此部分地重疊。連接導體68及貫通連接導體 69分別連接至第一連接墊65及第二連接墊〇，且第一半導 體曰曰片單元22及第一半導體晶片單元％經由包括將連接導 體68及69兩者彼此連接之連接導體71之連接佈線67彼此電 連接。連接導體68及貫通連接導體69可經形成以具有與對 應連接墊65及63之平面表面相同之八邊形形狀之剖面。在 此實例中，連接佈線67經形成而與第三實施例中相同。亦 即、’’邑緣膜77係隱埋於半導體移除區52中，且連接導體65 及貫通連接導體63經形成以穿透絕緣膜77,且將連接導體 71平坦化以使得連接導體71之表面與絕緣膜”之表面齊 平。 在本實施例中，對應於四個行之垂直信號線之敷設佈線 40d及53d分別連接至連接墊對89之四個級之第—連接墊μ 及第二連接墊63。在第-半導體晶片單元22中，第一連接 塾係由帛yf金屬Ml形成，且每一敷設佈線侧係由另 157964.docThe second connection pad 63 formed by the S 201246520 is electrically connected to the routing wiring 53d formed of the first layer metal via the via conductor 88 and the connection portion 87 formed of the third layer metal and the second layer metal. The positional deviation of the junction of the first semiconductor wafer unit 22 and the second semiconductor wafer unit % is considered, and the second connection pad 63 has an area larger than the area of the first connection pad 65. One pair of a first connection pad 65 and a second connection pad 63 are collectively referred to as a connection pad pair 89. In general, vertical signal lines are placed at each pixel pitch. However, when the pixel pitch is minute, the connection pad pair 89 is relatively larger than the pixel pitch and thus it is difficult to place the wiring. Moreover, since the vertical signal lines are densely arranged, the adjacent coupling capacitance between the vertical signal lines increases and thus a disadvantage occurs. In the present embodiment, the connection wiring and one of the vertical k-number lines are arranged to prevent this problem. The grounding capacitance is preferably 2 〇 fF or less in a vertical signal line, a connecting conductor or a through connecting conductor. Further, the adjacent coupling capacitor is preferably about 1/1 或 or less of the ground capacitance, i.e., 2 fF or less to avoid a smear phenomenon. In a plan view, the first connection pad 65 and the second connection pad 63 have an octagonal shape in a plan view, and preferably have a regular octagonal shape. The first connection pads and the second connection pads forming a pair of connection pads 89 are disposed in a horizontal direction. A plurality of connection pairs 8 9 are arranged in the horizontal direction along which the respective layout wirings 4〇d and 53d are arranged. In this example, four stages of the connection pads 89 are arranged in a vertical direction. That is, the first connection pad 65 and the second connection pad 63 having a regular octagonal shape are alternately disposed in the wiring connection portion between the semiconductor wafer units 22 and 26 in the horizontal direction and the vertical direction. 157964.doc -41· 201246520 Here, a connection pad array 91 is formed such that a plurality of connection pad pairs 89 are arranged in the horizontal direction and four stages of the connection pads 89 are arranged in the vertical direction. In the following 'the octagonal shape will be defined. In some cases, the octagonal first connection pad 65 integrally has a portion protruding from the protruding portion 65& to supply a connection with the laying wiring 40d (see Fig. 32). In this case, since the extent of the projection is small in consideration of the entire octagonal shape, the projection is incorporated into the category of the octagon. For example, in a plan view, in the connection pad array 91, the first connection pads 65 are closely arranged with the second connection pads 63. The first connection pad 65 and the second connection pad 63 may partially overlap each other. The connection conductor 68 and the through connection conductor 69 are respectively connected to the first connection pad 65 and the second connection pad, and the first semiconductor die unit 22 and the first semiconductor wafer unit % include the connection conductors 68 and 69 via the other The connection wirings 67 of the connected connection conductors 71 are electrically connected to each other. The connecting conductor 68 and the through connecting conductor 69 may be formed to have a cross section of the same octagonal shape as the planar surfaces of the corresponding connecting pads 65 and 63. In this example, the connection wiring 67 is formed in the same manner as in the third embodiment. That is, the ''edge film 77 is buried in the semiconductor removal region 52, and the connection conductor 65 and the through-connection conductor 63 are formed to penetrate the insulating film 77, and the connection conductor 71 is planarized so that the connection conductor 71 The surface of the surface is flush with the surface of the insulating film. In the present embodiment, the routing wires 40d and 53d corresponding to the vertical signal lines of the four rows are respectively connected to the fourth connection pad μ of the four stages of the connection pad pair 89 and a second connection pad 63. In the first semiconductor wafer unit 22, the first connection is formed of 帛yf metal M1, and each of the wiring sides is provided by another 157964.doc
S -42· 201246520 一層金屬（在此實例中，第四層金屬M4)形成。因此，由於 敷設佈線40d可經安置以在第一連接墊65下方跨越，因此 可擴大ffltt鄰敷設佈線40d之間的一距離。同樣，在第二半 導體晶片單元26中，第二連接塾63係由第四層金屬μ 14形 成且每一敷設佈線5 3 d係由另一層金屬（在此實例中，第一 層金屬Mil)形成。因此’由於敷設佈線53d可經安置以在 第二連接墊63下方跨越，因此可擴大毗鄰敷設佈線53d之 間的一距離。 在本實施例中，實現該佈置以使得於在水平方向上之連 接墊對89之一個間距P内配置在垂直方向上對應於連接墊 對89之複數個級之複數個行之垂直信號線。在圖3丨中，實 現該佈置以使得於在連接塾對8 9之一個間距p内配置在作 為對應於在垂直方向上之四個級連接墊對89之四個行之垂 直信號線之敷設佈線40d及53d。 在根據第四實施例之固態成像元件84中，連接墊陣列91 經形成以使得第一連接墊65及第二連接墊63之平面表面形 狀各自具有八邊形形狀且第一連接墊65及第二連接墊63在 水平方向及垂直方向上係密集地交替配置。亦即，密集連 接塾陣列91經形成而位於兩個半導體晶片單元22與26之間 的佈線連接部分中。由於作為四個行之垂直信號線之敷設 佈線40d及53d係連接至連接墊陣列9丨之連接墊對89之四個 級，因而毗鄰敷設佈線4〇d之間的間隙及敷設佈線53d之間 的間隙得以擴大，藉此減小B比鄰耦合電容。此外，由於絕 緣膜77係存在於毗鄰連接導體對之間，因而在連接墊對之 157964.doc •43· 201246520 間的毗鄰耦合電容亦可得以減小。 由於連接導體68係連接至由第一半導體晶片單元22中之 第一層金屬Ml形成之連接墊65，因而連接孔之深度得以 縮短且因此易於處理該連接孔，此外，易於隱埋連接導體 68 〇 在連接墊對89中，第二半導體晶片單元26中之連接墊63 之面積大於第一半導體晶片單元22之連接墊65之面積。可 參考形成於第一半導體晶片單元22中之對準標記使第一半 導體晶片單元22中之連接孔64與連接墊65之位置彼此精確 地匹配。另一方面，當將第一半導體晶片單元22與第二半 導體晶片單元26彼此接合時，存在在該接合中可發生一偏 離之一憂慮。然而，由於連接墊63之面積大，因而貫通連 接孔62與連接墊63可彼此匹配。因此，如上文所闡述，即 使當發生接合之位置偏離時，仍可實現連接墊65及63與連 接導體64及貫通連接導體69之間的連接。 由於連接墊對89之兩個行與四個級沿垂直方向交替地配 置’因而較大連接墊63及較小連接墊65之方向、連接塾63 及65可密集地配置。因此，即使當像素間距因像素之微型 化而係微小的時，仍可敷設敷設佈線。 與下文所述之其中在垂直方向上配置第一連接整65與第 二連接墊63對之一組態相比，在其中在水平方向配置第_ 連接墊65與第二連接墊63對之組態中因四個行之敷設佈線 之佈線長度之一差所致之一佈線電阻差減小。 連接墊65及63之面積及間距大於像素之面積及間距。然 157964.doc -44 - 201246520 而’由於可藉由形成連接墊65及63之佈置來敷設佈線4〇d 及53d ’因而可提供具有高效能之固態成像元件。 在第四實施例中，即使當利用第一實施例及第二實施例 之連接佈線67之 '纟且態時，仍可同樣地減小视鄰耗合電容。 在第四實施例中，可獲得與第一實施例至第三實施例之 優點相同之優點。 6·第五實施例 固態成像元件之組態實例 圖3 6係根據本發明之一實施例之一半導體元件亦即根據 一第五實施例之一 MOS固態成像元件之一圖示。特定而 言，圖36僅展示包括將第一半導體晶片單元22與第二半導 體晶片單元26彼此電連接之連接墊65及63之一佈線連接區 段之佈置。 在根據第五實施例之一固態成像元件93中，如上文所闡 述，將兩個半導體晶片單元22與26彼此接合，移除第一半 導體晶片單元22之一部分之半導體區段，且經由半導體移 除區52中之連接佈線67將半導體晶片單元22與26兩者彼此 連接。在本實施例中，由於將上文所闡述之實施例之數個 組態應用於除佈線連接區段之佈置外之其他組態，因此將 不重複對其之詳細說明。 在第五實施例中，連接墊陣列91A及91B經安置而兩者 皆在外部，在垂直方向上其之間間置有像素陣列23地彼此 面對。對應於垂直信號線之敷設佈線40d及53d係交替地連 接至連接墊陣列91A及91B。在本實施例中，舉例而言， 157964.doc -45- 201246520 如在圖31中，連接墊對89(其中第一連接墊65與第二連接 墊6 3對係在水平方向上配置）在水平方向上係以複數個級 (在此實例中兩個級）之形式配置。舉例而言，密集地配置 連接墊陣列91A及91B之連接墊對89。敷設佈線對4〇d及 53d以每兩行交替地連接至連接墊陣列9丨八及91]3之連接墊 對89之該兩個級。連接墊陣列91八及91]3兩者分別形成於 圖15B中所展示之半導體移除區52a及52b中。 在圖36中，連接墊65及63之平面表面具有八邊形形狀且 較佳地具有正八邊形形狀。然而，由於可擴大佈線之間的 間隙，因而連接墊之平面表面可具有一矩形形狀或一六邊 形形狀（較佳地一正六邊形形狀）。在本實施例中，如下文 所闡述，連接墊對89可適用於其中（其甲第一連接墊65與 第二連接墊63)連接墊對代替地在垂直方向上配置之一組 態。 在根據第五實施例之固態成像元件93中，連接墊陣列 91A及91B經配置而在其之間間置有像素陣列23，且對應 於垂直信號線之敷設佈線交替地連接至每複數個行（在此 實例中，每兩個行）中連接墊陣列91A及91B之連接墊對89 之兩個級。在此組態中，不必強制窄化毗鄰敷設佈線4〇d 之間的間隙及毗鄰敷設佈線53d之間的間隙。換言之，可 以一充分空間擴大眺鄰敷設佈線4〇d之間的間隙及础鄰敷 設佈線53d之間的間隙。因此，可減小毗鄰耦合電容。由 於減小了敷设佈線之間的佈線長度之一差，因此可進一步 減小佈線電阻差。 157964.doc -46- 201246520 連接墊65及63之面積及間距大於像素之面積及間距。然 而，由於可藉由形成連接墊之佈置來敷設佈線4〇d及53d， 因而可提供具有高效能之固態成像元件。 在第五實施例中，即使當利用第一實施例、第二實施例 及第三實施例之連接佈線之組態時，仍可同樣地減小毗鄰 耦合電容。 在第五實施例t，可獲得與第一實施例至第三實施例之 優點相同之優點。 7 ·第六實施例 固態成像元件之組態之實例 圖3 7及圖3 8係根據一第六實施例之一半導體元件（亦 即’一 MOS固態成像元件）之圖示。特定而言，圖37及圖 38僅展示包括將第一半導體晶片單元22與第二半導體晶片 單元26彼此電連接之一連接墊65及63之一佈線連接區段之 佈置。 在根據第六實施例之一固態成像元件95中，如上文所闡 述，將兩個半導體晶片單元22與26彼此接合，移除第一半 導體BB片單元22之一部分之半導體區段，且經由半導體移 除區52中之連接佈線67使兩個半導體晶片單元22與26彼此 連接。在本實施例中，由於將上文所闡述之實施例之數個 組態應用於除佈線連接區段之佈置外的其他組態，因此將 不重複對其之詳細說明。 在第六實施例中，舉例而言，連接墊陣列91經形成以使 得具有與圖31之八邊形形狀相同之八邊形形狀之第一連接 157964.doc -47- 201246520 墊65及第二連接墊63在垂直方向及水平方向上交替地配 置。四個行之敷設佈線4〇d及53d係連接至連接墊陣列91之 連接墊對89之四個級。第一半導體晶片單元22中之第一連 接墊65係由第一層金屬河丨形成且連接至連接墊65之敷設 佈線40d係由第四層金屬M4，形成。第二半導體晶片單元％ 中之第二連接墊63係由第四層金屬M14形成，且連接至連 接墊63之敷設佈線53d係由第一層金屬Mil形成。 第一半導體晶片單元22中之敷設佈線4〇d經安置而在未 連接之第一連接墊65下方跨越。由於連接墊65之面積相對 大，因而存在在連接墊65與具有不同電位且跨越連接墊65 之敷設佈線40d之間可出現耦合電容之一憂慮。因此，在 本實施例中，在第一連接墊65與敷設佈線4〇d之間形成由 介於第一連接墊65與敷設佈線4〇d之間的一層金屬形成之 一屏蔽佈線96。亦即，在第一連接墊65與敷設佈線4〇d之 間形成由第二或第三層金屬（在此實例中，第二層金屬M2) 形成之屏蔽佈線96»舉例而言，在某些情形中，如在圖38 中所展示，由於三個敷設佈線40d在第一連接墊65下方跨 越’因而屏蔽佈線96係連續地形成達連接墊對89之四個級 以具有對應於連接墊65之寬度之一寬度。 第二半導體晶片單元26中之敷設佈線53d經安置而在未 連接之第二連接墊63下方跨越。由於第二連接墊63之面積 亦相對大，因而存在在連接墊63與具有不同電位且跨越連 接墊63之敷设佈線53d之間可出現耦合電容之一憂慮。因 此，在第二連接墊63與敷設佈線53d之間形成由介於第二 157964.doc -48- 201246520 連接墊63與敷設佈線53d之間的一層金屬形成之一屏蔽佈 線。亦即’在第二連接墊63與敷設佈線53d之間形成由第 二層金屬或第三層金屬（在此實例中，第三層金屬Mi3)形 成之屏蔽佈線。舉例而言，在某些情形中，由於三個敷設 佈線53d在第二連接墊63下方跨越，因而屏蔽佈線係連續 地形成達連接墊對89之四個級以具有對應於連接墊63之寬 度之一寬度。 在根據第六實施例之固態成像元件中，藉由安置於第一 連接墊65與在連接墊65下方跨越之敷設佈線4〇d之間的屏 蔽佈線96來防止在具有不同電位之連接墊65與敫設佈線 40d之間出現耦合電容。此外，藉由安置於第二連接墊〇 與在連接墊63下方跨越之敷設佈線53d之間的屏蔽佈線來 防止在具有不同電位之連接墊63與敷設佈線53d之間出現 耦合電容。因此，可實現具有較高效能之固態成像元件。 在第六實施例令，可獲得減小減小寄生電容之優點，如 在第一至第三實施例_所闡述。 在第六實施例中，可自屏蔽佈線96獲得該優點，而無論 連接墊65之平面表面之形狀或連接墊65之佈置。 8 ·第七貫施例 固態成像元件之組態之實例 圖3 9係根據本發明之一實施例之一半導體元件亦即根據 一第器實施例之一MOS固態成像元件之一圖示。特定而 言，圖39僅展示包括將第一半導體晶片單元22與第二半導 體晶片單元26彼此電連接之連接墊65及63之—佈線連接區 157964.doc •49· 201246520 段之佈置。 在根據第七實施例之一固態成像元件9 7中，如上文所闡 述’將兩個半導體晶片單元22與26彼此接合，移除第一半 導體晶片單元22之一部分之半導體區段，且經由半導體移 除區52中之連接佈線67使兩個半導體晶片單元22與26彼此 連接。在本實施例中，由於將上文所闡述之實施例之數個 組態應用於除佈線連接區段之佈置外的其他組態，因此將 不重複對其之詳細說明。 在第七實施例中，在對應於垂直信號線之敷設佈線40d 及53d延伸所沿之一垂直方向（所謂之縱向方向）上配置第一 連接墊65與第二連接墊63對。一連接墊陣列98經形成以使 得在水平方向上配置複數個連接墊對99，其中敷設佈線 40d及53d在垂直方向上係以複數個級（在此實例中三個級） 配置。 舉例而言，如在第四實施例中所闡述，第一連接墊65及 第二連接墊63在一平面圖中具有一八邊形形狀，且較佳地 具有一正八邊形形狀。第一連接墊65與第二連接墊63經由 包括連接導體68、貫通連接導體69及連接導體71之連接佈 線67彼此電連接。 在第一半導體晶片單元22中，多層佈線層41之佈線40可 由複數個層（舉例而言，四層金屬Ml至M4)形成。此時， 第一連接墊65較佳地由第一層金屬Ml形成，連接至連接 墊65之敷設佈線40d較佳地由第四層金屬M4形成。本發明 之實施例並不限於此，且第一連接墊65及敷設佈線40d可 157964.doc ^S -42· 201246520 A layer of metal (in this example, a fourth layer of metal M4) is formed. Therefore, since the laying wiring 40d can be disposed to straddle under the first connection pad 65, a distance between the ffltt adjacent wirings 40d can be enlarged. Also, in the second semiconductor wafer unit 26, the second connection port 63 is formed of the fourth layer metal μ 14 and each of the laying wires 5 3 d is composed of another layer of metal (in this example, the first layer of metal Mil) form. Therefore, since the laying wiring 53d can be disposed to straddle under the second connecting pad 63, a distance between the adjacent laying wirings 53d can be enlarged. In the present embodiment, the arrangement is realized such that a vertical signal line corresponding to a plurality of rows of a plurality of stages of the connection pad pair 89 in the vertical direction is disposed in a pitch P of the pair of connection pads 89 in the horizontal direction. In Fig. 3, the arrangement is implemented such that the vertical signal lines corresponding to the four rows of the four-stage connection pad pairs 89 in the vertical direction are disposed in a pitch p of the connection pairs 88. Wirings 40d and 53d. In the solid-state imaging element 84 according to the fourth embodiment, the connection pad array 91 is formed such that the planar surface shapes of the first connection pad 65 and the second connection pad 63 each have an octagonal shape and the first connection pad 65 and the The two connection pads 63 are densely arranged alternately in the horizontal direction and the vertical direction. That is, the dense junction germanium array 91 is formed to be located in the wiring connection portion between the two semiconductor wafer units 22 and 26. Since the laying wirings 40d and 53d which are the vertical signal lines of the four rows are connected to the four stages of the connection pad pair 89 of the connection pad array 9, the gap between the adjacent wirings 4〇d and the laying wiring 53d is provided. The gap is enlarged to thereby reduce the B-nearest coupling capacitance. In addition, since the insulating film 77 is present between adjacent pairs of connecting conductors, the adjacent coupling capacitance between the pair of connecting pads 157964.doc • 43· 201246520 can also be reduced. Since the connection conductor 68 is connected to the connection pad 65 formed of the first layer metal M1 in the first semiconductor wafer unit 22, the depth of the connection hole is shortened and thus the connection hole is easily handled, and further, the connection conductor 68 is easily buried. In the connection pad pair 89, the area of the connection pads 63 in the second semiconductor wafer unit 26 is larger than the area of the connection pads 65 of the first semiconductor wafer unit 22. The positions of the connection holes 64 and the connection pads 65 in the first semiconductor wafer unit 22 can be precisely matched to each other with reference to the alignment marks formed in the first semiconductor wafer unit 22. On the other hand, when the first semiconductor wafer unit 22 and the second semiconductor wafer unit 26 are joined to each other, there is a concern that a deviation may occur in the bonding. However, since the area of the connection pad 63 is large, the through-connection holes 62 and the connection pads 63 can be matched with each other. Therefore, as explained above, the connection between the connection pads 65 and 63 and the connection conductor 64 and the through-connection conductor 69 can be achieved even when the position at which the bonding occurs is deviated. Since the two rows and the four stages of the pad pair 89 are alternately arranged in the vertical direction, the directions of the larger connection pads 63 and the smaller connection pads 65, and the ports 63 and 65 can be densely arranged. Therefore, even when the pixel pitch is minute due to miniaturization of the pixels, the laying wiring can be laid. Compared with the configuration in which one of the first connection 65 and the second connection pad 63 is disposed in the vertical direction, the pair of the connection pad 65 and the second connection pad 63 are disposed in the horizontal direction. In the state, one of the wiring resistance differences is reduced due to a difference in the wiring length of the four rows of wiring. The area and spacing of the connection pads 65 and 63 are larger than the area and spacing of the pixels. However, since the wirings 4〇d and 53d' can be laid by the arrangement of the connection pads 65 and 63, a solid-state imaging element having high performance can be provided. In the fourth embodiment, even when the "connected state" of the connection wirings 67 of the first embodiment and the second embodiment is utilized, the viewing-side consumable capacitance can be similarly reduced. In the fourth embodiment, the same advantages as those of the first to third embodiments can be obtained. 6. Fifth Embodiment Configuration Example of Solid-State Imaging Element FIG. 3 is a diagram showing one of semiconductor elements according to an embodiment of the present invention, that is, one of MOS solid-state imaging elements according to a fifth embodiment. In particular, Figure 36 shows only the arrangement of one of the connection pads 65 and 63 including the connection pads 65 and 63 that electrically connect the first semiconductor wafer unit 22 and the second semiconductor wafer unit 26 to each other. In the solid-state imaging element 93 according to the fifth embodiment, as explained above, the two semiconductor wafer units 22 and 26 are bonded to each other, the semiconductor portion of a portion of the first semiconductor wafer unit 22 is removed, and is moved via the semiconductor. The connection wiring 67 in the division area 52 connects the semiconductor wafer units 22 and 26 to each other. In the present embodiment, since a plurality of configurations of the above-described embodiments are applied to other configurations than the arrangement of the wiring connection sections, detailed description thereof will not be repeated. In the fifth embodiment, the connection pad arrays 91A and 91B are disposed while being externally opposed to each other with the pixel array 23 interposed therebetween in the vertical direction. The routing wirings 40d and 53d corresponding to the vertical signal lines are alternately connected to the connection pad arrays 91A and 91B. In this embodiment, for example, 157964.doc -45- 201246520, as in FIG. 31, the connection pad pair 89 (where the first connection pad 65 and the second connection pad 63 are arranged in the horizontal direction) The horizontal direction is configured in the form of a plurality of stages (two stages in this example). For example, the connection pad pairs 89 of the connection pad arrays 91A and 91B are densely arranged. The laying wiring pairs 4〇d and 53d are alternately connected in two rows to the two stages of the connection pad pair 89 of the connection pad arrays 丨8 and 91]3. The connection pad arrays 91 and 91] 3 are respectively formed in the semiconductor removal regions 52a and 52b shown in Fig. 15B. In Fig. 36, the planar surfaces of the connection pads 65 and 63 have an octagonal shape and preferably have a regular octagonal shape. However, since the gap between the wirings can be enlarged, the planar surface of the connection pad can have a rectangular shape or a hexagonal shape (preferably a regular hexagonal shape). In the present embodiment, as will be explained below, the pair of connection pads 89 can be applied to a configuration in which (the first first connection pad 65 and the second connection pad 63 of the first connection pad 63) are alternately arranged in the vertical direction. In the solid-state imaging element 93 according to the fifth embodiment, the connection pad arrays 91A and 91B are configured with a pixel array 23 interposed therebetween, and the laying wirings corresponding to the vertical signal lines are alternately connected to each of the plurality of lines (In this example, every two rows) two stages of the connection pad pair 89 of the pad arrays 91A and 91B are connected. In this configuration, it is not necessary to forcibly narrow the gap between the adjacent laying wirings 4〇d and the gap between the adjacent laying wirings 53d. In other words, the gap between the adjacent wirings 4dd and the gap between the adjacent wirings 53d can be enlarged in a sufficient space. Therefore, the adjacent coupling capacitance can be reduced. Since the difference in wiring length between the laid wirings is reduced, the wiring resistance difference can be further reduced. 157964.doc -46- 201246520 The area and spacing of the connection pads 65 and 63 are larger than the area and spacing of the pixels. However, since the wirings 4〇d and 53d can be laid by the arrangement in which the connection pads are formed, it is possible to provide a solid-state imaging element having high performance. In the fifth embodiment, even when the configurations of the connection wirings of the first embodiment, the second embodiment, and the third embodiment are utilized, the adjacent coupling capacitance can be similarly reduced. In the fifth embodiment t, the same advantages as those of the first to third embodiments can be obtained. 7. Sixth Embodiment Example of Configuration of Solid-State Imaging Element FIGS. 3 and 3 are diagrams showing a semiconductor element (i.e., a MOS solid-state imaging element) according to a sixth embodiment. In particular, Figures 37 and 38 show only an arrangement including one of the connection pads 65 and 63 of the first semiconductor wafer unit 22 and the second semiconductor wafer unit 26 electrically connected to each other. In the solid-state imaging element 95 according to the sixth embodiment, as described above, the two semiconductor wafer units 22 and 26 are bonded to each other, the semiconductor portion of a portion of the first semiconductor BB chip unit 22 is removed, and via the semiconductor The connection wiring 67 in the removal region 52 connects the two semiconductor wafer units 22 and 26 to each other. In the present embodiment, since a plurality of configurations of the above-described embodiments are applied to other configurations than the arrangement of the wiring connection sections, detailed description thereof will not be repeated. In the sixth embodiment, for example, the connection pad array 91 is formed such that the first connection 157964.doc -47 - 201246520 pad 65 and the second having the same octagonal shape as the octagonal shape of FIG. 31 The connection pads 63 are alternately arranged in the vertical direction and the horizontal direction. The four rows of routing wires 4〇d and 53d are connected to the four stages of the pad pair 89 of the pad array 91. The first connection pad 65 in the first semiconductor wafer unit 22 is formed of a first layer of metal rafts and the laying wiring 40d connected to the connection pads 65 is formed of a fourth layer of metal M4. The second connection pad 63 of the second semiconductor wafer unit % is formed of the fourth layer metal M14, and the laying wiring 53d connected to the connection pad 63 is formed of the first layer metal Mil. The laying wiring 4?d in the first semiconductor wafer unit 22 is disposed to straddle under the unconnected first connection pad 65. Since the area of the connection pad 65 is relatively large, there is a concern that a coupling capacitance may occur between the connection pad 65 and the application wiring 40d having a different potential and crossing the connection pad 65. Therefore, in the present embodiment, a shield wiring 96 formed of a layer of metal interposed between the first connection pad 65 and the laying wiring 4〇d is formed between the first connection pad 65 and the laying wiring 4〇d. That is, a shield wiring 96 formed of a second or third layer of metal (in this example, the second layer of metal M2) is formed between the first connection pad 65 and the laying wiring 4〇d, for example, at some In some cases, as shown in FIG. 38, since the three laying wirings 40d span under the first connection pads 65, the shield wirings 96 are continuously formed up to four stages of the connection pad pair 89 to have corresponding pads. One width of 65 width. The laying wiring 53d in the second semiconductor wafer unit 26 is disposed to straddle under the unconnected second connection pad 63. Since the area of the second connection pad 63 is also relatively large, there is a concern that a coupling capacitance may occur between the connection pad 63 and the laying wiring 53d having a different potential and crossing the connection pad 63. Therefore, a shield wiring formed of a layer of metal interposed between the second 157964.doc -48-201246520 connection pad 63 and the laying wiring 53d is formed between the second connection pad 63 and the laying wiring 53d. That is, a shield wiring formed of a second metal layer or a third layer metal (in this example, the third layer metal Mi3) is formed between the second connection pad 63 and the laying wiring 53d. For example, in some cases, since the three laying wirings 53d span under the second connection pads 63, the shield wirings are continuously formed up to four stages of the connection pad pair 89 to have a width corresponding to the connection pads 63. One width. In the solid-state imaging element according to the sixth embodiment, the connection pads 65 having different potentials are prevented by the shield wirings 96 disposed between the first connection pads 65 and the laying wirings 4〇d crossing under the connection pads 65. A coupling capacitance occurs between the wiring 40d and the wiring. Further, the coupling capacitance between the connection pads 63 having different potentials and the laying wiring 53d is prevented by the shield wiring disposed between the second connection pad 〇 and the laying wiring 53d crossing under the connection pad 63. Therefore, a solid-state imaging element having higher performance can be realized. In the sixth embodiment, the advantage of reducing the parasitic capacitance is reduced, as explained in the first to third embodiments. In the sixth embodiment, this advantage can be obtained from the shield wiring 96 regardless of the shape of the planar surface of the connection pad 65 or the arrangement of the connection pads 65. 8. Seventh Embodiment Example of Configuration of Solid-State Imaging Element FIG. 3 is a diagram showing a semiconductor element according to an embodiment of the present invention, that is, one of MOS solid-state imaging elements according to an embodiment of the first embodiment. In particular, Fig. 39 shows only the arrangement of the wiring pads 157964.doc • 49· 201246520 including the connection pads 65 and 63 which electrically connect the first semiconductor wafer unit 22 and the second semiconductor wafer unit 26 to each other. In the solid-state imaging element 97 according to the seventh embodiment, as described above, the two semiconductor wafer units 22 and 26 are bonded to each other, the semiconductor portion of a portion of the first semiconductor wafer unit 22 is removed, and via the semiconductor The connection wiring 67 in the removal region 52 connects the two semiconductor wafer units 22 and 26 to each other. In the present embodiment, since a plurality of configurations of the above-described embodiments are applied to other configurations than the arrangement of the wiring connection sections, detailed description thereof will not be repeated. In the seventh embodiment, the first connection pad 65 and the second connection pad 63 are disposed in one of the vertical directions (the so-called longitudinal direction) along which the laying wirings 40d and 53d corresponding to the vertical signal lines extend. A connection pad array 98 is formed such that a plurality of connection pad pairs 99 are disposed in the horizontal direction, wherein the routing wires 40d and 53d are arranged in a plurality of stages (three stages in this example) in the vertical direction. For example, as explained in the fourth embodiment, the first connection pad 65 and the second connection pad 63 have an octagonal shape in plan view, and preferably have a regular octagonal shape. The first connection pad 65 and the second connection pad 63 are electrically connected to each other via a connection wiring 67 including a connection conductor 68, a through connection conductor 69, and a connection conductor 71. In the first semiconductor wafer unit 22, the wiring 40 of the multilayer wiring layer 41 may be formed of a plurality of layers (for example, four layers of metal M1 to M4). At this time, the first connection pad 65 is preferably formed of the first layer metal M1, and the laying wiring 40d connected to the connection pad 65 is preferably formed of the fourth layer metal M4. The embodiment of the present invention is not limited thereto, and the first connection pad 65 and the laying wiring 40d may be 157964.doc ^
S 201246520 係任一層金屬。 在第二半導體晶片單元26中，多層佈線層55之佈線53可 由複數個層（舉例而言’四層金屬Μ11至Μ14)形成。此 時’第二連接墊63較佳地由第四層金屬Ml4形成，連接至 連接墊63之敷設佈線53d較佳地由第一層金屬Mil形成。 本發明之實施例並不限於此，且第二連接塾63及敷設佈線 53d可係任一層金屬。敷設佈線4〇d及53d每三行連接至連 接墊陣列98之連接墊對99之三個級。 在根據第七實施例之固態成像元件97中，可藉由形成連 接塾陣列9 8來敷設佈線4 0 d及5 3 d，在該連接塾陣列9 8中， 連接墊對99(其中第一連接墊65及第二連接墊63係在垂直 方向上配置）係以複數個級配置》特定而言，由於即使在 連接墊65及63具有大於像素面積之面積之情形下仍可敷設 佈線40d及53d ’因而可提供具有高效能之固態成像元件。 當敷設佈線40d及53d經安置以分別跨越連接墊65及63時， 可以一充分空間擴大毗鄰敷設佈線之間的間隙。因此，可 減小在敷設佈線之間隙中出現之邮t鄰耗合電容。 在第七實施例中，即使當利用第一實施例、第二實施例 及第三實施例之連接佈線之組態時，仍可同樣地減小毗鄰 耦合電容。 在第七實施例中’可獲得與第一實施例至第三實施例之 優點相同之優點。 在上文所闡述之實例中，連接墊65及63之平面表面具有 八邊形形狀，但可具有諸如一矩形形狀或一六邊形形狀 157964.doc -51- 201246520 (較佳地一正六邊形形狀）或一圓形形狀之一多邊形形狀β 連接導體68及貫通連接導體69之剖面形狀可與連接墊65及 63之平面表面之形狀相同。連接墊65及63之平面表面之形 狀與連接導體68及貫通連接導體69之剖面形狀可彼此不 同。 在根據上文所闡述實施例之固態成像元件中，將信號電 荷設定為電子’將第一導電類型設定為ρ型，且將第二導 電類型設定為11型。信號電荷可經設定係固態成像元件中 之電洞。在此情形中’顛倒設定半導體基板及半導體井區 或半導體區之導電類型’且因此將η型設定為第一導電類 型且將ρ型設定為第二導電類型。亦可將η通道電晶體及ρ 通道電晶體應用於邏輯電路中之MOS電晶體。 9.第八實施例 半導體元件之組態實例 圖40係根據本發明之一第八實施例之一半導體元件之一 圖示。根據第八實施例之一半導體元件131包括其中一第 一半導體晶片單元101與一第二半導體晶片單元116彼此接 合之一經堆疊半導體晶片100。在第一半導體晶片單元1〇1 中形成一第一半導體積體電路及一多層佈線層。在第二半 導體晶片單元116中形成一第二半導體積體電路及一多層 佈線層。將第一半導體晶片單元101與第二半導體晶片單 元116彼此接合以使得該等多層佈線層彼此面對。在此實 例中藉由一黏合劑層129經由保護膜1 i4及i27將該等半導 體晶片單元接合。另外，可藉由電漿焊接將該等半導體晶 157964.doc •52·S 201246520 is any layer of metal. In the second semiconductor wafer unit 26, the wiring 53 of the multilayer wiring layer 55 may be formed of a plurality of layers (for example, 'four-layer metal Μ11 to Μ14'). At this time, the second connection pad 63 is preferably formed of the fourth layer metal M14, and the laying wiring 53d connected to the connection pad 63 is preferably formed of the first layer metal Mil. The embodiment of the present invention is not limited thereto, and the second connection port 63 and the laying wiring 53d may be any layer of metal. The laying wirings 4〇d and 53d are connected to the three stages of the pair of connection pads 99 of the connection pad array 98 every three rows. In the solid-state imaging element 97 according to the seventh embodiment, the wirings 40d and 5d can be laid by forming the connection array 9 8 in which the pad pair 99 is connected (the first of which The connection pad 65 and the second connection pad 63 are arranged in the vertical direction in a plurality of stages. In particular, since the connection pads 65 and 63 have an area larger than the pixel area, the wiring 40d can be laid and 53d 'Therefore, a solid-state imaging element with high performance can be provided. When the laying wirings 40d and 53d are disposed to extend across the connection pads 65 and 63, respectively, a sufficient space can be enlarged to enlarge the gap between the adjacent laying wirings. Therefore, it is possible to reduce the amount of adjacent capacitance that occurs in the gap between the laid wirings. In the seventh embodiment, even when the configurations of the connection wirings of the first embodiment, the second embodiment, and the third embodiment are utilized, the adjacent coupling capacitance can be similarly reduced. In the seventh embodiment, the same advantages as those of the first to third embodiments can be obtained. In the example set forth above, the planar surfaces of the connection pads 65 and 63 have an octagonal shape, but may have a rectangular shape or a hexagonal shape 157964.doc -51 - 201246520 (preferably a positive hexagon) One of the polygonal shapes β connecting conductor 68 and the through connecting conductor 69 may have the same cross-sectional shape as the planar surfaces of the connecting pads 65 and 63. The shape of the planar surface of the connection pads 65 and 63 and the cross-sectional shape of the connection conductor 68 and the through-connection conductor 69 may be different from each other. In the solid-state imaging element according to the embodiment explained above, the signal charge is set to electron ', the first conductivity type is set to p-type, and the second conductivity type is set to type 11. The signal charge can be set to a hole in the solid state imaging device. In this case, the semiconductor substrate and the semiconductor well region or the conductivity type of the semiconductor region are set upside down and thus the n-type is set to the first conductivity type and the p-type is set to the second conductivity type. The η channel transistor and the ρ channel transistor can also be applied to the MOS transistor in the logic circuit. 9. Eighth Embodiment Configuration Example of Semiconductor Element Fig. 40 is a view showing one of semiconductor elements according to an eighth embodiment of the present invention. The semiconductor element 131 according to the eighth embodiment includes a stacked semiconductor wafer 100 in which a first semiconductor wafer unit 101 and a second semiconductor wafer unit 116 are bonded to each other. A first semiconductor integrated circuit and a multilayer wiring layer are formed in the first semiconductor wafer unit 101. A second semiconductor integrated circuit and a multilayer wiring layer are formed in the second semiconductor wafer unit 116. The first semiconductor wafer unit 101 and the second semiconductor wafer unit 116 are bonded to each other such that the multilayer wiring layers face each other. In this embodiment, the semiconductor wafer units are bonded via a protective film 1 i4 and i27 by an adhesive layer 129. In addition, the semiconductor crystals can be soldered by plasma welding 157964.doc •52·
S 201246520 片單元彼此接合。 在本實施例中，完全移除第一半導體晶片單元1〇丨之一 部分之一半導體區段以形成半導體移除區52。在半導體移 除區52中’形成一連接佈線67以將第一 |導體晶片單元 ιοί連接至第二半導體晶片單元116。半導體移除區52係一 整個區’丨包括其中形成半導體積體電路之每__連接佈線 67之一部分且係形成於（舉例而言）第一半導體晶片單元⑺1 之周邊部分中。 在第一半導體晶片單元1〇1中，在經薄化之第一半導體 基板103中形成第一半導體積體電路（在此實例中，邏輯電 )亦即’在形成於半導體基板（舉例而言，一石夕基 板）103中之一半導體井區1〇4中形成複數個MOS電晶體S 201246520 The chip units are joined to each other. In the present embodiment, one of the semiconductor segments of one of the first semiconductor wafer units 1 is completely removed to form the semiconductor removal region 52. A connection wiring 67 is formed in the semiconductor removal region 52 to connect the first |conductor wafer unit ιοί to the second semiconductor wafer unit 116. The semiconductor removal region 52 is an integral portion 丨 including a portion of each of the connection wirings 67 in which the semiconductor integrated circuit is formed and formed in, for example, a peripheral portion of the first semiconductor wafer unit (7) 1. In the first semiconductor wafer unit 101, a first semiconductor integrated circuit (in this example, a logic electric) is formed in the thinned first semiconductor substrate 103, that is, formed on a semiconductor substrate (for example, a plurality of MOS transistors formed in one of the semiconductor well regions 103 in one of the 103 substrates
Trll、Trl2及Trl3。MOS電晶體Trll至Trl3各自包括經形 成而在其之間間置有一閘極絕緣膜之一對源極/汲極區丨〇5 及一閘極電極106。藉由一器件隔離區107來隔離MOS電晶 體Trll至 Trl3。 圖解說明代表性MOS電晶體Trll至Trl3。邏輯電路1〇2 可係藉由CMOS電晶體來形成。因此，該複數個^1〇3電晶 體可組態為η通道MOS電晶體或p通道MOS電晶體。因此， 田形成η通道MOS電晶體時，在ρ型半導體井區中形成源極/ 汲極區。當形成Ρ通道MOS電晶體時，在η型半導體井區中 形成ρ型源極/没極區。 在半導體基板103上形成一多層佈線層m，在該多層佈 線層中堆疊於其之間間置有一層間絕緣膜1〇8之複數個 157964.doc -53· 201246520 層，在此實例中，由三層金屬形成之若干佈線1〇9»佈線 109可由（舉例而言）Cu佈線形成。MOS電晶體Trll至Trl3經 由第一層佈線109及連接導體112彼此連接β此外，三層佈 線109經由連接導體彼此連接。 在第二半導體晶片單元116中，在第二半導體基板118中 形成第二半導體積體電路（在此實例中，積體電路117)。亦 即，在形成於半導體基板（舉例而言，一矽基板）118中之一 半導體井區119中形成複數個MOS電晶體Tr21、Tr22及 Tr23。MOS電晶體Tr21至Tr23各自包括經形成而在其之間 間置有一閘極絕緣膜之一對源極/汲極區丨21及一閘極電極 122。藉由一器件隔離區123來隔離MOS電晶體Tr21至 Tr23。 圖解說明代表性MOS電晶體Tr21至Tr23。邏輯電路117 可係藉由CMOS電晶體來形成。因此，該複數個MOS電晶 體可組態為η通道MOS電晶體或p通道MOS電晶體。因此， 當形成η通道MOS電晶體時，在ρ型半導體井區中形成源極/ 沒極區》當形成ρ通道MOS電晶體時，在η型半導體井區中 形成Ρ型源極/汲極區。 在半導體基板118上形成一多層佈線層126，在該多層佈 線層中堆疊於其之間間置有一層間絕緣膜124之複數個 層’在此實例中’由三層金屬形成之若干佈線丨25。佈線 I25可由（舉例而言）Cu佈線形成。MOS電晶體Tr21至Tr23 經由第一層佈線125及連接導體12〇彼此連接。此外，三層 佈線125經由連接導體120彼此連接。第二晶片單元u6之 157964d〇c -54-Trll, Tr1 and Tr3. The MOS transistors Tr11 to Tr13 each include a source/drain region 丨〇5 and a gate electrode 106 which are formed with a gate insulating film interposed therebetween. The MOS transistors Tr11 to Trl3 are isolated by a device isolation region 107. Representative MOS transistors Tr11 to Tr13 are illustrated. The logic circuit 1〇2 can be formed by a CMOS transistor. Therefore, the plurality of ^1〇3 transistors can be configured as an n-channel MOS transistor or a p-channel MOS transistor. Therefore, when the field forms an n-channel MOS transistor, a source/drain region is formed in the p-type semiconductor well region. When a germanium channel MOS transistor is formed, a p-type source/nomogram region is formed in the n-type semiconductor well region. A plurality of wiring layers m are formed on the semiconductor substrate 103, and a plurality of layers 157964.doc-53·201246520 are interposed between the multilayer wiring layers with an interlayer insulating film 1〇8, in this example, A plurality of wirings 1〇9»wiring 109 formed of three layers of metal may be formed of, for example, Cu wiring. The MOS transistors Tr11 to Tr13 are connected to each other via the first layer wiring 109 and the connection conductor 112. Further, the three-layer wiring 109 is connected to each other via a connection conductor. In the second semiconductor wafer unit 116, a second semiconductor integrated circuit (in this example, the integrated circuit 117) is formed in the second semiconductor substrate 118. That is, a plurality of MOS transistors Tr21, Tr22, and Tr23 are formed in one of the semiconductor well regions 119 formed in a semiconductor substrate (for example, a substrate) 118. The MOS transistors Tr21 to Tr23 each include a source/drain region 21 and a gate electrode 122 which are formed with a gate insulating film interposed therebetween. The MOS transistors Tr21 to Tr23 are isolated by a device isolation region 123. Representative MOS transistors Tr21 to Tr23 are illustrated. The logic circuit 117 can be formed by a CMOS transistor. Therefore, the plurality of MOS transistors can be configured as an n-channel MOS transistor or a p-channel MOS transistor. Therefore, when an n-channel MOS transistor is formed, a source/nopole region is formed in the p-type semiconductor well region. When a p-channel MOS transistor is formed, a Ρ-type source/drain is formed in the n-type semiconductor well region. Area. A plurality of wiring layers 126 are formed on the semiconductor substrate 118, and a plurality of layers in which an interlayer insulating film 124 is interposed therebetween are disposed in the multilayer wiring layer. In this example, a plurality of wiring layers formed of three layers of metal are formed. 25. The wiring I25 can be formed by, for example, a Cu wiring. The MOS transistors Tr21 to Tr23 are connected to each other via the first layer wiring 125 and the connection conductor 12A. Further, the three-layer wirings 125 are connected to each other via the connection conductors 120. 157964d〇c -54- of the second wafer unit u6
S 201246520 半導體基板118亦充當經薄化第一半導體晶片單元1〇1之一 支撐基板。 舉例而言，可代替邏輯電路1〇2，將一半導體記憶體電 路用作第一半導體積體電路。於此情形中，提供充當第二 半導體積體電路之邏輯電路117以執行半導體記憶體電路 之信號處理。 在半導體移除區52中，藉由（舉例而言）蝕刻來移除整個 第一半導體基板118。由（舉例而言）氧化矽（以〇2)膜58及氮 化石夕（SiN)膜59形成之一經堆疊絕緣膜6丨係以自半導體移 除區52之底表面及侧表面延伸至半導體基板118之表面來 形成。經堆疊之絕緣膜61保護半導體基板丨丨8之表面及朝 向半導體移除區52之側表面曝露之半導體基板118。 在半導體移除區52中，形成一連接孔64，以自氮化矽膜 59延伸至電連接至第一半導體晶片單元ι〇1中之多層佈線 層111之一佈線（在此實例中’由第三層金屬形成之敷設佈 線109d)之一第一連接墊65。此外，形成一貫通連接孔62 以穿透第一半導體晶片單元101且到達電連接至第二半導 體晶片單元116中之多層佈線層126之一佈線（在此實例 中，由第三層金屬形成之一敷設佈線125d)之第二連接墊 63 ° 連接佈線67包括隱埋於連接孔64及62中且電連接至第一 連接墊65之連接導體68、電連接至第二連接墊63之貫通連 接導體69、及電連接連接導體68之上部端與貫通連接導體 69之上部端之連接導體71。曝露於每一連接佈線67之外的 157964.doc -55- 201246520 連接導體71充當經由接合線連接至一外部佈線之一電極 塾。 可使用根據上文所闡述之第一實施例之製造方法製造根 據第八實施例之半導體元件。然而，由第一半導體積體電 路替代根據第一實施例之第一半導體晶片單元之像素陣列 及控制電路’且由第二半導體積體電路替代第二半導體晶 片單元之邏輯電路。 在根據第八實施例之半導體元件中’將第一半導體晶片 單元101與第二半導體晶片單元116彼此接合，且因此在形 成第一半導體積體電路及第二半導體積體電路中可使用最 佳處理技術。因此，由於第一半導體積體電路及第二半導 體積體電路可發揮效能，因而可提供具有高效能之半導體 元件。 特疋而5，在本貫施例中，完全移除第一半導體晶片單 元101之一部分，亦即其中形成有連接導體68及貫通連接 導體69之區之半導體區段。由於連接導體68及貫通連接導 體69係形成於半導體移除區52中，因此可減少半導體基板 1〇4與連接導體68及貫通連接導體的之間的寄生電容，藉 此提供具有較高效能之固態成像元件。 在第八實施例中，在形成晶片之前將半完成之第一半導 體基板1G4與半完成之第二半導體基板ιΐ8兩者彼此接合， 且然後將第—半導體基板1G4薄化。亦即，將第二半導體 基板118用作在薄化第一半導體基板104時之第一半導體義 板，支撑基板。因此，可節約構件且可第減；= 157964.docThe S 201246520 semiconductor substrate 118 also serves as a support substrate for thinning the first semiconductor wafer unit 101. For example, instead of the logic circuit 1〇2, a semiconductor memory circuit can be used as the first semiconductor integrated circuit. In this case, a logic circuit 117 serving as a second semiconductor integrated circuit is provided to perform signal processing of the semiconductor memory circuit. In the semiconductor removal region 52, the entire first semiconductor substrate 118 is removed by, for example, etching. One of the yttrium oxide (by 〇2) film 58 and the nitriding (SiN) film 59 is formed by stacking the insulating film 6 to extend from the bottom surface and the side surface of the semiconductor removal region 52 to the semiconductor substrate. The surface of 118 is formed. The stacked insulating film 61 protects the surface of the semiconductor substrate 8 and the semiconductor substrate 118 exposed to the side surface of the semiconductor removal region 52. In the semiconductor removal region 52, a connection hole 64 is formed to extend from the tantalum nitride film 59 to one of the plurality of wiring layers 111 electrically connected to the first semiconductor wafer unit ι1 (in this example One of the first connection pads 65 of the laying wiring 109d) formed by the third layer of metal. Further, a through connection hole 62 is formed to penetrate the first semiconductor wafer unit 101 and reach one of the plurality of wiring layers 126 electrically connected to the second semiconductor wafer unit 116 (in this example, formed of a third layer of metal) The second connection pad 63 of the laying wiring 125d) includes a connection conductor 68 buried in the connection holes 64 and 62 and electrically connected to the first connection pad 65, and a through connection electrically connected to the second connection pad 63. The conductor 69 and the upper end of the electrical connection connecting conductor 68 and the connecting conductor 71 that penetrates the upper end of the connecting conductor 69. The connection conductor 71 exposed to the outside of each of the connection wirings 67 serves as an electrode 连接 connected to one of the external wirings via a bonding wire. The semiconductor element according to the eighth embodiment can be manufactured using the manufacturing method according to the first embodiment explained above. However, the pixel array and the control circuit ' of the first semiconductor wafer unit according to the first embodiment are replaced by the first semiconductor integrated circuit and the logic circuit of the second semiconductor wafer unit is replaced by the second semiconductor integrated circuit. In the semiconductor element according to the eighth embodiment, the first semiconductor wafer unit 101 and the second semiconductor wafer unit 116 are bonded to each other, and thus the best use in forming the first semiconductor integrated circuit and the second semiconductor integrated circuit Processing technology. Therefore, since the first semiconductor integrated circuit and the second semiconductor thin body circuit can perform as a function, a semiconductor element having high performance can be provided. In particular, in the present embodiment, a portion of the first semiconductor wafer unit 101, that is, a semiconductor portion in which the connection conductor 68 and the region through the connection conductor 69 are formed, is completely removed. Since the connection conductor 68 and the through connection conductor 69 are formed in the semiconductor removal region 52, the parasitic capacitance between the semiconductor substrate 1 4 and the connection conductor 68 and the through connection conductor can be reduced, thereby providing higher performance. Solid-state imaging element. In the eighth embodiment, both the semi-finished first semiconductor substrate 1G4 and the semi-finished second semiconductor substrate ι 8 are bonded to each other before the wafer is formed, and then the first semiconductor substrate 1G4 is thinned. That is, the second semiconductor substrate 118 is used as the first semiconductor substrate when the first semiconductor substrate 104 is thinned, and the substrate is supported. Therefore, components can be saved and can be reduced; = 157964.doc
S -56· 201246520 驟。在本實施例中，由於將第一半導體基板104薄化且將 貫通連接孔62及連接孔64形成於其中移除半導體區段之半 導體移除區52中’因而減小了孔之縱橫比且可以高精度形 成連接孔62及64。因此，可以高精度製造具有高效能之固 態成像裝置。 10.第九實施例 半導體元件之組態實例 圖41係根據本發明之一第九實施例之一半導體元件之一 圖示。根據第九實施例之一半導體元件132包括其中第一 半導體晶片單元101與第二半導體晶片單元116彼此接合之 經堆疊半導體晶片100。在第一半導體晶片單元101中形成 一第一半導體積體電路及一多層佈線層。在第二半導體晶 片單元116中形成一第二半導體積體電路及一多層佈線 層。將第一半導體晶片單元1〇1與第二半導體晶片單元116 彼此接合以使得該等多層佈線層彼此面對。 在本實施例中，形成其中完全移除第一半導體晶片單元 101之一部分之半導體區段之半導體移除區52，且形成自 半導體移除區52之内表面延伸至半導體基板1〇3之後表面 之經堆疊絕緣膜61。在半導體移除區52中形成與半導體基 板103上之經堆疊絕緣膜61之表面齊平之經平坦化絕緣膜 77。經平坦化絕緣膜77之钱刻速率不同於在經堆疊絕緣膜 61之表面上之氮化矽膜59之蝕刻速率。舉例而言，經平坦 化絕緣膜77係形成為一絕緣膜，諸如氧化妙膜。 連接孔64及貝通連接孔62經形成以穿透絕緣膜77且到達 157964.doc •57· 201246520 第一連接墊65及第二連接墊63。連接第一連接墊65與第二 連接墊63之連接佈線67係穿經連接孔64及62兩者而形成。 連接佈線67包括電連接至第一連接墊65之連接導體68、電 連接至第二連接墊63之貫通連接導體69、及電連接連接導 體68之上部端與貫通連接導體69之上部端之連接導體η。 連接導體68及貫通連接導體69經形成以分別隱埋於連接孔 64及62中。連接導體68、貫通連接導體69及連接導體71係 由金屬整體地形成。連接導體71係形成於經平坦化絕緣膜 77上。 其他組態與第八實施例中所闡述之組態相同。給對應於 圖40之組成器件之組成器件賦予相同參考編號，且將不重 複對其之說明。 可使用根據上文所闡述之第二實施例之製造方法製造根 據第九實施例之半導體元件132。然而，由第一半導體積 體電路替代根據第二實施例之第一半導體晶片單元之像素 陣列及控制電路，且由第二半導體積體電路替代第二半導 體晶片單元之邏輯電路。 根據第九貫施例之固態成像元件13 2，完全移除第一半 導體晶片單元101之一部分（亦即其中形成有連接佈線67之 區之半導體區段）’且將絕緣膜77隱埋於經移除之半導體 移除區52中。由於連接導體68及貫通連接導體69係隱埋於 形成於絕緣膜77中之連接孔64及貫通連接孔62中，因而連 接導體68及69因絕緣膜77而遠離半導體基板1 〇3之側表 面《因此減少了半導體基板1〇3與連接導體68及69之間的 -58- 157964.docS -56· 201246520. In the present embodiment, since the first semiconductor substrate 104 is thinned and the through connection holes 62 and the connection holes 64 are formed in the semiconductor removal region 52 in which the semiconductor segments are removed, the aspect ratio of the holes is reduced and The connection holes 62 and 64 can be formed with high precision. Therefore, it is possible to manufacture a solid-state imaging device with high performance with high precision. 10. Ninth Embodiment Configuration Example of Semiconductor Element Fig. 41 is a view showing one of semiconductor elements according to a ninth embodiment of the present invention. The semiconductor element 132 according to the ninth embodiment includes the stacked semiconductor wafer 100 in which the first semiconductor wafer unit 101 and the second semiconductor wafer unit 116 are bonded to each other. A first semiconductor integrated circuit and a multilayer wiring layer are formed in the first semiconductor wafer unit 101. A second semiconductor integrated circuit and a multilayer wiring layer are formed in the second semiconductor wafer unit 116. The first semiconductor wafer unit 101 and the second semiconductor wafer unit 116 are bonded to each other such that the plurality of wiring layers face each other. In the present embodiment, the semiconductor removal region 52 in which the semiconductor portion of a portion of the first semiconductor wafer unit 101 is completely removed is formed and formed from the inner surface of the semiconductor removal region 52 to the surface after the semiconductor substrate 1〇3 The insulating film 61 is stacked. A planarization insulating film 77 which is flush with the surface of the stacked insulating film 61 on the semiconductor substrate 103 is formed in the semiconductor removal region 52. The etching rate of the planarized insulating film 77 is different from the etching rate of the tantalum nitride film 59 on the surface of the stacked insulating film 61. For example, the planarized insulating film 77 is formed as an insulating film such as a oxidized film. The connection hole 64 and the Beton connection hole 62 are formed to penetrate the insulating film 77 and reach the first connection pad 65 and the second connection pad 63 of 157964.doc • 57· 201246520. The connection wiring 67 connecting the first connection pad 65 and the second connection pad 63 is formed to pass through both of the connection holes 64 and 62. The connection wiring 67 includes a connection conductor 68 electrically connected to the first connection pad 65, a through connection conductor 69 electrically connected to the second connection pad 63, and a connection between the upper end of the electrical connection connection conductor 68 and the upper end of the through connection conductor 69. Conductor η. The connecting conductor 68 and the through connecting conductor 69 are formed to be buried in the connecting holes 64 and 62, respectively. The connecting conductor 68, the through connecting conductor 69, and the connecting conductor 71 are integrally formed of a metal. The connection conductor 71 is formed on the planarized insulating film 77. The other configuration is the same as that explained in the eighth embodiment. The constituent elements of the constituent devices corresponding to those of Fig. 40 are given the same reference numerals, and the description thereof will not be repeated. The semiconductor element 132 according to the ninth embodiment can be fabricated using the manufacturing method according to the second embodiment set forth above. However, the pixel array and the control circuit of the first semiconductor wafer unit according to the second embodiment are replaced by the first semiconductor integrated circuit, and the logic circuit of the second semiconductor wafer unit is replaced by the second semiconductor integrated circuit. According to the solid-state imaging element 13 2 of the ninth embodiment, a portion of the first semiconductor wafer unit 101 (that is, a semiconductor portion in which a region connecting the wiring 67 is formed) is completely removed and the insulating film 77 is buried in the via film The semiconductor removal area 52 is removed. Since the connection conductor 68 and the through-connection conductor 69 are buried in the connection hole 64 and the through-connection hole 62 formed in the insulating film 77, the connection conductors 68 and 69 are away from the side surface of the semiconductor substrate 1 〇3 by the insulating film 77. "Therefore, the -58-157964.doc between the semiconductor substrate 1〇3 and the connecting conductors 68 and 69 is reduced.
S 201246520 寄生電容。此外’半導體移除區52之内側係隱埋於絕緣膜 77中，可與經堆疊絕緣膜6丨合作以機械方式可靠地保護半 導體基板103之面對半導體移除區52之側壁之表面。因 此’可提供具有較高效能之固態成像元件。 在本實施例中，由於將第一半導體基板丨〇3薄化且形成 貫通連接孔62及連接孔64，因而減小了孔之縱橫比且可以 南精度开> 成連接孔62及64。因此’可以高精度製造具有高 效能之固態成像裝置。 雖然未作其他說明，但可獲得與第八實施例之優點相同 之優點。 11.第十實施例 半導體元件之組態實例 圖42係根據本發明之一第十實施例之一半導體、元件之一 圖示。根據第十實施例之一半導體元件133包括其中第一 半導體晶片單元101與第二半導體晶片單元116彼此接合之 經堆疊半導體晶片100。在第一半導體晶片單元1〇1中形成 一第一半導體積體電路及一多層佈線層。在第二半導體晶 片單元116中形成一第二半導體積體電路及一多層佈線 層。將第一半導體晶片單元101與第二半導體晶片單元 彼此接合以使得該等多層佈線層彼此面對。 在本實施例中，形成其中完全移除第一半導體晶片單元 101之一部分之半導體區段之半導體移除區52，且形成自 半導體移除區52之内表面延伸至半導體基板103之後表面 之經堆疊絕緣膜61。在半導體移除區52中形成與半導體基 157964.doc -59* 201246520 板103上之經堆疊絕緣膜6丨之表面齊平之經平坦化絕緣膜 77 ’且在對應於絕緣膜77之連接佈線67之一部分中形成自 表面具有一定深度之凹陷部分81。 連接孔64及貫通連接孔62經形成以穿透凹陷部分81下方 之絕緣膜77到達第一連接墊65及第二連接墊63。連接第一 連接墊65與第二連接墊63之連接佈線67係穿經連接孔64及 62兩者而形成。連接佈線67包括電連接至第一連接墊65之 連接導體68、電連接至第二連接墊63之貫通連接導體69、 及電連接連接導體68之上部端與貫通連接導體69之上部端 之連接導體71。連接導體68及貫通連接導體69經形成以分 別隱埋於連接孔64及62中。連接導體68、貫通連接導體69 及連接導體71係由金屬整體地形成。連接導體71係隱埋於 絕緣膜77之凹陷部分81中且連接導體7丨之表面經形成以與 經平坦化絕緣膜77之表面齊平。 其他組態與第八實施例中所闡述之組態相同。給對應於 圖40之組成器件之組成器件賦予相同參考編號’且將不重 複對其之說明。 可使用根據上文所闡述之第三實施例之製造方法製造根 據第十實施例之半導體元件133。然而，由第一半導體積 體電路替代根據第三實施例之第一半導體晶片單元之像素 陣列及控制電路，且由第二半導體積體電路替代第二半導 體晶片單元之邏輯電路。 根據第十實施例之固態成像元件133，完全移除第一半 導體晶片單元101之-部分（亦即其中形成有連接佈線67之 157964.docS 201246520 Parasitic capacitance. Further, the inside of the semiconductor removal region 52 is buried in the insulating film 77, and the surface of the semiconductor substrate 103 facing the sidewall of the semiconductor removal region 52 can be mechanically and reliably protected in cooperation with the stacked insulating film 6A. Therefore, a solid-state imaging element with higher performance can be provided. In the present embodiment, since the first semiconductor substrate 3 is thinned and the through-connection holes 62 and the connection holes 64 are formed, the aspect ratio of the holes is reduced and the connection holes 62 and 64 can be formed. Therefore, it is possible to manufacture a high-performance solid-state imaging device with high precision. Although not otherwise illustrated, the same advantages as those of the eighth embodiment can be obtained. 11. Tenth Embodiment Configuration Example of Semiconductor Element Fig. 42 is a view showing one of semiconductors and elements according to a tenth embodiment of the present invention. The semiconductor element 133 according to the tenth embodiment includes the stacked semiconductor wafer 100 in which the first semiconductor wafer unit 101 and the second semiconductor wafer unit 116 are bonded to each other. A first semiconductor integrated circuit and a multilayer wiring layer are formed in the first semiconductor wafer unit 101. A second semiconductor integrated circuit and a multilayer wiring layer are formed in the second semiconductor wafer unit 116. The first semiconductor wafer unit 101 and the second semiconductor wafer unit are bonded to each other such that the multilayer wiring layers face each other. In the present embodiment, the semiconductor removal region 52 in which the semiconductor portion of a portion of the first semiconductor wafer unit 101 is completely removed is formed, and is formed to extend from the inner surface of the semiconductor removal region 52 to the rear surface of the semiconductor substrate 103. The insulating film 61 is stacked. A planarization insulating film 77' which is flush with the surface of the stacked insulating film 6A on the semiconductor substrate 157964.doc-59*201246520 plate 103 and a connection wiring corresponding to the insulating film 77 is formed in the semiconductor removal region 52. A recessed portion 81 having a certain depth from the surface is formed in one of the portions 67. The connection hole 64 and the through connection hole 62 are formed to penetrate the insulating film 77 under the recessed portion 81 to reach the first connection pad 65 and the second connection pad 63. The connection wiring 67 connecting the first connection pad 65 and the second connection pad 63 is formed to pass through both of the connection holes 64 and 62. The connection wiring 67 includes a connection conductor 68 electrically connected to the first connection pad 65, a through connection conductor 69 electrically connected to the second connection pad 63, and a connection between the upper end of the electrical connection connection conductor 68 and the upper end of the through connection conductor 69. Conductor 71. The connecting conductor 68 and the through connecting conductor 69 are formed to be buried in the connecting holes 64 and 62, respectively. The connecting conductor 68, the through connecting conductor 69, and the connecting conductor 71 are integrally formed of a metal. The connecting conductor 71 is buried in the recessed portion 81 of the insulating film 77 and the surface of the connecting conductor 7 is formed to be flush with the surface of the planarizing insulating film 77. The other configuration is the same as that explained in the eighth embodiment. The constituent elements corresponding to the constituent devices of Fig. 40 are given the same reference numerals ' and will not be repeatedly described. The semiconductor element 133 according to the tenth embodiment can be manufactured using the manufacturing method according to the third embodiment set forth above. However, the pixel array and the control circuit of the first semiconductor wafer unit according to the third embodiment are replaced by the first semiconductor integrated circuit, and the logic circuit of the second semiconductor wafer unit is replaced by the second semiconductor integrated circuit. According to the solid-state imaging element 133 of the tenth embodiment, the portion of the first semiconductor wafer unit 101 is completely removed (i.e., 157964.doc in which the connection wiring 67 is formed)
S •60- 201246520 區之半導體區段），且將絕緣膜77隱埋於經移除之半導體 移除區52中。凹陷部分81係形成於絕緣膜77中，連接導體 68及貫通連接導體69係穿經形成於凹陷部分81下方之絕緣 膜77中之連接孔64及貫通連接孔62而形成，且形成連接佈 線67»因此’由於连接導體68及69因絕緣膜77而遠離半導 體基板103之側表面，因此減少了半導體基板ι〇3與連接導 體68及6、9之間的寄生電容。此外，半導體移除區52之内側 係隱埋於絕緣膜77中，可與經堆疊絕緣膜61合作以機械方 式可靠地保護半導體基板1〇3之面對半導體移除區52之侧 壁之表面。因此，可提供具有較高效能之固態成像元件。 由於連接導體71係隱埋於絕緣膜7 7之凹面部分8 1中，且 連接導體71經平坦化以與絕緣膜77之表面齊平，因此，可 形成具有較小表面步差之固態成像裝置。 在第十實施例中，薄化第一半導體基板1〇3，在絕緣膜 77中進一步形成凹面部分81 ’且形成貫通連接孔62及連接 孔64。因此’減小了孔之縱橫比且可以高精度形成連接孔 64及貫通連接孔62。因此，可以高精度製造具有高效能之 固態成像裝置。 雖然未作其他說明，但可獲得與第八實施例之優點相同 之優點。 根據上文所闡述之第八至第十實施例，將兩個半導體晶 片彼此接合。此外，根據本發明之實施例之固態成像元 件，可將二個或三個以上半導體晶片單元彼此接合。即使 在彼此接合之二個或二個以上半導體晶片單元中，仍可應 157964.doc 201246520 用上文所闡述之組態’其中完全移除在包括第一半導體積 體電路之第一半導體晶片單元與包括第二半導體積體電路 之第一半導體晶片單元之間的連接部分中之半導體區段。 可將除邏輯電路之外的一記憶體電路或另一電子電路應用 為半導體積體電路。 在上文所闡述，將第四至第七實施例中所闡述之連接墊 陣列91、91A、91B及98之佈置應用於其中完全移除在其 中形成有第一至第三實施例中所闡述之連接佈線67之區中 之半導體區段之固態成像元件。連接墊陣列9丨、9丨A、 91B及98之佈置可應用於根據第八至第十實施例之半導體 元件。連接塾陣列91、91A、91B、及98之佈置並不限於 此，而可應用於其中在接合另一晶圓或晶片且形成連接佈 線時不移除連接佈線附近之半導體之一情形。舉例而言， 連接墊陣列91、91A、91B及98之佈置適用於一固態成像 疋件或半導體積體電路（半導體元件），在該固態成像元件 或半導體積體電路中，不移除半導體區段且藉由穿透半導 體基板且隱埋其之間間置有絕緣膜之連接導體68及貫通連 接導體69來形成一連接佈線。 圖43及圖44係其中形成有連接佈線而不移除半導體區段 且應用連接墊佈置之一固態成像元件之圖示。根據本實施 例之一固態成像兀件135具有一組態，在該組態中在其中 在上文所闡述之圖16中所展示之第二實施财形成連接佈 線67之區巾*移除半導體區段。在本實施财，形成穿透 第一半導體基板31且到達第一連接墊65之連接孔64。此 157964.doc -62- 201246520 外’形成穿透包括半導體基板31之第一半導體晶片22且到 達第二連接墊63之貫通連接孔62。在連接孔64及貫通連接 孔62中之每一者之内表面上形成與半導體基板31絕緣之一 絕緣膜1 36。形成一連接佈線以使得將連接導體68及貫通 連接導體69隱埋於連接孔64及貫通連接孔62中以便分別連 接至第一連接塾65及第二連接塾63，且藉由連接導體71彼 此連接。其他組態與第二實施例之組態相同。給與圖丨6中 所展示之組成器件相同之組成器件賦予相同參考編號，且 將不重複對其之說明。 另一方面’如在圖44中所展示，在根據本實施例之固態 成像元件135中，包括連接墊63及65之佈線連接部分之佈 置具有與圖3 1中所展示之組態相同之組態。亦即，連接塾 陣列91經組態使得由八邊形連接墊6 3及6 5形成之連接塾對 89係以四個級密集地配置。其他詳細組態與參考圖3丨所闡 述之組態相同。給與圖3 1中所展示之組成器件相同之組成 器件賦予相同參考編號，且將不重複對其之說明。 在固態成像元件135中’如參考圖31所闡述，毗鄰敷設 佈線40d之間的間隙及敷設佈線53(1之間的間隙得以擴大， 藉此減小就鄰麵合電容。 圖45及圖46係其中形成有連接佈線而不移除半導體區段 且將連接墊佈置應用於一半導體積體電路之一半導體元件 之圖示。根據本實施例之一固態成像元件137具有一組 態’在該組態中在其中在上文所闡述之圖41中所展示之第 九實施例中形成連接佈線67之區中不移除半導體區段。在 157964.doc -63· 201246520 本實施例中’ Μ穿透第—半導體基板31且到達第一連接 塾65之連接孔64。此外，形成穿透包括半導體基板31之第 一半導體晶片22且到達第二連接墊63之貫通連接孔62。在 連接孔64及貫通連接孔62中之每一者之内表面上形成與半 導體基板31絕緣之-絕緣膜136 n連接佈線以使得 將連接導體68及貫通連接導體69隱埋於連接孔64及貫通連 接孔62中以便分別連接至第一連接墊65及第二連接墊〇， 且藉由連接導體71彼此連接。其他組態與第六實施例之組 態相同。給與圖41中所展示之組成器件相同之組成器件賦 予相同參考編號’且將不重複對其之說明。 另一方面，如在圖46中所展示，在本實施例中，包括連 接墊63及65之佈線連接部分之佈置具有與圖31中所展示之 組態相同之組態。亦即’連接墊陣列9丨經組態使得由八邊 形連接墊63及65形成之連接墊對89係以四個級密集地配 置。其他詳細組態與參考圖31所闡述之組態相同。給與圖 31中所展示之組成器件相同之組成器件賦予相同參考編 號，且將不重複對其之說明。 在固態成像元件13 7中，如參考圖3 1所闡述，毗鄰敷設 佈線40d之間的間隙及敷設佈線53d之間的間隙得以擴大， 藉此減小毗鄰耦合電容》 在其中形成有連接佈線而不移除包括一積體電路之半導 體區段及一半導體元件之一固態成像元件中，可將第五實 施例（圖36)、第六實施例（圖37及圖38)、第七實施例（圖39) 或諸如此類之佈置應用於連接塾之佈置。 157964.doc -64·The semiconductor portion of the S 60-201246520 region is buried in the removed semiconductor removal region 52. The recessed portion 81 is formed in the insulating film 77, and the connection conductor 68 and the through-connection conductor 69 are formed through the connection hole 64 and the through-connection hole 62 formed in the insulating film 77 under the recessed portion 81, and the connection wiring 67 is formed. Therefore, since the connection conductors 68 and 69 are away from the side surface of the semiconductor substrate 103 by the insulating film 77, the parasitic capacitance between the semiconductor substrate 10 and the connection conductors 68 and 6, 9 is reduced. Further, the inner side of the semiconductor removal region 52 is buried in the insulating film 77, and the surface of the side surface of the semiconductor removal region 52 facing the semiconductor removal region 52 can be mechanically and reliably protected in cooperation with the stacked insulating film 61. . Therefore, a solid-state imaging element having higher performance can be provided. Since the connection conductor 71 is buried in the concave portion 81 of the insulating film 77, and the connection conductor 71 is planarized to be flush with the surface of the insulating film 77, a solid-state imaging device having a small surface step can be formed. . In the tenth embodiment, the first semiconductor substrate 1?3 is thinned, and the concave portion 81' is further formed in the insulating film 77 and the through-connection hole 62 and the connection hole 64 are formed. Therefore, the aspect ratio of the hole is reduced and the connection hole 64 and the through connection hole 62 can be formed with high precision. Therefore, it is possible to manufacture a high-performance solid-state imaging device with high precision. Although not otherwise illustrated, the same advantages as those of the eighth embodiment can be obtained. According to the eighth to tenth embodiments explained above, the two semiconductor wafers are bonded to each other. Furthermore, according to the solid-state imaging element of the embodiment of the present invention, two or more semiconductor wafer units can be bonded to each other. Even in the case of two or more semiconductor wafer units bonded to each other, the configuration described above can be used 157964.doc 201246520, in which the first semiconductor wafer unit including the first semiconductor integrated circuit is completely removed. a semiconductor segment in a connection portion with a first semiconductor wafer unit including a second semiconductor integrated circuit. A memory circuit other than the logic circuit or another electronic circuit can be applied as the semiconductor integrated circuit. As explained above, the arrangement of the connection pad arrays 91, 91A, 91B, and 98 set forth in the fourth to seventh embodiments is applied to the case where the complete removal is formed therein in which the first to third embodiments are formed. A solid-state imaging element that connects the semiconductor segments in the region of the wiring 67. The arrangement of the connection pad arrays 9A, 9A, 91B, and 98 can be applied to the semiconductor elements according to the eighth to tenth embodiments. The arrangement of the connection stacks 91, 91A, 91B, and 98 is not limited thereto, but can be applied to a case where the semiconductor in the vicinity of the connection wiring is not removed when another wafer or wafer is bonded and the connection wiring is formed. For example, the arrangement of the connection pad arrays 91, 91A, 91B, and 98 is suitable for a solid-state imaging element or a semiconductor integrated circuit (semiconductor element) in which the semiconductor region is not removed. A connection wiring is formed by penetrating the semiconductor substrate and burying the connection conductor 68 and the through connection conductor 69 with the insulating film interposed therebetween. 43 and 44 are diagrams showing a solid-state imaging element in which a connection wiring is formed without removing a semiconductor segment and a connection pad arrangement is applied. The solid-state imaging element 135 according to one embodiment of the present embodiment has a configuration in which the second implementation shown in FIG. 16 set forth above forms a region* of the connection wiring 67. Section. In the present embodiment, the connection hole 64 penetrating the first semiconductor substrate 31 and reaching the first connection pad 65 is formed. The 157964.doc -62-201246520 outer portion forms a through-connection hole 62 that penetrates the first semiconductor wafer 22 including the semiconductor substrate 31 and reaches the second connection pad 63. An insulating film 136 which is insulated from the semiconductor substrate 31 is formed on the inner surface of each of the connection hole 64 and the through connection hole 62. A connection wiring is formed such that the connection conductor 68 and the through connection conductor 69 are buried in the connection hole 64 and the through connection hole 62 to be respectively connected to the first connection port 65 and the second connection port 63, and are connected to each other by the connection conductor 71 connection. The other configuration is the same as that of the second embodiment. The same component numbers as those of the constituent devices shown in Fig. 6 are given the same reference numerals, and the description thereof will not be repeated. On the other hand, as shown in Fig. 44, in the solid-state imaging element 135 according to the present embodiment, the arrangement of the wiring connection portions including the connection pads 63 and 65 has the same configuration as that shown in Fig. 31. state. That is, the connection port array 91 is configured such that the connection pairs 89 formed by the octagonal connection pads 6 3 and 6 are densely arranged in four stages. The other detailed configuration is the same as the configuration described with reference to Figure 3丨. The same components as those shown in Fig. 31 are given the same reference numerals, and the description thereof will not be repeated. In the solid-state imaging element 135', as explained with reference to Fig. 31, the gap between the adjacent laying wirings 40d and the laying wiring 53 (the gap between the ones is enlarged, thereby reducing the adjacent surface capacitance. Fig. 45 and Fig. 46 A diagram in which a connection wiring is formed without removing a semiconductor section and a connection pad arrangement is applied to one semiconductor element of a semiconductor integrated circuit. According to the present embodiment, the solid state imaging element 137 has a configuration 'in the In the configuration, the semiconductor segment is not removed in the region in which the connection wiring 67 is formed in the ninth embodiment shown in Fig. 41 explained above. In 157964.doc -63· 201246520 In the present embodiment, 'Μ The through-semiconductor substrate 31 is penetrated and reaches the connection hole 64 of the first connection port 65. Further, a through-connection hole 62 penetrating through the first semiconductor wafer 22 including the semiconductor substrate 31 and reaching the second connection pad 63 is formed. An insulating film 136 n that is insulated from the semiconductor substrate 31 is formed on the inner surface of each of the 64 and the through-connection holes 62 to connect the wiring so that the connection conductor 68 and the through-connection conductor 69 are buried in the connection hole 64 and the through-connection 62 is connected to the first connection pad 65 and the second connection pad respectively, and is connected to each other by the connection conductor 71. Other configurations are the same as those of the sixth embodiment. The components shown in Fig. 41 are given. The same constituent elements are given the same reference numerals 'and their description will not be repeated. On the other hand, as shown in Fig. 46, in the present embodiment, the arrangement of the wiring connecting portions including the connection pads 63 and 65 has and The configuration shown in Fig. 31 is the same. That is, the 'connecting pad array 9' is configured such that the connecting pad pairs 89 formed by the octagonal connecting pads 63 and 65 are densely arranged in four stages. The detailed configuration is the same as that explained with reference to Fig. 31. The same constituent elements as those of the constituent devices shown in Fig. 31 are given the same reference numerals, and the description thereof will not be repeated. In the solid-state imaging element 137, As explained with reference to FIG. 31, the gap between the adjacent laying wirings 40d and the gap between the laying wirings 53d is enlarged, thereby reducing the adjacent coupling capacitance" in which the connection wiring is formed without removing the integrated circuit including In the semiconductor segment and one of the solid-state imaging elements of a semiconductor element, the fifth embodiment (FIG. 36), the sixth embodiment (FIG. 37 and FIG. 38), the seventh embodiment (FIG. 39), or the like may be applied. Arranged in the connection. 157964.doc -64·
S 201246520 在上文所闡述之根據該等實施例之固態成像元件中，需 要使其中形成第一半導體晶片單元22之像素陣列23之半導 體基板或半導體井區之電位穩定。亦即，需要即使當使貫 通連接導體69及連接導體68之電位變化時仍使在貫通連接 導體69及連接導體68附近之半導體基板或半導體井區之電 位（所謂之基板電位）穩定。為使基板電位穩定，在此實例 中，藉由一雜質擴散層在半導體井區32中形成一觸點單 元。該觸點單元經由連接導體44及佈線4〇連接至形成於第 一半導體晶片單元22附近之一電極墊單元。藉由將（舉例 而言）一電源電壓VDD或接地電壓（0 v)供應至該電極墊單 元來經由該觸點單元將一電源電壓或一接地電壓（〇 v)施加 至半導體井區32。因此，使半導體井區之基板電位穩定。 舉例而言，當半導體基板或半導體井區係一 n型時，供應 電源電壓。當半導體基板或半導體井區係一ρ型時，供應 接地電壓。 在上文所闡述之根據該等實施例之固態成像元件中，安 裝一保護二極體以使得當處理由貫通連接導體69及連接導 體68形成之連接佈線67時邏輯電路中之電晶體不受到電漿 損壞。㈣成連接佈線67時，藉由電衆蝕刻形成到達墊Μ 及65之連接孔62及65。然而，在該電漿處理中將過量電漿 離子充電至（尤其）邏輯電路中之連接塾63。當所充電之過 量電離子經由佈線53施加至輯電路中之電晶體時，該等 電晶體受到所謂之電漿損壞。使用保護二極體來防止電毁 損壞。 157964.doc -65· 201246520 在本實施例中’在形成行信號處理電路5之每—行電路 單元之每-邏輯電路中形成保護二極體。如上文所閣述， 對應於每一垂直信號線之敷設佈線經由連接墊63及65中之 每者連接至每一連接佈線67之貫通連接導體69及連接導 體68。在第二半導體晶片單元26中，針對其中形成有行電 路單元之MOS電晶體之半導體基板45中之每一行電路單元 形成保護二極體。每一保護二極體連接至行電路單元之 MOS電晶體之閘極電極所連接至之同一敷設佈線。連接至 敷設佈線之保護二極體係自行電路單元之M〇s電晶體靠近 連接墊63來安裝。在電漿處理中，已充電於邏輯電路中之 連接墊單元63中之過量電漿離子之電荷流至保護二極體而 不在該行電路單元中造成損壞。因此，可在連接佈線67之 處理中防止對行電路單元之電漿損壞。此外，可提供相同 保護二極體以不僅防止對行電路單元之電漿損壞且亦防止 對形成另一周邊電路之MOS電晶體之電漿損壞。 將參考圖47之示意圖闡述一特定實例。此處，將該實例 應用於其中在其中圖43中所展示之上文所闡述之連接佈線 67之區中不移除半導體區段之固態成像元件135中。在此 實例中’第一半導體晶片單元22與第二半導體晶片單元26 經由連接佈線67彼此電連接。在第一半導體晶片單元22 中’連接佈線67之連接導體68穿透第一半導體基板31且連 接至由多層佈線層41之第一層金屬Ml形成之第一連接墊 65。第一連接塾65經由第一層金屬Ml之一擴展部分65 a、 一導通導體88、第二層金屬M2、一導通導體88、第三層 157964.doc •66· 201246520 金屬M3及一導通導體88連接至由第四層金屬M4形成之敷 設佈線40d。敷設佈線40d對應於垂直信號線，如上文所闊 述0 在第二半導體晶片單元26中’連接佈線67之連接導體69 穿透第一半導體基板22且連接至由多層佈線層55之第四層 金屬M14形成之第二連接墊63。第二連接墊63經由一導通 導體88、第三層金屬M13、一導通導體88、第二層金屬 M12及一導通導體88連接至由第一層金屬Mil形成之敷設 佈線53d。敷設佈線53d對應於垂直信號線，如上文所闡 述。 連接墊65及63較佳地由（舉例而言）一 Ai膜形成。使用A1 膜之原因如下。亦即’藉由使用一 CF氣體之電漿蝕刻來形 成分別隱埋連接導體68及貫通連接導體69之連接孔64及貫 通連接孔62。由於該電漿處理係過蝕刻的且連接墊65及63 曝露至該電漿’因而作為一 Cu膜而可不被移除之一反應物 附接至連接塾65及63之表面《可不令人滿意地實現因反應 物所致的Cu而在連接墊65及63與連接導體68及貫通連接導 體69之間的電連接。然而，在A1膜之情形中，由於反應物 不附接’因而可令人滿意地實現連接墊65及63與連接導體 68及貫通連接導體69之間的電連接。 在A1膜之情形中，提供在A1膜上具有一 Ti膜或一 TiN膜 之一膜組態。除連接墊65之金屬Ml之外的一金屬（M2至 M4)及除連接墊6；3之金屬Ml4之外的金屬（Ml3至Mil)係由 一 Cu膜形成。 157964.doc 67· 201246520 舉例而言，如下文所闡述，當連接佈線67安置於一比較 器與一計算迴路之間時，將以高速運作形成一計算迴路之 一 MOS電晶體連接至垂直信號線。M〇s電晶體係由高速運 作之南速電晶體7>21形成。高速電晶體Tr21亦稱作一最小 電BB體且閘極絕緣膜係薄的。因此，高速電晶體1連接 至充當第二半導體晶片26中之垂直信號線之敷設佈線 53d。 在電漿處理中’過量電流經由連接墊63流至敷設佈線 53d，且形成計算迴路之高速電晶體Tr21之閘極絕緣膜可 被損毁’亦即被損壞。因此’將具有一 pn接面之一保護二 極體D21連接至靠近連接墊63之敷設佈線53d之區而非高速 電晶體Tr21。即使當在電漿處理中過量電流流至敷設佈線 53d，過量電流亦可經由保護二極體〇21流向基板，且可藉 由保護二極體D21防止對高速電晶體Tr21之損壞。 在上文所闡述之第六實施例（參見圖38)中，藉由在第一 連接墊65與具有不同電位且緊在第一連接墊65下方跨越之 敷设佈線（垂直彳§號線）4 0 d之間安置屏蔽佈線9 6來防止出現 毗鄰耦合電容。雖然未圖解說明，但藉由在第二連接墊·63 與具有不同電位且緊在第二連接墊63下方跨越之敷設佈線 (垂直信號線）53d之間安置屏蔽佈線來防止出現Β比鄰麵合電 容。 在上文所闡述之固態成像元件中，對於第一半導體晶片 單元22及第二半導體晶片單元26，較佳地電屏蔽毗鄰敷設 佈線之間的間隙及毗鄰之敷設佈線與連接導體或貫通連接 157964.doc ·68·S 201246520 In the solid-state imaging element according to the embodiments described above, it is necessary to stabilize the potential of the semiconductor substrate or the semiconductor well region in which the pixel array 23 of the first semiconductor wafer unit 22 is formed. That is, it is necessary to stabilize the potential (so-called substrate potential) of the semiconductor substrate or the semiconductor well region in the vicinity of the through-connection conductor 69 and the connection conductor 68 even when the potentials of the through-connection conductor 69 and the connection conductor 68 are changed. In order to stabilize the substrate potential, in this example, a contact unit is formed in the semiconductor well region 32 by an impurity diffusion layer. The contact unit is connected to one of the electrode pad units formed in the vicinity of the first semiconductor wafer unit 22 via the connection conductor 44 and the wiring 4'. A power supply voltage or a ground voltage (?v) is applied to the semiconductor well region 32 via the contact unit by supplying, for example, a power supply voltage VDD or a ground voltage (0v) to the electrode pad unit. Therefore, the substrate potential of the semiconductor well region is stabilized. For example, when the semiconductor substrate or semiconductor well is an n-type, the supply voltage is supplied. When the semiconductor substrate or the semiconductor well region is of a p-type, a ground voltage is supplied. In the solid-state imaging element according to the embodiments described above, a protective diode is mounted such that the transistor in the logic circuit is not subjected to the processing of the connection wiring 67 formed by the through-connection conductor 69 and the connection conductor 68. The plasma is damaged. (4) When the wiring 67 is connected, the connection holes 62 and 65 reaching the pads 65 65 are formed by the plasma etching. However, excess plasma ions are charged to the port 63 in the logic circuit, particularly in the plasma process. When the charged excess ions are applied to the transistors in the circuit via the wiring 53, the transistors are damaged by the so-called plasma. Use a protective diode to prevent damage from electrical damage. 157964.doc -65· 201246520 In the present embodiment, a protection diode is formed in each of the logic circuits of each of the row circuit units forming the row signal processing circuit 5. As described above, the laying wiring corresponding to each vertical signal line is connected to the through-connecting conductor 69 and the connecting conductor 68 of each of the connecting wirings 67 via each of the connection pads 63 and 65. In the second semiconductor wafer unit 26, a protective diode is formed for each of the row of circuit cells 45 of the MOS transistor in which the row circuit unit is formed. Each of the protective diodes is connected to the same routing wiring to which the gate electrode of the MOS transistor of the row circuit unit is connected. The M〇s transistor connected to the self-circuit unit of the protective diode system of the laying wiring is mounted close to the connection pad 63. In the plasma processing, the charge of the excess plasma ions that has been charged in the connection pad unit 63 in the logic circuit flows to the protection diode without causing damage in the row circuit unit. Therefore, plasma damage to the row circuit unit can be prevented in the process of connecting the wiring 67. In addition, the same protective diode can be provided to not only prevent plasma damage to the row circuit unit but also prevent plasma damage to the MOS transistor forming another peripheral circuit. A specific example will be explained with reference to the schematic diagram of FIG. Here, the example is applied to the solid-state imaging element 135 in which the semiconductor section is not removed in the region of the connection wiring 67 explained above in Fig. 43. In this example, the first semiconductor wafer unit 22 and the second semiconductor wafer unit 26 are electrically connected to each other via the connection wiring 67. The connection conductor 68 of the connection wiring 67 in the first semiconductor wafer unit 22 penetrates the first semiconductor substrate 31 and is connected to the first connection pad 65 formed of the first layer metal M1 of the multilayer wiring layer 41. The first connection port 65 extends through a portion 65a of the first layer of metal M1, a conduction conductor 88, a second layer of metal M2, a conduction conductor 88, a third layer 157964.doc • 66· 201246520 metal M3 and a conduction conductor 88 is connected to the laying wiring 40d formed of the fourth layer metal M4. The laying wiring 40d corresponds to a vertical signal line, as described above. In the second semiconductor wafer unit 26, the connecting conductor 69 of the connecting wiring 67 penetrates the first semiconductor substrate 22 and is connected to the fourth layer of the multilayer wiring layer 55. The metal M14 forms a second connection pad 63. The second connection pad 63 is connected to the laying wiring 53d formed of the first layer metal Mil via a conduction conductor 88, a third layer metal M13, a conduction conductor 88, a second layer metal M12, and a conduction conductor 88. The laying wiring 53d corresponds to a vertical signal line as explained above. The connection pads 65 and 63 are preferably formed of, for example, an Ai film. The reason for using the A1 film is as follows. That is, the connection hole 64 and the through-connection hole 62 which respectively bury the connection conductor 68 and the through-connection conductor 69 are formed by plasma etching using a CF gas. Since the plasma treatment is over-etched and the connection pads 65 and 63 are exposed to the plasma 'so as a Cu film, one of the reactants may not be removed to the surface of the ports 65 and 63. The electrical connection between the connection pads 65 and 63 and the connection conductor 68 and the through connection conductor 69 is achieved by Cu due to the reactant. However, in the case of the A1 film, the electrical connection between the connection pads 65 and 63 and the connection conductor 68 and the through connection conductor 69 can be satisfactorily achieved because the reactants are not attached. In the case of the A1 film, a film configuration having a Ti film or a TiN film on the A1 film is provided. A metal (M2 to M4) other than the metal M1 of the connection pad 65 and a metal (Ml3 to Mil) other than the metal M14 of the connection pad 6; 3 are formed of a Cu film. 157964.doc 67· 201246520 For example, as explained below, when the connection wiring 67 is disposed between a comparator and a calculation loop, one of the calculation loops is formed at a high speed to form a MOS transistor connected to the vertical signal line. . The M〇s electro-crystalline system is formed by a high-speed operation of a south-speed transistor 7>21. The high speed transistor Tr21 is also referred to as a minimum electric BB body and the gate insulating film is thin. Therefore, the high speed transistor 1 is connected to the laying wiring 53d serving as a vertical signal line in the second semiconductor wafer 26. In the plasma processing, an excessive current flows to the laying wiring 53d via the connection pad 63, and the gate insulating film of the high-speed transistor Tr21 forming the calculation loop can be damaged', i.e., damaged. Therefore, one of the protective diodes D21 having one pn junction is connected to the region of the laying wiring 53d close to the connection pad 63 instead of the high speed transistor Tr21. Even when excessive current flows to the laying wiring 53d in the plasma processing, excess current can flow to the substrate via the protective diode 21, and damage to the high-speed transistor Tr21 can be prevented by the protective diode D21. In the sixth embodiment (see FIG. 38) set forth above, by laying the wiring (vertical 彳 线 line) 4 at the first connection pad 65 with a different potential and immediately below the first connection pad 65 A shield wiring 9 6 is placed between 0 d to prevent adjacent coupling capacitance from occurring. Although not illustrated, the placement of the shield wiring is prevented by placing the shield wiring between the second connection pad 63 and the laying wiring (vertical signal line) 53d having a different potential and immediately below the second connection pad 63. capacitance. In the solid-state imaging device described above, for the first semiconductor wafer unit 22 and the second semiconductor wafer unit 26, it is preferable to electrically shield the gap between the adjacent laying wirings and the adjacent laying wiring and the connecting conductor or the through connection 157964. .doc ·68·
S 201246520 導體之間的間隙。此外，根據連接墊對之配置，較佳地電 磁屏蔽彼此毗鄰之連接導體與貫通連接導體之間的間隙、 田比鄰連接導體之間的間隙及毗鄰貫通連接導體之間的間 隙。在此情形中’可使用多層佈線層之該等層之金屬佈線 來配置對應屏蔽佈線。 雖然未圖解說明，但屏蔽佈線係藉由介於毗鄰敷設佈線 之間的、在與敷設佈線相同的層中的或在敷設佈線附近的 其他層金屬來配置。將接地電位施加至屏蔽佈線。因此， 可減小毗鄰敷設佈線之間的毗鄰耦合電容。 當連接塾及敷設佈線係由同一層之金屬形成時，藉由介 於®比鄰之連接導體68與敷設佈線4〇d之間的、在與敷設佈 線40d相同之層中的或在佈線4〇d附近的其他層之金屬來配 置屏蔽佈線。此外，藉由介於毗鄰之貫通連接導體69與敷 設佈線53d之間的、在與佈線53(1相同之層中的或在佈線 53d附近的其他層之金屬來配置屏蔽佈線。將接地電位施 加至屏蔽佈線。因此，可減小础鄰之敷設佈線4如與連接 導體68之間的及在毗鄰之敷設佈線53d與貫通連接導體的 之間的®比鄰耦合電容。 在其中形成有複數個連接佈線67之連接佈線區中，可藉 由形成一導電型半導體雜質區以圍繞其之間間置有一絕緣 膜之貫通連接導體及連接導體來減小該毗鄰耦合電容。亦 即，可減小毗鄰之貫通連接導體與連接導體之間的、毗鄰 貫通連接導體之間的或毗鄰連接導體之間的毗鄰耦合電 容。圖48及圖49(沿圖49之線ΧΧΧΧΙΧ-ΧΧΧΧΙΧ截取之剖 157964.doc -69- 201246520 面圖）係該實例之示意性圖示。在此實例中，使用圖43中 之固態成像元件135。 在圖48及圖49中，連接墊對89係與圖37中所展示相反地 交替配置。在連接佈線區中，一 P型半導體區151形成於圍 繞半導體基板31之連接導體68及貫通連接導體69之一區中 且將P型半導體區151接地。p型半導體區151藉由絕緣膜 136與連接導體68及貫通連接導體69電隔離。在此組態 中，經接地之p型半導體區151充當一屏蔽層，且因此可減 小毗鄰之連接導體68與貫通連接導體69之間的毗鄰耦合電 容。當將一雜質擴散層（亦即一 p型半導體區）用作隔離各別 像素之光電一極體PD之器件隔離區時，可同時以器件隔離 區之P型半導體區來形成P型半導體區151。 當將經接地p型半導體區151用作屏蔽層時，接地電容趨 於增加。藉由控制絕緣膜136之一膜厚度u來抑制接地電 谷。可將s亥膜厚度tl設定為在自50 nm至300 nm之範圍 中，舉例而言可設定為約1 〇〇 nm。膜厚度11越大，接地電 容[fF]越小。然而，當膜厚度u等於或大於3〇〇 nm時接 地電容幾乎不變化。 在圖39中所展示之連接墊對99之配置中，如在圖的中， 連接導體68與貫通連接導體69在垂直方向上彼此毗鄰地配 置。如在圆5 0中，連接導體6 8在橫向方向上彼此毗鄰地配 置，且如在圖51中，貫通連接導體69在橫向方向上彼此毗 鄰地配置。在圖50及圖51中，給與圖49之組成器件相同之 組成器件賦予相同參考編號且將不重複對其之說明。 157964.doc •70- 201246520 雖然未圖解說明，但在p型半導體區151中形成由一雜質 擴散層形成之一觸點單元（基板觸點單元）以使在連接導體 68及貫通連接導體69附近之p型半導體區151之電位（亦即 所謂之基板電位）穩定。觸點單元經形成以圍繞對應於複 數個連接墊陣列之連接佈線區且可連接至第一半導體晶片 單元22上之電極墊。藉由將接地電壓（〇 v)供應至電極墊， 可使連接導體68及貫通連接導體69附近之p型半導體區ι51 之基板電位穩定。 第一半導體晶片單元22之半導體基板31係藉由設定 半導體基板作為一開始材料來形成。第二半導體晶片單元 26之半導體基板45係藉由設定p型半導體基板作為一開始 材料來形成。當圖2B中所展示之控制電路24及像素陣列23 係形成於帛|導體晶片單元22中時’在像素陣列η之p 型半導體井區與控制電路以之㈣半導體井區之間存在η型 基板因此’在第—半導體晶片單元22中，將用於使對應 電位穩疋之電壓自該等電極墊經由基板觸點單元供應至ρ 型半導體井區、η型半導體基板、ρ型半導體區ΐ5ι。在第 半導體單⑦26巾，將用於使對應f位穩定之電壓經 由各別基板觸點單元供應至p型半導體基板及其中形成有p 通道MOS電晶體之n型半導體井區。 當第-半導體晶片單元22及第二半導體晶片單元％中之 基板觸點單元皆連接至（舉例而言）第—半導體晶片單元Μ 表面之電極墊時’㈣單獨之貫通連接導體、連接導體 及一層之金屬佈線來實現連接。 157964.doc •71- 201246520 當第一半導體晶片單元22及第二半導體晶片單元26中之 基板觸點單元皆連接至（舉例而言）第二半導體晶片單元26 之表面之電極墊時，經由單獨之貫通連接導體、連接導體 及一層之金屬佈線來實現連接。 接下來，將闡述在固態成像元件之一電路上由上文所闡 述之連接導體68及貫通連接導體69形成之連接佈線67之一 ***部分。圖52係該固態成像元件之主要單元之一示意 圖。如上文所闡述，該固態成像元件包括其中以一矩陣形 式配置複數個像素2之像素陣列3。行信號處理電路5連接 至對應於每一像素2行之垂直信號線行信號處理電路5 包括一行ADC單元13。行ADC單元13自轉換開始隨時間將 一類比信號轉換成一數位信號以判定一參考電壓（燈電壓） 與欲被處理之一信號電壓相同。原則上，行ADC單元13包 括一比較器（電壓比較器）14及一計算迴路15。行ADC單元 13將燈電壓供應至比較器14且用供應至計算迴路15之一參 考信號開始計算。藉由比較經由垂直信號線9輸入之一類 比影像信號，行ADC單元13執行AD轉換直至可獲得一脈 衝信號。 在本實施例中，連接佈線67係安置於圖52中之比較器14 與計算迴路15之間的一位置（1)處。在此情形中，比較器j 4 之電路組態係由像素陣列3及第一半導體晶片單元22來形 成。第二半導體晶片單元26具有在計算迴路15之後的一電 路組態。控制電路可形成於第一半導體晶片單元22或第二 半導體晶片單元26中。第一半導體晶片單元22及第二半導 157964.doc -72-S 201246520 The gap between the conductors. Further, depending on the arrangement of the connection pads, it is preferable to electromagnetically shield the gap between the connection conductor and the through-connection conductor adjacent to each other, the gap between the adjacent connection conductors, and the gap between the adjacent connection conductors. In this case, the corresponding shield wiring can be configured using the metal wiring of the layers of the multilayer wiring layer. Although not illustrated, the shield wiring is disposed by other layer metals interposed between adjacent laying wirings in the same layer as the laying wiring or in the vicinity of the laying wiring. Apply the ground potential to the shield wiring. Therefore, the adjacent coupling capacitance between adjacent laying wirings can be reduced. When the connection port and the laying wiring are formed of the same layer of metal, by the connection between the adjacent connection conductor 68 and the laying wiring 4〇d, in the same layer as the laying wiring 40d or in the wiring 4〇d The shielded wiring is configured with metal of other layers nearby. Further, the shield wiring is disposed by a metal interposed between the adjacent through-connection conductor 69 and the laying wiring 53d in the same layer as the wiring 53 (or in the vicinity of the wiring 53d). The ground potential is applied to The wiring is shielded. Therefore, the adjacent coupling capacitor between the adjacent wiring 4 such as the connecting conductor 68 and the adjacent routing wiring 53d and the through connecting conductor can be reduced. A plurality of connecting wirings are formed therein. In the connection wiring region of 67, the adjacent coupling capacitance can be reduced by forming a conductive semiconductor impurity region to surround the through-connecting conductor and the connecting conductor with an insulating film interposed therebetween. Adjacent coupling capacitance between the connecting conductor and the connecting conductor adjacent to or between adjacent connecting conductors. Figure 48 and Figure 49 (taken along line ΧΧΧΧΙΧ-ΧΧΧΧΙΧ of Figure 49, section 157964.doc -69 - 201246520 (a) is a schematic illustration of this example. In this example, the solid state imaging element 135 of Figure 43 is used. In Figures 48 and 49, the connection pad pair 89 and Figure 3 The arrangement is reversed alternately shown in 7. In the connection wiring region, a P-type semiconductor region 151 is formed in a region surrounding the connection conductor 68 and the through-connection conductor 69 of the semiconductor substrate 31 and grounds the P-type semiconductor region 151. The type semiconductor region 151 is electrically isolated from the connection conductor 68 and the through connection conductor 69 by the insulating film 136. In this configuration, the grounded p-type semiconductor region 151 acts as a shield layer, and thus the adjacent connection conductor 68 can be reduced. Adjacent coupling capacitance between the through-connection conductor 69. When an impurity diffusion layer (i.e., a p-type semiconductor region) is used as a device isolation region for isolating the photodiode PD of each pixel, the device isolation can be simultaneously performed. The P-type semiconductor region of the region forms a P-type semiconductor region 151. When the grounded p-type semiconductor region 151 is used as a shield layer, the ground capacitance tends to increase. The grounding voltage is suppressed by controlling the film thickness u of the insulating film 136. The thickness tl of the film can be set to be in the range from 50 nm to 300 nm, for example, about 1 〇〇 nm. The larger the film thickness 11, the smaller the ground capacitance [fF]. When the film thickness u is equal to or The grounding capacitance hardly changes at 3 〇〇 nm. In the configuration of the connection pad pair 99 shown in Fig. 39, as in the figure, the connection conductor 68 and the through-connection conductor 69 are arranged adjacent to each other in the vertical direction. As in the circle 50, the connection conductors 68 are disposed adjacent to each other in the lateral direction, and as in Fig. 51, the through-connection conductors 69 are disposed adjacent to each other in the lateral direction. In Figs. 50 and 51, The constituent elements of the same components of Fig. 49 are given the same reference numerals and will not be repeatedly described. 157964.doc • 70-201246520 Although not illustrated, a p-type semiconductor region 151 is formed by an impurity diffusion layer. A contact unit (substrate contact unit) stabilizes the potential (i.e., the so-called substrate potential) of the p-type semiconductor region 151 in the vicinity of the connection conductor 68 and the through-connection conductor 69. The contact unit is formed to surround the electrode pad corresponding to the connection wiring region of the plurality of connection pad arrays and connectable to the first semiconductor wafer unit 22. By supplying the ground voltage (?v) to the electrode pad, the substrate potential of the p-type semiconductor region ι51 in the vicinity of the connection conductor 68 and the through-connection conductor 69 can be stabilized. The semiconductor substrate 31 of the first semiconductor wafer unit 22 is formed by setting a semiconductor substrate as a starting material. The semiconductor substrate 45 of the second semiconductor wafer unit 26 is formed by setting a p-type semiconductor substrate as a starting material. When the control circuit 24 and the pixel array 23 shown in FIG. 2B are formed in the 帛|conductor wafer unit 22, there is an n-type between the p-type semiconductor well region of the pixel array η and the control circuit (4) semiconductor well region. The substrate is thus 'in the first semiconductor wafer unit 22, a voltage for stabilizing the corresponding potential is supplied from the electrode pads via the substrate contact unit to the p-type semiconductor well region, the n-type semiconductor substrate, the p-type semiconductor region ΐ5ι . In the first semiconductor sheet 726, a voltage for stabilizing the corresponding f-bit is supplied to the p-type semiconductor substrate and the n-type semiconductor well region in which the p-channel MOS transistor is formed via the respective substrate contact unit. When the substrate contact units of the first semiconductor wafer unit 22 and the second semiconductor wafer unit % are both connected to, for example, the electrode pads of the first semiconductor wafer unit Μ surface, (4) separate through-connection conductors, connection conductors, and A layer of metal wiring is used to make the connection. 157964.doc • 71- 201246520 When the substrate contact units in the first semiconductor wafer unit 22 and the second semiconductor wafer unit 26 are both connected to, for example, the electrode pads on the surface of the second semiconductor wafer unit 26, via separate The connection is made through the connecting conductor, the connecting conductor and the metal wiring of one layer. Next, an insertion portion of the connection wiring 67 formed by the connection conductor 68 and the through-connection conductor 69 explained above on one of the circuits of the solid-state imaging element will be explained. Figure 52 is a schematic view of one of the main units of the solid-state imaging element. As explained above, the solid-state imaging element includes the pixel array 3 in which a plurality of pixels 2 are arranged in a matrix form. The row signal processing circuit 5 is connected to the vertical signal line corresponding to 2 rows of each pixel. The signal processing circuit 5 includes a row of ADC units 13. The row ADC unit 13 converts an analog signal into a digital signal over time from the start of the conversion to determine that a reference voltage (lamp voltage) is the same as one of the signal voltages to be processed. In principle, row ADC unit 13 includes a comparator (voltage comparator) 14 and a calculation loop 15. The row ADC unit 13 supplies the lamp voltage to the comparator 14 and starts counting with a reference signal supplied to one of the calculation loops 15. By comparing one of the analog image signals input via the vertical signal line 9, the row ADC unit 13 performs AD conversion until a pulse signal is obtained. In the present embodiment, the connection wiring 67 is disposed at a position (1) between the comparator 14 and the calculation circuit 15 in FIG. In this case, the circuit configuration of the comparator j 4 is formed by the pixel array 3 and the first semiconductor wafer unit 22. The second semiconductor wafer unit 26 has a circuit configuration after the calculation loop 15. The control circuit can be formed in the first semiconductor wafer unit 22 or the second semiconductor wafer unit 26. First semiconductor wafer unit 22 and second semiconductor 157964.doc -72-
S 201246520 體晶片單元26可係藉由包括連接導體68及貫通連接導體的 之連接佈線67來彼此連接。 由於計算迴路15快速地執行處理，因而即使對計算迴路 15之電晶體亦需要可以高速操作之一高速電晶體。必須藉 由一先進設備來製造高速電晶體。根據上文所闞述之組 態，具有直至比較器14之電路組態之第一半導體晶片單元 22及具有在計算迴路15之後的電路組態之第二半導體晶片 單元26可分別藉由若干先進設備來單獨地製造。 在圖52中，可考量固態成像元件之效能（影像品質）將連 接佈線67安置於位置（3)或位置（2)處。亦即，連接佈線67 可安置於像素陣列3與行信號處理電路5之間的位置（3)處。 在此情形中，像素陣列3形成於第一半導體晶片單元22 中，且包括行信號處理電路5之信號處理電路形成於第二 半導體晶片單元26中。然後藉由包括連接導體68及貫通連 接導體69之連接佈線67將第—半導體晶片單元與第二半 導體晶片單元2 6彼此連接。 此外’連接佈線67可安置於計算迴路15之輸出之位置 (2)處。在此情形中’直至計算迴路η及像素陣列3之電路 、且J係形成於第半導體晶片單元22中。在第二半導體晶 片單7L 26中’形成在計算迴路15之輸出之後的信號處理電 路然後，藉由包括連接導體68及貫通連接導體69之連接 佈線67將帛I導體晶片單元22與第二半導體晶片單元26 彼此連接。 提i、其中上文所闡述之保護二極體肋之組態、其中在 157964.doc •73- 201246520 圖48及圓51中p型半導體區151在連接佈線67附近之組態， 了將基板觸點單元之組態、用於減小B比鄰搞合電容之每一 屏蔽佈線之組態及諸如此類應用於上文所闡述之實施例。 12.第十一實施例 電子裝置之實例 根據本發明之上文所闡述實施例之固態成像元件可應用 於電子裝置，諸如相機系統（諸如數位相機或視頻攝影 機）、具有一成像功能之行動電話及具有一成像功能之其 他裝置。 圖5 3係作為根據本發明之一第十一實施例之一電子裝置 之一實例之一相機之一圖示。根據本實施例之相機係能夠 使一靜態影像及一視頻成像的一視頻攝影機之一實例。根 據本實施例之一相機141包括一固態成像元件142、將入射 光引導至固態成像元件142之一光接收感測器單元之一光 學系統143及一快門元件144。相機141包括驅動固態成像 元件142之一驅動電路145、及處理自固態成像元件142輸 出之一信號之一信號處理電路146。 將根據上文所闡述實施例之固態成像元件中之一者應用 為固態成像元件142。光學系統（光學透鏡）143在固態成像 元件142之一成像表面上使來自一被攝體之影像光（入射光） 成像。因此，信號電荷在固態成像元件142中積聚達一既 定週期。光學系統143可係包括複數個光學透鏡之一光學 透鏡系統。快門元件144控制固態成像元件142之一光發射 週期及一光遮擋週期。驅動電路145供應一驅動信號用於 157964.doc 201246520 控制固態成像元件142之一傳輸操作及快門元件“A之—， 門操作。藉由自驅動電路145供應之驅動信號（計^之 執行固態成像之信號傳輸。信號處理電路^執二 各種信號處理。將已經受信號處理之一影像信號錯存於： 如一記憶體之一儲存媒體中或輸出至一監視器。 在諸如根據第Ί—實施例之相機之電子奘番ώ 衣直Τ，可實現 固態成像元件142且因此提供具有高可靠性之電子裝置。 本發明含有與在2010年12月15日在日本專利 之日本優先權專利申請案一 7則中所== 物相關之標的物，該申請案之全部内容以引用方式藉此併 入本文中。 熟習此項技術者應理解，可端視設計要求及其他因素進 行各種修改、組合、子組合及變更，只要其在隨.附申請專 利範圍或其等效内容之範疇内。 【圖式簡單說明】 圖1係應用於本發明之實施例之一 MOS固態成像元件之 一實例之整體組態之一圖示； 圖2Α至圖2C係根據本發明之實施例之一固態成像元件 及根據相關技術之一固態成像元件之示意圖； 圖3係根據本發明之一第一實施例之一固態成像元件之 主要單元之整體組態之一圖示； 圖4係根據該第一實施例製造該固態成像元件之一製程 (部分1)之一實例之一圖示； 圖5係根據該第一實施例製造該固態成像元件之一製程 157964.doc •75· 201246520 (部分2)之一實例之一圖示； 圖6係根據該第一實施例製造該固態成像元件之一製程 (部分3)之一實例之一圖示； 圖7係根據該第一實施例製造該固態成像元件之一製程 (部分4)之一實例之一圖示； 圖8係根據該第一實施例製造該固態成像元件之一製程 (部分5)之一實例之一圖示； 圖9係根據該第一實施例製造該固態成像元件之—製程 (部分6)之一實例之一圖示； 圖係根據該第一實施例製造該固態成像元件之一製程 (部分7)之一實例之一圖示； 圖11係根據該第一實施例製造該固態成像元件之一製程 (部分8)之一實例之一圖示； 圖12係根據該第一實施例製造該固態成像元件之一製程 (部分9)之一實例之一圖示； 圖13係根據該第一實施例製造該固態成像元件之—製程 (部分10)之一實例之一圖示； 圖14係根據該第一實施例製造該固態成像元件之一製程 (部分11)之一實例之一圖示； 圖15 A及圖15B係根據本發明之實施例之一半導體移除 區之位置之示意性平面圖； 圖16係根據本發明之一第二實施例之一固態成像元件之 主要單元之整體組態之一圖示； 圖17係根據該第二實施例製造該固態成像元件之〜製程 I57964.doc -76· 201246520 (部分1)之一實例之一圖示； 圖1 8係根據該第二實施例製造S亥固態成像元件之一製程 (部分2)之一實例之一圖示； 圖1 9係根據該第二實施例製造該固態成像元件之一製程 (部分3)之一實例之一圖示； 圖20係根據該第二實施例製造該固態成像元件之一製程 (部分4 )之一實例之一圖示； 圖21係根據該第二實施例製造該固態成像元件之一製程 (部分5)之一實例之一圖示； 圖22係根據該第二實施例製造該固態成像元件之一製程 (部分6)之一實例之一圖示； 圖23係根據該第二實施例製造該固態成像元件之一製程 (部分7)之一實例之一圖示； 圖24係根據該第二實施例製造該固態成像元件之一製程 (部分8)之一實例之一圖示； 圖25係根據本發明之一第三實施例之一固態成像元件之 主要單元之整體組態之一圖示； 圖26係根據該第三實施例製造該固態成像元件之一製程 〔部分1)之—實例之_圖心 圖7係根據該第三實施例製造該固態成像元件之一製程 (部分2)之—實例之一 圖28係根據該第三 (部分3)之—實例之一 圖29係根據該第 一圖示； 三實施例製造該固態成像元件之 一圖示；The S 201246520 body wafer unit 26 can be connected to each other by a connection wiring 67 including a connection conductor 68 and a through connection conductor. Since the calculation loop 15 performs the processing quickly, even for the transistor of the calculation loop 15, it is required to operate one of the high speed transistors at a high speed. High-speed transistors must be manufactured with an advanced device. According to the configuration described above, the first semiconductor wafer unit 22 having the circuit configuration up to the comparator 14 and the second semiconductor wafer unit 26 having the circuit configuration after the calculation loop 15 can be respectively by several advanced devices. Made separately. In Fig. 52, the performance (image quality) of the solid-state imaging element can be considered to place the connection wiring 67 at the position (3) or the position (2). That is, the connection wiring 67 may be disposed at a position (3) between the pixel array 3 and the line signal processing circuit 5. In this case, the pixel array 3 is formed in the first semiconductor wafer unit 22, and the signal processing circuit including the line signal processing circuit 5 is formed in the second semiconductor wafer unit 26. Then, the first semiconductor wafer unit and the second semiconductor wafer unit 26 are connected to each other by a connection wiring 67 including a connection conductor 68 and a through-connection conductor 69. Further, the connection wiring 67 can be disposed at the position (2) of the output of the calculation circuit 15. In this case, it is up to the circuit of the calculation circuit η and the pixel array 3, and the J system is formed in the semiconductor wafer unit 22. The signal processing circuit formed after the output of the calculation circuit 15 is formed in the second semiconductor wafer sheet 7L 26, and then the 导体I conductor wafer unit 22 and the second semiconductor are connected by the connection wiring 67 including the connection conductor 68 and the through connection conductor 69. The wafer units 26 are connected to each other. The configuration of the protective diode rib described above, wherein the p-type semiconductor region 151 is arranged near the connection wiring 67 in 157964.doc • 73- 201246520 FIG. 48 and circle 51, the substrate is The configuration of the contact unit, the configuration of each shielded wiring for reducing the B-parallel capacitance, and the like are applied to the embodiments set forth above. 12. Example of Electronic Apparatus of Eleventh Embodiment A solid-state imaging element according to the above-described embodiments of the present invention can be applied to an electronic device such as a camera system (such as a digital camera or a video camera), a mobile phone having an imaging function And other devices having an imaging function. Figure 5 is a diagram showing one of the cameras as an example of an electronic device according to an eleventh embodiment of the present invention. The camera according to the present embodiment is an example of a video camera capable of imaging a still image and a video. The camera 141 according to one embodiment of the present invention includes a solid-state imaging element 142, an optical system 143 that directs incident light to one of the light-receiving sensor units of the solid-state imaging element 142, and a shutter element 144. The camera 141 includes a drive circuit 145 that drives one of the solid-state imaging elements 142, and a signal processing circuit 146 that processes one of the signals output from the solid-state imaging element 142. One of the solid-state imaging elements according to the embodiments set forth above is applied as the solid-state imaging element 142. An optical system (optical lens) 143 images image light (incident light) from a subject on an imaging surface of one of the solid-state imaging elements 142. Therefore, signal charges are accumulated in the solid-state imaging element 142 for a predetermined period. Optical system 143 can be an optical lens system that includes one of a plurality of optical lenses. The shutter element 144 controls one of the light-emitting periods and one of the light-shielding periods of the solid-state imaging element 142. The driving circuit 145 supplies a driving signal for 157964.doc 201246520 to control one of the transmission operations of the solid-state imaging element 142 and the shutter element "A., the gate operation. The driving signal supplied from the driving circuit 145 (the solid-state imaging is performed) The signal processing circuit performs various signal processing. The image signal that has been subjected to signal processing is stored in: one of the memory storage media or the output to a monitor. For example, according to the third embodiment - the embodiment The electronic camera of the camera can realize the solid-state imaging element 142 and thus provide an electronic device with high reliability. The present invention contains a Japanese priority patent application filed on Dec. 15, 2010 in the Japanese patent. 7 is the subject matter of the object, and the entire contents of this application are incorporated herein by reference. Those skilled in the art should understand that various modifications and combinations can be made depending on design requirements and other factors. Sub-combinations and alterations as long as they are within the scope of the accompanying claims or their equivalents. [Simplified Schematic] Figure 1 is applied to the present invention. One of the embodiments of the MOS solid-state imaging device is one of the overall configurations; FIG. 2A to FIG. 2C are schematic diagrams of a solid-state imaging device according to an embodiment of the present invention and a solid-state imaging device according to the related art; Figure 3 is a diagram showing an overall configuration of a main unit of a solid-state imaging element according to a first embodiment of the present invention; Figure 4 is a process for manufacturing the solid-state imaging element according to the first embodiment (Part 1) One of the examples is illustrated; FIG. 5 is an illustration of one of the examples of manufacturing one of the solid-state imaging elements according to the first embodiment 157964.doc • 75· 201246520 (Part 2); FIG. 6 is based on the One embodiment is an illustration of one of the examples of the process (part 3) of manufacturing one of the solid-state imaging elements; and FIG. 7 is a diagram showing one of the examples of the process (part 4) of manufacturing the solid-state imaging element according to the first embodiment. Figure 8 is a diagram showing one example of a process (part 5) for manufacturing the solid-state imaging device according to the first embodiment; Figure 9 is a process for manufacturing the solid-state imaging device according to the first embodiment (partial) 6) One of the examples Figure 1 is a diagram showing one of the examples of manufacturing one of the solid-state imaging elements (Part 7) according to the first embodiment; Figure 11 is a process for manufacturing the solid-state imaging element according to the first embodiment (Part 8) One of the examples is illustrated; FIG. 12 is an illustration of one example of a process (part 9) of manufacturing one of the solid-state imaging elements according to the first embodiment; FIG. 13 is a manufacturing of the solid-state imaging according to the first embodiment. 1 is an illustration of one of the examples of the process (part 10); FIG. 14 is a diagram showing one example of a process (part 11) of manufacturing the solid state imaging device according to the first embodiment; FIG. 15A and FIG. 15B is a schematic plan view of a position of a semiconductor removal region according to an embodiment of the present invention; FIG. 16 is a diagram showing an overall configuration of a main unit of a solid-state imaging device according to a second embodiment of the present invention; Figure 17 is a diagram showing an example of manufacturing the solid-state imaging device according to the second embodiment, I57964.doc-76·201246520 (Part 1); Figure 18 is a manufacturing solid state according to the second embodiment. One of the imaging elements (part 2) 1 is a diagram showing one example of a process (part 3) for manufacturing the solid-state imaging element according to the second embodiment; FIG. 20 is a manufacturing method of the solid-state imaging element according to the second embodiment. One of the examples of one process (part 4) is illustrated; FIG. 21 is an illustration of one example of a process (part 5) of manufacturing one of the solid-state imaging elements according to the second embodiment; FIG. 22 is based on the second DETAILED DESCRIPTION OF THE INVENTION One of the examples of one of the processes (part 6) for manufacturing the solid-state imaging element is shown in FIG. 23; FIG. 23 is a diagram showing an example of one of the processes (part 7) of manufacturing the solid-state imaging element according to the second embodiment. Figure 24 is a diagram showing an example of a process (part 8) of manufacturing one of the solid-state imaging elements according to the second embodiment; Figure 25 is a main unit of a solid-state imaging element according to a third embodiment of the present invention; One of the overall configurations is shown in FIG. 26; FIG. 26 is a process for manufacturing one of the solid-state imaging elements according to the third embodiment [Part 1] - Example 7 is based on the third embodiment. One of the components of the process (part 2) - one of the examples Figure 28 (Part 3) According to the third of - one of the example of FIG. 29 illustrates a system according to the first; the illustrated embodiment for producing a solid-state imaging device of the third embodiment;
一製程 一製程 157964.doc -77- 201246520 (部分4)之一實例之一圖示； 圖30係根據該第三實施例製造該固態成像元件之一製程 (部分5)之一實例之一圖示； 圖3 1係根據本發明之一第四實施例之一固態成像元件之 主要單元之整體組態之一圖示； 圖32係沿圖3 1之線ΧΧΧΙΙ-ΧΧΧΠ截取之一示意性剖面 圆， 圖33係沿圖31之線ΧΧΧΙΠ-ΧΧΧΙΠ截取之一示意性剖面 圖； 圖34係圖31中之一第一連接墊之一分解平面圖； 圖35係圖31中之一第二連接墊之一分解平面圖； 圖36係根據本發明之一第五實施例之一固態成像元件之 主要單元之整體組態之一圖示； 圖37係根據本發明之一第六實施例之一固態成像元件之 主要單元之整體組態之一圖示； 圖3 8係沿圖37之線又又又乂111-又又乂¥111截取之一示意性剖 面圖； 圖39係根據本發明之一第七實施例之一固態成像元件之 主要單元之整體組態之一圖示； 圖40係根據本發明之一第八實施例之一半導體元件之整 體組態之一圖示； 圖41係根據本發明之一第九實施例之一半導體元件之整 體組態之一圖示； 圖42係根據本發明之一第十實施例之一半導體元件之整 157964.docOne of the examples of one of the processes 157964.doc-77-201246520 (Part 4) is an illustration of one of the examples of manufacturing one of the solid-state imaging elements (Part 5) according to the third embodiment. Figure 3 is a diagram showing an overall configuration of a main unit of a solid-state imaging element according to a fourth embodiment of the present invention; Figure 32 is a schematic cross-sectional view taken along line ΧΧΧΙΙ-ΧΧΧΠ of Figure 31 Figure 33 is a schematic cross-sectional view taken along line ΧΧΧΙΠ-ΧΧΧΙΠ of Figure 31; Figure 34 is an exploded plan view of one of the first connection pads of Figure 31; Figure 35 is a second connection pad of Figure 31 Figure 36 is a diagram showing an overall configuration of a main unit of a solid-state imaging element according to a fifth embodiment of the present invention; Figure 37 is a solid-state imaging according to a sixth embodiment of the present invention. A schematic diagram of one of the overall configurations of the main elements of the component; FIG. 3 is a schematic cross-sectional view taken along line 37 of FIG. 37 and further 乂111- and 乂¥111; FIG. 39 is a diagram according to one of the present invention. The overall unit of the solid state imaging element of one of the seven embodiments Figure 40 is a diagram showing an overall configuration of a semiconductor device according to an eighth embodiment of the present invention; and Figure 41 is an overall group of semiconductor devices according to a ninth embodiment of the present invention. One of the states is illustrated; Figure 42 is a 169964.doc of a semiconductor device in accordance with a tenth embodiment of the present invention.
S -78 - 201246520 體組態之一圖示； 圖43係根據本發明之一實施例應用連接墊之一佈置之一 固態成像元件之另一實例之整體組態之一圖示； 圖44係圖43之固態成像元件中之連接墊佈置之一實例之 一示意性平面圖； 圖45係根據本發明之實施例應用連接墊之一佈置之一固 態成像元件之又一實例之整體組態之一圖示； 圖46係圖45之固態成像元件中之連接墊佈置之一實例之 一示意性平面圖； 圖4 7係根據本發明之一實施例包括一保護二極體之一固 態成像元件之整體組態之一圖示； 圖48係根據本發明之一實施例在連接佈線區之一實例中 之主要單元之一示意性剖面圖； 圖49係沿圖48之線χχχχιχ-χχχχιχ截取之一示意性剖 面圖； 圖50係根據本發明之一實施例在彼此毗鄰之連接導體之 區之一實例中之主要單元之一示意性剖面圖； 圖5 1係根據本發明之一實施例在彼此毗鄰之貫通連接導 體之區組態之一實例中主要單元之一示意性剖面圖； 圖52係根據本發明之一實施例在半導體晶片之間的一電 路上之連接佈線之***位置之一示意圖；及 圖5 3係根據本發明之第十一實施例之一電子裝置之整體 組態之一圖示。 【主要元件符號說明】 I57964.doc •79· 201246520 1 固態成像元件 2 像素 3 像素陣列 4 垂直驅動電路 5 行信號處理電路 6 水平驅動電路 7 輸出電路 8 控制電路 9 垂直信號線 10 水平信號線 11 半導體基板 12 輸入/輸出端子 13 行ADC單元 14 比較器 15 計算迴路 20 金屬氧化物半導體固態成像元件 21 金屬氧化物半導體固態成像元件 22 第一半導體晶片單元 23 像素陣列 24 控制電路 25 邏輯電路 26 第二半導體晶片單元 27 經堆疊半導體晶片 28 固態成像元件 157964.doc -80 - 201246520 30 單元像素 31 半導體基板 31a 表面 31b 後表面 32 半導體井區 33 源極/汲極區 34 η型半導體區 35 ρ型半導體區 36 閘極電極 38 器件隔離區 39 層間絕緣膜 40 佈線 40a 佈線 40b 佈線 40c 佈線 40d 佈線 41 多層佈線層 42 保護膜 43a 絕緣薄膜 43b 絕緣薄膜 44 連接導體 45 第二半導體基板 45a 表面 46 Ρ型半導體井區 157964.doc •81 · 201246520 47 對n型源極/沒極區 48 閘極電極 49 層間絕緣膜 50 器件隔離區 52 半導體移除區 52a 半導體移除區 52b 半導體移除區 53 佈線 53a 佈線 53b 佈線 53c 佈線 53d 佈線 54 連接導體 55 多層佈線層 56 保護膜 57 黏合劑層 58 氧化矽膜 59 氮化矽膜 61 經堆疊絕緣膜 62 貫通連接孔 63 第二連接墊 64 連接孔 65 第一連接墊 65a 連接突出部分/擴^ -82- 157964.doc s 201246520 67 連接佈線 68 連接導體 69 貫通連接導體 71 連接導體 72 光遮蔽膜 73 經平坦化膜 74 滤色器 75 晶片上微透鏡 77 經平坦化絕緣膜 78 固態成像元件 81 凹陷部分 82 固態成像元件 84 固態成像元件 85 連接部分 86 導通導體 87 連接部分 88 導通導體 89 連接墊對 91 連接墊陣列 91A 連接墊陣列 91B 連接墊陣列 93 固態成像元件 95 固態成像元件 96 屏蔽佈線 157964.doc -83- 201246520 97 固態成像元件 98 連接墊陣列 99 連接墊對 100 經堆疊半導體晶片 101 第一半導體晶片單元 102 邏輯電路 103 半導體基板 104 半導體井區 105 對源極/汲極區 106 閘極電極 107 器件隔離區 108 層間絕緣膜 109a 佈線 109b 佈線 109c 佈線 109d 佈線 111 多層佈線層 112 連接導體 114 保護膜 116 第二半導體晶片單元 117 積體電路 118 第二半導體基板 119 半導體井區 120 連接導體 157964.doc -84- s 201246520 121 對源極/汲極區 122 閘極電極 123 器件隔離區 124 層間絕緣膜 125 佈線 125a 佈線 125b 佈線 125c 佈線 125d 佈線 126 佈線層 127 保護膜 129 黏合劑層 131 半導體元件 132 半導體元件 133 半導體元件 135 固態成像元件 136 絕緣膜 137 固態成像元件 141 相機 142 固態成像元件 143 光學系統 144 快門元件 145 驅動電路 146 信號處理電路 157964.doc -85- 201246520 151 152 153 154 155 D21 FD Ml M2 M3 M4 Mil M12 M13 M14 P PD Trl Tr2 Tr3 Tr4 Tr6 Tr7 Tr8 金屬氧化物半導體固態成像元件 半導體晶片 像素陣列 控制電路 邏輯電路 保護二極體 浮動擴散部 金屬 金屬 金屬 金屬 金屬 金屬 金屬 金屬 間距 光電二極體 金屬氧化物半導體電晶體 金屬氧化物半導體電晶體 金屬氧化物半導體電晶體 金屬氧化物半導體電晶體 金屬氧化物半導體電晶體 金屬氧化物半導體電晶體 金屬氧化物半導體電晶體S-78 - 201246520 One of the body configuration diagrams; Figure 43 is a diagram showing an overall configuration of another example of a solid state imaging element in which one of the connection pads is applied in accordance with an embodiment of the present invention; A schematic plan view of one example of a connection pad arrangement in the solid state imaging device of FIG. 43; FIG. 45 is one of the overall configurations of yet another example of a solid state imaging device in which one of the connection pads is applied in accordance with an embodiment of the present invention. Figure 46 is a schematic plan view showing an example of a connection pad arrangement in the solid-state imaging element of Figure 45; Figure 4 is an overall solid-state imaging element including a protective diode according to an embodiment of the present invention. Figure 48 is a schematic cross-sectional view of one of the main elements in an example of a connection wiring area according to an embodiment of the present invention; Figure 49 is a schematic diagram taken along line χχχχιχ-χχχχιχ of Figure 48 Figure 50 is a schematic cross-sectional view of one of the main elements in an example of a region of a connecting conductor adjacent to each other in accordance with an embodiment of the present invention; Figure 51 is an embodiment of the present invention in accordance with one embodiment of the present invention BRIEF DESCRIPTION OF THE DRAWINGS FIG. 52 is a schematic cross-sectional view showing one of main units in an example of a configuration of a region adjacent to a connecting conductor; FIG. 52 is a view showing a position of insertion of a connecting wiring on a circuit between semiconductor wafers according to an embodiment of the present invention. And FIG. 5 is a diagram showing an overall configuration of an electronic device according to an eleventh embodiment of the present invention. [Main component symbol description] I57964.doc •79· 201246520 1 Solid-state imaging device 2 Pixel 3 pixel array 4 Vertical drive circuit 5 line signal processing circuit 6 Horizontal drive circuit 7 Output circuit 8 Control circuit 9 Vertical signal line 10 Horizontal signal line 11 Semiconductor substrate 12 Input/output terminal 13 Row ADC unit 14 Comparator 15 Calculation loop 20 Metal oxide semiconductor solid-state imaging element 21 Metal oxide semiconductor solid-state imaging element 22 First semiconductor wafer unit 23 Pixel array 24 Control circuit 25 Logic circuit 26 Two semiconductor wafer unit 27 stacked semiconductor wafer 28 Solid-state imaging element 157964.doc -80 - 201246520 30 unit pixel 31 semiconductor substrate 31a surface 31b rear surface 32 semiconductor well region 33 source/drain region 34 n-type semiconductor region 35 p-type Semiconductor region 36 gate electrode 38 device isolation region 39 interlayer insulating film 40 wiring 40a wiring 40b wiring 40c wiring 40d wiring 41 multilayer wiring layer 42 protective film 43a insulating film 43b insulating film 44 connecting conductor 45 second semiconductor Plate 45a Surface 46 Ρ-type semiconductor well region 157964.doc •81 · 201246520 47 Pair n-type source/nothing region 48 Gate electrode 49 Interlayer insulating film 50 Device isolation region 52 Semiconductor removal region 52a Semiconductor removal region 52b Semiconductor Removal region 53 wiring 53a wiring 53b wiring 53c wiring 53d wiring 54 connecting conductor 55 multilayer wiring layer 56 protective film 57 adhesive layer 58 hafnium oxide film 59 tantalum nitride film 61 via stacked insulating film 62 through connection hole 63 second connection pad 64 connection hole 65 first connection pad 65a connection protrusion/expansion - -82- 157964.doc s 201246520 67 connection wiring 68 connection conductor 69 through connection conductor 71 connection conductor 72 light shielding film 73 through planarization film 74 color filter 75 On-wafer microlens 77 via planarization insulating film 78 Solid-state imaging element 81 recessed portion 82 solid-state imaging element 84 solid-state imaging element 85 connection portion 86 conduction conductor 87 connection portion 88 conduction conductor 89 connection pad pair 91 connection pad array 91A connection pad array 91B Connection pad array 93 solid state imaging element 95 solid state imaging element 96 Shielded wiring 157964.doc -83- 201246520 97 Solid-state imaging element 98 Connection pad array 99 Connection pad pair 100 Stacked semiconductor wafer 101 First semiconductor wafer unit 102 Logic circuit 103 Semiconductor substrate 104 Semiconductor well region 105 Pair source/drain region 106 gate electrode 107 device isolation region 108 interlayer insulating film 109a wiring 109b wiring 109c wiring 109d wiring 111 multilayer wiring layer 112 connection conductor 114 protective film 116 second semiconductor wafer unit 117 integrated circuit 118 second semiconductor substrate 119 semiconductor well region 120 Connecting conductor 157964.doc -84- s 201246520 121 Pair source/drain region 122 Gate electrode 123 Device isolation region 124 Interlayer insulating film 125 Wiring 125a Wiring 125b Wiring 125c Wiring 125d Wiring 126 Wiring layer 127 Protective film 129 Adhesive layer 131 semiconductor element 132 semiconductor element 133 semiconductor element 135 solid state imaging element 136 insulating film 137 solid state imaging element 141 camera 142 solid state imaging element 143 optical system 144 shutter element 145 drive circuit 146 signal processing circuit 157964.do C -85- 201246520 151 152 153 154 155 D21 FD Ml M2 M3 M4 Mil M12 M13 M14 P PD Trl Tr2 Tr3 Tr4 Tr6 Tr7 Tr8 Metal oxide semiconductor solid-state imaging device semiconductor wafer pixel array control circuit logic circuit protection diode floating diffusion Metal metal metal metal metal metal metal metal pitch photodiode metal oxide semiconductor transistor metal oxide semiconductor transistor metal oxide semiconductor transistor metal oxide semiconductor transistor metal oxide semiconductor transistor metal oxide semiconductor transistor Metal oxide semiconductor transistor
I57964.doc -86- S 201246520I57964.doc -86- S 201246520
Trll 金屬氧化物半導體電晶體 Trl2 金屬氧化物半導體電晶體 Trl3 金屬氧化物半導體電晶體 Tr21 金屬氧化物半導體電晶體 Tr22 金屬氧化物半導體電晶體 Tr23 金屬氧化物半導體電晶體 tl 膜厚度 157964.doc -87-Trll metal oxide semiconductor transistor Trrl metal oxide semiconductor transistor Tr13 metal oxide semiconductor transistor Tr21 metal oxide semiconductor transistor Tr22 metal oxide semiconductor transistor Tr23 metal oxide semiconductor transistor tl film thickness 157964.doc -87 -
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| JP2014135326A (en) * | 2013-01-08 | 2014-07-24 | Toshiba Corp | Solid-state imaging device |
| US10056353B2 (en) | 2013-12-19 | 2018-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC interconnect apparatus and method |
| US9412719B2 (en) | 2013-12-19 | 2016-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC interconnect apparatus and method |
| US9455158B2 (en) | 2014-05-30 | 2016-09-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC interconnect devices and methods of forming same |
| US9449914B2 (en) | 2014-07-17 | 2016-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked integrated circuits with redistribution lines |
| US9659985B2 (en) * | 2015-02-17 | 2017-05-23 | Taiwan Semiconductor Manufacturing Company Ltd. | Integrated circuit and image sensing device having metal shielding layer and related fabricating method |
| KR102422224B1 (en) * | 2015-07-31 | 2022-07-18 | 삼성전자주식회사 | Stacked image sensor and system including the same |
| JP6917716B2 (en) | 2017-01-23 | 2021-08-11 | ソニーセミコンダクタソリューションズ株式会社 | Information processing method for solid-state image sensor and solid-state image sensor |
| US11025846B2 (en) * | 2017-02-01 | 2021-06-01 | Sony Semiconductor Solutions Corporation | Imaging system, imaging apparatus, and control apparatus |
| JP7102119B2 (en) | 2017-09-29 | 2022-07-19 | キヤノン株式会社 | Semiconductor devices and equipment |
| CN108183114A (en) * | 2017-12-26 | 2018-06-19 | 德淮半导体有限公司 | Back side illumination image sensor and forming method thereof |
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| US6674108B2 (en) * | 2000-12-20 | 2004-01-06 | Honeywell International Inc. | Gate length control for semiconductor chip design |
| US6815787B1 (en) * | 2002-01-08 | 2004-11-09 | Taiwan Semiconductor Manufacturing Company | Grid metal design for large density CMOS image sensor |
| JP2005322745A (en) * | 2004-05-07 | 2005-11-17 | Sony Corp | Semiconductor element, method for manufacturing the same, solid-state imaging element, and method for manufacturing the same |
| CN101228631A (en) * | 2005-06-02 | 2008-07-23 | 索尼株式会社 | Solid imaging element and manufacturing method thereof |
| JP4675231B2 (en) * | 2005-12-28 | 2011-04-20 | パナソニック株式会社 | Semiconductor integrated circuit device |
| FR2910707B1 (en) * | 2006-12-20 | 2009-06-12 | E2V Semiconductors Soc Par Act | IMAGE SENSOR WITH HIGH DENSITY INTEGRATION |
| KR100855408B1 (en) * | 2007-12-27 | 2008-08-29 | 주식회사 동부하이텍 | Image sensor and method for manufacturing thereof |
| JP5353201B2 (en) * | 2008-11-21 | 2013-11-27 | ソニー株式会社 | Method for manufacturing solid-state imaging device |
| JP5985136B2 (en) * | 2009-03-19 | 2016-09-06 | ソニー株式会社 | SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE |
| TWI515885B (en) * | 2009-12-25 | 2016-01-01 | 新力股份有限公司 | Semiconductor device and method of manufacturing the same, and electronic apparatus |
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