201220660 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種脈波寬度調變（ v P^lse width modulation，PWM )控制器，特別是關於一種_制。 其提供用於功率轉換器之過溫度保護。 t ^ 【先前技術】 圖1繪示利用具有過溫度保護之控制器6〇之習 轉換器。功率轉換器包括變壓器10、功率電晶體2〇: 器25、控制器60、熱敏電阻器36、整流器丨丨與 々 器12與22以及二次側回授電路16。控制器 電今 端vcc '輸出端GATE、感測端cs、回授端吒具^共電 測端RT以及接地端GND。變壓H 1〇包括一次，凰度侦 輔助繞組N A以及二次側繞組N s。輔助繞組、=N p、 21對電阻器29 ☆雨 _ 八竭·過整流器 供電。二-欠側^ 產生供電電壓Vcc來對控制器的 ，、一側繞組NS透過整流器11來產生跨於電容器12 之^率轉換11的輪出電壓V。。二次側回授電路16包括電 阻器13、齊納二極體14以及光耦合器15。電阻器13耦接 於轉換器之輪出端與齊納二極體14之陰極端之間。光 耦二器15之輸入端耦接齊納二極體14之陽極端。二次侧 回授電=16接收功率轉換器之輸出端上的輸出電壓％以 產生回授化號VpB。電阻器25耦接於功率電晶體20之源 ?與參考接地之間。當功率電晶體20被控制器60之輸出 端GATE所導通時’電阻器％將把流經功率電晶體之 c 201220660 切換電流Ip轉換為感測電壓vcs。 控制器60包括過溫度保護電路、過電流保護電路、調 節電路以及脈波寬度調變（pulse width modulation，PWM ) 電路30。過溫度保護電路包括電流源34、比較器33以及 延遲電路35。電流源34耦接至控制器60之溫度偵測端RT 以及比較器33之負端。熱敏電阻器36耦接於控制器60之 溫度偵測端RT與參考接地之間。比較器33之正端接收臨 界值電壓VT。比較器33之輸出端透過延遲電路35來產生 • 過溫度信號S0T。過電流保護電路包括比較器31。比較器 31具有接收限制電壓VLMT之正端以及接收感測電壓v 之負端。比較器31之輸出端產生過電流信號s〇c。調節電 路包括比較器32與電阻器37。比較器32之正端接收回授 信號VFB，且透過電阻器37而被上拉。比較器32之負端 接收感測電壓Vcs。比較器32之輸出端產生調節信號Srq。 PWM電路30接收過電流信號Soc、調節信號sRG以及過溫 度信號S0T，以在控制器60之輸出端GATE上產生驅動信 •號 VG。 圖2繪示控制器60之PWM電路的實施例。pwm電 路30包括振盪器301、反相器302、正反器303、及閘304、 反及閘305與306、遮沒電路（blanking circuit) 307以及 緩衝器308。反相器302之輸入端接收振盪器3〇1所產生 之振盪信號PLS。反相器302之輸出端麵接正反器303之 頻率輸入端ck，以致能正反器303。反相器302之輸出也 耦接及閘304之第一輸入端。正反器303之輸入端D接收 過溫度信號S〇t。正反器303之輸出端Q耦接及閘304之 201220660 第二輸入端。及閘304之輸出端產生切換信號Spwm。過電 流信號Soc與調節信號SRG提供至反及閘305之兩輸入端。 反及閘305之輸出端搞接反及閘306之第一輸入端。遮沒 電路307耦接於及閘304之輸出端與反及閘306之第二輸 入端。反及閘306之輸出端麵接正反器303之重置輸入端 R，以重置正反器303。緩衝器308接收切換信號SPWM來 產生驅動信號VG。 在習知控制器中，為了實現過溫度保護功能，通常需要一專用 • 的封裝接腳。因此，需要一方案用以減少控制器之接腳數量同時 不破壞其原有功能，達到節省成本的目的。 【發明内容】 本發明提供一種提供過溫度保護之控制器，適用於功 率轉換器。此控制器包括切換電路、驅動電路、過溫度保 護電路以及信號產生器。切換電路產生切換信號。驅動電 φ 路由高壓側電晶體以及低壓側電晶體所組成，以產生驅動 信號。驅動信號用來調節功率轉換器。過溫度保護電路耦 接驅動電路。熱敏電阻器耦接驅動電路，且在切換信號之 截止期間，調整跨於熱敏電阻器之驅動信號。信號產生器 控制過溫度保護電路。信號產生器更耦接驅動電路，以驅 動高壓側電晶體以及低壓側電晶體。 過溫度保護電路包括電流源電路以及比較器。電流源 電路被致能以提供電流至熱敏電阻器，以在切換信號之截 止期間根據信號產生器所產生之第一信號來調整跨於熱敏 201220660 電阻器之驅動信號。比較器在切換信號之截止期間比較臨 界值電壓與驅動信號’以產生過溫度信號。過溫度信號用 以禁能驅動信號以關閉功率轉換器。 信號產生器包括鋸齒信號、第一比較電路、致能電路 以及第二比較電路。鋸齒電路根據切換信號來產生第一驅 動信號以及鋸齒信號。第一驅動信號用來驅動高壓側電晶 體。第一比較電路比較鋸齒信號與第一參考電壓，以禁能 第一驅動信號。第二驅動信號根據第一驅動信號之下降緣 • 而被致能，以驅動低壓側電晶體。致能電路根據第二驅動 信號之下降緣來產生第一信號。第一信號用來致能過溫度 保護電路。第二比較電路比較鋸齒信號與第二參考電壓， 以致能第二信號。第二信號用來禁能過溫度保護電路。熱 敏電阻器為負溫度係數電阻器。當在切換信號之戴止期間 功率轉換器之環境溫度升高時，切換信號之準位降低。 控制益更包括箝制電路。此箝制電路被致能來輕接至 熱敏電阻器，以在切換信號之截止期間籍制驅動信號之上 本發明更提供-種提供過溫度保護之功率轉換 i歡吳、<丄杰sa扣…^ . ' ---------------- 功率開關以及控制器。變壓器具有一次側繞•且、 ::人氣組以及辅助繞組。功率開_接變㈣之 、〜且以調節功率轉換器。控制 信號產生驅動㈣來如“^錢料卩根據切換 制器之輸出端。在切換料破絲㈣接至控 阻器之驅動信號。 截期間，調整跨於熱敏電 控制器包括切換電路、過、、θ 過μ度保護電路以及箝制電 7 201220660 =換電路產生七刀換信號。過溫度保護電路_接至熱敏 "阻益’ Μ在㈣信號之截止期間，調整跨於熱敏電阻器 之驅動信號。籍制電路被致能來輕接至熱敏電阻器，以在 =換#號之截止期間箝制驅動信號之上限準位。熱敏電阻 器為負溫度係數電阻器。 本^明更提供一種提供過溫度保護之方法，適用於功 =轉換:。此方法包括：提供切換信號；根據⑽信號產 驅動信號以切換功率開關，藉以調節功率轉換器；在切 換4。號^截止期間’產生雜削m當鑛齒信號超過第一 2電壓時’致能過溫度賴電路；根據功率轉換器之環 兄/皿度來調整驅動信號；比較驅動信號與臨界值電壓以致 能延遲信號’藉以在延遲時間後產生過溫度信號；以及當 鑛齒仏號超過第二參考電壓時，禁能過溫度保護電路。在 刀換l號之截止期間，驅動信號被調整為低於一上限準 位、。此上限準位用來避免功率開關在减信號之截止期間 内被導通。過溫度信號用來截止功率關。第二參考電屋 準位大於第一參考電壓準位。 本發明之一目的在於提供過溫度保護給功率轉換器。 ^發明之另一目的在於減少功率轉換器之控制器之接 腳數量，同時不破壞功率轉換器之原有保護功能。 【實施方式】 為使本發明之上述目的、特徵和優點能更明顯易僅， 下文特舉-較佳實施例’並配合所附圖式，作詳細 下。 ς 201220660 圖3繪示根據本發明實施例之功率轉換器。此功率轉 換器包括變壓器10、功率開關20、電阻器25、控制器100、 熱敏電阻器36、整流器11與21、電容器12與22以及二 次側回授電路16。在此實施例中，功率開關20為一功率 電晶體。控制器100具有供電端VCC、輸出端GATE、感 測端CS、回授端FB以及接地端GND。變壓器10包括一 次側繞組NP、輔助繞組NA以及二次側繞組Ns。輔助繞組 Na透過整流器21對電容器22充電，以產生供電電壓Vcc • 來對控制器60供電。二次侧繞組Ns透過整流器11來產生 跨於電容器12之功率轉換器的輸出電壓V〇。二次側回授 電路16包括電阻器13、齊納二極體14以及光耦合器15。 電阻器13耦接於功率轉換器之輸出端與齊納二極體14之 陰極端之間。光耦合器15之輸入端耦接齊納二極體14之 陽極端。二次側回授電路16接收功率轉換器之輸出端上的 輸出電壓V〇以產生一回授信號VFB。電阻器25耦接於功 率電晶體20之源極與參考接地之間。當功率電晶體20被 • 控制器60之輸出端GATE控制而導通時，電阻器25將把 流經功率電晶體20之切換電流Ip轉換為感測電壓Vcs。 控制器100包括過電流保護電路、調節電路以及脈波 寬度調變（pulse width modulation，PWM)電路 50。根據 本發明的一實施例，具有負溫度係數特性的熱敏電阻器36 耦接於控制器100之輸出端GATE。當環境溫度升高時， 熱敏電阻器36之電阻值將降低，反之亦然。過電流保護電 路包括比較器31。比較器31之正端接收限制電壓VLMT， 其負端接收感測電壓Vcs。比較器31之輸出端產生過電流 201220660 信號Soc。調節電路包括比較器32與電阻器37。比較器 32之正端接收回授電壓VFB，且透過電阻器37來上拉。比 較器32之負端接收感測電壓Vcs。比較器32之輸出端產 生調節信號srg。過電流信號Soc與調節信號SRG被提供至 PWM電路50以產生驅動信號VG。 圖4繪示根據本發明實施例之控制器1〇〇之pwM電路 50。PWM電路50包括切換電路、過溫度保護電路、箝制 電路、信號產生器70以及驅動電路。切換電路包括振盪器 φ 301、反相器302、正反器303、及閘304、反及閘305與 306以及遮沒電路（blanking circuit) 307。過溫度保護電 路包括電流源311、開關312、比較器310、反及閘309以 及延遲電路319 ’其中’電流源311與開關312形成電流 源電路。驅動電路包括緩衝器315與317以及電晶體316 與318。在此實施例中’箝制電路由開關313與二極體314 來實現。 振盪器301產生振盪信號PLS。振盪信號PLS透過反 • 相器302而被提供至正反器303之時脈輸入端Ck與及閘 304之第一輸入端。正反器303之輸出端Q耦接及閘304 之第二輸入端。及閘304的輸出端產生切換信號sPWM。過 電流信號Soc與調節信號sRG被提供至反及閘305之兩輸 入端。反及閘305之輸出端耦接反及閘306之第一輸入端。 反及閘306之第二輸入端透過遮沒電路307來接收切換信 號SPWM。反及閘306之輸出端耦接正反器303之重置輸入 端R，以重置正反器303。 切換信號SPWM被提供至信號產生器70以產生第一驅 201220660 動信號sH、第二驅動信號Sl、第一信號s〗以及第二信號 S2。電流源311之第一端耦接供電電壓Vcc。開關3丨2與 ，關313串聯麵接於電流源311之第二端與二極體 陽極之間。二極體314之陰極耦接參考接地。開關3D及 313皆由第一信號Si所控制。電晶體316及電晶體Mg串 聯耦接於供電電壓vcc與參考接地之間，其中，耦接供電 電壓Vcc之電晶體316稱為高壓側電晶體，而耦接參考接 地之電晶體318稱為低壓側電晶體。第一驅動信號^透過 •綾衝态315控制電晶體316。第二驅動信號Sl透過緩衝器 3Π控制電晶體318。電晶體316與318之共同連接點耦接 控制器100之輸出端GATE，以產生驅動信號¥〇。開關312 與開關313之共通連接點也耦接控制器1〇〇之輸出端 GATE。控制1〇〇之輸出端GATE耦接比較器31〇之正輸 入端。比較器310之負輸入端接收臨界值電壓Vt。比較器 310之輸出端耦接反及閘309之第一輸入端。反及閘3〇9 之第二輸入端接收第二信號&。反及閘3〇9之輸出端提供 鲁延遲信號sD至延遲電路319之輸入端。延遲電路319之輸 出端產生過溫度信號S〇t至正反器303的輸入端D。 圖5繪示根據本發明實施例之控制器1〇〇之信號產生 器70。信號產生器70包括鋸齒電路、第一比較電路、第 二比較電路以及致能電路。鋸齒電路包括反相器711與 712、電流源713、開關714與715以及電容器716。第一 比較電路包括比較器717以及反或閘720。第二比較電路 包括比較器718以及反或閘722。在此實施例中，致能電 路由反或閘721來實現。電流源713之第一端耦接供電電 201220660 壓Vcc。開關714與715串聯耦接於電流源713之第二端 與參考接地之間。開關715受控於切換信號SpwM。反相器 712之輸入端接收切換信號SpwM。反相器712之輸出端耦 接反相器711之輸入端。 反相器711之輸出端產生第一驅動信號Sh。切換信號 Spwm透過反相712控制開關714。電容器716與開關715 並聯。由跨於電容器7丨6上獲得斜坡電壓VRMP。斜坡電壓 vRMP被提供至比較器717之正端以及比較器718之負端。 • 比較器717之負端以及比較器718之正端分別接收第一參 考信號VR1與第二參考信號Vr2。第二參考信號準位係大於 第一參考信號準位。反或閘720、721 '及722之第一輸入 端皆接收第一驅動信號SH。反或閘720之第二輸入端耦接 比較器717之輸出端。反或閘722之第二輸入端耦接比較 器718之輸出端。反或閘720之輸出端產生第二驅動信號 Sl。第二驅動信號SL被提供至反或閘721之第二輸入端。 反或閘721之輸出端以及反或閘722之輸出端分別產生第 籲一信號Si以及第二信號S2。 圖6繪示根據本發明實施例之控制器1〇〇之各種波 形。同時參閱圖5，當切換信號SPWM被禁能（disabled)時， 開關714將導通，且開關715將截止。電流源713將透過 開關714對電容器716充電，以產生跨於電容器716之斜 坡電壓VRMP。參閱圖6,斜坡電壓Vrmp視為鋸齒信號。一 旦切換信號SPWM被禁能，第一驅動信號心將被禁能。第 二驅動信號SL將依據第一驅動信號SH的下降緣而被致能 (enabled)。複參閱圖4，電晶體318透過緩衝器317而 12 201220660 被第二驅動信號sL導通。驅動信號Vg因此而將被下拉至 參考接地之準位（例如0V)。一旦斜坡電壓Vrmp持續增 加且超過第_參考電壓VR1之準位時，第二驅動信號^將 被禁能。第-信號Si將根據第二驅動信號Sl之下降緣而 被致能。這將截止電晶體318，並導通開關312及313。 參閱圖3,熱敏電阻器36耦接於控制器1〇〇之輸出端 GATE與參考接地之間。當開關312與313被第一信號 導通時，二極體314之-串聯寄生電阻器（未顯示）將透 眷過控制ϋ 1GG之輸出端GATE而與熱敏電阻^ %並聯。由 於二極體314之寄生電阻器的電阻值相對地小於熱敏電阻 器36之電阻值，因此由電流源、3n所提供之大部分電流將 々丨l至一極肢314。在此時，驅動信號之準位接著將被上 拉至二極體3i4之正向電壓Vf的準位。二極體叫之正向 電壓VF確保了此時驅動信?虎％的上限準位，以避免功率 電晶體在切換信號Sp·的截止期間内被導通。被提供 至比較器、310之負端的臨界值電壓％定義過溫度條件，且 •臨界值電壓VT係低於二極體314之正向電1%。由於熱 敏電阻5 36具有負溫度係數特性，因此熱敏電阻器％之 電f準位（其也等於驅動信號％之準位）將隨著環境溫度 升间而降低。當驅動信號ν〇之準位變為低於二極體 電壓VF時，電流源311所提供之大部分電流將流至 36。當驅動信號％之準位持續地隨著環境溫 -南而降低且變為低於臨界值電壓^時（例如在圖6中 ΓΑ”所㈣時間點），比較器训將透過反及閘306來致 %延遲w Sn延遲錢Sd#致能的時間長於延遲 201220660 電路319所提供的延遲時間，延遲電路319將產生低邏輯 過溫度信號SOT給正反器303之輸入端D，以禁能切換信 號SpwM ’這將會禁能驅動信號Vg以切斷能量轉移，且保 護功率轉換器避免受到過溫度狀態的損壞。 '—旦斜坡信號VrmP持續地增加且超過第二參考電壓 VR2的準位時，第二信號s2將被致能。被致能的第二信號 S2將透過反及閘309來禁能延遲信號SD。只要反及閘309 之第二輸入端接收被禁能之第二信號S2，過溫度保護電路 • 將被禁能。因此，過溫度保護電路係由第一信號致能， 且被第二信號s2所禁能。 圖7繪示根據本發明實施例之PWM電路50之延遲電 路319。延遲電路319實質上係為一計數器，其包括串聯 的正反器321、322、及326。這些串聯之正反器的時脈輸 入端ck接收振盪信號PLS。這些串聯之正反器的重置輸入 端R接收延遲信號SD。當延遲信號SD被致能時，振盪信 號PLS將驅動這些正反器器以產生延遲時間。在本發明之 # 一實施例中，切換期間為lOps，且延遲時間則為10ms。在 延遲時間之後，正反器326之反相輸出端泛將產生低邏輯 過溫度信號SOT。當延遲信號SD被禁能時，這些正反器將 被重置，且過溫度信號S0T將再次變為高邏輯。 圖8繪示根據本發明實施例之提供給功率轉換器過溫 度保護的方法。首先，產生切換信號（步驟1001)。接著， 根據所述切換信號來產生驅動信號以切換功率開關，藉以 調節功率轉換器（步驟1002)。然後，在所述切換信號之 截止期間產生鋸齒信號（步驟1003 )。接著，當所述鋸齒 14 201220660 信號超過第一參考電壓時，致能過溫度保護電路（步驟 1004)。接著，根據所述功率轉換器之環境溫度來調整驅 動信號（步驟1005)。接著，藉由比較所述驅動信號與臨 界值電壓，以致能延遲信號而在延遲時間後產生過溫度信 號（步驟1006)。最後，當所述鋸齒信號超過第二參考電 壓時，禁能過溫度保護電路（步驟1007)。在切換信號截 止期間，驅動信號被調整為低於一上限準位。過溫度信號 用來關閉功率轉換器。所述上限準位則用來避免功率開關 • 在切換信號之截止期間内被導通。第二參考信號準位係大 於第一參考信號準位。 本發明雖以較佳實施例揭露如上，然其並非用以限定 本發明的範圍，任何所屬技術領域中具有通常知識者，在 不脫離本發明之精神和範圍内，當可做些許的更動與潤 飾，因此本發明之保護範圍當視後附之申請專利範圍所界 定者為準。 • 【圖式簡單說明】 圖1繪示習知功率轉換器； 圖2繪示圖1中習知功率轉換器内控制器之PWM電 路； 圖3繪示根據本發明實施例之功率轉換器； 圖4繪示根據本發明實施例之控制器之PWM電路； 圖5繪示根據本發明實施例之控制器之信號產生器； 圖6繪示根據本發明實施例之控制器之各種波形； 圖7繪示根據本發明實施例之PWM電路之延遲電路； 15 201220660 以及 圖8繪示根據本發明實施例之提供給功率轉換器過溫 度保護的方法。 【主要元件符號說明】 圖1 : 10, -變壓 為， 11- y整流器； 12, -電容 裔， 13- -電阻器； 14〜齊納 二極體； 15- -光耦合器； 16- '二次側回授電路； 20〜 功率電晶體； 21- /整流器； 22〜 電容器； 25〜電阻器； 30- /脈波寬度調變（PWM)電路； 31、 32、33〜比較器； 34〜 電流源； 35- /延遲電路； 36〜 熱敏電阻器； 37- /電阻器； 60〜 控制器； CS- -感測端； FB- /回授端； GATE〜輸出端； GND〜接地端； Ip〜 切換電流； Na- /輔助繞組； Np、 -一次側繞組； Ν§〜 •二次側繞組； RT- ^溫度偵測端； S〇c" -過電流信號 S〇t/ 〜過溫度信號； Srg" ^調節信號； Vcc 〜供電電壓； Vcs^ 〜感測電壓； Vfb' 〜回授信號； vG- /驅動信號； 16 201220660 vLMT〜限制電壓； v〇〜輸出電壓； VT〜臨界值電壓； VCC〜供電端。201220660 VI. Description of the Invention: [Technical Field] The present invention relates to a pulse width modulation (PWM) controller, and more particularly to a system. It provides over temperature protection for the power converter. t ^ [Prior Art] Fig. 1 shows a conventional converter using a controller with over temperature protection. The power converter includes a transformer 10, a power transistor 2, a controller 25, a controller 60, a thermistor 36, rectifiers and buffers 12 and 22, and a secondary side feedback circuit 16. Controller electric current terminal vcc 'output terminal GATE, sensing terminal cs, feedback terminal cooker ^ common terminal RT and ground GND. The transformer H 1 〇 includes one time, the phoenix detection auxiliary winding N A and the secondary side winding N s . Auxiliary winding, =N p, 21 pairs of resistors 29 ☆ Rain _ Eight exhausted over rectifiers Power supply. The second-lower side generates a supply voltage Vcc for the controller, and the one side winding NS passes through the rectifier 11 to generate a turn-off voltage V across the voltage conversion 11 of the capacitor 12. . The secondary side feedback circuit 16 includes a resistor 13, a Zener diode 14, and an optical coupler 15. The resistor 13 is coupled between the wheel terminal of the converter and the cathode terminal of the Zener diode 14. The input end of the photocoupler 15 is coupled to the anode terminal of the Zener diode 14. The secondary side feedback power = 16 receives the output voltage % at the output of the power converter to generate the feedback number VpB. The resistor 25 is coupled between the source of the power transistor 20 and the reference ground. When the power transistor 20 is turned on by the output terminal GATE of the controller 60, the resistor % will convert the c 201220660 switching current Ip flowing through the power transistor into the sensing voltage vcs. The controller 60 includes an over temperature protection circuit, an overcurrent protection circuit, a regulation circuit, and a pulse width modulation (PWM) circuit 30. The over temperature protection circuit includes a current source 34, a comparator 33, and a delay circuit 35. The current source 34 is coupled to the temperature detecting terminal RT of the controller 60 and the negative terminal of the comparator 33. The thermistor 36 is coupled between the temperature detecting terminal RT of the controller 60 and the reference ground. The positive terminal of comparator 33 receives the threshold voltage VT. The output of the comparator 33 is passed through the delay circuit 35 to generate an over temperature signal S0T. The overcurrent protection circuit includes a comparator 31. The comparator 31 has a positive terminal receiving the limit voltage VLMT and a negative terminal receiving the sensing voltage v. An output of the comparator 31 produces an overcurrent signal s〇c. The regulating circuit includes a comparator 32 and a resistor 37. The positive terminal of the comparator 32 receives the feedback signal VFB and is pulled up through the resistor 37. The negative terminal of the comparator 32 receives the sensing voltage Vcs. The output of comparator 32 produces an adjustment signal Srq. The PWM circuit 30 receives the overcurrent signal Soc, the adjustment signal sRG, and the overtemperature signal SOT to generate a drive signal VG at the output GATE of the controller 60. FIG. 2 illustrates an embodiment of a PWM circuit of controller 60. The pwm circuit 30 includes an oscillator 301, an inverter 302, a flip-flop 303, and a gate 304, anti-gates 305 and 306, a blanking circuit 307, and a buffer 308. The input terminal of the inverter 302 receives the oscillation signal PLS generated by the oscillator 3.1. The output end face of the inverter 302 is connected to the frequency input terminal ck of the flip-flop 303 to enable the flip-flop 303. The output of inverter 302 is also coupled to the first input of gate 304. The input terminal D of the flip-flop 303 receives the temperature signal S〇t. The output terminal Q of the flip-flop 303 is coupled to the 201220660 second input terminal of the gate 304. The output of the gate 304 generates a switching signal Spwm. The overcurrent signal Soc and the regulation signal SRG are supplied to the two inputs of the inverse gate 305. The output of the opposite gate 305 is coupled to the first input of the gate 306. The occlusion circuit 307 is coupled to the output of the AND gate 304 and the second input of the NAND gate 306. The output end face of the gate 306 is connected to the reset input terminal R of the flip-flop 303 to reset the flip-flop 303. The buffer 308 receives the switching signal SPWM to generate the drive signal VG. In conventional controllers, a dedicated package pin is typically required to achieve over temperature protection. Therefore, a solution is needed to reduce the number of pins of the controller without destroying its original functions, thereby achieving cost saving. SUMMARY OF THE INVENTION The present invention provides a controller that provides over temperature protection for a power converter. The controller includes a switching circuit, a driving circuit, an over temperature protection circuit, and a signal generator. The switching circuit generates a switching signal. The driving power φ is composed of a high-voltage side transistor and a low-voltage side transistor to generate a driving signal. The drive signal is used to regulate the power converter. The over temperature protection circuit is coupled to the drive circuit. The thermistor is coupled to the driving circuit and adjusts the driving signal across the thermistor during the off period of the switching signal. The signal generator controls the over temperature protection circuit. The signal generator is further coupled to the driving circuit to drive the high side transistor and the low side transistor. The over temperature protection circuit includes a current source circuit and a comparator. The current source circuit is enabled to provide current to the thermistor to adjust the drive signal across the thermal 201220660 resistor based on the first signal generated by the signal generator during the switching signal. The comparator compares the threshold voltage with the drive signal ' during the off period of the switching signal to generate an over temperature signal. The over temperature signal is used to disable the drive signal to turn off the power converter. The signal generator includes a sawtooth signal, a first comparison circuit, an enable circuit, and a second comparison circuit. The sawtooth circuit generates a first drive signal and a sawtooth signal based on the switching signal. The first drive signal is used to drive the high side side of the transistor. The first comparison circuit compares the sawtooth signal with the first reference voltage to disable the first drive signal. The second drive signal is enabled in accordance with a falling edge of the first drive signal to drive the low side transistor. The enabling circuit generates a first signal based on a falling edge of the second drive signal. The first signal is used to enable the over temperature protection circuit. The second comparison circuit compares the sawtooth signal with the second reference voltage to enable the second signal. The second signal is used to disable the over temperature protection circuit. The thermistor is a negative temperature coefficient resistor. When the ambient temperature of the power converter rises during the wearing of the switching signal, the level of the switching signal decreases. Control benefits include clamping the circuit. The clamping circuit is enabled to be lightly connected to the thermistor to encode the driving signal during the cutoff period of the switching signal. The present invention further provides a power conversion that provides over temperature protection i Huan Wu, <丄杰sa Buckle...^ . ' ---------------- Power switch and controller. The transformer has a side-wound • and , :: popularity group and auxiliary windings. The power is turned on and off (4), and the power converter is adjusted. The control signal generates a drive (4) such as "^ money material according to the output end of the switching controller. The switching signal is broken (4) connected to the control signal of the control resistor. During the interception, the adjustment across the thermistor controller includes the switching circuit, Over, θ over μ degree protection circuit and clamped power 7 201220660 = Change circuit produces seven-knife change signal. Over-temperature protection circuit _ connected to thermal "blocking Μ Μ During (4) signal cut-off, adjustment across thermal The drive signal of the resistor is enabled to lightly connect to the thermistor to clamp the upper limit of the drive signal during the cutoff of the =#. The thermistor is a negative temperature coefficient resistor. ^ Ming provides a method of providing over temperature protection, suitable for work = conversion: This method includes: providing a switching signal; generating a driving signal according to the (10) signal to switch the power switch, thereby adjusting the power converter; During the cut-off period, 'generating m is used when the mined tooth signal exceeds the first 2 voltage' to enable the over temperature circuit; the drive signal is adjusted according to the ring/span of the power converter; comparing the drive signal with the critical value Pressing the delay signal to generate an over temperature signal after the delay time; and disabling the over temperature protection circuit when the ore nickname exceeds the second reference voltage. During the cutoff of the knife, the drive signal is adjusted to Below the upper limit level, the upper limit level is used to prevent the power switch from being turned on during the off period of the decrement signal. The over temperature signal is used to turn off the power off. The second reference electric level is greater than the first reference voltage level One of the objects of the present invention is to provide over temperature protection to the power converter. Another object of the invention is to reduce the number of pins of the controller of the power converter without destroying the original protection function of the power converter. The above described objects, features and advantages of the present invention will become more apparent and obvious, and the following detailed description of the preferred embodiments of the present invention will be described in conjunction with the accompanying drawings. ς 201220660 FIG. 3 illustrates an embodiment of the present invention. Power converter. The power converter includes a transformer 10, a power switch 20, a resistor 25, a controller 100, a thermistor 36, rectifiers 11 and 21, and capacitors 12 and 22. And the secondary side feedback circuit 16. In this embodiment, the power switch 20 is a power transistor. The controller 100 has a power supply terminal VCC, an output terminal GATE, a sensing terminal CS, a feedback terminal FB, and a ground terminal GND. The transformer 10 includes a primary side winding NP, an auxiliary winding NA, and a secondary side winding Ns. The auxiliary winding Na charges the capacitor 22 through the rectifier 21 to generate a supply voltage Vcc to supply power to the controller 60. The secondary side winding Ns passes through the rectifier 11 The output voltage V〇 of the power converter across the capacitor 12 is generated. The secondary side feedback circuit 16 includes a resistor 13, a Zener diode 14, and an optocoupler 15. The resistor 13 is coupled to the power converter. The output end is connected to the cathode end of the Zener diode 14. The input end of the optocoupler 15 is coupled to the anode terminal of the Zener diode 14. The secondary side feedback circuit 16 receives the output voltage V〇 at the output of the power converter to generate a feedback signal VFB. The resistor 25 is coupled between the source of the power transistor 20 and the reference ground. When the power transistor 20 is turned on by the output terminal GATE of the controller 60, the resistor 25 converts the switching current Ip flowing through the power transistor 20 into the sensing voltage Vcs. The controller 100 includes an overcurrent protection circuit, an adjustment circuit, and a pulse width modulation (PWM) circuit 50. According to an embodiment of the invention, the thermistor 36 having a negative temperature coefficient characteristic is coupled to the output terminal GATE of the controller 100. When the ambient temperature rises, the resistance of the thermistor 36 will decrease, and vice versa. The overcurrent protection circuit includes a comparator 31. The positive terminal of the comparator 31 receives the limit voltage VLMT, and the negative terminal thereof receives the sense voltage Vcs. The output of comparator 31 produces an overcurrent 201220660 signal Soc. The adjustment circuit includes a comparator 32 and a resistor 37. The positive terminal of the comparator 32 receives the feedback voltage VFB and is pulled up through the resistor 37. The negative terminal of comparator 32 receives the sense voltage Vcs. The output of comparator 32 produces an adjustment signal srg. The overcurrent signal Soc and the adjustment signal SRG are supplied to the PWM circuit 50 to generate a drive signal VG. 4 illustrates a pwM circuit 50 of a controller 1 in accordance with an embodiment of the present invention. The PWM circuit 50 includes a switching circuit, an over temperature protection circuit, a clamp circuit, a signal generator 70, and a drive circuit. The switching circuit includes an oscillator φ 301, an inverter 302, a flip flop 303, and a gate 304, NAND gates 305 and 306, and a blanking circuit 307. The over temperature protection circuit includes a current source 311, a switch 312, a comparator 310, an inverse gate 309, and a delay circuit 319' where the current source 311 and the switch 312 form a current source circuit. The drive circuit includes buffers 315 and 317 and transistors 316 and 318. In this embodiment, the clamp circuit is implemented by the switch 313 and the diode 314. The oscillator 301 generates an oscillation signal PLS. The oscillating signal PLS is supplied to the clock input terminal Ck of the flip flop 303 and the first input terminal of the AND gate 304 through the inverse phase converter 302. The output terminal Q of the flip-flop 303 is coupled to the second input terminal of the gate 304. The output of the gate 304 generates a switching signal sPWM. The overcurrent signal Soc and the adjustment signal sRG are supplied to the two inputs of the inverse gate 305. The output of the anti-gate 305 is coupled to the first input of the anti-gate 306. The second input of the NAND gate 306 receives the switching signal SPWM through the occlusion circuit 307. The output of the anti-gate 306 is coupled to the reset input terminal R of the flip-flop 303 to reset the flip-flop 303. The switching signal SPWM is supplied to the signal generator 70 to generate a first drive 201220660 motion signal sH, a second drive signal S1, a first signal s〗, and a second signal S2. The first end of the current source 311 is coupled to the supply voltage Vcc. The switches 3丨2 and 313 are connected in series between the second end of the current source 311 and the anode of the diode. The cathode of the diode 314 is coupled to the reference ground. Both switches 3D and 313 are controlled by a first signal Si. The transistor 316 and the transistor Mg are coupled in series between the supply voltage vcc and the reference ground. The transistor 316 coupled to the supply voltage Vcc is referred to as a high voltage side transistor, and the transistor 318 coupled to the reference ground is referred to as a low voltage. Side transistor. The first drive signal passes through the buffer state 315 to control the transistor 316. The second drive signal S1 controls the transistor 318 through the buffer 3. The common connection point of the transistors 316 and 318 is coupled to the output terminal GATE of the controller 100 to generate a drive signal 〇. The common connection point of the switch 312 and the switch 313 is also coupled to the output terminal GATE of the controller 1 . The output terminal GATE of the control unit is coupled to the positive input terminal of the comparator 31. The negative input of comparator 310 receives a threshold voltage Vt. The output of the comparator 310 is coupled to the first input of the NAND gate 309. The second input of the gate 3〇9 receives the second signal & The output of the anti-gate 3〇9 provides a delay signal sD to the input of the delay circuit 319. The output of delay circuit 319 produces an over temperature signal S〇t to input terminal D of flip flop 303. Figure 5 illustrates a signal generator 70 of a controller 1 in accordance with an embodiment of the present invention. The signal generator 70 includes a sawtooth circuit, a first comparison circuit, a second comparison circuit, and an enable circuit. The sawtooth circuit includes inverters 711 and 712, a current source 713, switches 714 and 715, and a capacitor 716. The first comparison circuit includes a comparator 717 and an inverse OR gate 720. The second comparison circuit includes a comparator 718 and an inverse OR gate 722. In this embodiment, enabling the electrical routing is reversed or gate 721 to be implemented. The first end of the current source 713 is coupled to the power supply 201220660 and the voltage Vcc. Switches 714 and 715 are coupled in series between the second end of current source 713 and the reference ground. The switch 715 is controlled by the switching signal SpwM. The input of the inverter 712 receives the switching signal SpwM. The output of inverter 712 is coupled to the input of inverter 711. The output of the inverter 711 generates a first drive signal Sh. The switching signal Spwm controls the switch 714 through the inverting phase 712. Capacitor 716 is coupled in parallel with switch 715. The ramp voltage VRMP is obtained across the capacitors 7丨6. The ramp voltage vRMP is supplied to the positive terminal of the comparator 717 and the negative terminal of the comparator 718. • The negative terminal of the comparator 717 and the positive terminal of the comparator 718 receive the first reference signal VR1 and the second reference signal Vr2, respectively. The second reference signal level is greater than the first reference signal level. The first input terminals of the inverse gates 720, 721' and 722 both receive the first drive signal SH. The second input of the inverse OR gate 720 is coupled to the output of the comparator 717. The second input of the inverse OR gate 722 is coupled to the output of the comparator 718. The output of the inverse OR gate 720 generates a second drive signal Sl. The second drive signal SL is provided to the second input of the inverse OR gate 721. The output of the inverse gate 721 and the output of the inverse gate 722 respectively generate a first signal Si and a second signal S2. Figure 6 illustrates various waveforms of the controller 1 in accordance with an embodiment of the present invention. Referring also to Figure 5, when the switching signal SPWM is disabled, the switch 714 will be turned "on" and the switch 715 will be turned "off". Current source 713 will charge capacitor 716 through switch 714 to produce ramp voltage VRMP across capacitor 716. Referring to Figure 6, the ramp voltage Vrmp is considered a sawtooth signal. Once the switching signal SPWM is disabled, the first drive signal heart will be disabled. The second drive signal SL will be enabled in accordance with the falling edge of the first drive signal SH. Referring to FIG. 4, the transistor 318 is transmitted through the buffer 317 and 12 201220660 is turned on by the second driving signal sL. The drive signal Vg will therefore be pulled down to the reference ground level (e.g., 0V). Once the ramp voltage Vrmp continues to increase and exceeds the level of the first reference voltage VR1, the second drive signal ^ will be disabled. The first signal Si will be enabled in accordance with the falling edge of the second drive signal S1. This will turn off transistor 318 and turn on switches 312 and 313. Referring to FIG. 3, the thermistor 36 is coupled between the output terminal GATE of the controller 1 and the reference ground. When switches 312 and 313 are turned on by the first signal, a series parasitic resistor (not shown) of diode 314 will pass through the output terminal GATE of control ϋ 1GG in parallel with the thermistor. Since the resistance value of the parasitic resistor of the diode 314 is relatively smaller than the resistance value of the thermistor 36, most of the current supplied by the current source, 3n, will be 々丨1 to one pole 314. At this time, the level of the drive signal is then pulled up to the level of the forward voltage Vf of the diode 3i4. The diode is called the forward voltage VF to ensure the upper limit of the drive signal at this time to avoid the power transistor being turned on during the off period of the switching signal Sp·. The threshold voltage % supplied to the negative terminal of the comparator 310 defines an over temperature condition, and • the threshold voltage VT is less than 1% of the forward power of the diode 314. Since the thermistor 5 36 has a negative temperature coefficient characteristic, the electric f-level of the thermistor (which is also equal to the level of the drive signal %) will decrease as the ambient temperature rises. When the level of the drive signal ν〇 becomes lower than the diode voltage VF, most of the current supplied by the current source 311 will flow to 36. When the level of the drive signal % continuously decreases with the ambient temperature - south and becomes lower than the threshold voltage ^ (for example, at time (4) in FIG. 6), the comparator trains through the anti-gate 306. The delay of the %S delay w Sn delay money Sd# is longer than the delay time provided by the delay 201220660 circuit 319, and the delay circuit 319 will generate the low logic over temperature signal SOT to the input terminal D of the flip flop 303 to disable the switch. Signal SpwM 'This will disable the drive signal Vg to cut off the energy transfer and protect the power converter from over-temperature conditions. - Once the ramp signal VrmP continues to increase and exceeds the level of the second reference voltage VR2 The second signal s2 will be enabled. The enabled second signal S2 will pass the inverse gate 309 to disable the delay signal SD. As long as the second input of the gate 309 receives the disabled second signal S2. The over temperature protection circuit will be disabled. Therefore, the over temperature protection circuit is enabled by the first signal and disabled by the second signal s2. Figure 7 illustrates the delay of the PWM circuit 50 in accordance with an embodiment of the present invention. Circuit 319. Delay circuit 319 is essentially Is a counter comprising series of flip-flops 321, 322, and 326. The clock input ck of these series-connected flip-flops receives the oscillating signal PLS. The reset input R of these series-connected flip-flops receives the delay. Signal SD. When the delay signal SD is enabled, the oscillating signal PLS will drive these flip-flops to generate a delay time. In an embodiment of the invention, the switching period is 10 ps and the delay time is 10 ms. After the delay time, the inverted output of the flip-flop 326 will generate a low logic over-temperature signal SOT. When the delay signal SD is disabled, these flip-flops will be reset and the over-temperature signal S0T will become again High logic. Figure 8 illustrates a method of providing over-temperature protection to a power converter in accordance with an embodiment of the present invention. First, a switching signal is generated (step 1001). Next, a driving signal is generated in accordance with the switching signal to switch the power switch, The power converter is adjusted (step 1002). Then, a sawtooth signal is generated during the off period of the switching signal (step 1003). Then, when the sawtooth 14 201220660 signal exceeds the first parameter At voltage, the over temperature protection circuit is enabled (step 1004). Then, the drive signal is adjusted according to the ambient temperature of the power converter (step 1005). Then, by comparing the drive signal with the threshold voltage, Delaying the signal and generating an over temperature signal after the delay time (step 1006). Finally, when the sawtooth signal exceeds the second reference voltage, the over temperature protection circuit is disabled (step 1007). During the switching signal off period, the drive signal is Adjusted to be below an upper limit. The over temperature signal is used to turn off the power converter. The upper limit is used to avoid the power switch • is turned on during the off period of the switching signal. The second reference signal level is greater than the first reference signal level. The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the scope of the present invention. Any one of ordinary skill in the art can make a few changes without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a conventional power converter; FIG. 2 is a diagram showing a PWM circuit of a controller in a conventional power converter of FIG. 1. FIG. 3 is a diagram showing a power converter according to an embodiment of the present invention; 4 is a PWM circuit of a controller according to an embodiment of the invention; FIG. 5 is a diagram showing a signal generator of a controller according to an embodiment of the invention; FIG. 6 is a diagram showing various waveforms of a controller according to an embodiment of the invention; 7 illustrates a delay circuit of a PWM circuit in accordance with an embodiment of the present invention; 15 201220660 and FIG. 8 illustrates a method of providing over-temperature protection to a power converter in accordance with an embodiment of the present invention. [Major component symbol description] Figure 1: 10, - Transformer is, 11-y rectifier; 12, - Capacitor, 13--resistor; 14~ Zener diode; 15--optical coupler; 16- 'Secondary feedback circuit; 20~ power transistor; 21- / rectifier; 22~ capacitor; 25~ resistor; 30- / pulse width modulation (PWM) circuit; 31, 32, 33~ comparator; 34~ current source; 35- / delay circuit; 36~ thermistor; 37- / resistor; 60~ controller; CS--sensing terminal; FB- / feedback terminal; GATE~ output; GND~ Ground terminal; Ip~ switching current; Na-/auxiliary winding; Np, - primary winding; Ν§~ • secondary winding; RT-^temperature detection terminal; S〇c" - overcurrent signal S〇t/ ~ over temperature signal; Srg " ^ adjustment signal; Vcc ~ supply voltage; Vcs^ ~ sense voltage; Vfb' ~ feedback signal; vG- / drive signal; 16 201220660 vLMT ~ limit voltage; v 〇 ~ output voltage; VT ~ Threshold voltage; VCC ~ power supply terminal.
圖2 : 30〜脈波寬度調變（PWM)電路； 301 〜振盪器； 302- ^反相器； 303 〜正反器； 304- 及閘； 305 、306〜反及閘； 307- -遮沒電路； 308〜緩衝器； ck〜 正反器之頻率輸入端 D〜 正反器303之輸入端 ；PLS 〜振盪信號； Q〜 正反器303之輸出端 5 R〜 正反器303之重置輸入端； S〇c 〜過電流信號； S〇T^ ^過溫度信號； Sp\VM〜切換信號； Srg^ -調節信號； VG- -驅動信號。 圖3 10- -變壓器； 11〜 整流器； 12- -電容器； 13〜 電阻器； 14、 -齊納二極體； 15〜 光耦合器； 16、 “二次側回授電路； 20〜 功率電晶體； 2卜 -整流器； 22〜 電容器； 25〜電阻器； 31、 32〜比較器 36- “熱敏電阻器； 37〜 電阻器； 50〜脈波寬度調變（PWM)電路； 17 201220660Figure 2: 30 ~ pulse width modulation (PWM) circuit; 301 ~ oscillator; 302 - ^ inverter; 303 ~ forward and reverse; 304 - and gate; 305, 306 ~ reverse gate; 307 - - cover No circuit; 308~buffer; ck~ frequency inverter input terminal D~ input terminal of flip-flop 303; PLS~ oscillation signal; Q~ output terminal of Rectifier 303 5 R~ Set input; S〇c ~ over current signal; S〇T^ ^ over temperature signal; Sp\VM~ switching signal; Srg^ - adjustment signal; VG- - drive signal. Figure 3 10--transformer; 11~ rectifier; 12--capacitor; 13~ resistor; 14, Zener diode; 15~ optocoupler; 16, "secondary feedback circuit; 20~ power Crystal; 2 b - rectifier; 22 ~ capacitor; 25 ~ resistor; 31, 32 ~ comparator 36 - "Thermistor; 37 ~ resistor; 50 ~ pulse width modulation (PWM) circuit; 17 201220660
100〜控制器； CS〜感測端； FB〜回授端； GATE〜輸出端； GND〜接地端； Ip〜切換電流； NA〜辅助繞組； Np〜一次側繞組； Ns〜二次側繞組； Soc〜過電流信號； SRG〜調節信號； Vcc〜供電電壓； Vcs〜感測電壓； VFB〜回授信號； VG〜驅動信號； Vlmt〜限制電壓； v0〜輸出電壓； VCC〜供電端。 圖4 50〜脈波寬度調變（PWM)電路； 70〜信號產生器； 301〜振盪器； 302〜反相器； 303〜正反器； 304〜及閘； 305、306〜反及閘； 307〜遮沒電路； 309〜反及閘； 310〜比較器； 311〜電流源； 312、313〜開關； 314〜二極體； 315〜緩衝器； 316〜電晶體； 317〜緩衝器； 318〜電晶體； 319〜延遲電路； ck〜正反器303之時脈輸入端； D〜正反器303之輸入端 j GATE〜輸出端； PLS〜振盪信號； Q〜正反器303之輸出端 18 201220660100~controller; CS~ sensing terminal; FB~ feedback terminal; GATE~output terminal; GND~ground terminal; Ip~ switching current; NA~ auxiliary winding; Np~ primary side winding; Ns~ secondary side winding; Soc ~ over current signal; SRG ~ adjustment signal; Vcc ~ supply voltage; Vcs ~ sense voltage; VFB ~ feedback signal; VG ~ drive signal; Vlmt ~ limit voltage; v0 ~ output voltage; VCC ~ power supply terminal. Figure 4 50 ~ pulse width modulation (PWM) circuit; 70 ~ signal generator; 301 ~ oscillator; 302 ~ inverter; 303 ~ forward and reverse; 304 ~ and gate; 305, 306 ~ reverse gate; 307~mask circuit; 309~reverse gate; 310~ comparator; 311~current source; 312, 313~switch; 314~diode; 315~buffer; 316~ transistor; 317~buffer; 〜 _ _ _ _ _ 18 201220660
R〜正反器303之重置輸入端； s 1〜第一信號； S2〜第二信號； Sd〜延遲信號； Sh〜第一驅動信號； SL〜第二驅動信號； S〇c〜過電流信號； SpWM〜切換信號； Srg〜調節信號； S〇t〜過溫度信號； vcc〜供電電壓； VG〜驅動信號； Vr〜臨界值電壓。 圖5 70〜信號產生器； 711、712〜反相器； 713〜電流源； 714、715〜開關； 716〜電容器； 717、718〜比較器； 720、721、722〜反或閘 S1〜第一信號； S2〜第二信號； Sh〜第一驅動信號； SL〜第二驅動信號； SpWM〜切換信號； vcc〜供電電壓； VR1〜第一參考信號； Vrmp〜斜坡信號。 VR2〜第二參考信號 圖6 : A〜時間點； S 1〜第一信號； S2〜第二信號； Sh〜第一驅動信號； Sl〜第二驅動信號； S P WM〜切換信號； VF〜二極體314之正向電壓； VG〜驅動信號； VR1〜第一參考信號； 19 201220660 vR2〜第二參考信號 ； Vrmp 〜 斜坡信號； VT〜臨界值電壓。 圖7 : 319〜延遲電路； 321、322、326〜正反器 ck〜正反器之時脈輸入端； D〜正反器之輸入端； GATE〜輸出端； PLS〜振盪信號； Q〜正反器之輸出端；R~reset input terminal of regula 303; s 1~first signal; S2~second signal; Sd~delay signal; Sh~first drive signal; SL~second drive signal; S〇c~over current Signal; SpWM~ switching signal; Srg~ regulating signal; S〇t~ over temperature signal; vcc~ supply voltage; VG~ drive signal; Vr~ threshold voltage. Figure 5 70 ~ signal generator; 711, 712 ~ inverter; 713 ~ current source; 714, 715 ~ switch; 716 ~ capacitor; 717, 718 ~ comparator; 720, 721, 722 ~ reverse or gate S1 ~ a signal; S2 ~ second signal; Sh ~ first drive signal; SL ~ second drive signal; SpWM ~ switch signal; vcc ~ supply voltage; VR1 ~ first reference signal; Vrmp ~ ramp signal. VR2 ~ second reference signal Figure 6: A ~ time point; S 1 ~ first signal; S2 ~ second signal; Sh ~ first drive signal; Sl ~ second drive signal; SP WM ~ switch signal; VF ~ two Forward voltage of the polar body 314; VG~ drive signal; VR1~first reference signal; 19 201220660 vR2~ second reference signal; Vrmp~ ramp signal; VT~threshold voltage. Figure 7: 319 ~ delay circuit; 321, 322, 326 ~ forward and reverse ck ~ forward and reverse clock input; D ~ positive and negative input; GATE ~ output; PLS ~ oscillating signal; Q ~ positive The output of the counter;
ρ〜正反器之反相輸出端； R〜正反器之重置輸入端； S〇t〜過溫度信號； SD〜延遲信號；ρ~ inverting output of the flip-flop; R~ reset input of the flip-flop; S〇t~over temperature signal; SD~delay signal;
Vcc〜供電電壓。 圖8 . 1001... 1007〜方法步驟。Vcc~ supply voltage. Figure 8. 1001... 1007~ Method steps.
2020