201133235 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明涉及一種電腦狀態偵測電路。 【先前技秫ί】 [0002] 習知的電腦經常會工作在複數不同的狀態，例如S3狀態 (睡眠狀態）、S4狀態（深度睡眠狀態）等，用戶也可 以在BIOS (基本輸入輸出系統，Basic Input/Output Sy s t em )裡設定電腦的一些功能狀態，例如網路喚醒處 於有效或無效狀態等。有時用戶需獲知目前電腦所處的 狀態，以期望電腦在其預想的狀態下工作。惟，目前獲 知電腦所處狀態的方法大都根據電腦的外部表現的特徵 來作判斷，由此使得用戶需花費一定的時間與精力，並 且極容易出錯，無法在短時間内作出正確判斷，因此其 準確度和效率極低。 【發明内容】 [0003] 鑒於以上内容，有必要提供一種可自動偵測電腦各狀態 的電腦狀態偵測電路，方便用戶查看。 [0004] 一種電腦狀態偵測電路，包括第一至第三電開關及一第 •一發光二極體，第一電開關的第一端連接該第一發光二 極體的陰極，還透過一第一電阻連接一第一電源，該第 一發光二極體的陽極透過一第二電阻連接該第一電源， 該第一電開關的第二端連接一主機板上的深度睡眠狀態 引腳，該第一電開關的第三端連接該第二電開關的第一 端，該第二電開關的第二端連接該第三電開關的第一端 ，該第二電開關的第三端接地，該第三電開關的第一端 099109104 表單編號A0101 第4頁/共17頁 0992016250-0 201133235 還透過一第三電阻連接該第一電源，該第三電開關的第 二端連接主機板上的睡眠狀態引腳，該第三電開關的第 三端接地，當電腦在睡眠狀態時，該睡眠狀態引腳為低 電平，該第三電開關截止，該第一及第二電開關導通， 該第一發光二極體導通並發光。 [0005] Ο [0006] ❹ [0007] 本發明電腦狀態偵測電路透過電腦在睡眠狀態時該睡眠 狀態引腳為低電平，該第三電開關截止，該第一及第二 電開關導通，該第一發光二極體導通並發光，實現了自 動偵測並即時顯示電腦的工作狀態，便於用戶查看。 【實施方式】 如圖1所示，本發明電腦狀態偵測電路用於偵測一電腦的 工作狀態（S3、S4狀態）、網路狀態及硬碟工作狀態， 還用於偵測網路喚醒功能、網路啟動功能、低電源功能 及管理引擎（Management Engine)功能的無效及有效 狀態，其較佳實施方式包括一主機板插槽（如前置面板 插槽）F1、一S3狀態偵測電路10、一S4狀態偵測電路20 、一硬碟工作狀態偵測電路30、一結果顯示電路40及一 南橋晶片5 0。 該主機板插槽F1包括兩接地引腳2、4、兩電源引腳5、14 、一S3狀態引腳6、一S4狀態引腳8、一 S5狀態引腳10、 一網路引腳12、一開機引腳1、一網路喚醒功能引腳3、 一管理引擎功能引腳7、一低電源功能引腳9、一網路啟 動功能引腳11及一硬碟工作狀態引腳13。接地引腳2及4 接地。開機引腳1連接一開機訊號端PWRBT。電源引腳5連 接電源VI，還透過一電容C1接地。電源引腳14連接電源 099109104 表單編號A0101 第5頁/共17頁 0992016250-0 201133235 V2 ’還透過一電容C2接地。在本實施方式中，該電源^ 為3. 3伏特的備用（stand by )電源，該電源V2為3 3 伏特的系統電源。 [〇〇〇8] 該S3狀態偵測電路10包括場效應電晶體、Q2及Q3、電 阻R1及R2。場效應電晶體Q1的汲極連接結果顯示電路4〇 ，還透過電阻R1連接電源VI。場效應電晶體…的閘極連 接S4狀態引腳8 ◊場效應電晶體Q1的源極連接場效應電晶 體Q2的汲極。場效應電晶體Q2的源極接地。場效應電晶 體Q2的閘極連接場效應電晶體Q3的汲極。場效應電晶體 Q3的汲極還透過電阻R2連接電源VI。場效應電晶體q3的 閘極連接S3狀態引腳6。場效應電晶體Q3的源極接地。在 本實施方式中，場效應電晶體Q1、Q2及Q3作為電開關均 為一NM0S型場效應電晶體，在其他實施方式中，也可採 用其他類型的電開關，例如NPN型電晶體等。 [0009]該S4狀態偵測電路20包括場效應電晶體Q4、Q5及Q6、電 阻R3及R4。場效應電晶體Q4的汲極速接結果顯示電路4〇 ’還透過電阻R3連接電源VI。場效應電晶體Q4的閘極連 接S5狀態引腳1〇。場效應電晶體Q4的源極連接場效應電 晶體Q5的汲極。場效應電晶體Q5的源極接地。場效應電 晶體Q5的閘極連接場效應電晶體Q6的汲極。場效應電晶 體Q6的汲極透過電阻以連接電源VI。場效應電晶體卯的 閘極連接S4狀態引腳8。場效應電晶體Q6的源極接地。在 本實施方式中，場效應電晶體Q4、Q5及Q6作為電開關均 為一NMOS型場效應電晶體，在其他實施方式中，也可採 用其他類型的電開關，例如NPN型電晶體等。 099109104 表單編號A0101 第6頁/共17頁 0992016250-0 201133235 [0010] 該硬碟工作狀態偵測電路30包括兩電晶體叭及㈧、電阻 R5-R8。電晶體Q7的集極連接硬碟工作狀態引腳13，還 透過電阻R5連接電源V2，電晶體Q7的射極接地，電晶體 Q7的基極透過電阻{?6連接電源¥2，還連接電晶體卯的集 極，電晶體Q8的射極接地，電晶體⑽的基極透過電阻尺？ 連接南橋晶月50的硬碟控制引_SA。電阻R8的一端連接 電源V2，電阻R8的另一端連接電阻R7與南橋晶片5〇的硬 碟控制引腳SA之間的節點。在本實施方式中，電晶體… 及Q8作為電開關均為一NPN型電晶體。在其他實施方式中 ’也可採用其他類型的電開關，例如NM〇s型場效應電晶 體等。 [0011] 戎結果顯示電路40包括8個發光二極艟led卜LED8、電阻 R9-R19。發光二極體LED1的陽極透過電阻⑽連接電源^ ，陰極連接場效應電晶體Q4的汲極。發光二極體^⑽的 陽極透過電阻R10連接電源V卜陰極連接場效應電晶體Qi 的汲極。發光二極體LED3的陽極透過電阻R11連接電源 〇 V1，陰極連接管理引擎功能引腳7。發光二極體LED4的陽 極透過電阻R12連接電源vi，陰極連接網路啟動功能引腳 11，還透過電阻R13連接電源η。發光二極體LED5的陽 極透過電阻R14連接電源Π ’陰極連接低電源功能引腳9 ，還透過電阻R15連接電源VI。發光二極體LED6的陽極 透過電阻R16連接電源VI，陰極連接網路喚醒功能引腳3 ，還透過電阻R17連接電源VI。發光二極體LED7的陽極 透過電阻R18連接電源V2，陰極連接網路引腳12。發光二 極體LED8的陽極透過電阻R19連接電源”，陰極連接硬 099109104 表單編號A0101 第7頁/共17頁 0992016250-0 201133235 碟工作狀態引腳13。 [0012] 下面詳細介紹本發明電腦狀態偵測電路偵測電腦的工作 及功能狀態的工作過程： [0013] S3狀態引腳6、S4狀態引腳8、引腳及S5狀態引腳10在電 腦處於S0 (正常工作）、S3(睡眠）、S4(深度睡眠） 及S5 (關機）狀態時的電平如下表所示： 引腳 S0狀態的 S3狀態的 S4狀態的 S 5狀態的 電平 電平 電平 電平 S3狀態引 低 低 I 低 腳6 S4狀態引 南 低 低 腳8 S5狀態引 南 南 低 腳10 低電源功能引腳9、網路喚醒功能引腳3、網路啟動功能 引腳11及管理引擎功能引腳7在有效狀態（Enable)和 無效狀態（Disable)時的電平如下表所示： 引腳 有效狀態電平 無效狀態電平 低電源功能引腳9 低 南 網路喚醒功能引腳3 低 1¾ 網路啟動功能引腳 低 南 11 管理引擎功能引腳7 低 S3狀態偵測過程：當電腦在S3 (睡眠）狀態時，S3狀態 099109104 表單編號A0101 第8頁/共17頁 0992016250-0 201133235 引腳6為低電平，S4狀態引腳8為高電平，場效應電晶體 Q3截止，場效應電晶體Q2的閘極為高電平，場效應電晶 體Q2導通，場效應電晶體Q1的閘極為高電平，場效應電 晶體Q1導通，場效應電晶體Q1的汲極為低電平，發光二 極體LED2導通並發光，指示電腦處於S3狀態。反之，發 光二極體LED2截止不發光，指示電腦不處於S3狀態。 [0016] S4狀態偵測過程：當電腦在S4 (深度睡眠）狀態時，S4 狀態引腳8為低電平，S5狀態引腳10為高電平，場效應電 晶體Q6截止，場效應電晶體Q5的閘極為高電平，場效應 〇 電晶體Q5導通’場效應電晶體Q4的間極為高電平，場效 應電晶體Q4導通’場效應電..晶體、Q4的渡極為低電平，發 光二極體LED1導通並發光，指示電腦處於S4狀態。反之 +i1-+.+![+: ' !-.rv： >·; ’發光二極體LED1截止不發光，指示電腦不處於S4狀態 〇 [0017] 管理引擎功能偵測過程：當管理引擎處於有效狀態時， 管理引擎功能引腳7為低電平，發光二極體LED3導通並發 〇 光，指示管理引擎處於有效狀態。當管理引擎處於無效 狀態時，管理引擎功能引腳7為高電平，發光二極體LED3 截止不發光’指示管理引擎處於無效狀態。 [0018] 網路啟動功能偵測過程：當網路啟動功能處於有效狀態 時，網路啟動功能引腳11為低電平，發光二極體LED4導 通並發光，指示網路啟動功能處於有效狀態。當網路啟 動功能處於無效狀態時，網路啟動功能引腳11為高電平 ，發光二極體LED4截止不發光，指示網路啟動功能處於 無效狀態。 099109104 表單編號A0101 第9頁/共17頁 0992016250-0 201133235 [0019] 低電源功能偵測過程：當低電源功能處於有效狀態時， 低電源功能引腳9為低電平，發光二極體LED5導通並發光 ，指示低電源功能處於有效狀態。當低電源功能處於無 效狀態時，低電源功能引腳9為高電平，發光二極體LED5 截止不發光，指示低電源功能處於無效狀態。 [0020] 網路喚醒功能偵測過程：當網路喚醒功能處於有效狀態 時，網路喚醒功能引腳3為低電平，發光二極體LED6導通 並發光，指示網路喚醒功能處於有效狀態。當網路喚醒 功能處於無效狀態時，網路喚醒功能引腳3為高電平，發 光二極體LED6截止不發光，指示網路喚醒功能處於無效 狀態。 [0021] 網路狀態偵測過程：當電腦插接上網線時，網路引腳1 2 為低電平，發光二極體LED7導通並發光，指示電腦已插 接網線。當電腦未插接上網線時，網路引腳1 2為高電平 ，發光二極體LED7截止不發光，指示電腦未插接網線。 [0022] 硬碟工作狀態偵測過程：當凌碟處於傳輸資料狀態時， 南橋晶片50的硬碟控制引腳SA輸出高低電平的脈衝，當 南橋晶片50的硬碟控制引腳SA輸出高電平時，電晶體Q8 導通，電晶體Q7截止，硬碟工作狀態引腳13為高電平， 發光二極體LED8截止不發光，當南橋晶片50的硬碟控制 引腳SA輸出低電平時，電晶體Q8截止，電晶體Q7導通， 硬碟工作狀態引腳13為低電平，發光二極體LED8導通並 發光，這樣發光二極體LED8 —亮一滅，指示電腦硬碟處 於傳輸資料狀態。 099109104 表單編號A0101 第10頁/共17頁 0992016250-0 201133235 _]本發明電腦狀態福測電路透過發光二極體L E m - L E D 8是 否發光自動偵測及指示電腦的工作及各個功能狀態，可 、將么光—極體LED1 -LED8設置於電腦機箱的前置面板 或其他部件上，以即時準確地顯示電腦各個狀態，便 =用戶查看，如此，實現了電腦各狀態的自動债測，提 面了偵測的效率及準確度。 [0024] 〇 綜上所述，本發明符合發明專利要件，爰依法提出專利 申請。惟’以上所述者僅為本發明之較佳實施例，舉凡 熟悉本案技藝之人士，在纽本發明精神所作之等效修 飾或變化，皆應涵蓋於以下之申請專利範圍内。 【圖式簡單說明】 [0025] 圖1係本發明電腦狀態偵測電路的較佳實施方式的電路圖 〇 :、： + 【主要元件符號說明】 [0026] 主機板插槽：F1 [0027] S3狀態偵測電路：1〇 〇 [0028] S4狀態偵測電路：2 0 [0029] 硬碟工作狀態偵測電路：30 [0030] 結果顯示電路：40 [0031] 南橋晶片：50 [0032] 場效應電晶體：Q1-Q6 [0033] 電晶體：Q7、Q8 099109104 表單編號A0101 第11頁/共17頁 0992016250-0 201133235201133235 VI. Description of the Invention: [Technical Field of the Invention] [0001] The present invention relates to a computer state detection circuit. [Previous Technology] [0002] Conventional computers often work in a variety of different states, such as S3 state (sleep state), S4 state (deep sleep state), etc., and users can also use BIOS (basic input and output system, Basic Input/Output Sy st em ) sets some functional states of the computer, such as whether the network wakeup is active or inactive. Sometimes the user needs to know the current state of the computer in order to expect the computer to work as expected. However, the current methods of knowing the state of the computer are mostly judged according to the characteristics of the external performance of the computer, which makes the user take a certain amount of time and energy, and is extremely error-prone and cannot make a correct judgment in a short time, so Accuracy and efficiency are extremely low. SUMMARY OF THE INVENTION [0003] In view of the above, it is necessary to provide a computer state detection circuit that can automatically detect various states of the computer, which is convenient for the user to view. [0004] A computer state detecting circuit includes first to third electrical switches and a first light emitting diode, wherein a first end of the first electrical switch is connected to a cathode of the first light emitting diode, and The first resistor is connected to the first power source, the anode of the first LED is connected to the first power source through a second resistor, and the second end of the first electrical switch is connected to a deep sleep state pin on the motherboard. The third end of the first electric switch is connected to the first end of the second electric switch, the second end of the second electric switch is connected to the first end of the third electric switch, and the third end of the second electric switch is grounded The first end of the third electric switch 099109104 Form No. A0101 Page 4 / Total 17 page 0992016250-0 201133235 The first power source is also connected through a third resistor, and the second end of the third electric switch is connected to the motherboard a sleep state pin, the third end of the third electrical switch is grounded, when the computer is in a sleep state, the sleep state pin is low, the third electrical switch is turned off, and the first and second electrical switches are turned on The first light emitting diode is turned on and emits light. [0006] [0006] The computer state detecting circuit of the present invention is low when the sleep state is in a sleep state by the computer, the third electrical switch is turned off, and the first and second electrical switches are turned on. The first light-emitting diode is turned on and emits light, which realizes automatic detection and instantly displays the working state of the computer, which is convenient for the user to view. [Embodiment] As shown in FIG. 1, the computer state detecting circuit of the present invention is used for detecting the working state (S3, S4 state), network state and hard disk working state of a computer, and is also used for detecting network wake-up. The function, the network boot function, the low power function, and the management engine function are invalid and valid. The preferred embodiment includes a motherboard slot (such as a front panel slot) F1, an S3 state detection. The circuit 10, an S4 state detecting circuit 20, a hard disk working state detecting circuit 30, a result display circuit 40, and a south bridge chip 50. The motherboard slot F1 includes two ground pins 2, 4, two power pins 5, 14, an S3 state pin 6, an S4 state pin 8, an S5 state pin 10, and a network pin 12. A boot pin 1, a network wake-up function pin 3, a supervisor engine function pin 7, a low power function pin 9, a network boot function pin 11, and a hard disk operating state pin 13. Ground pins 2 and 4 are grounded. The power-on pin 1 is connected to a power-on signal terminal PWRBT. Power pin 5 is connected to the power supply VI and is also grounded through a capacitor C1. Power pin 14 is connected to the power supply. 099109104 Form No. A0101 Page 5 of 17 0992016250-0 201133235 V2 ' is also grounded through a capacitor C2. In the present embodiment, the power supply is a 3.3 volt standby (stand by) power supply, and the power supply V2 is a 3 3 volt system power supply. [8] The S3 state detecting circuit 10 includes field effect transistors, Q2 and Q3, and resistors R1 and R2. The drain connection result display circuit 4 of the field effect transistor Q1 is also connected to the power source VI through the resistor R1. The gate of the field effect transistor... is connected to the S4 state pin 8. The source of the field effect transistor Q1 is connected to the drain of the field effect transistor Q2. The source of the field effect transistor Q2 is grounded. The gate of the field effect transistor Q2 is connected to the drain of the field effect transistor Q3. The drain of the field effect transistor Q3 is also connected to the power supply VI through the resistor R2. The gate of field effect transistor q3 is connected to S3 state pin 6. The source of the field effect transistor Q3 is grounded. In the present embodiment, the field effect transistors Q1, Q2, and Q3 are each an NM0S type field effect transistor as an electrical switch. In other embodiments, other types of electrical switches, such as an NPN type transistor, may also be used. The S4 state detecting circuit 20 includes field effect transistors Q4, Q5 and Q6, and resistors R3 and R4. The draining result display circuit 4' of the field effect transistor Q4 is also connected to the power source VI through the resistor R3. The gate of field effect transistor Q4 is connected to the S5 state pin 1〇. The source of field effect transistor Q4 is connected to the drain of field effect transistor Q5. The source of the field effect transistor Q5 is grounded. The gate of field effect transistor Q5 is connected to the drain of field effect transistor Q6. The drain of the field effect transistor Q6 is transmitted through a resistor to connect to the power source VI. The gate of the field effect transistor 连接 is connected to the S4 state pin 8. The source of the field effect transistor Q6 is grounded. In the present embodiment, the field effect transistors Q4, Q5, and Q6 are each an NMOS type field effect transistor as an electrical switch. In other embodiments, other types of electrical switches, such as an NPN type transistor, may be used. 099109104 Form No. A0101 Page 6 of 17 0992016250-0 201133235 [0010] The hard disk working state detecting circuit 30 includes two transistors and (8) and resistors R5-R8. The collector of transistor Q7 is connected to the hard disk working state pin 13, and is also connected to the power supply V2 through the resistor R5. The emitter of the transistor Q7 is grounded, and the base of the transistor Q7 is transmitted through the resistor {?6 to connect the power supply to ¥2, and is also connected to the battery. The collector of the crystal germanium, the emitter of the transistor Q8 is grounded, and the base of the transistor (10) is transmitted through the resistor. Connect the hard disk control _SA of Nanqiao Jingyue 50. One end of the resistor R8 is connected to the power source V2, and the other end of the resistor R8 is connected to a node between the resistor R7 and the hard disk control pin SA of the south bridge wafer 5. In the present embodiment, the transistors... and Q8 are all an NPN-type transistor as an electrical switch. Other types of electrical switches may be employed in other embodiments, such as NM〇s type field effect transistors and the like. [0011] The result display circuit 40 includes eight light-emitting diodes LEDs 8 and resistors R9-R19. The anode of the light-emitting diode LED1 is connected to the power source through the resistor (10), and the cathode is connected to the drain of the field effect transistor Q4. The anode of the light-emitting diode (10) is connected to the drain of the power supply V and the cathode connected to the field effect transistor Qi through the resistor R10. The anode of the LED 3 is connected to the power supply 〇 V1 through the resistor R11, and the cathode is connected to the management engine function pin 7. The anode of the LED 2 is connected to the power supply vi through the resistor R12, the cathode is connected to the network start function pin 11, and the power supply η is also connected through the resistor R13. The anode of the LED 2 is connected to the power supply Π ' cathode connected to the low power function pin 9 through the resistor R14, and is also connected to the power source VI through the resistor R15. The anode of the LED 6 is connected to the power supply VI through the resistor R16, the cathode is connected to the network wake-up function pin 3, and the power supply VI is also connected through the resistor R17. The anode of the LED LED 7 is connected to the power source V2 through a resistor R18, and the cathode is connected to the network pin 12. The anode of the LED LED8 is connected to the power supply through the resistor R19, and the cathode is connected to the hard 099109104. Form No. A0101 Page 7 / Total 17 Page 0992016250-0 201133235 Disc Operation Status Pin 13. [0012] The computer state detection of the present invention is described in detail below. The test circuit detects the working and functional status of the computer: [0013] S3 status pin 6, S4 status pin 8, pin and S5 status pin 10 are in the computer at S0 (normal operation), S3 (sleep) The levels in the S4 (deep sleep) and S5 (off) states are as follows: Level S level of the S5 state of the S3 state of the S0 state S3 state Level level S3 State low I Low pin 6 S4 state leads south low pin 8 S5 state leads south south low pin 10 low power function pin 9, network wake-up function pin 3, network start function pin 11 and management engine function pin 7 are valid The levels at the Enable and Disable states are as follows: Pin Active State Level Invalid State Level Low Power Function Pin 9 Low South Wake-up Function Pin 3 Low 13⁄4 Network Start Function lead Low South 11 Management Engine Function Pin 7 Low S3 Status Detection Process: When the computer is in S3 (Sleep) state, S3 Status 099109104 Form No. A0101 Page 8 / Total 17 Pages 0992016250-0 201133235 Pin 6 is Low The S4 state pin 8 is at a high level, the field effect transistor Q3 is turned off, the gate of the field effect transistor Q2 is extremely high, the field effect transistor Q2 is turned on, and the gate of the field effect transistor Q1 is extremely high, the field The effect transistor Q1 is turned on, the field effect transistor Q1 is extremely low level, the light emitting diode LED2 is turned on and emits light, indicating that the computer is in the S3 state. Conversely, the light emitting diode LED2 is turned off and does not emit light, indicating that the computer is not in the S3 state. [0016] S4 state detection process: When the computer is in the S4 (deep sleep) state, S4 state pin 8 is low level, S5 state pin 10 is high level, field effect transistor Q6 is off, field effect The gate of transistor Q5 is extremely high, the field effect 〇 transistor Q5 is turned on. The field effect transistor Q4 is extremely high, and the field effect transistor Q4 is turned on. The field effect is electric. The crystal and Q4 are extremely low. Flat, LED diode 1 is turned on and Lights up, indicating that the computer is in S4 state. Otherwise +i1-+.+![+: ' !-.rv: >·; 'Lighting diode LED1 is not illuminated, indicating that the computer is not in S4 state 〇[0017] Management Engine function detection process: When the management engine is in the active state, the management engine function pin 7 is low level, and the LED LED3 is turned on and the light is turned on, indicating that the management engine is in an active state. When the supervisor engine is in an inactive state, the supervisor engine function pin 7 is high and the LED LED3 is turned off and does not emit light, indicating that the supervisor engine is in an invalid state. [0018] The network startup function detection process: when the network startup function is in an active state, the network startup function pin 11 is at a low level, and the LED LED 4 is turned on and emits light, indicating that the network startup function is in an active state. . When the network start function is in an inactive state, the network start function pin 11 is at a high level, and the LED 2 is turned off and does not emit light, indicating that the network start function is in an inactive state. 099109104 Form No. A0101 Page 9 of 17 0992016250-0 201133235 [0019] Low power function detection process: When the low power function is active, the low power function pin 9 is low, LED LED5 Turns on and illuminates, indicating that the low power function is active. When the low power function is in an inactive state, the low power function pin 9 is at a high level, and the light emitting diode LED5 is turned off and does not emit light, indicating that the low power function is in an inactive state. [0020] The network wake-up function detection process: when the network wake-up function is in an active state, the network wake-up function pin 3 is low, and the LED LED 6 is turned on and emits light, indicating that the network wake-up function is in an active state. . When the network wake-up function is in an inactive state, the network wake-up function pin 3 is at a high level, and the light-emitting diode LED 6 is turned off and does not emit light, indicating that the network wake-up function is in an inactive state. [0021] Network state detection process: When the computer is plugged into the Internet cable, the network pin 1 2 is low level, and the LED LED 7 is turned on and emits light, indicating that the computer has been plugged into the network cable. When the computer is not plugged into the Internet cable, the network pin 1 2 is at a high level, and the LED LED 7 is turned off and does not emit light, indicating that the computer is not plugged into the network cable. [0022] Hard disk working state detecting process: when the spinning disk is in the transmission data state, the hard disk control pin SA of the south bridge chip 50 outputs a high and low level pulse, when the hard disk control pin SA of the south bridge chip 50 outputs high At the level, the transistor Q8 is turned on, the transistor Q7 is turned off, the hard disk working state pin 13 is at a high level, and the light emitting diode LED 8 is turned off and does not emit light. When the hard disk control pin SA of the south bridge wafer 50 outputs a low level, The transistor Q8 is turned off, the transistor Q7 is turned on, the hard disk working state pin 13 is low level, and the light emitting diode LED 8 is turned on and emits light, so that the light emitting diode LED 8 is turned on and off, indicating that the computer hard disk is in the state of transmitting data. 099109104 Form No. A0101 Page 10 / Total 17 Pages 0992016250-0 201133235 _] The computer state measuring circuit of the present invention automatically detects and indicates the operation of the computer and various functional states through the LEDs of the LEDs LE m - LED 8 The light-polar LED1-LED8 is placed on the front panel or other components of the computer case to instantly and accurately display the various states of the computer, so that the user can view it, thus realizing the automatic debt measurement of each state of the computer. The efficiency and accuracy of detection. [0024] In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. However, the above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by the inventor of the present invention should be included in the following claims. BRIEF DESCRIPTION OF THE DRAWINGS [0025] FIG. 1 is a circuit diagram of a preferred embodiment of a computer state detecting circuit of the present invention:,: + [Description of main component symbols] [0026] Motherboard slot: F1 [0027] S3 State detection circuit: 1〇〇[0028] S4 state detection circuit: 2 0 [0029] Hard disk working state detection circuit: 30 [0030] Result display circuit: 40 [0031] Southbridge chip: 50 [0032] Field Effect transistor: Q1-Q6 [0033] Transistor: Q7, Q8 099109104 Form No. A0101 Page 11 of 17 0992016250-0 201133235
[0034] 發光二極體：LED卜LEM[0034] Light Emitting Diode: LED Bu LEM
[0035] 電容：Cl、C2 [0036] 電阻：R1 - R1 9 099109104 表單編號A0101 第12頁/共17頁 0992016250-0[0035] Capacitance: Cl, C2 [0036] Resistance: R1 - R1 9 099109104 Form No. A0101 Page 12 of 17 0992016250-0