201121109 31988twf.doc/n 六、發明說明： 【發明所屬之技術領域】 且 的發光二極 【先前技術】 發光近it ^發光"極體光效率销提升，使得 3-極體在某些領域已漸漸取代日光燈與白熱燈泡 速反應的掃描器燈源、液晶顯示器的背光源或前 先源 >'車的儀表板照明、交通號紐，以及—般的 置等。一般常見的發光二極體係屬於—種半導體元件，^ 材料通常係使用III-V族元素如舰鎵（GaP)、坤化嫁 (GaAs)等。發光二極體的發光原理是將電能轉換為光， 也就疋對上述之化合物半導體施加電流，透過電子、電洞201121109 31988twf.doc/n VI. Description of the invention: [Technical field of invention] Light-emitting diodes [Prior Art] Light-emitting near-^luminescence"polar body light efficiency pin lifting, making 3-pole body in some fields It has gradually replaced the scanner light source of the fluorescent lamp and the white heat bulb, the backlight of the liquid crystal display or the front panel of the vehicle, the traffic light, and the general setting. Generally, the common light-emitting diode system belongs to a kind of semiconductor component, and the material generally uses a group III-V element such as a gallium (GaP) or a GaAs. The principle of illumination of a light-emitting diode is to convert electrical energy into light, that is, to apply current to the compound semiconductor described above, through electrons and holes.
的結合而將過剩的能量以光的型態釋放出來，進而達到發 光的效果。 X 圖1A〜圖ID為習知之一種發光二極體晶片的製作流 程圖。請參照圖1A，首先，提供一半導體基板11〇，其中 此半導體基板110包括一磊晶基板112以及一位於蟲晶基 板112的一第一表面ii2a上的一半導體層114。半導體層 114包括一 η型半導體層114a、一發光層11仙以及一 p 型半導體層114c，其中η型半導體層114a配置於兹晶基 板U2上’而發光層114b位於η型半導體層i14a與p型 201121109 31988twf.doc/n 半導體層114c之間。 接著，利用雷射製程於半導體基板u〇上形成多個凹 槽120，其中這些凹槽12〇位於磊晶基板112的一相對第 一表面112a的第二表面ii2b，且這些凹槽12〇暴露出部 分η型半導體層114a，如圖所示。 然後，於磊晶基板112的第二表面U2b上與凹槽112 内形成一導熱材料層130，如圖1C所示。導熱材料層130 的材質例如是使用金屬、合金或其他適合的導熱材料，如 此，導熱材料層130除了可用以散熱外，也可視為發光二 極體晶片的一電極。 之後，於p型半導體層114C上形成另一電極142,如 圖1D所不。至此大致完成一種習知垂直式的發光二極體 曰曰片100。身又而吕，施加一電壓差於導熱材料廣13〇斑 電極142之間時’發光層1121)將會發光，且在發光層u2b 發光的同時會有熱產生。 採用前述圖1A至圖1D的製程方法所形成位於第二 癱表面112b上的凹槽12〇結構雖然有助於提高發光二極體 100的散熱面積，從而提升其散熱速度。 no的材質通常散熱性質不佳，且厚度偏厚而因= 前述技術的步驟後並無法使磊晶基板11〇的厚度獲得適當 地縮減，如此會使得散熱路徑無法有效獲得降^，進而^ 成發光二極體晶片100的散熱速度提升有限。 ^外’在使用雷射製程貫穿基板11(Ux形成暴露出η 型半¥體層114a的凹槽120結構時，由於蟲晶基板ιι〇 201121109 31988twi.doc/n 的厚度並未獲得適當地縮減，因此會增加雷射製程的困難 度。再者’雷射貫穿蠢晶基板110的厚度大小會盘製作成 本成正比，因此也會造成製造成本的負擔。 【發明内容】 有鑑於此，本發明提供一種發光二極體晶片的製造方 法，其可製造出散熱能力較佳、製程困難度較低、以及成 本較低廉的發光二極體晶片。 枣發明提出 ，工《〜一H肢曲片的衮适万法，豆包4 下列步驟。首S，提供—基板，其中基板具有—第二表6 ::第—表面的第二表面。接著，於基板的第-的靜夕個凹槽，其中凹槽分別具有-深度，且基本 ==凹度。然後，形成一半導體層於編 :二層其::導置於基板上· 雜半導騎與帛二卵料及赌第一型. 著，縮、诗其扨沾/雜+V體層之間的一發光層。· 第二表面:與==凹?貫穿基板。然後，於基板 層上形成至少—電2成一導熱材料層。接著，於半導‘ 法 在本發明之1_中，、贼基㈣核包括一研磨 在本發明之一,, 。 、β ，被縮減後的基板的厚度等於 在本發明之一眘始也,丨山 J中，被縮減後的基板的厚度小於 201121109 31988twf.doc/n 深度。 在本發明之一實施例中， 上介於Ιμιη至ΙΟΟμιη之間。 在本發明之一實施例中 500μιη 之間。 被縮減後的基板的厚度實質 凹槽的直徑介於1 μιη至 在本發明之一實施例中，導熱材料層的厚度實質上介 於Ιμηι至ΙΟΟμιη之間。The combination of the excess energy is released in the form of light, thereby achieving the effect of illuminating. X Figure 1A to Figure ID are flow diagrams of a conventional light-emitting diode wafer. Referring to FIG. 1A, first, a semiconductor substrate 11 is provided. The semiconductor substrate 110 includes an epitaxial substrate 112 and a semiconductor layer 114 on a first surface ii2a of the insect crystal substrate 112. The semiconductor layer 114 includes an n-type semiconductor layer 114a, a light-emitting layer 11 and a p-type semiconductor layer 114c, wherein the n-type semiconductor layer 114a is disposed on the zigzag substrate U2 and the light-emitting layer 114b is located at the n-type semiconductor layer i14a and p Type 201121109 31988twf.doc/n between the semiconductor layers 114c. Then, a plurality of grooves 120 are formed on the semiconductor substrate u by a laser process, wherein the grooves 12 are located on the second surface ii2b of an opposite first surface 112a of the epitaxial substrate 112, and the grooves 12 are exposed A portion of the n-type semiconductor layer 114a is formed as shown. Then, a layer of thermally conductive material 130 is formed on the second surface U2b of the epitaxial substrate 112 and the recess 112, as shown in FIG. 1C. The material of the heat conductive material layer 130 is, for example, a metal, an alloy or other suitable heat conductive material. Therefore, the heat conductive material layer 130 can be regarded as an electrode of the light emitting diode chip in addition to heat dissipation. Thereafter, another electrode 142 is formed on the p-type semiconductor layer 114C as shown in Fig. 1D. Thus, a conventional vertical light-emitting diode chip 100 has been substantially completed. When the voltage is different from the heat conductive material, the light-emitting layer 1121 will emit light, and heat will be generated while the light-emitting layer u2b emits light. The groove 12〇 structure formed on the second surface 112b by the above-described process method of FIGS. 1A to 1D helps to increase the heat dissipation area of the light-emitting diode 100, thereby increasing the heat dissipation speed. The material of no usually has poor heat dissipation properties, and the thickness is too thick. Therefore, the thickness of the epitaxial substrate 11〇 cannot be appropriately reduced after the steps of the foregoing techniques, so that the heat dissipation path cannot be effectively reduced, and thus The heat dissipation speed of the LED chip 100 is limited. ^Outside' when the laser process is used to penetrate the substrate 11 (Ux forms a recess 120 structure exposing the n-type half body layer 114a, since the thickness of the insect crystal substrate ιι〇201121109 31988twi.doc/n is not appropriately reduced, Therefore, the difficulty of the laser process is increased. Furthermore, the thickness of the laser through the stray substrate 110 is proportional to the manufacturing cost of the disk, and thus also causes a burden on the manufacturing cost. [Invention] In view of this, the present invention provides A method for manufacturing a light-emitting diode wafer, which can produce a light-emitting diode chip with better heat dissipation capability, lower process difficulty, and lower cost. The invention of the jujube is proposed, the work of the "H-[H] limb piece适法法,豆包4 The following steps: First S, providing a substrate, wherein the substrate has a second surface of the second surface of the substrate: the second surface of the substrate: The grooves have a depth of - and a basic == concavity. Then, a semiconductor layer is formed on the second layer: the second layer is placed on the substrate. The semi-conducting rider and the second egg are gambling and the first type. Between the poetry and the smear / miscellaneous + V body layer Light-emitting layer. · Second surface: and == concave? through the substrate. Then, at least - electrically formed into a layer of heat conductive material on the substrate layer. Next, in the semi-conductive method in the 1_ of the present invention, (4) The core comprises a grinding in one of the inventions, and the thickness of the reduced substrate is equal to one of the thicknesses of the substrate of the present invention, and the thickness of the substrate after being reduced is less than 201121109 31988 twf.doc In one embodiment of the present invention, the upper portion is between Ιμιη and ΙΟΟμιη. In one embodiment of the present invention, between 500 μm. The thickness of the reduced substrate is substantially the diameter of the groove between 1 μm In an embodiment of the invention, the thickness of the layer of thermally conductive material is substantially between Ιμηι and ΙΟΟμιη.
在本發明之一實施例中，導熱材料層可為金屬或合金 材料。在本發明之一實施例中，導熱材料層可為銅、銀、 金、鑷、鉬、鋁、銀或及其合金。 在本發明之-實施例中，在形成導熱材料層之前，更 包括在凹槽内形成多個歐姆接觸層，以與半導體声連接。 在本發明之一實施例中，基板為-絕緣基板^而半導 體層的形成紐包括下列步驟。首先，在第—表面上 第一型摻雜半導體層。織n型摻雜半導體層I开； 成發光層。接著’在發光層切成第二雜料導體^ 在本發明之-實施财，在形成至少―電極: 包括^辩賴層，峰㈣部分第-歸科導體層更 在本發明之-實施例中，於半導體層上形成至少—曰 ί包驟第形ί:第—電極於第二型摻雜半導體層 層上。$成—4二祕於被暴露出的第-型摻雜半導體 更 在本發明之-實施财，在形成導崎料層 包括在凹槽㈣成残介電層，以與半導體層連接。 201121109 3iy88twt.doc/n 的過程中，貫施例巾，在形成第—雜雜半導體層 、^括形成-絕緣層於第-型摻料導體層内。 實施例中，絕緣層的材f包括氮化铭、 = 鎵錢純、氮化贿（A1如xN，_ 瞧以⑽9tf碳、鎮之氣化録或氛化_(他伽讽 雷美：本：二之—實施例中’基板為一具有-接合層的導 2基板成半導騎於導電基板时法包括下列步 :U’在-蟲晶基板上形成第—型摻雜半導體層。然 γ 一型摻雜半導體層上形成發光層。接著，在發光 ί上形成第二型摻雜半導體層，其中第-型掺雜半i體 ^、發光層與第二型摻雜半導體層構成半導體層。而後， 提供具有—黏著層的轉移基板，並藉由黏 板與半導體層接合。接著，移除蟲晶基板，以將半 轉移至轉移基板上。紐，藉域合層使導電基板與 體層接合。接著，移除轉移基板。 在本發明之一實施例中，形成第一型摻雜半導體層的 過程中，更包括形成一絕緣層於第一型摻雜半導體層内。 基於上述，本發明之發光二極體晶片的製造方法藉由 先於基板上形成多個凹槽，而後再形成半導體層於凹^所 在的基板表面上，並iig減基板的厚度直到凹槽貫穿基板。 如此，覆蓋導熱材料層於凹槽内時，便可增加基板與導熱 材料層的表面積，從而提高散熱速度。同時，基板的厚度 被適當地縮減後，亦縮短了散熱路徑，進而更進一步地提 201121109 31988twf.doc/n 升散熱效果。 為讓本發日狀上料徵和優點缺日物祕，下文特 舉實施例，並配合所附圖式作詳細說明如下。 【實施方式】 圖2A至圖2F為本發明一實施例之發光二極體晶片的 製作流程剖面圖，而圖2C，至圖2F，為本發明另一實施形態In an embodiment of the invention, the layer of thermally conductive material may be a metal or alloy material. In one embodiment of the invention, the layer of thermally conductive material may be copper, silver, gold, rhenium, molybdenum, aluminum, silver, or alloys thereof. In an embodiment of the invention, prior to forming the layer of thermally conductive material, a plurality of ohmic contact layers are formed in the recess to acoustically connect with the semiconductor. In an embodiment of the invention, the substrate is an insulating substrate and the formation of the semiconductor layer comprises the following steps. First, the first type is doped with a semiconductor layer on the first surface. The n-type doped semiconductor layer I is opened; into a light-emitting layer. Then, 'cutting the light-emitting layer into the second impurity conductor ^ in the present invention - in forming at least "electrode: including the arbitrage layer, the peak (four) portion of the - - - - - - - - - - - - - - - - Forming at least one of the semiconductor layers on the semiconductor layer: the first electrode is on the second type doped semiconductor layer. The first type-doped semiconductor is exposed. In the present invention, the formation of the gas-conducting layer includes a dielectric layer in the recess (4) to be connected to the semiconductor layer. In the process of 201121109 3iy88twt.doc/n, a pattern is formed, in which a first impurity-type semiconductor layer is formed, and an insulating layer is formed in the first-type dopant conductor layer. In the embodiment, the material f of the insulating layer includes nitriding, = gallium pure, brix brittle (A1 such as xN, _ 瞧 with (10) 9tf carbon, gasification of the town or atmosphere _ (He Jiajiao Leimei: Ben In the embodiment, the substrate is a semiconducting substrate having a bonding layer, and the method comprises the following steps: U' forming a first-type doped semiconductor layer on the insect substrate. Forming a light-emitting layer on the γ-type doped semiconductor layer. Then, forming a second-type doped semiconductor layer on the light-emitting layer, wherein the first-type doped semiconductor layer, the light-emitting layer and the second-type doped semiconductor layer form a semiconductor Then, a transfer substrate having an adhesive layer is provided, and bonded to the semiconductor layer by the adhesive layer. Then, the insect crystal substrate is removed to transfer the semiconductor to the transfer substrate. The bulk layer is bonded. Then, the transfer substrate is removed. In an embodiment of the invention, the forming of the first type doped semiconductor layer further includes forming an insulating layer in the first type doped semiconductor layer. The method for manufacturing a light-emitting diode wafer of the present invention is preceded by Forming a plurality of grooves on the plate, and then forming a semiconductor layer on the surface of the substrate on which the recess is located, and reducing the thickness of the substrate until the groove penetrates the substrate. Thus, when the layer of the heat conductive material is covered in the groove, the substrate can be increased. The surface area of the layer of thermally conductive material increases the heat dissipation rate. At the same time, the thickness of the substrate is appropriately reduced, and the heat dissipation path is also shortened, thereby further improving the heat dissipation effect of 201121109 31988 twf.doc/n. The present invention is described in detail below with reference to the accompanying drawings. [Embodiment] FIG. 2A to FIG. 2F illustrate the fabrication of a light-emitting diode wafer according to an embodiment of the present invention. Flowchart cross-sectional view, and FIG. 2C to FIG. 2F, another embodiment of the present invention
之發光,極體晶片的製作流程剖面圖，其中圖，〜圖迚， 係為延續目2A至圖2B的製程步驟。首先，請表考圖2八， 提供-基板210，其中基板21〇具有—第—表面2i2以及 -相對於第-表面212的第二表面214。在本實施例中， 基板210的材質例如為介電（絕緣）材料。舉例而言，基 板210可以疋監寶石基板，或是以i化紹或碳化梦為材質 的基板。 接著，於基板210的第一表面212上形成多個凹槽 216，其中這些凹槽216分別具有一深度Hi ，且基板210 的厚度H2大於這些深度H卜如圖2B所示。在本實施例 中，形成凹槽216的方法例如是使用傳統的雷射製程進行 钱刻。舉例^言，可以使肖高能量的雷射光束照射於基板 21〇的第一表面212上，藉以形成如圖2B所繪示的凹槽 此外根據雷射光束的大小，凹槽216的直徑D亦 會Ik之而變。在本實施例中’凹槽216的直徑〇可以是介 於Ιμηι至500μιη之間。 另外’由於凹槽216的深度Η1小於基板210的厚度 201121109 3iy»5twt.doc/n ，因此，本實施例所使用的雷射製程並無須將基板 貝穿以形成類似習知技術所提及的凹槽12〇(可同時參照圖 1B與圖2B)。換言之，本實施例在進行雷射製程的步驟時°， 便可縮減製程所需的時間、降低製程的困難度以及製程所 需的能量，從而可提高製程的可靠度以及降低整體製作的 成本。需要說明的是，凹槽216的深度H1可隨使用 需求而定，其可以是介於Ιμιη與100μηι之間。 之後，形成一半導體層220於基板21〇的第一表面212 上，其中半導體層220包括一配置於基板21〇上的第一型 ，雜半導體層222、-第二型摻雜半導體層224以及位於 第一型摻雜半導體層222與第二型摻雜半導體層224之間 的一發光層226 ’如圖2C所示。在本實施例中，形成半導 體層220的方法可以是使用傳統蟲晶方式依序形成第一型 摻雜半導體層222、發光層226與第二型摻雜半導體層224 於基板210的第一表面212上，藉以形成如圖％所緣示 的半導體層220。 另外，第一型摻雜半導體層222可以是N型摻雜半導 體層，而第二型摻雜半導體層224可以是p型換雜半導體 層二或是，第一型摻雜半導體層222為p型摻雜半導體層， 而第-型摻雜半導體層224為N型摻雜半導體層。在本實 施例中，發光層226可為—多重量子井結構(MultipleThe illuminating, cross-sectional view of the fabrication process of the polar body wafer, wherein the figure, the figure 迚, is the process step of continuing the object 2A to 2B. First, please refer to FIG. 28, which provides a substrate 210 in which the substrate 21 has a first surface 2i2 and a second surface 214 with respect to the first surface 212. In the present embodiment, the material of the substrate 210 is, for example, a dielectric (insulating) material. For example, the substrate 210 can be used to monitor a gemstone substrate, or a substrate made of a material or a carbonized dream. Next, a plurality of grooves 216 are formed on the first surface 212 of the substrate 210, wherein the grooves 216 respectively have a depth Hi, and the thickness H2 of the substrate 210 is greater than the depths H as shown in FIG. 2B. In the present embodiment, the method of forming the recess 216 is, for example, a conventional laser process. For example, a high-energy laser beam can be irradiated onto the first surface 212 of the substrate 21 to form a groove as shown in FIG. 2B. Further, according to the size of the laser beam, the diameter D of the groove 216. It will also change. In the present embodiment, the diameter 〇 of the groove 216 may be between Ιμηι and 500 μm. In addition, since the depth Η1 of the groove 216 is smaller than the thickness of the substrate 210 201121109 3iy»5twt.doc/n, the laser process used in the embodiment does not need to be worn to form a substrate similar to that mentioned in the prior art. The groove 12 is (refer to both FIG. 1B and FIG. 2B). In other words, in the embodiment, when the laser processing step is performed, the time required for the process, the difficulty of the process, and the energy required for the process can be reduced, thereby improving the reliability of the process and reducing the cost of the overall fabrication. It should be noted that the depth H1 of the groove 216 may be determined according to the needs of use, and may be between Ιμιη and 100μηι. Thereafter, a semiconductor layer 220 is formed on the first surface 212 of the substrate 21A, wherein the semiconductor layer 220 includes a first type, a hetero semiconductor layer 222, a second type doped semiconductor layer 224, and a second semiconductor layer 224 disposed on the substrate 21A. A light-emitting layer 226' between the first type doped semiconductor layer 222 and the second type doped semiconductor layer 224 is as shown in FIG. 2C. In this embodiment, the method of forming the semiconductor layer 220 may be to sequentially form the first type doped semiconductor layer 222, the light emitting layer 226 and the second type doped semiconductor layer 224 on the first surface of the substrate 210 by using a conventional insect crystal method. 212, whereby the semiconductor layer 220 as shown in FIG. In addition, the first type doped semiconductor layer 222 may be an N-type doped semiconductor layer, and the second type doped semiconductor layer 224 may be a p-type doped semiconductor layer 2 or the first type doped semiconductor layer 222 may be p The doped semiconductor layer is doped, and the first doped semiconductor layer 224 is an N-type doped semiconductor layer. In this embodiment, the luminescent layer 226 can be a multiple quantum well structure (Multiple
Quantum Well，MQW)。 在另一只施形悲中，在形成前述的第一型摻雜半導體 層222的過程中，可於第一型摻雜半導體層222内形成- 201121109 31988twf.doc/n 絕緣層222a，如圖2C’所示。絕緣層222a的材質例如是氮 化紹、低溫成長之氮化鎵或氮化鋁，氮化鋁鎵 (AlxGauNCO.OOlSXsow%)或摻雜碳、鎂之氮化鎵或氮 化紹鎵(AlxGauxNCO.OOlgXSO^W)。詳細而言，低溫成 長之氮化鎵或氮化鋁鎵(AlxGauxNCO.OOl $ XS 0.999))或摻 雜碳、鎮之氮化鎵或氮化鋁鎵(AlxGaixN (；〇〇〇1$χ$ 0.999))的成長溫度介於攝氏3〇〇度到8〇〇度之間。此外， 摻雜碳的碳摻雜源的材質包括四溴化碳(CB1·4)或四氣化碳 攀（CC14)。 在分別完成前述圖2C與圖2C’的步驟後，接著，縮 減基板210的厚度H2直到凹槽216貫穿基板210，如圖 2D與圖2D’所示。在本實施例中，縮減基板21〇的厚度 H2的方法例如是使用一研磨法於第二表面214上進行研 磨，藉以縮減基板210的厚度H2直到凹槽216貫穿基板 210 ’意即被縮減後的基板21〇的厚度H3等於凹槽216的 深度m。 ® 需要說明的是’在凹槽216貫穿基板210之後仍可持 續使用研磨法繼續縮減基板210的厚度H3，使得被縮減厚 度的基板210的厚度H3小於原凹槽216的深度H1。在本 實施例中，被縮減後的基板21〇的厚度H3實質上可介於 Ιμηι 至 ΙΟΟμιη 之間。 在分別完成圖2D與圖2D，的步驟後，接著，於基板 210的第二表面214上與凹槽216内形成一導熱材料層 230，如圖2Ε與圖2Ε’所繪示。在本實施例中，形成導熱 11 201121109 3iy8«twi.doc/n 材料層230的方法包括濺鍍、化學氣相沉積及電鍍等適合 的形成方法。在圖2E中，導熱材料層230可採用金屬、 合金或其他適合的導熱材料，如：銅、銀、金、鑷、鉬、 鋁、銀或及其合金等等。此時，導熱材料層230可視為發 光_一極體晶片的—電極。而在圖2E’中，導熱材料層230 除了可使用鈾述的導熱材料外，也可使用一般常見的導熱 材料。另外’上述的導熱材料層230的厚度實質上可介於 Ιμιη 至 ΙΟΟμιη 之間。 在完成圖2Ε的步驟後，接著，於半導體層220上形 成一電極Ε1，如圖2F所示。在本實施例中，形成電極E1 可以疋使用金屬氣化化學氣相沉積法或是其他適當的製 程。至此大致完成一種垂直式發光二極體晶片200的製作 方法。需要說明的是，有時為了提高半導體層與導熱 材料層230之間的導電性，更可在進行圖2E的步驟之前， 於凹槽216内形成多個歐姆接觸層242,以與半導體層220 連接。/如此一來，在進行前述的圖2E與圖2F的步驟後， 便會形成另一種垂直式發光二極體晶片2〇〇a，如圖2G 緣示。 在另一實施形態中，於完成圖2E’的步驟後，圖案化 半導體層220以暴露出部分第一型摻雜半導體層222了並 形成二第一電極E2於第二型摻雜半導體層224上以及形 成第一電極E3於被暴露出的第一型摻雜半導體層222 上，如圖2F，所示。在本實施例中，圖案化半導體芦 的方式例如是使用乾式侧、濕式軸彳或其他適當^刻 12 201121109 31988twf.doc/n 製程。另外，形成電極E2、E3的方式可以是使用金屬氧 化化學氣相沉積法或其他適當的製程。至此大致完成一種 水平式發光二極體晶片300的製作方法。 在水平式發光二極體晶片300中，由於第一型摻雜半 導體層222内形成有絕緣層222a，因此驅動電流j會在第 一電極E2與第二電極E3之間的半導體層22〇進行&遞， 而不同於垂直式發光二極體晶片是以電極E1與導電材料 層230作為正負電極的結構。因此，水平式發光二極體晶 片300可達到電熱分離的效果。需要說明的是，有時為了 避免半導體層220與導熱材料層230產生電性連接而造成 短路的可能性，更可在進行圖2E，的步驟之前，於凹槽216 内形成多個介電層244，以與半導體層22〇連接。如此一 來，在進行前述的圖2E’與圖2F，的步驟後，便會形成另一 種水平式發光二極體晶片3〇〇a，如圖2G，所繪示。 、，承上述，由於垂直式發光二極體晶片200、200a與水 平式發光二極體晶片3〇〇、3〇〇a係採用如圖2A至圖以 及圖fC至圖2F’所描述的製作方式，因此可降低製程時 1製私的困難度以及製作成本。另外，透過上述的製作 步驟除了製作出可增加基板210與導熱材料層230的表面 凹槽216結構外，同時更藉由基板210的厚度被適當 土縮減，從而縮短了發光二極體晶片200、200a、300、300a 的散熱路徑。 另外，當基板210為一具有一接合層218的導電基板 ^則形成其上的半導體層220可以下列方法達成之。 13 201121109 jiiy88twt.doc/n 圖3A〜圖3E為本發明另一實施例之形成半導體層於 基板的製造流程剖面圖。首先，請參照圖3A，在一磊晶基 板310上形成前述的第一型摻雜半導體層222。接著，在 第一型摻雜半導體層222上形成前述的發光層226。然後， 在發光層226上形成前述的第二型摻雜半導體層224，其 中第一型掺雜半導體層222、發光層226與第二型摻雜半 導體層224構成前述的半導體層220。Quantum Well, MQW). In another process of forming the first type doped semiconductor layer 222, the insulating layer 222a may be formed in the first type doped semiconductor layer 222, as shown in FIG. 2C' is shown. The material of the insulating layer 222a is, for example, nitriding, low-growth gallium nitride or aluminum nitride, aluminum gallium nitride (AlxGauNCO.OOlSXsow%) or doped carbon, magnesium gallium nitride or gallium nitride (AlxGauxNCO. OOlgXSO^W). In detail, low-temperature growth of gallium nitride or aluminum gallium nitride (AlxGauxNCO.OOl $ XS 0.999) or doped carbon, town of gallium nitride or aluminum gallium nitride (AlxGaixN (;〇〇〇1$χ$ The growth temperature of 0.999)) is between 3 degrees Celsius and 8 degrees Celsius. In addition, the material of the carbon doped carbon doping source includes carbon tetrabromide (CB1·4) or carbon tetrachloride (CC14). After the steps of the foregoing Figs. 2C and 2C' are respectively completed, the thickness H2 of the substrate 210 is then reduced until the recess 216 penetrates the substrate 210 as shown in Figs. 2D and 2D'. In the present embodiment, the method of reducing the thickness H2 of the substrate 21 is, for example, grinding on the second surface 214 using a grinding method, thereby reducing the thickness H2 of the substrate 210 until the groove 216 penetrates the substrate 210', that is, after being reduced The thickness H3 of the substrate 21A is equal to the depth m of the groove 216. ® It should be noted that the thickness H3 of the substrate 210 can be continuously reduced by the grinding method after the groove 216 penetrates the substrate 210, so that the thickness H3 of the substrate 210 whose thickness is reduced is smaller than the depth H1 of the original groove 216. In the present embodiment, the thickness H3 of the reduced substrate 21A may be substantially between Ιμηι and ΙΟΟμιη. After completing the steps of FIG. 2D and FIG. 2D, respectively, a layer of thermally conductive material 230 is formed on the second surface 214 of the substrate 210 and the recess 216, as shown in FIG. 2A and FIG. In the present embodiment, a method of forming the heat conductive layer 11 201121109 3iy8 «twi.doc / n material layer 230 includes a suitable forming method such as sputtering, chemical vapor deposition, and plating. In FIG. 2E, the layer of thermally conductive material 230 may be a metal, alloy, or other suitable thermally conductive material such as copper, silver, gold, tantalum, molybdenum, aluminum, silver, or alloys thereof, and the like. At this time, the heat conductive material layer 230 can be regarded as an electrode of a light-emitting body wafer. In Fig. 2E', the thermally conductive material layer 230 may be a commonly used thermally conductive material in addition to the uranium heat conductive material. Further, the thickness of the above-mentioned thermally conductive material layer 230 may be substantially between Ιμιη to ΙΟΟμιη. After the step of Fig. 2A is completed, next, an electrode ?1 is formed on the semiconductor layer 220 as shown in Fig. 2F. In the present embodiment, the electrode E1 may be formed by metal gasification chemical vapor deposition or other suitable processes. Thus, a method of fabricating a vertical light-emitting diode wafer 200 has been substantially completed. It should be noted that, in order to improve the conductivity between the semiconductor layer and the heat conductive material layer 230, a plurality of ohmic contact layers 242 may be formed in the recess 216 to form the semiconductor layer 220 before the step of FIG. 2E is performed. connection. / Thus, after performing the aforementioned steps of FIG. 2E and FIG. 2F, another vertical light-emitting diode wafer 2A is formed, as shown in FIG. 2G. In another embodiment, after the step of FIG. 2E′ is completed, the semiconductor layer 220 is patterned to expose a portion of the first type doped semiconductor layer 222 and form two first electrodes E2 and a second type doped semiconductor layer 224. And forming a first electrode E3 on the exposed first type doped semiconductor layer 222, as shown in FIG. 2F. In the present embodiment, the patterning of the semiconductor reed is, for example, a dry side, a wet shaft, or other suitable process 12 201121109 31988 twf.doc/n. Alternatively, the electrodes E2, E3 may be formed by metal oxide chemical vapor deposition or other suitable processes. Thus, a method of fabricating a horizontal light-emitting diode wafer 300 has been substantially completed. In the horizontal light-emitting diode wafer 300, since the insulating layer 222a is formed in the first-type doped semiconductor layer 222, the driving current j is performed on the semiconductor layer 22 between the first electrode E2 and the second electrode E3. And, unlike the vertical light-emitting diode wafer, the electrode E1 and the conductive material layer 230 are used as the positive and negative electrodes. Therefore, the horizontal light-emitting diode wafer 300 can achieve the effect of electrothermal separation. It should be noted that, in order to avoid the possibility of short circuit caused by the electrical connection between the semiconductor layer 220 and the heat conductive material layer 230, a plurality of dielectric layers may be formed in the recess 216 before the step of FIG. 2E is performed. 244 is connected to the semiconductor layer 22A. Thus, after the steps of Fig. 2E' and Fig. 2F described above are performed, another horizontal light emitting diode chip 3A is formed, as shown in Fig. 2G. According to the above, since the vertical light-emitting diode chips 200, 200a and the horizontal light-emitting diode chips 3〇〇, 3〇〇a are fabricated as described in FIG. 2A to FIG. 2F and FIG. In this way, the difficulty of manufacturing and the manufacturing cost can be reduced. In addition, through the above-mentioned fabrication steps, in addition to the structure of the surface recess 216 which can increase the substrate 210 and the heat conductive material layer 230, and at the same time, the thickness of the substrate 210 is appropriately reduced, thereby shortening the light-emitting diode wafer 200, The heat dissipation path of 200a, 300, and 300a. In addition, when the substrate 210 is a conductive substrate having a bonding layer 218, the semiconductor layer 220 formed thereon can be achieved by the following method. 13 201121109 jiiy88twt.doc/n FIG. 3A to FIG. 3E are cross-sectional views showing a manufacturing process of forming a semiconductor layer on a substrate according to another embodiment of the present invention. First, referring to FIG. 3A, the aforementioned first type doped semiconductor layer 222 is formed on an epitaxial substrate 310. Next, the foregoing light-emitting layer 226 is formed on the first-type doped semiconductor layer 222. Then, the aforementioned second type doped semiconductor layer 224 is formed on the light emitting layer 226, wherein the first type doped semiconductor layer 222, the light emitting layer 226 and the second type doped semiconductor layer 224 constitute the aforementioned semiconductor layer 220.
之後，請參照圖3B，提供一具有一黏著層322的轉 移基板320，並藉由黏著層322使轉移基板320與半導體 層220接合。接著，請參照圖3C，移除磊晶基板21〇以將 半‘體層220轉移至轉移基板320上。然後，請參照圖3d， 藉由接合層218使導電基板C與半導體層22〇接合。之後， π參照圖3E’移除轉移基板320以將半導體層220轉移至 導電基板C上。至此大致完成一種利用轉移基板的方法， 將半‘體層220轉移至具有接合層218的導電基板c，藉 以完成前述形成半導體層22〇於基板21〇的步驟。 S 綜上所述，本發明之發光二極體晶片的製造方法至少 具有下列優點。首先，於基板上形成多個凹槽，並於凹槽 所在t基板表面上形成半導體層後，縮減基板的厚度直到 凹槽貝穿基板。如此將可有效地縮減製程所需的時間、降 低製程的困難度以及製程所需的能量，從而可提高製程的 可靠度以及降低整體製作的成本。 另外，由於基板的厚度被適當地縮減，因此覆蓋導熱 材料層於凹槽内時，除了可增加基板與導熱材料層的表面 14 201121109 31988twf.d〇c/n 積外，亦縮紐了散熱路徑，進而更進一步地提升散熱效果。 換&之’採用本發明之發光二極體晶片的製造方法可製作 出散熱表現較佳、製程較為簡易、以及成本較低廉的發光 二極體晶片。 雖然本發明已以實施例揭露如上，然其並非用以限定 本發明’任何所屬技術領域中具有通常知識者，在不脫離 本發明之精神和範圍内，當可作許之更動與潤飾，故本發 ^ 明之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1A〜圖1D為習知之一種發光二極體晶片的製作流 程圖。 圖2A至圖2F為本發明一實施例之發光二極體晶片的 製作流程剖面圖。 圖2G為本發明另''貫施例之發光—極體晶片的剖面 圖。 % 圖2C，至圖2F，為本發明另一實施形態之發光二極體 晶片的製作流程剖面圖。 圖2G，為本發明另一實施例之發光二極體晶片的剖面 圖。 圖3A〜圖3E為本發明另一實施例之形成半導體層 220於基板210的製造流程剖面圖。 15 201121109 jiy«8twi.aoc/n 【主要元件符號說明】 100、200、200a、300、300a :發光二極體晶片 110 :半導體基板 112、310 ·蟲晶基板 112a、212 :第一表面 114、220 :半導體層 114a : η型半導體層 114b、226 :發光層 114c : p型半導體層 120、216 :凹槽 112b、214 :第二表面 130、230 :導熱材料層 142、E1 :電極 210 :基板 218 :接合層 222 :第一型摻雜半導體層 222a :絕緣層 224 :第二型摻雜半導體層 242 :歐姆接觸層 244 :介電層 320 :轉移基板 322 :黏著層 C:導電基板 D :直徑 E2 :第一電極 E3 :第二電極 H1 :深度 H2、H3 :厚度Thereafter, referring to FIG. 3B, a transfer substrate 320 having an adhesive layer 322 is provided, and the transfer substrate 320 is bonded to the semiconductor layer 220 by an adhesive layer 322. Next, referring to FIG. 3C, the epitaxial substrate 21 is removed to transfer the semi-body layer 220 onto the transfer substrate 320. Then, referring to FIG. 3d, the conductive substrate C and the semiconductor layer 22 are bonded by the bonding layer 218. Thereafter, π is removed from the transfer substrate 320 with reference to FIG. 3E' to transfer the semiconductor layer 220 onto the conductive substrate C. Thus, a method of transferring a substrate is generally completed, and the semi-body layer 220 is transferred to the conductive substrate c having the bonding layer 218, thereby completing the step of forming the semiconductor layer 22 to the substrate 21A. In summary, the method of manufacturing a light-emitting diode wafer of the present invention has at least the following advantages. First, a plurality of grooves are formed on the substrate, and after the semiconductor layer is formed on the surface of the substrate where the groove is located, the thickness of the substrate is reduced until the groove penetrates the substrate. This will effectively reduce the time required for the process, reduce the difficulty of the process, and the energy required for the process, thereby improving process reliability and reducing overall manufacturing costs. In addition, since the thickness of the substrate is appropriately reduced, when the layer of the heat conductive material is covered in the groove, in addition to increasing the surface of the substrate and the surface of the heat conductive material, the heat dissipation path is also reduced. , and further improve the heat dissipation effect. By using the method of manufacturing a light-emitting diode wafer of the present invention, a light-emitting diode wafer having a better heat dissipation performance, a simpler process, and a lower cost can be produced. The present invention has been disclosed in the above embodiments, but it is not intended to limit the invention to those skilled in the art, and it can be modified and retouched without departing from the spirit and scope of the invention. The scope of protection of this document is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A to Fig. 1D are flowcharts showing the fabrication of a conventional light-emitting diode wafer. 2A to 2F are cross-sectional views showing a manufacturing process of a light-emitting diode wafer according to an embodiment of the present invention. Fig. 2G is a cross-sectional view showing a light-emitting body wafer of another embodiment of the present invention. 2C to 2F are cross-sectional views showing a manufacturing process of a light-emitting diode wafer according to another embodiment of the present invention. Fig. 2G is a cross-sectional view showing a light emitting diode wafer according to another embodiment of the present invention. 3A to 3E are cross-sectional views showing a manufacturing process of forming a semiconductor layer 220 on a substrate 210 according to another embodiment of the present invention. 15 201121109 jiy«8twi.aoc/n [Description of main component symbols] 100, 200, 200a, 300, 300a: light-emitting diode wafer 110: semiconductor substrate 112, 310 - insect crystal substrate 112a, 212: first surface 114, 220: semiconductor layer 114a: n-type semiconductor layer 114b, 226: light-emitting layer 114c: p-type semiconductor layer 120, 216: groove 112b, 214: second surface 130, 230: heat conductive material layer 142, E1: electrode 210: substrate 218: bonding layer 222: first type doped semiconductor layer 222a: insulating layer 224: second type doped semiconductor layer 242: ohmic contact layer 244: dielectric layer 320: transfer substrate 322: adhesive layer C: conductive substrate D: Diameter E2: first electrode E3: second electrode H1: depth H2, H3: thickness