201114002 六、發明說明： 【發明所屬之技術領域】 本發明係有關一種封裝結構之製法，尤指一種用以形 成具有對外電性連接點之封裝結構之製法。 【先前技術】 . 傳統半導體封裝結構係以導線架（Lead Frame)作為晶 片承載件，於該導線架上接置半導體晶片，而該導線架係 具有一晶片座及形成於該晶片座周圍之複數引腳，將該半 • 導體晶片固設於該晶片座上’並以焊線電性連接該半導體 晶片與引腳後’再以封裝材包覆該半導體晶片、晶片座、 焊線以及引腳之内段而形成具有導線架之半導體封裝結 習知以導線架作為晶片承載件之半導體封裝結構之 型態及種類繁多，如 QFP (Quad Flat Package)、QFN (Quad-Flat Non-leaded)、SOP (Small Outline Package)、或 I DIP (Dual in-line Package)等，而為提昇半導體封裝結構之 散熱效率與兼顧晶片尺寸封裝（Chip Scale Package, CSP)之 小尺寸要求，目前多以晶片座底部外露之QFN半導體封裝 結構或露墊式(Exposed Pad)半導體封裝結構為封裝主流。 對於QFN半導體封裝結構而言，其特徵在於未設置 有外引腳’即未形成有如習知四邊形平面半導體封裝結構 (QFP)中用以與外界電性連接之外引腳，因而得以縮小半導 體封裝結構之尺寸。 請蒼閱第]A及1B圖所示之習知qFN半導體封裝結 1Π366 201114002 構示意圖5其中，該第Jfl於、s π 第认圖之俯視圖；如圖所示==’而該第ιβ圖係為 y、係方；具有引腳1 1之導牟 =10上固設半導體晶片12,且該半 = 連接至該引腳1於該導線架晶…。 架晶==引及焊線13上形成封裳材14，並使該導線 ΑΛ 腳11之底面外露於該封裝材】4身而由 該QFN半導體封裝結構藉由 / :4 (圖式中未表不）而與係如印刷電路板（P_ed circuit ⑽d)(圖式中未表示）之外部裝置電性連接。 ! 隹f知之半導體封裝結構係僅於其 ==:的排列形式與數量受到較大的限制: 接二: = 裝結構的對外 目前題解決的^艮⑩不易制等問題，實已成為 【發明内容】 鑑於上述習知技術之種種缺失，本發明之 提供一種具有較佳之對外電性連接點之封裝結構之 為達上述及其他目的，本發明揭露_種封裝 =’係包括：提供-具有相對兩表面之承載單元，於其: =上均具有第-金屬層’·於該第—金屬層上[、全 屬層，·於該第二金屬層上形成複數電性接觸塾；^:金 金屬層與電性接觸墊上形成—介電層，並於該介 成線路層，且於該介電層中形成複數電性連接該綠静Γ 】Π366 201114002 電性接觸墊之導電盲孔，且該線路層復具有複數分區之打 < 線墊，而各該分區之打線墊具有複數打線墊，其中，該介 ， 電層之材料可為 ABF (Ajinomoto Build-up Film)、BCB (Benzocyclo-buthene)、LCP (Liquid Crystal Polymer)、PI (Poly-imide) ' PPE (Poly (phenylene ether)) ' PTFE (Poly - (tetra-fluoroethylene))、FR4、FR5、BT (Bismaleimide Triazine)、芳香尼龍(Aramide)、或混合環氧樹脂玻璃纖維 (Glass fiber);於該介電層與該線路層上形成絕緣保護 鲁層，且該絕緣保護層中形成複數開孔，以令各該分區之打 線墊對應露出於各該開孔，而形成上下成對的整版面封裝 基板’其中’形成該絕緣保護層之材料可為ABF(Ajinomoto Build-up Film) ' BCB(Benzocyclo-buthene) ' LCP(Liquid201114002 VI. Description of the Invention: [Technical Field] The present invention relates to a method of fabricating a package structure, and more particularly to a method for forming a package structure having an external electrical connection point. [Previous Technology] A conventional semiconductor package structure uses a lead frame as a wafer carrier on which a semiconductor wafer is attached, and the lead frame has a wafer holder and a plurality of wafer holders formed around the wafer holder a pin, the semi-conductor wafer is fixed on the wafer holder and electrically connected to the semiconductor wafer and the lead by a bonding wire, and then the semiconductor wafer, the wafer holder, the bonding wire and the lead are covered with the packaging material Forming a semiconductor package with a lead frame to form a semiconductor package having a lead frame as a wafer carrier, such as QFP (Quad Flat Package), QFN (Quad-Flat Non-leaded), SOP (Small Outline Package), or I DIP (Dual in-line Package), etc., in order to improve the heat dissipation efficiency of the semiconductor package structure and the small size requirement of the Chip Scale Package (CSP), the wafer holder is currently used. The exposed QFN semiconductor package structure or the exposed surface semiconductor package structure at the bottom is the mainstream of the package. For the QFN semiconductor package structure, it is characterized in that no external pin is provided, that is, a pin which is electrically connected to the outside in a conventional quadrilateral planar semiconductor package structure (QFP) is not formed, thereby reducing the semiconductor package. The size of the structure. Please read the conventional qFN semiconductor package junction shown in the drawings]A and 1B. Figure 1 shows the top view of the Jfl, s π first figure; as shown in the figure ==' and the first ιβ It is y, the system side; the semiconductor wafer 12 is fixed on the lead 牟=10 of the pin 11 , and the half = is connected to the lead 1 to the lead frame crystal. The crystal grain is formed on the wire and the wire 13 is formed on the wire 13 and the bottom surface of the wire 11 is exposed to the package body by the QFN semiconductor package structure by /4 (not in the figure) It is not electrically connected to an external device such as a printed circuit board (P_ed circuit (10)d) (not shown).隹f knows that the semiconductor package structure is limited only by the arrangement and quantity of its ==:: 2: = The problem of the structure of the external problem solved by the current problem is not easy to manufacture, etc. In view of the above-mentioned various deficiencies of the prior art, the present invention provides a package structure having a preferred external electrical connection point for the above and other purposes, and the present invention discloses that the package includes: The bearing unit of the two surfaces has a first metal layer on the surface of the first metal layer on the first metal layer, and a plurality of electrical contacts on the second metal layer; Forming a dielectric layer on the metal layer and the electrical contact pad, and forming a wiring layer in the dielectric layer, and forming a plurality of conductive blind holes in the dielectric layer to electrically connect the green static Π 2011 366 201114002 electrical contact pads, and The circuit layer has a plurality of padded pads, and the wire pads of each of the zones have a plurality of wire pads, wherein the material of the electrical layer can be ABF (Ajinomoto Build-up Film), BCB (Benzocyclo- Buthene), LCP (Liquid Crysta l Polymer), PI (Poly-imide) ' PPE (Poly (phenylene ether)) ' PTFE (Poly - (tetra-fluoroethylene)), FR4, FR5, BT (Bismaleimide Triazine), aromatic nylon (Aramide), or mixed ring An oxidized glass fiber; an insulating protective layer is formed on the dielectric layer and the circuit layer, and a plurality of openings are formed in the insulating protective layer, so that the wire pads of each of the partitions are correspondingly exposed to each other a hole forming a pair of upper and lower surface-encapsulated substrates, wherein the material forming the insulating protective layer may be ABF (Ajinomoto Build-up Film) 'BCB (Benzocyclo-buthene) ' LCP (Liquid
Ciystal Polymer)、Pl(Poly-imide)、PPE(P〇ly(phenylene ether))、PTFE(Poly(tetra-fluoroethylene))、FR4、FR5、 BT(Bismaleimide Triazine)、芳香尼龍（Aramide)、防焊層或 馨混合環氧樹脂玻璃纖維（Glass fiber );沿該上下成對的整 版面封裝基板的邊緣與内部進行第一次裁切，以成為複數 上下成對的封裝基板區塊，而各該上下成對的封農基板區 塊具有呈（m X η)陣列排列的上下成對的封裝基板單元， 其中’ m與η皆為大於1之整數；於各該上下成對的封裝 基板單元上接置半導體晶片，該半導體晶片具有作用面與 非作用面’ έ亥非作用面係固設於該絕緣保護層上，且該作 用面具有複數電極墊，而各該電極墊藉由焊線以對應電性 連接至各該打線墊；於該半導體晶片、絕緣保護層 '打線 Π1366 5 201114002 墊與焊線上形成封裝材 結構單元之上下成對的封裝結:區=第下朗;封裝 該承載單元分離，以尾將忒弟一金屬層自 獨立的兩個封裝結構區塊'•移㈣分離成 層，以外露出電性接觸整表面；以及第層與弟二金屬 構區塊以分離成複數封裝結構單元。人裁切該封裝結 於上述之封裴結構之製法中， 包括··提供-具有相對兩表面之 载早f之衣知係可 表面上均形成面積小於該承載板之剝離二之兩 二未形成該剝離層之表面形成黏著層，：令二 =離層四周，·以及於該剝離層與黏著層成 ，層，者’該承載單元之製程係可包括:=二 承載板之兩表面上均、形= 增，万、鑌黏者層上全面貼設有面積 又於前述之製法中，該第—兮 剝離層。 —人裁切之裁切邊可通過該 依上所述之封裝結構之製法，該 係可包括：於該第二金屬層上形成_ 製程 複數阻層開孔，以外露部分之 ^阻θ形成 開孔中之第二金屬層上電㈣，成屬層；於各該阻層 該阻層。 毛糾成该電性接觸塾；以及移除 而構 前述之製法中’該介電層與該線路層可為複數， ]】】366 201114002 成一増層結構，該增層結構係包括+ 該介電層上之線路層、及複數形至夕介電層、形成於 接該線路層與電性接觸墊之導電亡於°玄；丨電層中並電性連 層之線路層復具有該等分區之孔，且該增層結構最外 又於上述之製法中，復可釭墊。 _ -表面處理層，而形㈣於該等打㈣上形成第 人辟/▲, 衣面處理層之材料可為鎳/ 金（Ni/Au)、鎳/!巴（Ni/pd)、# - 、果纪浸金（Electroless Nickel / Electroless Palladium / Immersion Gold，ENEPIG)、錫 • (Sn)、銀（Ag)、或金（Au)。 前述之封裝結構之製法中，復可包括於各該電性接觸 墊外露之表面上形成第二表面處理層，而形成該第二表面 處理層之材料可為鎳/金（Ni/Au)、鎳/鈀（Ni/Pd)、化鎳 在巴浸金（Electroless Nickel / Electroless Palladium / ImmersionGold，ENEPIG)、錫（Sn)、銀（Ag)、或金 (Au )。 依上所述之製法，於該第一次裁切前，復可包括於該 絕緣保護層與打線墊上形成第一保護膜，並於該第一次裁 切後，移除該第一保護膜；且於該第二次裁切前，復可包 括於該介電層與電性接觸塾上形成第二保護膜，並於該第 二次裁切後，移除該第二保護膜。 又於前述之封裝結構之製法中，於該第二次裁切前， 復可包括於各該電性接觸墊上形成焊球。 由上可知’本發明之封裝結構之製法係先將上下成對 的整版面封裝基板裁切成複數上下成對的封裝基板區塊， 7 ⑴366 201114002 各該上下成對的封裝基板區塊之面積適中且包括有複數上 下成對的封裝基板單元；接著，於各該封裝基板單元上接 置半導體晶片並以封裝材加以固定與保護；最後，裁切成 複數封裝結構單元。相較於習知技術，本發明之封裝结構 之製法係形成具有陣列式的密集電性連接墊的封裝結構， 因而應用範圍較廣，且有效利用整體基材面積；此外，本 發明之製法係整合封裝基板製造及半導體晶片封裝，而可 一次對各該封裝基板區塊中的全部封裝基板單元進行半導 體晶片封裝，以簡化製程步驟並提高產能；再者，本發明 之封裝基板區塊之面積適中，所以，各該封裝基板區塊中 的各該封裝基板單元同樣能擁有彼此較相近的製程精度與 良率，故，本發明之封裝結構之製法具有應用面較廣、產 能較高且良率較一致等優點。 【實施方式】 以下藉由特定的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。 請參閱第2A至2J圖，係本發明之封裝結構之製法的 剖視示意圖；其中，該第2A’圖係第2A圖的另一態樣，該 第2E’圖係第2E圖的另一態樣，該第2F’圖係第2F圖的俯 視圖。 如第2A及2A’圖所示，提供一具有相對兩表面之承 載單元2,於該承載單元2之兩表面上均具有第一金屬層 8 ΙΠ366 221。 201114002 上述之承載單元2之製程可如第2A圖所示’係提供 --具有相對兩表面之承載板2G ;接著，於該承載板2〇之 ,兩表面上均形成面積小於該承載板2〇之剝離層Μ〗；之 ，，於該承載板20上且未形成該剝離層2U之表面形成黏 著層212，以令該黏著層212環繞該剝離層211四周；最 .後，於該剝離層扣與黏著層212上形成第一金屬層221。 • 〃或者，上述之承載單元2之製程可如第2a，圖所示， 係提供-具有相對兩表面之承載板2〇;於該承載板加之 兩表面上均形成黏著層犯；接著，於該黏著層⑴上全 面貼設有面積小於該承載板2G且四周為該黏著層212環繞 之剝離層211 ;以及於該_層211與黏著層212上 第一金屬層221。 取 所述之剝離層211可為離型膜，形成該第—金屬層 2曰21之材質可為鋼’且該第一金屬層221可為電錢製程； 提供電流傳導路彳Λ之S插jg， j , "A圖作說明 種層（Seedlayer)。以下實施係以第 如第2B圖所示’於該第一金屬層22ι上形成第二金 屬層222，而該第二金屬層奶可為停止層（s邮一〇。 ▲如第2C圖所示，於該第二金屬層222上形成阻層23， 且雜層23中形成複數阻層開孔23〇，以外露部分之第二 金屬層222;接著，藉由該第一金屬層221作為電鐘之電 流傳導路技以於各該阻層開孔230中之第二金屬層奶上 電鑛形成電性接觸墊24。 如第2D圖所示，移除該阻層23，以露出該第二金屬 1Π366 9 201114002 層222與tn接觸塾24。 如第2F岡π - 卜相#、，圖所不，該第二金屬層222與電性接觸墊 y %層結構25,該増層結構25係包括至少一介電 層成於該介電層251上之線路層253、及複數形成 於°亥；丨:層251中並電性連接該線路I 253與電性接觸墊 導黾目孔252 ’且該增層結構25最外層之線路層253 復具有複數分區之打線塾254s (僅顯示於第2F，圖），又 各該分區之打線墊254s復具有複數打線墊254，形成該介 電層 251 之材料係 abf (Ajinomoto Build-up Film)、BCB (Benzocyclo-buthene)、LCP (Liquid Crystal Polymer)、PI (Poly-imide)、PPE (Poly(phenylene ether))、PTFE (Poly (tetra-fluoroethylene)) ' FR4、FR5、BT(BismaleimideCiystal Polymer), Pl (Poly-imide), PPE (P〇ly (phenylene ether)), PTFE (Poly (tetra-fluoroethylene)), FR4, FR5, BT (Bismaleimide Triazine), aromatic nylon (Aramide), solder mask a layer or a mixture of epoxy fiberglass (Glass fiber); along the upper and lower pairs of the entire surface of the package substrate edge and the inside of the first cutting, to become a plurality of upper and lower pairs of package substrate blocks, and each The upper and lower paired sealing substrate blocks have upper and lower pairs of package substrate units arranged in an array of (m x η), wherein 'm and n are both integers greater than 1; on each of the upper and lower paired package substrate units A semiconductor wafer having a working surface and an inactive surface is disposed on the insulating protective layer, and the active surface has a plurality of electrode pads, and each of the electrode pads is connected by a bonding wire Correspondingly electrically connected to each of the wire bonding pads; in the semiconductor wafer, the insulating protective layer 'wire Π 1366 5 201114002 pad and the wire forming a package structure unit above and below the pair of package junctions: zone = the next lang; encapsulating the carrier unit Separate to The younger brother te two separate package from a metal layer blocks' • shift iv delaminated, so as to expose the entire surface of the electrical contact; and a second metal layer and brother two blocks configured to separate into a plurality of unit package. The method of cutting the package into the above-mentioned sealing structure comprises: providing - having a relatively long surface, the surface of the coating is smaller than the peeling of the carrier plate. Forming the surface of the release layer to form an adhesive layer, such as: two = off the layer, and the release layer and the adhesive layer, the layer, the process unit of the carrier unit may include: = two surfaces of the two carrier plates The uniformity, shape = increase, 10,000, 镔 者 者 layer is fully affixed to the area and in the aforementioned method, the first 兮 detachment layer. The cut edge of the human cut can be passed through the method of fabricating the package structure as described above, and the system can include: forming a plurality of opening layers of the process layer on the second metal layer, and forming a resistive θ of the exposed portion The second metal layer in the opening is powered (4), and is formed into a layer; and the resist layer is formed in each of the resist layers. The hair is entangled into the electrical contact 塾; and in the method of removing the structure, the dielectric layer and the circuit layer may be plural,] 366 201114002 into a 増 layer structure, the layered structure includes + a circuit layer on the electrical layer, and a complex-to-seven dielectric layer, a conductive layer formed on the circuit layer and the electrical contact pad, and a circuit layer in the electrical layer and the electrical layer The hole of the partition, and the layered structure is the outermost and in the above-mentioned manufacturing method, the mat can be used. _ - surface treatment layer, and shape (4) forms the first person / ▲ on the top (four), the material of the clothing treatment layer may be nickel / gold (Ni / Au), nickel /! Pakistan (Ni / pd), # - , Electroless Nickel / Electroless Palladium / Immersion Gold (ENEPIG), Tin • (Sn), Silver (Ag), or Gold (Au). In the above method for manufacturing the package structure, the second surface treatment layer may be formed on the exposed surface of each of the electrical contact pads, and the material forming the second surface treatment layer may be nickel/gold (Ni/Au). Nickel/palladium (Ni/Pd), nickel immersion gold (Electroless Nickel / Electroless Palladium / Immersion Gold, ENEPIG), tin (Sn), silver (Ag), or gold (Au). According to the above-mentioned manufacturing method, before the first cutting, the first protective film is formed on the insulating protective layer and the wire bonding pad, and after the first cutting, the first protective film is removed. And before the second cutting, the composite comprises forming a second protective film on the dielectric layer and the electrical contact, and after the second cutting, removing the second protective film. In the method of fabricating the package structure described above, before the second cutting, a solder ball may be formed on each of the electrical contact pads. It can be seen from the above that the manufacturing method of the package structure of the present invention first cuts the upper and lower pairs of the full-face package substrate into a plurality of package substrate blocks, 7 (1) 366 201114002, the area of the upper and lower pairs of package substrate blocks. A plurality of package substrate units are arranged in a plurality of pairs; and then, the semiconductor wafers are attached to the package substrate units and fixed and protected by the package materials; and finally, the plurality of package structure units are cut. Compared with the prior art, the manufacturing method of the package structure of the present invention forms a package structure having an array of dense electrical connection pads, so that the application range is wide, and the overall substrate area is effectively utilized; further, the manufacturing method of the present invention The package substrate manufacturing and the semiconductor chip package are integrated, and the semiconductor chip package can be performed on all the package substrate units in each of the package substrate blocks at one time to simplify the process steps and increase the productivity; further, the area of the package substrate block of the present invention Therefore, each of the package substrate units in each of the package substrate blocks can have process precisions and yields that are similar to each other. Therefore, the method for manufacturing the package structure of the present invention has a wide application range, high productivity, and good quality. The rate is more consistent and so on. [Embodiment] The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can readily understand the other advantages and functions of the present invention from the disclosure. 2A to 2J are schematic cross-sectional views showing a method of fabricating the package structure of the present invention; wherein the 2A' diagram is another aspect of FIG. 2A, and the 2E' diagram is another 2E diagram. In the aspect, the 2F' diagram is a plan view of the 2Fth diagram. As shown in Figs. 2A and 2A', a carrier unit 2 having opposite surfaces is provided, and a first metal layer 8 ΙΠ 366 221 is provided on both surfaces of the carrier unit 2. 201114002 The above-mentioned process of the carrying unit 2 can be provided as shown in FIG. 2A--the carrier plate 2G having two opposite surfaces; then, the bearing plate 2 is formed on both surfaces with an area smaller than the carrying plate 2 The adhesive layer 212 is formed on the surface of the carrier 20 and the peeling layer 2U is not formed, so that the adhesive layer 212 surrounds the peeling layer 211; most, after the peeling A first metal layer 221 is formed on the layer buckle and the adhesive layer 212. • Alternatively, the above-described process of the carrying unit 2 can be provided as shown in FIG. 2a, which is provided with a carrier plate 2 having opposite surfaces; an adhesive layer is formed on both surfaces of the carrier plate; The adhesive layer (1) is entirely provided with a peeling layer 211 having a smaller area than the carrier board 2G and surrounded by the adhesive layer 212; and a first metal layer 221 on the layer 211 and the adhesive layer 212. The stripping layer 211 may be a release film, and the material forming the first metal layer 2曰21 may be steel 'and the first metal layer 221 may be an electric money process; Jg, j, " A picture to illustrate the seed layer (Seedlayer). In the following embodiment, the second metal layer 222 is formed on the first metal layer 22 ι as shown in FIG. 2B, and the second metal layer milk may be a stop layer. ▲ As shown in FIG. 2C A resist layer 23 is formed on the second metal layer 222, and a plurality of resistive opening 23〇 and an exposed second metal layer 222 are formed in the impurity layer 23; and then, the first metal layer 221 is used as the second metal layer 221 The current conduction path of the electric clock is used to form an electrical contact pad 24 on the second metal layer milk in each of the resistance layer openings 230. As shown in FIG. 2D, the resist layer 23 is removed to expose the The second metal 1 Π 366 9 201114002 The layer 222 is in contact with the tn 24 . As the 2F π - 卜 phase #, the figure is not, the second metal layer 222 and the electrical contact pad y % layer structure 25, the 増 layer structure 25 series includes at least one dielectric layer formed on the dielectric layer 251, and a plurality of layers formed on the dielectric layer 251, and a plurality of layers formed in the layer 251 and electrically connected to the line I 253 and the electrical contact pads 252 'and the outermost layer of the layer 2 of the layered structure 25 has a plurality of sections 254s (shown only in the 2F, figure), and each of the zones The pad 254s has a plurality of wire bonding pads 254, and the material layer abf (Ajinomoto Build-up Film), BCB (Benzocyclo-buthene), LCP (Liquid Crystal Polymer), PI (Poly-imide), PPE (PPE) Poly(phenylene ether), PTFE (Poly (tetra-fluoroethylene)) FR4, FR5, BT (Bismaleimide
Tnazine)、芳香尼龍(Aramide)、或混合環氧樹脂玻璃纖維 (Glass fiber)所構成，且該介電層251係較佳具有較高之 玻璃轉化溫度（glass transition temperature);接著，於該 增層結構25最外層上形成絕緣保護層26，且該絕緣保護 層26中形成複數開孔260，以令各該分區之打線墊254s 對應露出於各該開孔260 ;然後，於該等打線墊254上形 成第一表面處理層271，而形成上下成對的整版面封裝基 板2a，形成該第一表面處理層271之材料係鎳/金 (Ni/Au)、錄/把（Ni/Pd)、化鎳妃浸金（Electroless Nickel / Electroless Palladium / Immersion Go]d ’ ENEPIG)、錫 (Sn)、銀（Ag)、或金（Au)。亦可如第2E’圖所示， 其係第2E圖的另一態樣’係於該第二金屬層222與電性 111366 201114002 接觸塾24上形成一介略 ^ "免層251，並於該介電層 π 線路層253，9於兮公不 〇丨上形成 路声2…广層251中形成複數電性連接該線 路層253。氧性接觸塾24之導電盲孔说，且該線路層… 復具有複數分區之打線塾254s，各該分區之打線塗254s 具有複數打線墊254,接著，於該介電層251與線路層2兄 上形成絕緣保護層26，且該絕緣保護層26中形成複數開 孔260，以令各該分區之打線墊25屯對應露出於各該開孔 260 ’然後，於該等打線墊254上形成第一表面處理層271， 而形成上下成對的整版面封裝基板2a。以下實施係以第2E 圖做說明。 如第2F及2F，圖所示，該第2F，圖係第2F圖的俯視 圖，如圖所不，沿該上下成對的整版面封裝基板2a的邊緣 與内部進订第—次裁切，且裁切邊28通過該剝離層21ι， 、成為複數上下咸斟的封裝基板區塊％，而各該上下成對 的封裝基板區塊2b具有呈（m χ n )陣列排列的上下成對 的^裝基板單元2e ;其中，m#n皆為大於丨之整數，於 本貝施例中m與n分別為3與2，但不以此為限。此外， 於J第人裁切如，復可包括於該絕緣保護層％與打線塾 254 (或第表面處理層271 )上形成第一保護膜（未於圖 式中表不），以避免該絕緣保護層26與打線墊254 (或第 表面處理層271)於裁士刀時被液體或粉塵所影響，並於 或第-次裁切後’移除該第—保護膜。 如第2G圖所示’於各該上下成對的封裝基板單元2c 上接置半導體晶片29,而該半導體晶片29具有作用面29a Γ 1Π366 201114002 與非作用面29b 5 t玄北从m 非竹用面2%固設於該絕緣保護屛χ 上’且該作用面29a且女、—A 曰6 具有钹數電極墊291，而各該電極執 291藉由焊線30以對庙干ti ^ 十應％性連接至各該打線墊254;接 於該半導體晶片29、p铁扣上 考 、、、巴緣保護層26、打線墊254 ( 4敏— 表面處理層271)與煜的μ 、年線30上形成封裝材31，而成為 複數上下成對的封舉处进。。 /、有 , 衣、、·°構早元2c，之上下成對的封裴結椹 區塊2b’。 。何 如第2H圖所多 ϋ 、將该第一金屬層221自該承載單 2分離，以將該上·ρ & + 戟早兀 战對的封裝結構區塊2b，分離成獨古沾 兩個封裝結構區塊2h” η λ 坎竭立的 m D ’且各該封裝結構區塊2b”具有呈fTnazine), aromatic polyamide (Aramide), or mixed epoxy glass fiber, and the dielectric layer 251 preferably has a higher glass transition temperature; An insulating protective layer 26 is formed on the outermost layer of the layer structure 25, and a plurality of openings 260 are formed in the insulating protective layer 26, so that the wire bonding pads 254s of the respective regions are correspondingly exposed to the openings 260; and then, the wire bonding pads are A first surface treatment layer 271 is formed on the 254, and a pair of upper and lower surface package substrates 2a are formed. The material of the first surface treatment layer 271 is nickel/gold (Ni/Au), and Ni/Pd. , Electroless Nickel / Electroless Palladium / Immersion Go]d 'ENEPIG), tin (Sn), silver (Ag), or gold (Au). Alternatively, as shown in FIG. 2E', the other aspect of FIG. 2E is formed on the second metal layer 222 and the electrical 111366 201114002 contact 塾 24 to form a dielectric layer 251, and The dielectric layer π circuit layers 253, 9 form a road sound 2 on the ... 〇丨 ... ... ... ... 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The conductive blind hole of the oxygen contact port 24 is said, and the circuit layer has a plurality of wire 塾 254s, and the wire coating 254s of each of the partitions has a plurality of wire pads 254, and then the dielectric layer 251 and the circuit layer 2 An insulating protective layer 26 is formed on the brother, and a plurality of openings 260 are formed in the insulating protective layer 26, so that the bonding pads 25 of each of the partitions are correspondingly exposed to the openings 260', and then formed on the bonding pads 254. The first surface treatment layer 271 forms a pair of upper and lower surface package substrates 2a. The following implementation is illustrated in Figure 2E. As shown in FIGS. 2F and 2F, the second FF is a plan view of the second F-figure, and the first and second croppings are performed along the edges and the inside of the pair of upper and lower-faced package substrates 2a. And the cutting edge 28 passes through the peeling layer 21, and becomes a plurality of package substrate blocks % of the upper and lower sides, and the upper and lower paired package substrate blocks 2b have the upper and lower pairs arranged in an array of (m χ n ) The substrate unit 2e is mounted; wherein m#n is an integer greater than 丨, and m and n are 3 and 2, respectively, but not limited thereto. In addition, the cutting of the first person may include forming a first protective film (not shown in the figure) on the insulating protective layer % and the wire 塾 254 (or the surface treatment layer 271) to avoid the The insulating protective layer 26 and the wire bonding pad 254 (or the surface treatment layer 271) are affected by liquid or dust during the cutting of the knife, and the first protective film is removed after the first cutting. As shown in FIG. 2G, the semiconductor wafer 29 is attached to each of the pair of upper and lower package substrate units 2c, and the semiconductor wafer 29 has an active surface 29a Γ 1Π366 201114002 and an inactive surface 29b 5 t Xuanbei from m non-bamboo 2% of the surface is fixed on the insulating protection '' and the active surface 29a and the female, -A 曰6 have a plurality of electrode pads 291, and each of the electrodes is held 291 by the bonding wire 30 to the temple ti ^ Tenth wire is connected to each of the wire bonding pads 254; the semiconductor wafer 29, the p-iron clasp, the bar edge protective layer 26, the wire bonding pad 254 (4 sensitive - surface treatment layer 271) and the 煜 μ, The package material 31 is formed on the annual line 30, and is a plurality of upper and lower pairs of enclosing places. . /, Yes, Clothing,, · ° structure early yuan 2c, above and below the pair of sealed knots block 2b'. . For example, as shown in FIG. 2H, the first metal layer 221 is separated from the carrier sheet 2, and the package structure block 2b of the upper ρ & + 戟 兀 分离 is separated into two Package structure block 2h" η λ 竭 竭 m m 且 and each package structure block 2b" has f
Xn)陣列排列_裝結構單元2c”。 如第21圖所斤 b ’移除該第一金屬層221與第-仝戸 層222，以外露出/、弟一金屬 兒陡接觸墊24表面，並於各該電性接觸 墊24外露之表面上形成楚 ^ ^ ^ 1 工巾成弟二表面處理層272，而形成該第 二表面處理層272之材料係鎳/金（Ni/Au)、鎳/鈀（Ni/pd)、 化鎳在巴浸金（Electroless Nickel / Electroless Palladium / Immersion Gold，ENEPIG )、錫（Sn )、銀（Ag )、或金 (Au ) o 如第2J圖所示，進行第二次裁切以將該封震結構區 塊2b”分離成複數封裝結構單元2c，，。此外，於該第二次裁 切前’復可包括於該介電層251與電性接觸墊二(：二 表面處理層272)上形成第二保護觀（未於圖式中表示）， 以避免該介電層25與電性接觸墊24 r々μ 一·^ (或弟二表面處理層 2?2)於裁切時被液體或粉塵所影響 θ |於該第二次裁切 1Π366 12 201114002 後，移除該第二保護膜；其中，該電性接觸墊24 (或第二 表面處理層272 )可直接供作與墊閘陣列（Land grid array， 簡稱LGA)結構之電性連接；或者，於該第二次裁切前， 復包括於各該電性接觸墊24 (或第二表面處理層272)上 形成焊球（未於圖式中表示），以做為後續之電性連接用。 . 於上述之製法中，亦可先將上下成對的整版面封裝基 板分離成獨立的兩個整版面封裝基板，再裁切成複數封裝 基板區塊，而其他步驟同前面所述，在此不加以贅述。 • 綜上所述，本發明之封裝結構之製法係先將上下成對 的整版面封裝基板裁切成複數上下成對的封裝基板區塊， 令各該上下成對的封裝基板區塊之面積適中且包括有複數 上下成對的封裝基板單元；接著，於各該封裝基板單元上 接置半導體晶片並以封裝材加以固定與保護；最後，裁切 成複數封裝結構單元。相較於習知技術，本發明封裝結構 之製法係形成具有陣列式的密集電性連接墊的封裝結構， I 因而應用範圍較廣，且有效利用整體基材面積；此外，本 發明之製法係整合封裝基板製造及半導體晶片封裝，而可 一次對各該封裝基板區塊中的全部封裝基板單元進行半導 體晶片封裝，以簡化製程步驟並提高產能；再者，本發明 之封裝基板區塊之面積適中，所以，各該封裝基板區塊中 的各該封裝基板單元同樣能擁有彼此較相近的製程精度與 良率，故，本發明之封裝結構之製法具有應用面較廣、產 能較高且良率較一致等優點。 上述實施例係用以例示性說明本發明之原理及其功 111366 201114002 ㈣用於限制本發明。任何熟習此項技藝之 在不違背本發明之精神及範疇 、一 句可 改。因此本發明之權利保護範 ^述只知例進仃修 圍所列。 乾圍’應如後述之申請專利範 【圖式簡單説明】 第圖係習知之封裝結構之示意圖，1中， ^圖係剖視圖，且該第1B圖係第圖的俯視圖； 錢圖係本發明之封裝結構之製法的剖視 該第2Α，圖係第2Α圖的另一態樣，該第2Ε， 的另一態樣，該第2F，圖係第2F圖的俯視圖。 L主要7L件符號說明】 導線架晶片座 引腳 半導體晶片 焊線 封裝材 承載單元 上下成對的整版面封裝基板 上下成對的封裝基板區塊 上下成對的封裝結構區塊 封裝結構區塊 上下成對的封裝基板單元 上下成對的封裝結構單元 10 11 !2 ' 29 13 14 2 2a 2b 2b， 2b” 2c 2c’ 1Π366 14 201114002Xn) array arrangement _ mounting structural unit 2c". As shown in Fig. 21, the first metal layer 221 and the first-peer layer 222 are removed, and the surface of the pad 2 is exposed. On the exposed surface of each of the electrical contact pads 24, a surface treatment layer 272 is formed, and the material forming the second surface treatment layer 272 is nickel/gold (Ni/Au) and nickel. /Palladium (Ni/pd), nickel immersion gold (Electroless Nickel / Electroless Palladium / Immersion Gold, ENEPIG), tin (Sn), silver (Ag), or gold (Au) o as shown in Figure 2J, A second cutting is performed to separate the sealed structure block 2b" into a plurality of package structure units 2c. In addition, before the second cutting, the composite layer 251 and the electrical contact pad 2 (the second surface treatment layer 272) form a second protection view (not shown in the figure) to Avoiding the dielectric layer 25 and the electrical contact pads 24 r々μ·· (or the second surface treatment layer 2? 2) being affected by liquid or dust during cutting θ | at the second cutting 1 Π 366 12 After the 201114002, the second protective film is removed; wherein the electrical contact pad 24 (or the second surface treatment layer 272) can be directly used as an electrical connection with a Land Grid Array (LGA) structure; Alternatively, before the second cutting, a solder ball (not shown in the figure) is formed on each of the electrical contact pads 24 (or the second surface treatment layer 272) to serve as a subsequent electrical property. Used for connection. In the above method, the upper and lower pairs of the full-face package substrate may be separated into two independent full-page package substrates, and then cut into a plurality of package substrate blocks, and other steps are the same as described above. Do not repeat them. In summary, the method for manufacturing the package structure of the present invention first cuts the upper and lower pairs of the full-face package substrate into a plurality of upper and lower pairs of package substrate blocks, so that the area of the upper and lower pairs of package substrate blocks A plurality of package substrate units are arranged in a plurality of pairs; and then, the semiconductor wafers are attached to the package substrate units and fixed and protected by the package materials; and finally, the plurality of package structure units are cut. Compared with the prior art, the method for manufacturing the package structure of the present invention forms a package structure having an array of dense electrical connection pads, and thus has a wide application range and effectively utilizes the overall substrate area; further, the method of the present invention is The package substrate manufacturing and the semiconductor chip package are integrated, and the semiconductor chip package can be performed on all the package substrate units in each of the package substrate blocks at one time to simplify the process steps and increase the productivity; further, the area of the package substrate block of the present invention Therefore, each of the package substrate units in each of the package substrate blocks can have process precisions and yields that are similar to each other. Therefore, the method for manufacturing the package structure of the present invention has a wide application range, high productivity, and good quality. The rate is more consistent and so on. The above embodiments are intended to exemplify the principles of the invention and its work. 111366 201114002 (4) is used to limit the present invention. Any skill in the art may be made without departing from the spirit and scope of the invention. Therefore, the scope of the protection of the present invention is only described by way of example. The present invention is a schematic diagram of a conventional package structure, a schematic diagram of a package, a schematic view of the first embodiment, and a plan view of the first diagram; A cross-sectional view of the method of fabricating the package structure is shown in the second aspect, and another aspect of the second diagram is shown in the second aspect, and the second aspect is a plan view of the second F-figure. L main 7L parts symbol description] lead frame wafer holder pin semiconductor wafer bonding wire package material carrying unit upper and lower pairs of full-face surface package substrate upper and lower pairs of package substrate block upper and lower pairs of package structure block package structure block up and down Paired package substrate unit upper and lower paired package structure unit 10 11 !2 ' 29 13 14 2 2a 2b 2b, 2b” 2c 2c' 1Π366 14 201114002
2c” 封裝結構單元 20 承載板 211 剝離層 212 黏著層 221 第一金屬層 222 第二金屬層 23 阻層 230 阻層開孔 24 電性接觸墊 25 增層結構 251 介電層 252 導電盲孔 253 線路層 254 打線墊 254s 分區之打線墊 26 絕緣保護層 260 開孔 271 第一表面處理層 272 第二表面處理層 28 裁切邊 29a 作用面 29b 非作用面 291 電極墊 30 焊線 201114002 31 m η 封裝材 上下成對的封裝基板區塊之陣列行數 上下成對的封裝基板區塊之陣列列數2c" package structure unit 20 carrier plate 211 release layer 212 adhesion layer 221 first metal layer 222 second metal layer 23 resistance layer 230 resistance layer opening 24 electrical contact pad 25 build-up structure 251 dielectric layer 252 conductive blind hole 253 Circuit layer 254 wire pad 254s segmented wire pad 26 insulating protective layer 260 opening 271 first surface treatment layer 272 second surface treatment layer 28 cutting edge 29a active surface 29b non-active surface 291 electrode pad 30 bonding wire 201114002 31 m η Number of array rows of package substrate blocks in which the package material is paired up and down
16 11136616 111366