TWI706519B - Semiconductor package having routable encapsulated conductive substrate and method - Google Patents

Semiconductor package having routable encapsulated conductive substrate and method Download PDF

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Publication number
TWI706519B
TWI706519B TW105119098A TW105119098A TWI706519B TW I706519 B TWI706519 B TW I706519B TW 105119098 A TW105119098 A TW 105119098A TW 105119098 A TW105119098 A TW 105119098A TW I706519 B TWI706519 B TW I706519B
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Taiwan
Prior art keywords
conductive
layer
resin layer
surface finishing
semiconductor device
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TW105119098A
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Chinese (zh)
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TW201711144A (en
Inventor
班文貝
金本吉
金錦雄
權杰督
江詳燁
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美商艾馬克科技公司
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Publication of TW201711144A publication Critical patent/TW201711144A/en
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Publication of TWI706519B publication Critical patent/TWI706519B/en

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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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Abstract

A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame structure includes a first laminated layer including the surface finish layer, vias connected to the surface finish layer, and a first resin layer covering the vias leaving the top surface of the surface finish layer exposed. A second laminated layer includes second conductive patterns connected to the vias, bump pads connected to the second conductive patterns, and a second resin layer covering one side of the first resin layer, the second conductive patterns and the bump pads. A semiconductor die is electrically connected to the surface finish layer and an encapsulant covers the semiconductor die and another side of the first resin layer. The surface finish layer provides a customizable and improved bonding structure for connecting the semiconductor die to the routable molded lead frame structure.

Description

具有可路由囊封的傳導基板的半導體封裝及方法 Semiconductor package and method with routable encapsulated conductive substrate

本發明大體上涉及電子元件，並且更具體地說，涉及半導體封裝、其結構及製造半導體封裝的方法。 The present invention relates generally to electronic components, and more specifically, to semiconductor packages, their structures, and methods of manufacturing semiconductor packages.

相關申請案的交叉參考 Cross reference of related applications

本申請案主張名為“具有可路由囊封的傳導基板的半導體封裝及方法(SEMICONDUCTOR PACKAGE HAVING ROUTABLE ENCAPSULATED CONDUCTIVE SUBSTRATE AND METHOD)”的2016年6月3日在美國專利局申請的美國專利申請案第15/173,379號及2015年9月8日在韓國智慧財產權局申請的韓國專利申請案第10-2015-0126935號的優先權，且所有權益是依據35 U.S.C. §119而從所述專利申請案得到，其全部內容以引用的方式併入本文中。 This application claims the title of "SEMICONDUCTOR PACKAGE HAVING ROUTABLE ENCAPSULATED CONDUCTIVE SUBSTRATE AND METHOD", which was filed in the U.S. Patent Office on June 3, 2016. The priority of No. 15/173,379 and the Korean Patent Application No. 10-2015-0126935 filed at the Korean Intellectual Property Office on September 8, 2015, and all rights and interests are obtained from the patent application in accordance with 35 USC §119 , Its entire content is incorporated into this article by reference.

一般來說，半導體封裝經設計以保護積體電路或晶片免於物理損害及外部應力。並且，半導體封裝可提供熱導路徑以有效地移除半導體晶片中產生的熱，且可進一步將電連接提供到其它元件，例如印刷電路板。用於半導體封裝的材料通常包含陶瓷及/或塑膠，且封裝技術已從陶瓷扁平封裝及雙列直插式封裝發展為引腳柵陣列及無引線晶片載體封裝，以 及其它封裝。由於對小型化和較高性能的經封裝半導體裝置的持續需求，需要較精細線寬的傳導基板；尤其是支援各種外部互連結構的傳導基板。 Generally speaking, semiconductor packages are designed to protect integrated circuits or chips from physical damage and external stress. Also, the semiconductor package can provide a thermal conduction path to effectively remove the heat generated in the semiconductor wafer, and can further provide electrical connections to other components, such as a printed circuit board. The materials used for semiconductor packaging usually include ceramics and/or plastics, and the packaging technology has evolved from ceramic flat packages and dual in-line packages to lead grid array and leadless chip carrier packages. And other packages. Due to the continuing demand for miniaturization and higher performance packaged semiconductor devices, conductive substrates with finer line widths are required; especially conductive substrates that support various external interconnect structures.

相應地，希望具有形成包含可路由囊封的傳導基板結構的經封裝半導體裝置的結構和方法，所述結構例如可路由的微引線框架結構，其支援對小型化和較高性能電子裝置的需求。還希望在完成經封裝半導體裝置的組裝之前製造可路由囊封的傳導基板結構或其部分以縮減製造週期時間。另外，使所述結構及方法支援多個外部互連結構將為有益的。另外，還希望使所述結構及方法容易地併入到製造流程中並且使兩者具成本效益。 Accordingly, it is desirable to have a structure and method for forming a packaged semiconductor device including a routable encapsulated conductive substrate structure, such as a routable micro-lead frame structure, which supports the demand for miniaturization and higher performance electronic devices . It is also desirable to manufacture a routable encapsulated conductive substrate structure or part thereof before completing the assembly of the packaged semiconductor device to reduce the manufacturing cycle time. In addition, it would be beneficial to have the structure and method support multiple external interconnect structures. In addition, it is also desirable to make the structure and method easily incorporated into the manufacturing process and make both cost-effective.

本發明包含一種經封裝半導體裝置及其製造方法，以及其它特徵，所述經封裝半導體裝置包含具有傳導表面修整層的可路由囊封的傳導基板(例如，可路由的模制引線框架)。更具體地說，本文中所描述的實施例促進封裝級傳導圖案的有效路由且在表面修整層與半導體晶粒之間提供增強的連接可靠性。對於可路由囊封的傳導基板的一個實施例，表面修整層可在製造過程的初始階段形成。在可路由囊封的傳導基板的另一實施例中，表面修整層既可在製造過程的初始階段又可在最後階段形成。 The present invention includes a packaged semiconductor device including a routable encapsulated conductive substrate (e.g., a routable molded lead frame) with a conductive surface finishing layer and a method of manufacturing the same, as well as other features. More specifically, the embodiments described herein facilitate efficient routing of package-level conductive patterns and provide enhanced connection reliability between the surface finishing layer and the semiconductor die. For one embodiment of the routable encapsulated conductive substrate, the surface finishing layer may be formed in the initial stage of the manufacturing process. In another embodiment of the routable encapsulated conductive substrate, the surface finishing layer can be formed both in the initial and final stages of the manufacturing process.

在一些實施例中，傳導球在表面修整層於製造過程的初始階段形成時直接形成於不具有表面修整層的凸塊墊上、連接到所述凸塊墊或毗鄰所述凸塊墊以提供球柵陣列封裝。另外，當表面修整層於可路由囊封的傳導基板的製造過程的初始及最後階段中的每一者處形成時，形成於最後階段的表面修整層可用作輸入/輸出終端以提供柵格陣列封裝。 In some embodiments, the conductive ball is directly formed on the bump pad without the surface modification layer, connected to the bump pad or adjacent to the bump pad to provide the ball when the surface modification layer is formed in the initial stage of the manufacturing process. Grid array package. In addition, when the surface finishing layer is formed at each of the initial and final stages of the manufacturing process of the routable encapsulated conductive substrate, the surface finishing layer formed in the final stage can be used as an input/output terminal to provide a grid Array package.

在一些優選實施例中，用於形成可路由的模制引線框架的第一樹脂層及第二樹脂層的材料以及用於形成囊封半導體晶粒的封裝體的材料為相同的，或具有相似的熱膨脹係數以及其它相似材料屬性，進而在裝置的製造過程或操作期間有效地抑制翹曲。 In some preferred embodiments, the materials used to form the first resin layer and the second resin layer of the routable molded lead frame and the materials used to form the package body encapsulating the semiconductor die are the same or have similar The thermal expansion coefficient and other similar material properties can effectively suppress warpage during the manufacturing process or operation of the device.

更具體地說，在一個實施例中，一種半導體裝置包括第一層壓層，所述第一層壓層包含：第一表面修整層；第一傳導圖案，其包括連接到第一表面修整層的第一部分及與第一表面修整層側向隔開的第二部分；傳導導通孔，其連接到第一傳導圖案；及第一樹脂層，其覆蓋第一傳導圖案、傳導導通孔，及第一表面修整層的一部分，其中第一表面修整層暴露於第一樹脂層的第一表面中且傳導導通孔暴露於第一樹脂層的第二表面中。第二層壓層鄰近於第一層壓層而安置，且包含連接到傳導導通孔的第二傳導圖案、連接到第二傳導圖案的傳導墊，及覆蓋第一樹脂層、第二傳導圖案及傳導墊的至少一部分的第二樹脂層，其中傳導墊暴露於第二樹脂層的第一表面中。半導體晶粒電連接到第一表面修整層，且囊封物覆蓋第一層壓層及半導體晶粒的至少一部分。 More specifically, in one embodiment, a semiconductor device includes a first laminate layer including: a first surface trimming layer; a first conductive pattern including a first surface trimming layer connected to The first part and the second part laterally separated from the first surface finishing layer; the conductive via, which is connected to the first conductive pattern; and the first resin layer, which covers the first conductive pattern, the conductive via, and the first A part of a surface finishing layer, wherein the first surface finishing layer is exposed in the first surface of the first resin layer and the conductive via is exposed in the second surface of the first resin layer. The second laminate layer is disposed adjacent to the first laminate layer, and includes a second conductive pattern connected to the conductive via, a conductive pad connected to the second conductive pattern, and covering the first resin layer, the second conductive pattern, and The second resin layer of at least a part of the conductive pad, wherein the conductive pad is exposed in the first surface of the second resin layer. The semiconductor die is electrically connected to the first surface finishing layer, and the encapsulant covers at least a part of the first laminate layer and the semiconductor die.

在另一實施例中，一種經封裝半導體裝置包含可路由囊封的傳導基板，其包括囊封在第一樹脂層內的第一傳導結構、電連接到第一傳導結構且囊封在第二樹脂層內的第二傳導結構，及安置在第一傳導結構的至少部分上的第一表面修整層。第一表面修整層暴露於第一樹脂層中且第二傳導結構的至少部分暴露於第二樹脂層中。半導體晶粒電連接到第一表面修整層且囊封物囊封半導體晶粒及第一表面修整層。 In another embodiment, a packaged semiconductor device includes a routable encapsulated conductive substrate, which includes a first conductive structure encapsulated in a first resin layer, electrically connected to the first conductive structure, and encapsulated in a second conductive structure. A second conductive structure in the resin layer, and a first surface finishing layer disposed on at least part of the first conductive structure. The first surface finishing layer is exposed in the first resin layer and at least part of the second conductive structure is exposed in the second resin layer. The semiconductor die is electrically connected to the first surface conditioning layer and the encapsulant encapsulates the semiconductor die and the first surface conditioning layer.

在另一實施例中，製造半導體裝置的方法包含提供可路由囊 封的傳導基板，其包括囊封在第一樹脂層內的第一傳導結構、電連接到第一傳導結構且囊封在第二樹脂層內的第二傳導結構以及安置在第一傳導結構的至少部分上的第一表面修整層，其中第一表面修整層暴露在第一樹脂層中且第二傳導結構的至少部分暴露在第二樹脂層中。所述方法包含將半導體晶粒電連接到第一表面修整層以及形成覆蓋半導體晶粒及第一表面修整層的囊封物。 In another embodiment, a method of manufacturing a semiconductor device includes providing a routable capsule Encapsulated conductive substrate, which includes a first conductive structure encapsulated in a first resin layer, a second conductive structure electrically connected to the first conductive structure and encapsulated in the second resin layer, and a second conductive structure arranged in the first conductive structure At least part of the first surface finishing layer, wherein the first surface finishing layer is exposed in the first resin layer and at least part of the second conductive structure is exposed in the second resin layer. The method includes electrically connecting the semiconductor die to a first surface trimming layer and forming an encapsulant covering the semiconductor die and the first surface trimming layer.

100:半導體裝置 100: Semiconductor device

101:可路由囊封的傳導基板/可路由的模制引線框架 101: routable encapsulated conductive substrate / routable molded lead frame

110:第一層壓層/第一囊封層 110: The first laminate layer / the first encapsulation layer

111:第一表面修整層/第一接合層/第一可線接合修整層 111: first surface finishing layer/first bonding layer/first wire bonding finishing layer

112,112’:第一傳導圖案 112,112’: The first conductive pattern

113:導通孔/傳導導通孔/傳導柱 113: Via/Conducting Via/Conducting Post

114,114’:第一樹脂層 114, 114’: First resin layer

114a,114a’:第一開口 114a, 114a’: First opening

120:第二層壓層/第二囊封層 120: second laminate layer/second encapsulation layer

121:第二傳導圖案 121: second conductive pattern

122,122’:凸塊墊 122,122’: bump pad

123,123’:第二樹脂層 123,123’: The second resin layer

123a,123a’:第二開口 123a, 123a’: second opening

130:半導體晶粒 130: semiconductor die

135:黏著劑 135: Adhesive

140:傳導連接結構/導線 140: Conductive connection structure/wire

150:囊封物 150: Encapsulation

160:傳導凸塊 160: Conductive bump

170:載體 170: carrier

171:載體 171: Carrier

172:載體 172: Carrier

200:半導體裝置 200: Semiconductor device

224:第二表面修整層 224: second surface finishing layer

300:半導體裝置 300: Semiconductor device

311:第一表面修整層/第一接合層/第一可線接合修整層 311: first surface finishing layer/first bonding layer/first wire bonding finishing layer

400:半導體裝置 400: Semiconductor device

411:第一表面修整層/第一接合層/第一可線接合修整層 411: first surface finishing layer/first bonding layer/first wire bonding finishing layer

435:微凸塊 435: Micro bump

通過參考附圖詳細描述其示例性實施例，本發明的上述以及其它特徵將變得更加顯而易見，在附圖中：圖1A為根據本發明的實施例的說明經封裝半導體裝置的橫截面圖；圖1B為說明圖1A的區的放大橫截面圖；圖2A為根據本發明的另一實施例的說明經封裝半導體裝置的橫截面圖；圖2B為說明圖2A的區的放大橫截面圖；圖2C為根據替代性實施例的說明圖2A的區的放大橫截面圖；圖3為根據本發明的另一實施例的說明經封裝半導體裝置的橫截面圖；圖4為根據本發明的又一實施例的說明經封裝半導體裝置的橫截面圖；圖5A為說明由(N×M)個單元構成的載體的平面圖； 圖5B為說明由N個單元構成的載體的平面圖；圖6A到圖6J為根據本發明的實施例的依序說明經封裝半導體裝置的製造方法的橫截面圖；圖7A到圖7C為根據本發明的另一個實施例的依序說明經封裝半導體裝置的製造方法的橫截面圖；圖8A到圖8I為根據本發明的另一實施例的依序說明經封裝半導體裝置的製造方法的橫截面圖；且圖9A到圖9C為根據本發明的又一實施例的依序說明經封裝半導體裝置的製造方法的橫截面圖。 The above and other features of the present invention will become more apparent by describing in detail the exemplary embodiments thereof with reference to the accompanying drawings. In the accompanying drawings: FIG. 1A is a cross-sectional view illustrating a packaged semiconductor device according to an embodiment of the present invention; 1B is an enlarged cross-sectional view illustrating the area of FIG. 1A; FIG. 2A is a cross-sectional view illustrating a packaged semiconductor device according to another embodiment of the present invention; FIG. 2B is an enlarged cross-sectional view illustrating the area of FIG. 2A; 2C is an enlarged cross-sectional view illustrating the area of FIG. 2A according to an alternative embodiment; FIG. 3 is a cross-sectional view illustrating a packaged semiconductor device according to another embodiment of the present invention; FIG. 4 is another according to the present invention A cross-sectional view illustrating a packaged semiconductor device of an embodiment; FIG. 5A is a plan view illustrating a carrier composed of (N×M) units; 5B is a plan view illustrating a carrier composed of N units; FIGS. 6A to 6J are cross-sectional views sequentially illustrating a method of manufacturing a packaged semiconductor device according to an embodiment of the present invention; FIGS. 7A to 7C are based on this Another embodiment of the invention is a cross-sectional view illustrating a method of manufacturing a packaged semiconductor device in sequence; FIGS. 8A to 8I are cross-sectional views illustrating a method of manufacturing a packaged semiconductor device in sequence according to another embodiment of the present invention 9A to 9C are cross-sectional views illustrating a method of manufacturing a packaged semiconductor device in sequence according to another embodiment of the present invention.

為了說明的簡單和清楚起見，圖中的元件未必按比例繪製，並且相同參考數位在不同圖中表示相同元件。另外，為了描述的簡單起見省略眾所周知的步驟和元件的描述和細節。如本文中所使用，術語“及/或”包含相關聯的所列項目中的一或多者的任何及所有組合。另外，本文中所使用的術語僅僅是出於描述特定實施例的目的而並不意圖限制本發明。如本文中所使用，除非上下文另外明確指示，否則單數形式也意圖包含複數形式。將進一步理解術語“包括(comprises/comprising)”及/或“包含(includes/including)”在用於本說明書時規定所陳述的特徵、數目、步驟、操作、元件及/或元件的存在，但是並不排除一個或多個其它特徵、數目、步驟、操作、元件、元件及/或其群組的存在或添加。將理解，儘管術語“第一”、“第二”等可在本文中使用以描述各個部件、元件、區、層及/或區段，但這些部件、元件、區、層及/或區段應不受這些術語限制。這些術語 僅用於區分一個部件、元件、區、層及/或區段與另一部件、元件、區、層及/或區段。因此，舉例來說，下文論述的第一部件、第一元件、第一區、第一層及/或第一區段可被稱為第二部件、第二元件、第二區、第二層及/或第二區段而不脫離本發明的教示。參考“一個實施例”或“實施例”意味著結合實施例描述的特定特徵、結構或特性包含於本發明的至少一個實施例中。因此，在本說明書通篇的各個位置中短語“在一個實施例中”或“在實施例中”的出現未必全部是指同一實施例，但是在一些情況下可以指同一實施例。此外，特定特徵、結構或特性可以任何合適方式組合，如在一或多個實施例中將對於所屬領域的一般技術人員是顯而易見的。另外，術語“在…時”是指某一動作至少出現在起始動作的持續時間的某一部分內。詞語“大約”、“近似”或“基本上”的使用是指元件的值預期為接近一種狀態值或位置。然而，眾所周知，在本領域中總是存在妨礙值或位置恰好如所陳述的一般的輕微變化。除非另外規定，否則如本文中所使用，詞語“在…上面”或“在…上”包含所規定的元件可直接或間接物理接觸的定向、放置或關係。應進一步理解，下文中所說明及描述的實施例適當地可具有實施例及/或可在無本文中確切地揭示的任何元件存在的情況下實踐。 For simplicity and clarity of description, the elements in the figures are not necessarily drawn to scale, and the same reference numerals represent the same elements in different figures. In addition, descriptions and details of well-known steps and elements are omitted for simplicity of description. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. In addition, the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to encompass the plural form. It will be further understood that the terms "comprises/comprising" and/or "includes/including" when used in this specification specify the existence of the stated features, numbers, steps, operations, elements and/or elements, but The existence or addition of one or more other features, numbers, steps, operations, elements, elements and/or groups thereof is not excluded. It will be understood that although the terms "first", "second", etc. may be used herein to describe various components, elements, regions, layers and/or sections, these components, elements, regions, layers and/or sections Should not be restricted by these terms. These terms It is only used to distinguish one component, element, region, layer and/or section from another component, element, region, layer and/or section. Therefore, for example, the first component, the first element, the first region, the first layer, and/or the first section discussed below may be referred to as the second component, the second element, the second region, the second layer And/or the second section without departing from the teachings of the present invention. Reference to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. Therefore, the appearances of the phrase "in one embodiment" or "in an embodiment" in various positions throughout this specification do not necessarily all refer to the same embodiment, but may refer to the same embodiment in some cases. In addition, specific features, structures or characteristics can be combined in any suitable manner, as will be apparent to those skilled in the art in one or more embodiments. In addition, the term "when" means that a certain action occurs at least within a certain part of the duration of the initial action. The use of the words "about", "approximately" or "substantially" means that the value of the element is expected to be close to a state value or location. However, it is well known that there are always slight changes in the art that prevent the value or position from being just as stated. Unless otherwise specified, as used herein, the word "on" or "on" encompasses the orientation, placement, or relationship in which the specified elements can be in direct or indirect physical contact. It should be further understood that the embodiments illustrated and described hereinafter may have embodiments as appropriate and/or may be practiced without the presence of any elements exactly disclosed herein.

圖1A為根據第一實施例的說明具有表面修整層的半導體裝置100或經封裝半導體裝置100的橫截面圖，且圖1B為說明圖1A的區的放大橫截面圖。如圖1A中所說明，半導體裝置100包含第一層壓層110或第一囊封層110、第二層壓層120或第二囊封層120、半導體晶粒130、傳導連接結構140(例如導線140)、囊封物150、凸塊墊122以及傳導凸塊160。 根據本實施例，第一層壓層110及第二層壓層120可被稱作可路由的模制引線框架101或可路由囊封的傳導基板101。 1A is a cross-sectional view illustrating a semiconductor device 100 having a surface modification layer or a packaged semiconductor device 100 according to the first embodiment, and FIG. 1B is an enlarged cross-sectional view illustrating the area of FIG. 1A. As illustrated in FIG. 1A, the semiconductor device 100 includes a first laminate layer 110 or a first encapsulation layer 110, a second laminate layer 120 or a second encapsulation layer 120, a semiconductor die 130, and a conductive connection structure 140 (eg The wire 140), the encapsulant 150, the bump pad 122, and the conductive bump 160. According to this embodiment, the first laminate layer 110 and the second laminate layer 120 may be referred to as a routable molded lead frame 101 or a routable encapsulated conductive substrate 101.

在一個實施例中，第一層壓層110包含第一表面修整層111、第一接合層111或第一可線接合修整層111、第一傳導圖案112、導通孔113、傳導導通孔113或傳導柱113以及第一樹脂層114。在一些實施例中，第一表面修整層111可為金屬材料，例如鎳/金(Ni/Au)、銀(Ag)、銅(Cu)、其組合以及其等效物，但本實施例的方面不限於此。在一個實施例中，第一傳導圖案112可安置在第一表面修整層111上或毗鄰所述第一表面修整層111，及/或可與第一表面修整層111隔開而安置。第一傳導圖案112可由金屬製成，例如銅(Cu)及其等效物，但本實施例的方面不限於此。在一個實施例中，導通孔113形成於第一傳導圖案112上、連接到所述第一傳導圖案112，或毗鄰所述第一傳導圖案112，且相較於第一傳導圖案112可具有較小寬度及較大厚度。導通孔113也可由金屬製成，例如銅(Cu)及其等效物，但本實施例的方面不限於此。第一樹脂層114可覆蓋第一表面修整層111、第一傳導圖案112及導通孔113。然而，第一表面修整層111及第一傳導圖案112的頂部表面可不由第一樹脂層114覆蓋。並且，導通孔113的底部表面可不由第一樹脂層114覆蓋。第一樹脂層114可由聚合物材料製成，例如一或多種聚醯亞胺(PI)、苯並環丁烯(BCB)、聚苯並惡唑(PBO)、雙馬來醯亞胺三嗪(BT)、酚系樹脂、環氧模制化合物及其等效物，但本實施例的方面不限於此。在一些實施例中，導通孔113連接到第一傳導圖案112的僅第一部分，從而使第一傳導圖案112的第二部分至少部分地嵌入在第一樹脂層114內，如圖1A中大體上所說明。 In one embodiment, the first laminate layer 110 includes a first surface finishing layer 111, a first bonding layer 111 or a first wire bondable finishing layer 111, a first conductive pattern 112, a via 113, a conductive via 113, or The conductive pillar 113 and the first resin layer 114. In some embodiments, the first surface finishing layer 111 may be a metal material, such as nickel/gold (Ni/Au), silver (Ag), copper (Cu), combinations thereof, and equivalents thereof, but in this embodiment The aspect is not limited to this. In one embodiment, the first conductive pattern 112 may be disposed on the first surface finishing layer 111 or adjacent to the first surface finishing layer 111, and/or may be disposed apart from the first surface finishing layer 111. The first conductive pattern 112 may be made of metal, such as copper (Cu) and its equivalent, but the aspect of the embodiment is not limited thereto. In one embodiment, the via 113 is formed on the first conductive pattern 112, is connected to the first conductive pattern 112, or is adjacent to the first conductive pattern 112, and may have a higher value than the first conductive pattern 112. Small width and large thickness. The via 113 may also be made of metal, such as copper (Cu) and its equivalent, but the aspect of the embodiment is not limited thereto. The first resin layer 114 may cover the first surface finishing layer 111, the first conductive pattern 112 and the via 113. However, the top surface of the first surface finishing layer 111 and the first conductive pattern 112 may not be covered by the first resin layer 114. Also, the bottom surface of the via hole 113 may not be covered by the first resin layer 114. The first resin layer 114 may be made of polymer materials, such as one or more of polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), phenolic resin, epoxy molding compound, and equivalents thereof, but the aspect of the embodiment is not limited thereto. In some embodiments, the via 113 is connected to only the first portion of the first conductive pattern 112, so that the second portion of the first conductive pattern 112 is at least partially embedded in the first resin layer 114, as shown in FIG. 1A generally Explained.

在一個實施例中，第二層壓層120包含第二傳導圖案121、凸塊墊122，及第二樹脂層123。在一個實施例中，第二傳導圖案121可安置在導通孔113上或毗鄰所述導通孔113，且可定位成鄰近於第一樹脂層114的底部表面。在一些實施例中，第二傳導圖案121可安置在第一樹脂層114的底部表面上或毗鄰所述第一樹脂層114的所述底部表面。另外，第二傳導圖案121可為金屬，例如銅(Cu)及其等效物，但本實施例的方面不限於此。在一個實施例中，凸塊墊122可形成於第二傳導圖案121上，連接到所述第二傳導圖案121，或毗鄰所述第二傳導圖案121，且可相較於第二傳導圖案121具有較小寬度及較大厚度。凸塊墊122也可為金屬，例如銅(Cu)及其等效物，但本實施例的方面不限於此。第二樹脂層123可覆蓋第一樹脂層114、第二傳導圖案121及凸塊墊122的至少部分。然而，第二傳導圖案121的頂部表面可不由第二樹脂層123覆蓋。並且，凸塊墊122的底部表面可不由第二樹脂層123覆蓋且可暴露於外部。第二樹脂層123可由聚合物材料製成，例如一或多種聚醯亞胺(PI)、苯並環丁烯(BCB)、聚苯並惡唑(PBO)、雙馬來醯亞胺三嗪(BT)、酚系樹脂、環氧模制化合物及其等效物，但本實施例的方面不限於此。 In one embodiment, the second laminate layer 120 includes a second conductive pattern 121, a bump pad 122, and a second resin layer 123. In one embodiment, the second conductive pattern 121 may be disposed on or adjacent to the through hole 113 and may be positioned adjacent to the bottom surface of the first resin layer 114. In some embodiments, the second conductive pattern 121 may be disposed on or adjacent to the bottom surface of the first resin layer 114. In addition, the second conductive pattern 121 may be a metal, such as copper (Cu) and its equivalent, but the aspect of the embodiment is not limited thereto. In one embodiment, the bump pad 122 can be formed on the second conductive pattern 121, connected to the second conductive pattern 121, or adjacent to the second conductive pattern 121, and can be compared to the second conductive pattern 121 It has a smaller width and a larger thickness. The bump pad 122 may also be a metal, such as copper (Cu) and its equivalent, but the aspect of the embodiment is not limited thereto. The second resin layer 123 may cover at least part of the first resin layer 114, the second conductive pattern 121 and the bump pad 122. However, the top surface of the second conductive pattern 121 may not be covered by the second resin layer 123. Also, the bottom surface of the bump pad 122 may not be covered by the second resin layer 123 and may be exposed to the outside. The second resin layer 123 may be made of polymer materials, such as one or more of polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), phenolic resin, epoxy molding compound, and equivalents thereof, but the aspect of the embodiment is not limited thereto.

根據本實施例，包含第一層壓層110及第二層壓層120的堆疊結構可被稱作可路由囊封的傳導基板101或可路由的模制引線框架101，所述可路由囊封的傳導基板101或所述可路由的模制引線框架101可在製造半導體裝置100的過程中作為單個單元處置。 According to the present embodiment, the stack structure including the first laminate layer 110 and the second laminate layer 120 may be referred to as a routable encapsulated conductive substrate 101 or a routable molded lead frame 101. The conductive substrate 101 or the routable molded lead frame 101 may be handled as a single unit in the process of manufacturing the semiconductor device 100.

在一個實施例中，半導體晶粒130連接到可路由的模制引線框架101。在一些實施例中，半導體晶粒130使用(例如)黏著劑135附接 到第一層壓層110，且進一步電連接到第一層壓層110。根據一個實施例，半導體晶粒130可使用導線140電連接到第一表面修整層111。在一個實施例中，導線140包括金線，且第一表面修整層111包括鎳/金(Ni/Au)或銀(Ag)。在此實施例中，導線140及第一表面修整層111可較容易地彼此連接。在一些實施例中，半導體晶粒130可包含電路，其包含(例如)數位訊號處理器(DSP)、網路處理器、功率管理單元、音訊處理器、RF電路、無線基帶晶片上系統(SoC)處理器、感測器、專用積體電路(ASIC)，及/或所屬技術領域中具有通常知識者已知的其它有源及/或無源電子裝置。 In one embodiment, the semiconductor die 130 is connected to a routable molded lead frame 101. In some embodiments, the semiconductor die 130 is attached using, for example, an adhesive 135 To the first laminate layer 110 and further electrically connected to the first laminate layer 110. According to one embodiment, the semiconductor die 130 may be electrically connected to the first surface finishing layer 111 using a wire 140. In one embodiment, the wire 140 includes a gold wire, and the first surface finishing layer 111 includes nickel/gold (Ni/Au) or silver (Ag). In this embodiment, the wire 140 and the first surface finishing layer 111 can be easily connected to each other. In some embodiments, the semiconductor die 130 may include circuits including, for example, a digital signal processor (DSP), a network processor, a power management unit, an audio processor, an RF circuit, and a wireless baseband system on chip (SoC ) Processors, sensors, dedicated integrated circuits (ASICs), and/or other active and/or passive electronic devices known to those with ordinary knowledge in the technical field.

在一個實施例中，囊封物150囊封、覆蓋或模制可路由的模制引線框架101，所述可路由的模制引線框架101包含(例如)半導體晶粒130及導線140，以及第一層壓層110的至少部分。在一些實施例中，囊封物150可覆蓋第一表面修整層111及第一傳導圖案112。囊封物150可為聚合物複合材料，例如，用於通過模制過程執行囊封的環氧模制化合物、用於通過分配器執行囊封的液體囊封部件，或其等效物，但本實施例的方面不限於此。在一個優選實施例中，當第一樹脂層114、第二樹脂層123及囊封物150使用同一材料形成時，其可具有相同熱膨脹係數，進而在半導體裝置100的製造過程或操作期間最小化翹曲。 In one embodiment, the encapsulant 150 encapsulates, covers, or molds a routable molded lead frame 101 that includes, for example, a semiconductor die 130 and wires 140, and a first At least part of a laminated layer 110. In some embodiments, the encapsulant 150 may cover the first surface modification layer 111 and the first conductive pattern 112. The encapsulant 150 may be a polymer composite material, for example, an epoxy molding compound used to perform encapsulation through a molding process, a liquid encapsulation component used to perform encapsulation through a dispenser, or an equivalent thereof, but The aspect of this embodiment is not limited to this. In a preferred embodiment, when the first resin layer 114, the second resin layer 123, and the encapsulant 150 are formed using the same material, they may have the same coefficient of thermal expansion, thereby minimizing during the manufacturing process or operation of the semiconductor device 100 Warped.

在一個實施例中，傳導凸塊160可連接到凸塊墊122。在一個實施例中，傳導凸塊160可熔接或附接到凸塊墊122，所述凸塊墊122不由第二樹脂層123覆蓋。傳導凸塊160可為導柱、具有焊蓋的導柱、傳導球、焊球及其等效物，但本實施例的方面不限於此。在所說明的實施例中，傳導凸塊160作為一個實例展示為傳導球。 In one embodiment, the conductive bump 160 may be connected to the bump pad 122. In one embodiment, the conductive bump 160 may be welded or attached to the bump pad 122 that is not covered by the second resin layer 123. The conductive bump 160 may be a guide post, a guide post with a solder cover, a conductive ball, a solder ball, and equivalents thereof, but the aspect of the embodiment is not limited thereto. In the illustrated embodiment, the conductive bump 160 is shown as a conductive ball as an example.

根據本實施例，半導體裝置100經配置為經線接合的可路由的模制引線框架封裝，其經進一步配置為球柵陣列類型封裝。 According to the present embodiment, the semiconductor device 100 is configured as a wire-bonded routable molded lead frame package, which is further configured as a ball grid array type package.

根據本實施例，包含(例如)第一層壓層110及第二層壓層120的可路由的模制引線框架101及囊封物150的側表面通過在製造半導體裝置100的過程中分離而經配置為彼此共面。在一個實施例中，以下各者的側表面基本上彼此共面：第一層壓層110的第一樹脂層114、第二層壓層120的第二樹脂層123以及囊封物150。在一個優選的實施例中，第一層壓層110的第一傳導圖案112不通過第一樹脂層114的側表面暴露於外部，且第二層壓層120的第二傳導圖案121不通過第二樹脂層123的側表面暴露於外部。因此，可防止第一傳導圖案112及第二傳導圖案121中的每一者與外部裝置之間的不必要的電短路。另外，因為第一表面修整層111形成於第一傳導圖案112上，因此導線140可容易地連接到第一表面修整層111。 According to this embodiment, the side surfaces of the routable molded lead frame 101 and the encapsulant 150 including, for example, the first laminate layer 110 and the second laminate layer 120 are separated in the process of manufacturing the semiconductor device 100 It is configured to be coplanar with each other. In one embodiment, the side surfaces of each of the following are substantially coplanar with each other: the first resin layer 114 of the first laminate layer 110, the second resin layer 123 of the second laminate layer 120, and the encapsulant 150. In a preferred embodiment, the first conductive pattern 112 of the first laminate layer 110 is not exposed to the outside through the side surface of the first resin layer 114, and the second conductive pattern 121 of the second laminate layer 120 does not pass through the The side surface of the second resin layer 123 is exposed to the outside. Therefore, unnecessary electrical short circuits between each of the first conductive pattern 112 and the second conductive pattern 121 and the external device can be prevented. In addition, because the first surface finishing layer 111 is formed on the first conductive pattern 112, the wire 140 may be easily connected to the first surface finishing layer 111.

如圖1B中所說明，在一個實施例中，第一表面修整層111的頂部表面基本上與第一樹脂層114的頂部表面共面。然而，與第一表面修整層111水準或側向隔開的第一傳導圖案112中的每一者的頂部表面可低於第一樹脂層114的頂部表面或相對於所述第一樹脂層114的所述頂部表面凹陷。此外，凸塊墊122中的每一者的底部表面高於第二樹脂層123的底部表面或相對於所述第二樹脂層123的所述底部表面凹陷。換句話說，第一傳導圖案112中的每一者的頂部表面在形成於第一樹脂層114中的第一開口114a內部凹陷。同樣地，凸塊墊122中的每一者的底部表面在形成於第二樹脂層123中的第二開口123a內部凹陷。 As illustrated in FIG. 1B, in one embodiment, the top surface of the first surface finishing layer 111 is substantially coplanar with the top surface of the first resin layer 114. However, the top surface of each of the first conductive patterns 112 that are horizontally or laterally spaced from the first surface finishing layer 111 may be lower than the top surface of the first resin layer 114 or relative to the first resin layer 114. The top surface is recessed. In addition, the bottom surface of each of the bump pads 122 is higher than the bottom surface of the second resin layer 123 or recessed relative to the bottom surface of the second resin layer 123. In other words, the top surface of each of the first conductive patterns 112 is recessed inside the first opening 114 a formed in the first resin layer 114. Likewise, the bottom surface of each of the bump pads 122 is recessed inside the second opening 123a formed in the second resin layer 123.

根據本實施例，此類配置特徵可由製造過程所造成。舉例來 說，當對第一樹脂層114執行移除步驟(例如研磨及/或蝕刻)時，第一表面修整層111充當遮罩，且第一傳導圖案112中的每一者的頂部表面可比第一樹脂層114略微多地過度蝕刻以使得第一傳導圖案112中的每一者的頂部表面可定位在第一開口114a內部或在所述第一開口114a內凹陷。另外，當對第二樹脂層123執行移除步驟(例如，研磨及/或蝕刻)時，第二傳導圖案121中的每一者的底部表面相對於第二樹脂層123過度蝕刻，以使得第二傳導圖案121中的每一者的底部表面可定位在第二開口123a內部或在所述第二開口123a內凹陷。 According to this embodiment, such configuration features can be caused by the manufacturing process. For example In other words, when a removal step (such as grinding and/or etching) is performed on the first resin layer 114, the first surface finishing layer 111 serves as a mask, and the top surface of each of the first conductive patterns 112 can be more The resin layer 114 is slightly over-etched so that the top surface of each of the first conductive patterns 112 can be positioned inside the first opening 114a or recessed in the first opening 114a. In addition, when a removing step (for example, grinding and/or etching) is performed on the second resin layer 123, the bottom surface of each of the second conductive patterns 121 is over-etched with respect to the second resin layer 123, so that The bottom surface of each of the two conductive patterns 121 may be positioned inside the second opening 123a or recessed in the second opening 123a.

因此，根據本實施例，形成於第一樹脂層114中的第一開口114a改進囊封物150與第一樹脂層114之間的耦合力，且形成於第二樹脂層123中的第二開口123a改進傳導凸塊160、凸塊墊122及第二樹脂層123中的每一者之間的耦合力。在一些實施例中，導通孔113及第一傳導圖案112及/或第二傳導圖案121以及凸塊墊122的部分於如在圖1B中大體上所說明的橫截面圖中形成如同“T”的形狀。在一些實施例中，第一傳導圖案112及導通孔113為第一傳導結構的實例，且第二傳導圖案121及凸塊墊122為第二傳導結構的實例。換句話說，第一傳導結構可包括第一傳導圖案112及導通孔113，且第二傳導結構可包括第二傳導圖案121及凸塊墊122。 Therefore, according to the present embodiment, the first opening 114a formed in the first resin layer 114 improves the coupling force between the encapsulant 150 and the first resin layer 114, and the second opening formed in the second resin layer 123 123a improves the coupling force between each of the conductive bump 160, the bump pad 122, and the second resin layer 123. In some embodiments, the portion of the via 113 and the first conductive pattern 112 and/or the second conductive pattern 121 and the bump pad 122 is formed like a "T" in the cross-sectional view as generally illustrated in FIG. 1B shape. In some embodiments, the first conductive pattern 112 and the via 113 are examples of the first conductive structure, and the second conductive pattern 121 and the bump pad 122 are examples of the second conductive structure. In other words, the first conductive structure may include the first conductive pattern 112 and the via 113, and the second conductive structure may include the second conductive pattern 121 and the bump pad 122.

圖2A為根據另一實施例的說明具有表面修整層的半導體裝置200或經封裝半導體裝置200的橫截面圖；圖2B為說明圖2A的區的放大橫截面圖；且圖2C為根據替代性實施例的說明不具有表面修整層的區的放大橫截面圖。 2A is a cross-sectional view illustrating a semiconductor device 200 with a surface modification layer or a packaged semiconductor device 200 according to another embodiment; FIG. 2B is an enlarged cross-sectional view illustrating the area of FIG. 2A; and FIG. 2C is a view based on the alternative Description of Examples An enlarged cross-sectional view of a region without a surface finishing layer.

如圖2A中所說明，代替使用傳導凸塊，可路由的模制引線 框架101可替代地包含形成於第二層壓層120的凸塊墊122上或連接到所述第二層壓層120的所述凸塊墊122的第二表面修整層224或第二接合層224。在一些實施例中，第二表面修整層224可包括金屬材料，例如鎳/金(Ni/Au)、銀(Ag)、錫(Sn)、其組合及其等效物，但本發明的實施例的方面不限於此。根據本實施例，半導體裝置200經配置為經線接合的可路由的模制引線框架封裝，其經進一步配置為柵格陣列類型封裝。在另一實施例中，傳導凸塊可連接到第二表面修整層224。 As illustrated in Figure 2A, instead of using conductive bumps, routable molded leads The frame 101 may alternatively include a second surface finishing layer 224 or a second bonding layer formed on the bump pad 122 of the second laminate layer 120 or connected to the bump pad 122 of the second laminate layer 120 224. In some embodiments, the second surface finishing layer 224 may include metal materials, such as nickel/gold (Ni/Au), silver (Ag), tin (Sn), combinations thereof, and equivalents thereof, but the implementation of the present invention The aspect of the example is not limited to this. According to the present embodiment, the semiconductor device 200 is configured as a wire-bonded routable molded lead frame package, which is further configured as a grid array type package. In another embodiment, the conductive bumps may be connected to the second surface finishing layer 224.

如圖2B中所說明，在一個實施例中，第一表面修整層111的頂部表面基本上與第一樹脂層114的頂部表面共面，且第二表面修整層224的底部表面基本上與第二樹脂層123的底部表面共面。然而，與第一表面修整層111水準或側向隔開的第一傳導圖案112中的每一者的頂部表面可低於第一樹脂層114的頂部表面或相對於所述第一樹脂層114的所述頂部表面凹陷。換句話說，第一傳導圖案112中的每一者的頂部表面在形成於第一樹脂層114中的第一開口114a內部凹陷。 As illustrated in FIG. 2B, in one embodiment, the top surface of the first surface modifying layer 111 is substantially coplanar with the top surface of the first resin layer 114, and the bottom surface of the second surface modifying layer 224 is substantially coplanar with the first resin layer 114. The bottom surfaces of the two resin layers 123 are coplanar. However, the top surface of each of the first conductive patterns 112 that are horizontally or laterally spaced from the first surface finishing layer 111 may be lower than the top surface of the first resin layer 114 or relative to the first resin layer 114. The top surface is recessed. In other words, the top surface of each of the first conductive patterns 112 is recessed inside the first opening 114 a formed in the first resin layer 114.

根據本實施例，此類配置特徵可由製造過程所造成。舉例來說，當對第一樹脂層114及/或第二樹脂層123執行移除步驟(例如，研磨及/或蝕刻)時，第一表面修整層111及/或第二樹脂層123充當遮罩，且第一傳導圖案112中的每一者的頂部表面可比第一樹脂層114略微多地過度蝕刻，以使得第一傳導圖案112中的每一者的頂部表面定位在形成於第一樹脂層114中的第一開口114a內部或在所述第一開口114a內凹陷。 According to this embodiment, such configuration features can be caused by the manufacturing process. For example, when performing a removal step (eg, grinding and/or etching) on the first resin layer 114 and/or the second resin layer 123, the first surface finishing layer 111 and/or the second resin layer 123 act as a mask Cover, and the top surface of each of the first conductive patterns 112 may be slightly over-etched than the first resin layer 114, so that the top surface of each of the first conductive patterns 112 is positioned at the top surface formed in the first resin layer. The first opening 114a in the layer 114 is inside or recessed in the first opening 114a.

如圖2C中所說明，當第一傳導圖案112'上無第一表面修整層形成且凸塊墊122'上無第二表面修整層形成時，第一傳導圖案112'中的每 一者的頂部表面可定位成低於第一樹脂層114'的頂部表面或相對於所述第一樹脂層114'的所述頂部表面凹陷，且凸塊墊122'中的每一者的底部表面可定位成高於第二樹脂層123'的底部表面或相對於所述第二樹脂層123'的所述底部表面凹陷。在一個實施例中，當在不存在遮罩層的情況下對第一樹脂層114'及/或第二樹脂層123'執行移除步驟(例如，研磨及/或蝕刻)時，第一傳導圖案112'中的每一者的頂部表面及/或凸塊墊122'中的每一者的底部表面可相較於第一樹脂層114'及/或第二樹脂層123'過度蝕刻。因此，第一傳導圖案112'定位在第一樹脂層114'的第一開口114a'內部或在所述第一樹脂層114'的所述第一開口114a'內凹陷，且凸塊墊122'中的每一者的底部表面定位在第二樹脂層123'的第二開口123a'內部或在所述第二樹脂層123'的所述第二開口123a'內凹陷。 As illustrated in FIG. 2C, when no first surface finishing layer is formed on the first conductive pattern 112' and no second surface finishing layer is formed on the bump pad 122', each of the first conductive patterns 112' The top surface of one may be positioned lower than the top surface of the first resin layer 114' or recessed relative to the top surface of the first resin layer 114', and the bottom of each of the bump pads 122' The surface may be positioned higher than the bottom surface of the second resin layer 123' or recessed relative to the bottom surface of the second resin layer 123'. In one embodiment, when the first resin layer 114' and/or the second resin layer 123' is removed (for example, grinding and/or etching) without the mask layer, the first conductive layer The top surface of each of the patterns 112' and/or the bottom surface of each of the bump pads 122' may be over-etched compared to the first resin layer 114' and/or the second resin layer 123'. Therefore, the first conductive pattern 112' is positioned inside the first opening 114a' of the first resin layer 114' or recessed in the first opening 114a' of the first resin layer 114', and the bump pad 122' The bottom surface of each of them is positioned inside the second opening 123a' of the second resin layer 123' or recessed in the second opening 123a' of the second resin layer 123'.

圖3為根據另一實施例的說明具有表面修整層的半導體裝置300或經封裝半導體裝置300的橫截面圖。如圖3中所說明，第一表面修整層311、第一接合層311或第一可線接合修整層311包括金屬材料，例如銀(Ag)，且由銅(Cu)製成的導通孔113可形成於第一表面修整層311上，連接到所述第一表面修整層311，或毗鄰所述第一表面修整層311。根據本實施例，在半導體裝置300中，導線140可較容易地接合到由銀(Ag)製成的第一表面修整層311。另外，根據本實施例，半導體裝置300經配置為經線接合的可路由的模制引線框架封裝，其經進一步配置為球柵陣列類型封裝。此外，根據本實施例，第一表面修整層311還可經配置為用於半導體裝置300的第一傳導圖案。在一些實施例中，導通孔113為第一傳導結構的實例，且第二傳導圖案121及凸塊墊122為第二傳導結構的實例。 3 is a cross-sectional view illustrating a semiconductor device 300 or a packaged semiconductor device 300 having a surface modification layer according to another embodiment. As illustrated in FIG. 3, the first surface trim layer 311, the first bonding layer 311, or the first wire bondable trim layer 311 includes a metal material, such as silver (Ag), and a via hole 113 made of copper (Cu) It can be formed on the first surface conditioning layer 311, connected to the first surface conditioning layer 311, or adjacent to the first surface conditioning layer 311. According to the present embodiment, in the semiconductor device 300, the wire 140 can be easily bonded to the first surface finishing layer 311 made of silver (Ag). In addition, according to the present embodiment, the semiconductor device 300 is configured as a wire-bonded routable molded lead frame package, which is further configured as a ball grid array type package. In addition, according to the present embodiment, the first surface finishing layer 311 may also be configured as a first conductive pattern for the semiconductor device 300. In some embodiments, the via 113 is an example of a first conductive structure, and the second conductive pattern 121 and the bump pad 122 are an example of a second conductive structure.

圖4為根據又一實施例的說明具有表面修整層的半導體裝置400或經封裝半導體裝置400的橫截面圖。如圖4中所說明，第一表面修整層411、第一接合層411或第一可線接合修整層411可包括金屬材料，例如銅(Cu)，且由銅(Cu)製成的導通孔113可形成於第一表面修整層411上，連接到所述第一表面修整層411，或毗鄰所述第一表面修整層411。根據本實施例，因為半導體晶粒130不通過線接合直接連接到第一表面修整層411，因此其可通過其它類型的傳導連接結構(例如，微凸塊435)連接到第一表面修整層411。在一個實施例中，半導體晶粒130以倒裝晶片型配置電連接到第一表面修整層411。另外，囊封物150***在半導體晶粒130與第一層壓層110之間，進而允許半導體晶粒130及第一層壓層110彼此機械地整合。另外，由金屬材料(例如，鎳/金(Ni/Au)、銀(Ag)或錫(Sn))製成的第二表面修整層224或第二接合層224可形成於凸塊墊122上而非傳導凸塊上。根據本實施例，半導體裝置400經配置為倒裝晶片可路由的模制引線框架封裝，其經進一步配置為柵格陣列類型封裝。根據本實施例，第一表面修整層411還可經配置為用於半導體裝置400的第一傳導圖案。在一替代性實施例中，傳導凸塊可形成於第二表面修整層224上。在一些實施例中，導通孔113為第一傳導結構的實例，且第二傳導圖案121及凸塊墊122為第二傳導結構的實例。應理解，圖4中用於半導體晶粒130的附接配置可用於本文中所描述的實施例中的任一者中。 4 is a cross-sectional view illustrating a semiconductor device 400 or a packaged semiconductor device 400 having a surface modification layer according to another embodiment. As illustrated in FIG. 4, the first surface trim layer 411, the first bonding layer 411, or the first wire bondable trim layer 411 may include a metal material, such as copper (Cu), and a via hole made of copper (Cu) 113 may be formed on the first surface finishing layer 411, connected to the first surface finishing layer 411, or adjacent to the first surface finishing layer 411. According to this embodiment, because the semiconductor die 130 is not directly connected to the first surface finishing layer 411 through wire bonding, it can be connected to the first surface finishing layer 411 through other types of conductive connection structures (for example, micro bumps 435) . In one embodiment, the semiconductor die 130 is electrically connected to the first surface finishing layer 411 in a flip-chip configuration. In addition, the encapsulant 150 is inserted between the semiconductor die 130 and the first laminate layer 110, thereby allowing the semiconductor die 130 and the first laminate layer 110 to be mechanically integrated with each other. In addition, a second surface finishing layer 224 or a second bonding layer 224 made of a metal material (for example, nickel/gold (Ni/Au), silver (Ag), or tin (Sn)) may be formed on the bump pad 122 Instead of conductive bumps. According to this embodiment, the semiconductor device 400 is configured as a flip-chip routable molded lead frame package, which is further configured as a grid array type package. According to this embodiment, the first surface finishing layer 411 may also be configured as a first conductive pattern for the semiconductor device 400. In an alternative embodiment, conductive bumps may be formed on the second surface finishing layer 224. In some embodiments, the via 113 is an example of a first conductive structure, and the second conductive pattern 121 and the bump pad 122 are an example of a second conductive structure. It should be understood that the attachment configuration for semiconductor die 130 in FIG. 4 may be used in any of the embodiments described herein.

圖5A為說明由經封裝單元的N×M矩陣或陣列構成的載體171的平面圖，且圖5B為說明由1xM個單元構成的載體172的平面圖。如圖5A中所說明，於其上製造(例如)半導體裝置100到400的載體171形 成於由N×M個單元構成的矩陣中。在一個實施例中，N及M優選地可為大於或等於2的整數。如上文所描述，由於載體171以矩陣類型形成，因此可大批量地製造根據本發明的實施例的半導體裝置100到半導體裝置400。如圖5B中所說明，載體172可作為1xM個單元的條帶形成。在一個實施例中，M優選地可為大於1的整數。 FIG. 5A is a plan view illustrating a carrier 171 composed of an N×M matrix or array of encapsulated cells, and FIG. 5B is a plan view illustrating a carrier 172 composed of 1×M cells. As illustrated in FIG. 5A, the carrier 171 on which, for example, the semiconductor devices 100 to 400 are manufactured It is formed in a matrix composed of N×M units. In one embodiment, N and M may preferably be integers greater than or equal to 2. As described above, since the carrier 171 is formed in a matrix type, the semiconductor device 100 to the semiconductor device 400 according to the embodiment of the present invention can be mass-produced. As illustrated in FIG. 5B, the carrier 172 may be formed as a strip of 1×M units. In one embodiment, M may preferably be an integer greater than one.

圖6A到圖6J為依序說明具有表面修整層111的半導體裝置100或經封裝半導體裝置100的製造方法的實施例的橫截面圖。如圖6A到圖6J中所說明，半導體裝置100的製造方法包含以下步驟：提供載體170及形成第一表面修整層111；形成第一傳導圖案112；形成導通孔113；提供第一樹脂層114；首先移除(例如，研磨)第一樹脂層114的一部分；形成第二傳導圖案121；形成凸塊墊122；提供第二樹脂層123；移除載體170；連接半導體晶粒130；形成囊封物150；以及形成傳導凸塊160。 6A to 6J are cross-sectional views sequentially illustrating embodiments of the semiconductor device 100 having the surface modification layer 111 or the method of manufacturing the packaged semiconductor device 100. As illustrated in FIGS. 6A to 6J, the manufacturing method of the semiconductor device 100 includes the following steps: providing a carrier 170 and forming a first surface finishing layer 111; forming a first conductive pattern 112; forming a via 113; providing a first resin layer 114 First remove (eg, grind) a portion of the first resin layer 114; form the second conductive pattern 121; form the bump pad 122; provide the second resin layer 123; remove the carrier 170; connect the semiconductor die 130; form a capsule Encapsulation 150; and forming conductive bumps 160.

如圖6A中所說明，在提供載體170及形成第一表面修整層111的步驟中，製備具有(例如)基本上扁平板狀形狀的載體170，且多個第一表面修整層111形成於載體170的主表面上或鄰近於所述載體170的所述主表面形成。在一個實施例中，載體170可由傳導材料(例如，銅(Cu))、絕緣材料(例如，聚醯亞胺)及/或陶瓷材料(例如，氧化鋁)，或所屬技術領域中具有通常知識者已知的其它材料製成。在載體170由傳導材料製成的一些實施例中，第一表面修整層111可形成於載體170的表面上，連接到所述載體170的所述表面，或毗鄰所述載體170的所述表面。在載體170由絕緣材料或陶瓷材料製成的其它實施例中，傳導晶種層(由(例如)鎢或鎢鈦製成)可首先形成，且第一表面修整層111接著可形成於傳導晶種層 上，連接到所述傳導晶種層，或毗鄰所述傳導晶種層。另外，第一表面修整層111可通過物理氣相沉積(PVD)、化學氣相沉積(CVD)、金屬濺鍍、金屬蒸鍍、電解或無電電鍍或所屬技術領域中具有通常知識者已知的其它形成技術形成。根據本實施例，第一表面修整層111包括較容易地接合到傳導連接結構(例如，連接線或凸塊)或與所述傳導連接結構形成接合的材料。另外，第一表面修整層111優選地包括相對於第一傳導圖案112選擇性地蝕刻的材料。在一些實施例中，第一表面修整層111可由鎳/金(Ni/Au)或銀(Ag)製成，但本實施例的方面不限於此。在一個實施例中，第一表面修整層111具有在從大約0.1微米到15微米的範圍內的厚度。 As illustrated in FIG. 6A, in the steps of providing the carrier 170 and forming the first surface finishing layer 111, a carrier 170 having, for example, a substantially flat plate shape is prepared, and a plurality of first surface finishing layers 111 are formed on the carrier. It is formed on or adjacent to the main surface of the carrier 170. In one embodiment, the carrier 170 may be made of conductive materials (for example, copper (Cu)), insulating materials (for example, polyimide), and/or ceramic materials (for example, alumina), or have general knowledge in the technical field. Made of other materials known to the author. In some embodiments where the carrier 170 is made of a conductive material, the first surface finishing layer 111 may be formed on the surface of the carrier 170, connected to the surface of the carrier 170, or adjacent to the surface of the carrier 170 . In other embodiments where the carrier 170 is made of an insulating material or a ceramic material, a conductive seed layer (made of, for example, tungsten or tungsten titanium) may be formed first, and the first surface modification layer 111 may then be formed on the conductive crystal. Seed layer Above, connected to the conductive seed layer, or adjacent to the conductive seed layer. In addition, the first surface finishing layer 111 can be obtained by physical vapor deposition (PVD), chemical vapor deposition (CVD), metal sputtering, metal evaporation, electrolysis or electroless plating, or those known to those with ordinary knowledge in the technical field. Other formation techniques are formed. According to the present embodiment, the first surface finishing layer 111 includes a material that is easily bonded to the conductive connection structure (for example, a connection line or bump) or forms a bond with the conductive connection structure. In addition, the first surface finishing layer 111 preferably includes a material that is selectively etched with respect to the first conductive pattern 112. In some embodiments, the first surface finishing layer 111 may be made of nickel/gold (Ni/Au) or silver (Ag), but aspects of the present embodiment are not limited thereto. In one embodiment, the first surface conditioning layer 111 has a thickness in a range from about 0.1 microns to 15 microns.

如圖6B中所說明，在形成第一傳導圖案112的步驟中，第一傳導圖案112形成於第一表面修整層111及載體170的表面上，連接到所述第一表面修整層111及所述載體170的表面，或毗鄰所述第一表面修整層111及所述載體170的表面。更具體地說，第一傳導圖案經配置為經路由的第一傳導圖案112，且可形成於第一表面修整層111及載體170的表面上。第一傳導圖案112可通過PVD、CVD、金屬濺鍍、金屬蒸鍍、電解或無電電鍍或所屬技術領域中具有通常知識者已知的其它形成技術形成。另外，第一傳導圖案112可由傳導材料製成，例如銅(Cu)。在一個實施例中，第一傳導圖案112具有在從大約3微米到30微米的範圍內的厚度。 As illustrated in FIG. 6B, in the step of forming the first conductive pattern 112, the first conductive pattern 112 is formed on the surface of the first surface finishing layer 111 and the carrier 170, and is connected to the first surface finishing layer 111 and the surface of the carrier 170. The surface of the carrier 170, or adjacent to the first surface finishing layer 111 and the surface of the carrier 170. More specifically, the first conductive pattern is configured as a routed first conductive pattern 112 and can be formed on the surface of the first surface finishing layer 111 and the carrier 170. The first conductive pattern 112 may be formed by PVD, CVD, metal sputtering, metal evaporation, electrolysis or electroless plating, or other forming techniques known to those having ordinary knowledge in the art. In addition, the first conductive pattern 112 may be made of a conductive material, such as copper (Cu). In one embodiment, the first conductive pattern 112 has a thickness in a range from about 3 microns to 30 microns.

如圖6C中所說明，在形成導通孔113、傳導導通孔113或傳導柱113的步驟中，形狀為相對厚的導柱的導通孔113形成於第一傳導圖案112上，連接到所述第一傳導圖案112，或毗鄰所述第一傳導圖案112。導通孔113可通過無電電鍍及/或電鍍形成且可由銅(Cu)製成。在一個實 施例中，導通孔113具有在從大約20微米到100微米的範圍內的厚度。 As illustrated in FIG. 6C, in the step of forming a via 113, a conductive via 113, or a conductive pillar 113, a via 113 shaped as a relatively thick conductive pillar is formed on the first conductive pattern 112 and is connected to the first conductive pattern 112. A conductive pattern 112 or adjacent to the first conductive pattern 112. The via 113 may be formed by electroless plating and/or electroplating and may be made of copper (Cu). In a real In an embodiment, the via hole 113 has a thickness in a range from about 20 microns to 100 microns.

如圖6D中所說明，在形成第一樹脂層114的步驟中，第一樹脂層114形成或被塗布到載體170上，進而允許第一樹脂層114覆蓋載體170、第一表面修整層111、第一傳導圖案112及導通孔113。在一些實施例中，第一樹脂層114可通過(例如)旋塗、噴塗或深塗接著通過UV及/或熱固化而形成於載體170上。第一樹脂層114可由聚合物材料製成，例如一或多種聚醯亞胺(PI)、苯並環丁烯(BCB)、聚苯並惡唑(PBO)、雙馬來醯亞胺三嗪(BT)、酚系樹脂、環氧模制化合物及其等效物，但本實施例的方面不限於此。在一個實施例中，第一樹脂層114與囊封物150相似可由普通環氧模制化合物製成。在此實施例中，第一樹脂層114可通過壓縮模塑或傳遞模塑形成。 As illustrated in FIG. 6D, in the step of forming the first resin layer 114, the first resin layer 114 is formed or coated on the carrier 170, thereby allowing the first resin layer 114 to cover the carrier 170, the first surface finishing layer 111, The first conductive pattern 112 and the via 113. In some embodiments, the first resin layer 114 may be formed on the carrier 170 by, for example, spin coating, spray coating or deep coating followed by UV and/or thermal curing. The first resin layer 114 may be made of polymer materials, such as one or more of polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), phenolic resin, epoxy molding compound, and equivalents thereof, but the aspect of the embodiment is not limited thereto. In one embodiment, the first resin layer 114 and the encapsulant 150 can be made of common epoxy molding compound similarly. In this embodiment, the first resin layer 114 may be formed by compression molding or transfer molding.

如圖6E中所說明，在第一次移除的步驟中，使用(例如)研磨及/或蝕刻製程部分地移除第一樹脂層114直到導通孔113暴露於第一樹脂層114外部為止。以此方式，導通孔113的頂部表面變得基本上與第一樹脂層114的頂部表面共面。 As illustrated in FIG. 6E, in the first removal step, the first resin layer 114 is partially removed using, for example, a grinding and/or etching process until the via 113 is exposed to the outside of the first resin layer 114. In this way, the top surface of the via hole 113 becomes substantially coplanar with the top surface of the first resin layer 114.

根據本實施例，第一表面修整層111、第一傳導圖案112、導通孔113及第一樹脂層114可共同地界定為第一層壓層110。 According to the present embodiment, the first surface finishing layer 111, the first conductive pattern 112, the via 113, and the first resin layer 114 may be collectively defined as the first laminate layer 110.

如圖6F中所說明，在形成第二傳導圖案121的步驟中，第二傳導圖案121形成於通過第一樹脂層114暴露於外部的導通孔113上，毗鄰所述導通孔113，或連接到所述導通孔113。在一個實施例中，第二傳導圖案121於第二樹脂層123上路由同時電連接到導通孔113。第二傳導圖案121可通過PVD、CVD、金屬濺鍍、金屬蒸鍍、電解或無電電鍍或所屬技術 領域中具有通常知識者已知的其它形成技術形成。另外，第二傳導圖案121可由傳導材料製成，例如銅(Cu)。在一個實施例中，第二傳導圖案121具有在從大約3微米到15微米的範圍內的厚度。 As illustrated in FIG. 6F, in the step of forming the second conductive pattern 121, the second conductive pattern 121 is formed on the via hole 113 exposed to the outside through the first resin layer 114, adjacent to the via hole 113, or connected to The via hole 113. In one embodiment, the second conductive pattern 121 is routed on the second resin layer 123 and electrically connected to the via 113 at the same time. The second conductive pattern 121 can be through PVD, CVD, metal sputtering, metal evaporation, electrolysis or electroless plating or other technologies. Other formation techniques known to those with ordinary knowledge in the field are formed. In addition, the second conductive pattern 121 may be made of a conductive material, such as copper (Cu). In one embodiment, the second conductive pattern 121 has a thickness in a range from about 3 microns to 15 microns.

如圖6G中所說明，在形成凸塊墊122的步驟中，凸塊墊122形成於第二傳導圖案121上，連接到所述第二傳導圖案121，或毗鄰或連接到所述第二傳導圖案121。凸塊墊122可通過PVD、CVD、金屬濺鍍、金屬蒸鍍、電解或無電電鍍或所屬技術領域中具有通常知識者已知的其它形成技術形成。另外，凸塊墊122可由傳導材料製成，例如銅(Cu)。在一個實施例中，凸塊墊122具有在從大約20微米到100微米的範圍內的厚度。 As illustrated in FIG. 6G, in the step of forming the bump pad 122, the bump pad 122 is formed on the second conductive pattern 121, connected to the second conductive pattern 121, or adjacent to or connected to the second conductive pattern 121 Pattern 121. The bump pad 122 may be formed by PVD, CVD, metal sputtering, metal evaporation, electrolysis or electroless plating, or other forming techniques known to those having ordinary knowledge in the art. In addition, the bump pad 122 may be made of a conductive material, such as copper (Cu). In one embodiment, the bump pad 122 has a thickness in a range from about 20 microns to 100 microns.

如圖6H中所說明，在形成第二樹脂層123的步驟中，第二樹脂層123形成或被塗布到第一層壓層110上，進而允許第二樹脂層123覆蓋第一樹脂層114、第二傳導圖案121及凸塊墊122。在一些實施例中，第二樹脂層123可以與第一樹脂層114相同的方法且使用與第一樹脂層114相同的材料塗布。另外，在塗布以及固化第二樹脂層123之後，可進一步執行第二次移除步驟。在第二次移除步驟中，使用(例如)研磨及/或蝕刻製程部分地移除第二樹脂層123直到凸塊墊122暴露於第二樹脂層123外部為止。以此方式，凸塊墊122的頂部表面變得基本上與第二樹脂層123的頂部表面共面。在一個實施例中，如果凸塊墊122上無遮罩層形成，那麼凸塊墊122的表面在如圖1B中所說明的蝕刻製程之後定位在第二樹脂層123的第二開口內部或在所述第二樹脂層123的所述第二開口內部凹陷。 As illustrated in FIG. 6H, in the step of forming the second resin layer 123, the second resin layer 123 is formed or coated on the first laminate layer 110, thereby allowing the second resin layer 123 to cover the first resin layer 114, The second conductive pattern 121 and the bump pad 122. In some embodiments, the second resin layer 123 may be coated with the same method as the first resin layer 114 and using the same material as the first resin layer 114. In addition, after coating and curing the second resin layer 123, a second removal step may be further performed. In the second removal step, the second resin layer 123 is partially removed using, for example, a grinding and/or etching process until the bump pad 122 is exposed to the outside of the second resin layer 123. In this way, the top surface of the bump pad 122 becomes substantially coplanar with the top surface of the second resin layer 123. In one embodiment, if no mask layer is formed on the bump pad 122, the surface of the bump pad 122 is positioned inside the second opening of the second resin layer 123 or in the second opening of the second resin layer 123 after the etching process as illustrated in FIG. 1B The second opening of the second resin layer 123 is recessed.

根據本實施例，第二傳導圖案121、凸塊墊122及第二樹脂層123可集體地界定為第二層壓層120。另外，第一層壓層110及第二層壓 層120可集體地界定為可路由的模制引線框架101。 According to the present embodiment, the second conductive pattern 121, the bump pad 122, and the second resin layer 123 may be collectively defined as the second laminate layer 120. In addition, the first laminated layer 110 and the second laminated layer The layer 120 may collectively be defined as a routable molded lead frame 101.

如圖6I中所說明，在移除載體170的步驟中，從第一層壓層110移除載體170。更具體地說，從第一表面修整層111、第一傳導圖案112及第一樹脂層114移除載體170，進而允許第一表面修整層111、第一傳導圖案112及第一樹脂層114暴露於外部。在一個實施例中，可使用研磨及/或蝕刻製程移除載體170。在一個實施例中，不具有第一表面修整層111的第一傳導圖案112的表面可過度蝕刻以定位在如圖1B中所說明的第一樹脂層114的第一開口內部或在所述第一樹脂層114的所述第一開口內凹陷。 As illustrated in FIG. 6I, in the step of removing the carrier 170, the carrier 170 is removed from the first laminate layer 110. More specifically, the carrier 170 is removed from the first surface finishing layer 111, the first conductive pattern 112, and the first resin layer 114, thereby allowing the first surface finishing layer 111, the first conductive pattern 112, and the first resin layer 114 to be exposed. To the outside. In one embodiment, the carrier 170 may be removed using a grinding and/or etching process. In one embodiment, the surface of the first conductive pattern 112 without the first surface finishing layer 111 may be over-etched to be positioned inside the first opening of the first resin layer 114 as illustrated in FIG. 1B or at the first opening The first opening of a resin layer 114 is recessed.

如圖6J中所說明，在連接半導體晶粒130、形成囊封物150及形成傳導凸塊160的步驟中，半導體晶粒130可使用(例如)黏著劑135附接到第一層壓層110。並且，半導體晶粒130可使用傳導連接結構(例如，導線140)電連接到第一表面修整層111。接下來，半導體晶粒130及導線140使用囊封物150加以囊封。囊封物150可為聚合物複合材料，例如，用於通過模制過程執行囊封的環氧模制化合物、用於通過分配器執行囊封的液體囊封部件，或其等效物，但本實施例的方面不限於此。在一個實施例中，傳導凸塊160形成於通過第二層壓層120暴露於外部的凸塊墊122上或連接到所述凸塊墊122。傳導凸塊160可選自由以下組成的群組：導柱、具有焊蓋的導柱、傳導球、焊球，及其等效物，但本實施例的方面不限於此。在圖6J的所說明的實施例中，傳導凸塊160作為一實例實施例展示為傳導球。 As illustrated in FIG. 6J, in the steps of connecting the semiconductor die 130, forming the encapsulant 150, and forming the conductive bump 160, the semiconductor die 130 may be attached to the first laminate layer 110 using, for example, an adhesive 135 . Also, the semiconductor die 130 may be electrically connected to the first surface finishing layer 111 using a conductive connection structure (for example, a wire 140). Next, the semiconductor die 130 and the wires 140 are encapsulated using the encapsulant 150. The encapsulant 150 may be a polymer composite material, for example, an epoxy molding compound used to perform encapsulation through a molding process, a liquid encapsulation component used to perform encapsulation through a dispenser, or an equivalent thereof, but The aspect of this embodiment is not limited to this. In one embodiment, the conductive bump 160 is formed on or connected to the bump pad 122 exposed to the outside through the second laminate layer 120. The conductive bump 160 may be selected from the group consisting of a guide post, a guide post with a solder cover, a conductive ball, a solder ball, and equivalents thereof, but the aspect of the embodiment is not limited thereto. In the illustrated embodiment of FIG. 6J, the conductive bump 160 is shown as a conductive ball as an example embodiment.

另外，如上文所描述，由於本實施例的過程可以N×M矩陣或1xM個條帶的形式執行，因此可接著執行分離過程(例如，鋸切過程) 以產生個別半導體裝置100。 In addition, as described above, since the process of this embodiment can be performed in the form of an N×M matrix or 1×M strips, a separation process (for example, a sawing process) can be subsequently performed To produce individual semiconductor devices 100.

根據本實施例，提供用於製造半導體裝置100的製造方法，其中第一表面修整層111首先形成且結構及元件的其餘部分可隨後形成。具體地說，本實施例提供經線接合的可路由的模制引線框架球柵陣列類型封裝。 According to the present embodiment, a manufacturing method for manufacturing the semiconductor device 100 is provided, in which the first surface modification layer 111 is formed first and the rest of the structure and elements can be formed later. Specifically, the present embodiment provides a routable molded lead frame ball grid array type package via wire bonding.

圖7A到圖7C為依序說明用於具有另一表面修整層224的半導體裝置200或經封裝半導體裝置200的製造方法的實施例的橫截面圖。在本實施例中，可使用結合圖6A到圖6H說明的製造步驟，且將不在此處再次重複其細節。 7A to 7C are cross-sectional views sequentially illustrating an embodiment of a method for manufacturing a semiconductor device 200 having another surface modification layer 224 or a packaged semiconductor device 200. In this embodiment, the manufacturing steps described in conjunction with FIGS. 6A to 6H can be used, and the details will not be repeated here.

如圖7A中所說明，在形成(例如，塗布以及固化)第二樹脂層123以及部分地移除(例如，研磨及/或蝕刻)第二樹脂層123的步驟之後，第二表面修整層224可進一步形成於通過第二樹脂層123暴露於外部的凸塊墊122上，連接到所述凸塊墊122，或毗鄰所述凸塊墊122。在一個實施例中，第二表面修整層224可通過PVD、CVD、金屬濺鍍、金屬蒸鍍、電解或無電電鍍或所屬技術領域中具有通常知識者已知的其它形成技術形成。根據本實施例，第二表面修整層224包括較容易地接合到安置在組裝的下一級上的傳導結構(例如，印刷電路板)或與所述傳導結構形成接合。在一些實施例中，第二表面修整層224可由鎳/金(Ni/Au)、銀(Ag)、錫(Sn)及其等效物製成，但本實施例的方面不限於此。 As illustrated in FIG. 7A, after the steps of forming (for example, coating and curing) the second resin layer 123 and partially removing (for example, grinding and/or etching) the second resin layer 123, the second surface finishing layer 224 It may be further formed on the bump pad 122 exposed to the outside through the second resin layer 123, connected to the bump pad 122, or adjacent to the bump pad 122. In an embodiment, the second surface finishing layer 224 may be formed by PVD, CVD, metal sputtering, metal evaporation, electrolysis or electroless plating, or other formation techniques known to those with ordinary knowledge in the art. According to the present embodiment, the second surface finishing layer 224 includes a conductive structure (for example, a printed circuit board) disposed on the next level of assembly or forms a bond with the conductive structure more easily. In some embodiments, the second surface finishing layer 224 may be made of nickel/gold (Ni/Au), silver (Ag), tin (Sn), and equivalents thereof, but the aspect of the embodiment is not limited thereto.

如圖7B中所說明，由於移除載體170，因此提供可路由的模制引線框架101，所述可路由的模制引線框架101具有通過第一層壓層110暴露於外部的第一表面修整層111及第一傳導圖案112，以及通過第二層壓 層120暴露於外部的第二表面修整層224。根據本實施例，第一表面修整層111在可路由的模制引線框架101的製造過程的初始階段形成，且第二表面修整層224在可路由的模制引線框架101的製造過程的最後階段形成。 As illustrated in FIG. 7B, since the carrier 170 is removed, a routable molded lead frame 101 is provided that has a first surface finish that is exposed to the outside through the first laminate layer 110 Layer 111 and first conductive pattern 112, and through the second lamination The layer 120 is exposed to the external second surface finishing layer 224. According to this embodiment, the first surface finishing layer 111 is formed in the initial stage of the manufacturing process of the routable molded lead frame 101, and the second surface finishing layer 224 is formed in the final stage of the manufacturing process of the routable molded lead frame 101 form.

如圖7C中所說明，半導體晶粒130使用(例如)黏著劑135附接到可路由的模制引線框架101，且半導體晶粒130由傳導連接結構(例如，導線140)電連接到第一表面修整層111。另外，半導體晶粒130及導線140可使用如先前所描述的囊封物150加以囊封或模制。 As illustrated in FIG. 7C, the semiconductor die 130 is attached to the routable molded lead frame 101 using, for example, an adhesive 135, and the semiconductor die 130 is electrically connected to the first by a conductive connection structure (e.g., wire 140). Surface finishing layer 111. In addition, the semiconductor die 130 and the wires 140 can be encapsulated or molded using the encapsulant 150 as previously described.

根據本實施例，傳導凸塊可不包含在凸塊墊122上，且先前形成的第二表面修整層224暴露於外部。因此，本實施例提供經線接合的可路由的模制引線框架柵格陣列封裝。在一替代性實施例中，傳導凸塊也可形成於第二表面修整層224上。 According to this embodiment, the conductive bumps may not be included on the bump pad 122, and the previously formed second surface finishing layer 224 is exposed to the outside. Therefore, the present embodiment provides a routable molded lead frame grid array package via wire bonding. In an alternative embodiment, the conductive bumps can also be formed on the second surface finishing layer 224.

圖8A到圖8I為根據另一實施例的依序說明具有表面修整層311的半導體裝置300或經封裝半導體裝置300的製造方法的橫截面圖。如圖8A到圖8I中所說明，半導體裝置300的製造方法可包含以下步驟：提供載體170及形成第一表面修整層311；形成導通孔113；提供第一樹脂層114；首先移除(例如，研磨)；形成第二傳導圖案121；形成凸塊墊122；提供第二樹脂層123；移除載體170；連接半導體晶粒130；形成囊封物150；以及形成傳導凸塊160。 8A to FIG. 8I are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device 300 having a surface modification layer 311 or a packaged semiconductor device 300 according to another embodiment. As illustrated in FIGS. 8A to 8I, the manufacturing method of the semiconductor device 300 may include the following steps: providing a carrier 170 and forming a first surface finishing layer 311; forming a via hole 113; providing a first resin layer 114; first removing (eg , Grinding); forming a second conductive pattern 121; forming a bump pad 122; providing a second resin layer 123; removing the carrier 170; connecting the semiconductor die 130; forming an encapsulant 150; and forming a conductive bump 160.

如圖8A中所說明，在提供載體170及形成第一表面修整層111的步驟中，製備如先前所描述的載體170，且第一表面修整層311形成於載體170上。在一個實施例中，第一表面修整層311可基本上充當第一傳導圖案。根據本實施例，第一表面修整層311包括較容易地接合到傳導連 接結構(例如，連接線或凸塊)或與所述傳導連接結構形成接合的材料。在一些實施例中，第一表面修整層311可由銀(Ag)製成。另外，第一表面修整層311可通過PVD、CVD、金屬濺鍍、金屬蒸鍍、電解或無電電鍍或所屬技術領域中具有通常知識者已知的其它形成技術形成。在一個實施例中，第一表面修整層311具有在從大約3微米到15000微米的範圍內的厚度。 As illustrated in FIG. 8A, in the steps of providing the carrier 170 and forming the first surface finishing layer 111, the carrier 170 as previously described is prepared, and the first surface finishing layer 311 is formed on the carrier 170. In one embodiment, the first surface finishing layer 311 may substantially serve as the first conductive pattern. According to this embodiment, the first surface finishing layer 311 includes the The connection structure (for example, a connection wire or bump) or a material that forms a bond with the conductive connection structure. In some embodiments, the first surface finishing layer 311 may be made of silver (Ag). In addition, the first surface finishing layer 311 can be formed by PVD, CVD, metal sputtering, metal evaporation, electrolysis or electroless plating, or other formation techniques known to those with ordinary knowledge in the art. In one embodiment, the first surface finishing layer 311 has a thickness in a range from about 3 microns to 15000 microns.

如圖8B中所說明，在形成導通孔113的步驟中，形狀為相對厚的導柱的導通孔113形成於第一表面修整層311上，連接到所述第一表面修整層311，或毗鄰所述第一表面修整層311。導通孔113可由銅(Cu)製成且如先前所描述而形成。 As illustrated in FIG. 8B, in the step of forming the via hole 113, the via hole 113 in the shape of a relatively thick guide post is formed on the first surface finishing layer 311, connected to the first surface finishing layer 311, or adjacent to The first surface finishing layer 311. The via 113 may be made of copper (Cu) and formed as previously described.

如圖8C中所說明，在提供第一樹脂層114的步驟中，第一樹脂層114形成或被塗布到如先前所描述的載體170上，進而允許第一樹脂層114覆蓋載體170、第一表面修整層311及導通孔113。 As illustrated in FIG. 8C, in the step of providing the first resin layer 114, the first resin layer 114 is formed or coated on the carrier 170 as previously described, thereby allowing the first resin layer 114 to cover the carrier 170, Surface finishing layer 311 and via 113.

如圖8D中所說明，在第一次移除的步驟中，使用(例如)研磨及/或蝕刻製程部分地移除第一樹脂層114直到導通孔113暴露於第一樹脂層114外部為止。根據本實施例，第一表面修整層311、導通孔113及第一樹脂層114可集體地界定為第一層壓層110。 As illustrated in FIG. 8D, in the first removal step, the first resin layer 114 is partially removed using, for example, a grinding and/or etching process until the via 113 is exposed to the outside of the first resin layer 114. According to the present embodiment, the first surface finishing layer 311, the via 113, and the first resin layer 114 may be collectively defined as the first laminate layer 110.

如圖8E中所說明，在形成第二傳導圖案121的步驟中，第二傳導圖案121形成於通過第一樹脂層114暴露於外部的導通孔113上，連接到所述導通孔113，或毗鄰所述導通孔113。根據本實施例，第二傳導圖案121於第二樹脂層123上路由同時電連接到導通孔113。第二傳導圖案121可如先前所描述而形成且可由銅(Cu)或所屬技術領域中具有通常知識者 已知的其它材料製成。 As illustrated in FIG. 8E, in the step of forming the second conductive pattern 121, the second conductive pattern 121 is formed on the via hole 113 exposed to the outside through the first resin layer 114, connected to the via hole 113, or adjacent to The via hole 113. According to this embodiment, the second conductive pattern 121 is routed on the second resin layer 123 and electrically connected to the via hole 113 at the same time. The second conductive pattern 121 can be formed as previously described and can be made of copper (Cu) or a person with general knowledge in the art Made of other known materials.

如圖8F中所說明，在形成凸塊墊122的步驟中，凸塊墊122形成於第二傳導圖案121上或連接到所述第二傳導圖案121。凸塊墊122可如先前所描述而形成且可由銅(Cu)或所屬技術領域中具有通常知識者已知的其它材料製成。 As illustrated in FIG. 8F, in the step of forming the bump pad 122, the bump pad 122 is formed on the second conductive pattern 121 or connected to the second conductive pattern 121. The bump pad 122 may be formed as previously described and may be made of copper (Cu) or other materials known to those having ordinary knowledge in the art.

如圖8G中所說明，在提供第二樹脂層123的步驟中，第二樹脂層123形成或被塗布到第一層壓層110上，進而安置第二樹脂層123以覆蓋第一樹脂層114、第二傳導圖案121及凸塊墊122。另外，在塗布以及固化第二樹脂層123之後，可進一步執行第二次移除步驟。在第二次移除步驟中，使用(例如)研磨及/或蝕刻製程部分地移除第二樹脂層123直到凸塊墊122暴露於第二樹脂層123外部為止。在一個實施例中，如果凸塊墊122上無遮罩層形成，那麼凸塊墊122的表面可在蝕刻步驟之後定位在第二樹脂層123的第二開口內部或在所述第二樹脂層123的所述第二開口內凹陷。 As illustrated in FIG. 8G, in the step of providing the second resin layer 123, the second resin layer 123 is formed or coated on the first laminate layer 110, and then the second resin layer 123 is disposed to cover the first resin layer 114 , The second conductive pattern 121 and the bump pad 122. In addition, after coating and curing the second resin layer 123, a second removal step may be further performed. In the second removal step, the second resin layer 123 is partially removed using, for example, a grinding and/or etching process until the bump pad 122 is exposed to the outside of the second resin layer 123. In one embodiment, if no mask layer is formed on the bump pad 122, the surface of the bump pad 122 may be positioned inside the second opening of the second resin layer 123 or in the second resin layer after the etching step. The second opening of 123 is recessed.

根據本實施例，第二傳導圖案121、凸塊墊122及第二樹脂層123可集體地界定為第二層壓層120。 According to the present embodiment, the second conductive pattern 121, the bump pad 122, and the second resin layer 123 may be collectively defined as the second laminate layer 120.

如圖8H中所說明，在移除載體170的步驟中，從第一層壓層110移除載體170。更具體地說，從第一表面修整層311及第一樹脂層114移除載體170，進而允許第一表面修整層311及第一樹脂層114暴露於外部。在一個實施例中，可使用研磨及/或蝕刻製程移除載體170。根據本實施例，包含銀(Ag)的第一表面修整層311充當遮罩，第一表面修整層311的表面變得基本上與第一樹脂層114的表面共面。 As illustrated in FIG. 8H, in the step of removing the carrier 170, the carrier 170 is removed from the first laminate layer 110. More specifically, the carrier 170 is removed from the first surface finishing layer 311 and the first resin layer 114, thereby allowing the first surface finishing layer 311 and the first resin layer 114 to be exposed to the outside. In one embodiment, the carrier 170 may be removed using a grinding and/or etching process. According to the present embodiment, the first surface finishing layer 311 containing silver (Ag) serves as a mask, and the surface of the first surface finishing layer 311 becomes substantially coplanar with the surface of the first resin layer 114.

如圖8I中所說明，在連接半導體晶粒130、形成囊封物150及形成傳導凸塊160的步驟中，半導體晶粒130可使用(例如)黏著劑135附接到第一層壓層110。並且，半導體晶粒130使用傳導連接結構(例如，導線140)電連接到第一表面修整層311。接下來，半導體晶粒130及導線140使用如先前所描述的囊封物150加以囊封。在一個實施例中，傳導凸塊160形成於通過第二層壓層120暴露於外部的凸塊墊122上或連接到所述凸塊墊122。 As illustrated in FIG. 8I, in the steps of connecting the semiconductor die 130, forming the encapsulant 150, and forming the conductive bump 160, the semiconductor die 130 may be attached to the first laminate layer 110 using, for example, an adhesive 135 . Also, the semiconductor die 130 is electrically connected to the first surface finishing layer 311 using a conductive connection structure (for example, a wire 140). Next, the semiconductor die 130 and the wires 140 are encapsulated using the encapsulant 150 as previously described. In one embodiment, the conductive bump 160 is formed on or connected to the bump pad 122 exposed to the outside through the second laminate layer 120.

如上文所描述，本實施例提供半導體裝置300的製造方法，其中可包括銀(Ag)的第一表面修整層311首先形成且結構及元件的其餘部分可隨後形成。另外，本實施例提供經線接合的可路由的模制引線框架球柵陣列封裝。 As described above, the present embodiment provides a method for manufacturing the semiconductor device 300, in which the first surface finishing layer 311, which may include silver (Ag), is formed first and the rest of the structure and components may be formed later. In addition, this embodiment provides a routable molded lead frame ball grid array package via wire bonding.

圖9A到圖9C為根據又一實施例的依序說明具有表面修整層的半導體裝置400或經封裝半導體裝置400的製造方法的橫截面圖。在本實施例中，可使用結合圖8A到圖8G說明的製造步驟，且將不在此處再次重複其細節。然而，半導體裝置400的製造方法不同於半導體裝置300的製造方法。確切地說，第一表面修整層411由不同材料製成。在一個實施例中，第一表面修整層411由銅(Cu)而不是銀(Ag)製成。 9A to 9C are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device 400 having a surface modification layer or a packaged semiconductor device 400 according to another embodiment. In this embodiment, the manufacturing steps described in conjunction with FIGS. 8A to 8G can be used, and the details will not be repeated here again. However, the manufacturing method of the semiconductor device 400 is different from the manufacturing method of the semiconductor device 300. Specifically, the first surface finishing layer 411 is made of different materials. In one embodiment, the first surface finishing layer 411 is made of copper (Cu) instead of silver (Ag).

如圖9A中所說明，在形成及固化第二樹脂層123以及研磨及/或蝕刻第二樹脂層123的步驟之後，第二表面修整層224可進一步形成於暴露於第二樹脂層123外部的凸塊墊122上或連接到所述凸塊墊122。在一個實施例中，第二表面修整層224可如先前所描述而製成且可包括鎳/金(Ni/Au)、銀(Ag)、錫(Sn)及其等效物中的一或多者，但本實施例的方 面不限於此。 As illustrated in FIG. 9A, after the steps of forming and curing the second resin layer 123 and grinding and/or etching the second resin layer 123, the second surface finishing layer 224 may be further formed on the surface exposed to the outside of the second resin layer 123 The bump pad 122 is on or connected to the bump pad 122. In one embodiment, the second surface finishing layer 224 may be made as described previously and may include one or one of nickel/gold (Ni/Au), silver (Ag), tin (Sn), and equivalents thereof. More, but the method of this embodiment The noodles are not limited to this.

如圖9B中所說明，在移除載體170之後，提供可路由的模制引線框架101，其包含具有以下各者的引線框架101：通過第一層壓層110暴露於外部的第一表面修整層411(如上文所描述，其還充當傳導圖案)；以及通過第二層壓層120暴露於外部的第二表面修整層224。根據本實施例，第一表面修整層411在可路由的模制引線框架101的製造過程的初始階段形成，且第二表面修整層224在可路由的模制引線框架101的製造過程的最後階段形成。 As illustrated in FIG. 9B, after the carrier 170 is removed, a routable molded lead frame 101 is provided, which includes a lead frame 101 having: a first surface that is exposed to the outside through a first laminate layer 110 The layer 411 (which also serves as a conductive pattern as described above); and the second surface finishing layer 224 exposed to the outside through the second laminate layer 120. According to this embodiment, the first surface finishing layer 411 is formed in the initial stage of the manufacturing process of the routable molded lead frame 101, and the second surface finishing layer 224 is formed in the final stage of the manufacturing process of the routable molded lead frame 101 form.

如圖9C中所說明，半導體晶粒130定位於可路由的模制引線框架101上且由傳導凸塊結構(例如，微凸塊435)電連接到由銅(Cu)製成的第一表面修整層411。更具體地說，在可路由的模制引線框架101中，半導體晶粒130以倒裝晶片型配置連接到第一層壓層110的第一表面修整層411。在一些實施例中，半導體晶粒130及微凸塊435使用如先前所描述的囊封物150加以囊封。 As illustrated in FIG. 9C, the semiconductor die 130 is positioned on the routable molded lead frame 101 and is electrically connected to the first surface made of copper (Cu) by conductive bump structures (eg, micro bumps 435) Finishing layer 411. More specifically, in the routable molded lead frame 101, the semiconductor die 130 is connected to the first surface finishing layer 411 of the first laminate layer 110 in a flip-chip configuration. In some embodiments, the semiconductor die 130 and the micro bumps 435 are encapsulated using the encapsulant 150 as previously described.

在一些實施例中，傳導凸塊並不分離地形成於凸塊墊122上，且先前形成的第二表面修整層224暴露於外部。因此，本實施例提供倒裝晶片可路由的模制引線框架柵格陣列封裝。在一替代性實施例中，傳導凸塊還可形成於第二表面修整層224上。 In some embodiments, the conductive bumps are not separately formed on the bump pad 122, and the previously formed second surface finishing layer 224 is exposed to the outside. Therefore, this embodiment provides a flip chip routable molded lead frame grid array package. In an alternative embodiment, the conductive bumps may also be formed on the second surface finishing layer 224.

根據所有上述內容，所屬技術領域中具有通常知識者可確定，根據一個實施例，半導體裝置包含：第一層壓層，其包含第一表面修整層、連接到第一表面修整層或與第一表面修整層隔開的第一傳導圖案、形成於第一傳導圖案上的導通孔，及覆蓋第一表面修整層、第一傳導圖案 及導通孔的第一樹脂層；第二層壓層，其包含形成於導通孔中的第二傳導圖案、形成於第二傳導圖案上的凸塊墊，及覆蓋第一樹脂層、第二傳導圖案及凸塊墊的第二樹脂層；半導體晶粒，其連接到第一層壓層的第一表面修整層；及囊封物，其覆蓋第一層壓層及半導體晶粒。 Based on all the foregoing, those with ordinary knowledge in the technical field can ascertain that, according to one embodiment, the semiconductor device includes: a first laminate layer, which includes a first surface conditioning layer, is connected to the first surface conditioning layer, or is connected to the first The first conductive pattern separated by the surface finishing layer, the via hole formed on the first conductive pattern, and covering the first surface finishing layer and the first conductive pattern And the first resin layer of the via hole; the second laminate layer, which includes a second conductive pattern formed in the via hole, a bump pad formed on the second conductive pattern, and covering the first resin layer and the second conductive pattern The second resin layer of the pattern and bump pad; the semiconductor die, which is connected to the first surface finishing layer of the first laminate layer; and the encapsulant, which covers the first laminate layer and the semiconductor die.

根據所有上述內容，所屬技術領域中具有通常知識者可確定，根據另一實施例，半導體裝置的製造方法包含：在載體上形成第一表面修整層；在載體及第一表面修整層中的每一者上形成第一傳導圖案；在第一傳導圖案上形成導通孔且在載體、第一表面修整層、第一傳導圖案及導通孔上塗布第一樹脂層；在導通孔上形成第二傳導圖案及凸塊墊且在第一樹脂層、第二傳導圖案及凸塊墊上塗布第二樹脂層；從第一表面修整層、第一傳導圖案及第一樹脂層移除載體；以及將半導體晶粒連接到第一表面修整層且使用囊封物囊封半導體晶粒。 Based on all the foregoing, those with ordinary knowledge in the technical field can determine that, according to another embodiment, a method for manufacturing a semiconductor device includes: forming a first surface modification layer on a carrier; and each of the carrier and the first surface modification layer A first conductive pattern is formed on one; a via hole is formed on the first conductive pattern and a first resin layer is coated on the carrier, the first surface finishing layer, the first conductive pattern and the via hole; the second conductive pattern is formed on the via hole Pattern and bump pads, and coat the second resin layer on the first resin layer, the second conductive pattern, and the bump pads; remove the carrier from the first surface finishing layer, the first conductive pattern, and the first resin layer; and remove the semiconductor crystal The die is connected to the first surface finishing layer and the semiconductor die is encapsulated using an encapsulant.

根據所有上述內容，所屬技術領域中具有通常知識者可確定，根據另一實施例，經封裝半導體裝置可進一步包括連接到第二傳導結構且暴露於第二樹脂層外部的第二表面修整層，其中第一表面修整層包括鎳/金(Ni/Au)、銀(Ag)或銅(Cu)中的一或多者；且第二表面修整層包括鎳/金(Ni/Au)、銀(Ag)或錫(Sn)中的一或多者。在經封裝半導體裝置的另一實施例中，半導體晶粒可通過傳導凸塊以倒裝晶片配置電耦合到第一表面修整層。在經封裝半導體裝置的又一實施例中，半導體晶粒附接到可路由囊封的傳導基板且通過連接線電耦合到第一表面修整層。 Based on all the foregoing, those with ordinary knowledge in the art can determine that according to another embodiment, the packaged semiconductor device may further include a second surface finishing layer connected to the second conductive structure and exposed to the outside of the second resin layer, Wherein the first surface finishing layer includes one or more of nickel/gold (Ni/Au), silver (Ag) or copper (Cu); and the second surface finishing layer includes nickel/gold (Ni/Au), silver ( One or more of Ag) or tin (Sn). In another embodiment of the packaged semiconductor device, the semiconductor die may be electrically coupled to the first surface finishing layer in a flip chip configuration through conductive bumps. In yet another embodiment of the packaged semiconductor device, the semiconductor die is attached to a routable encapsulated conductive substrate and is electrically coupled to the first surface finishing layer through a connecting wire.

根據所有上述內容，所屬技術領域中具有通常知識者可確定，根據另一實施例，在製造具有可路由囊封的傳導基板的半導體裝置的 方法中，提供可路由囊封的傳導基板可包括提供包括銅的第一表面修整層；且電耦合半導體晶粒可包括以倒裝晶片配置與傳導凸塊耦合。在另一實施例中，電耦合半導體晶粒可包括以倒裝晶片配置與傳導凸塊耦合。 Based on all the above contents, a person with ordinary knowledge in the technical field can determine that according to another embodiment, when manufacturing a semiconductor device with a routable encapsulated conductive substrate In the method, providing a routable encapsulated conductive substrate may include providing a first surface trim layer including copper; and electrically coupling the semiconductor die may include coupling with the conductive bump in a flip chip configuration. In another embodiment, electrically coupling the semiconductor die may include coupling with conductive bumps in a flip chip configuration.

鑒於所有上述內容，顯而易見，已揭示製造使用可路由囊封的傳導基板以及結構的半導體封裝的新穎方法。包含可路由囊封的傳導基板以及其它特徵包含囊封在第一樹脂層內的第一傳導結構、囊封在第二樹脂層內的第二傳導結構，及安置在第一傳導結構的至少部分上的表面修整層。表面修整層暴露在第一樹脂層中，第一傳導結構電連接到第二傳導結構，且第二傳導結構的至少部分暴露於第二樹脂層外部。半導體晶粒電耦合到表面修整層，且囊封物覆蓋半導體晶粒及第一表面修整層。可路由囊封的傳導基板促進封裝級嵌入式傳導圖案的有效路由，且表面修整層在可路由囊封的傳導基板與半導體晶粒之間提供增強的連接可靠性。另外，可路由囊封的傳導基板支援對小型化及較高性能的電子裝置的需求，針對組裝的下一級支持各種互連方案，可在進一步組裝步驟之前製造以縮短製造週期時間，可容易地併入到製造流程中，且具成本效益。 In view of all the foregoing, it is obvious that a novel method of manufacturing a semiconductor package using a routable encapsulated conductive substrate and structure has been disclosed. The conductive substrate including routable encapsulation and other features include a first conductive structure encapsulated in a first resin layer, a second conductive structure encapsulated in a second resin layer, and at least part of the first conductive structure Surface finishing layer on top. The surface finishing layer is exposed in the first resin layer, the first conductive structure is electrically connected to the second conductive structure, and at least part of the second conductive structure is exposed outside the second resin layer. The semiconductor die is electrically coupled to the surface finishing layer, and the encapsulant covers the semiconductor die and the first surface finishing layer. The routable encapsulated conductive substrate promotes effective routing of package-level embedded conductive patterns, and the surface finishing layer provides enhanced connection reliability between the routable encapsulated conductive substrate and the semiconductor die. In addition, the routable encapsulated conductive substrate supports the demand for miniaturization and higher performance electronic devices, and supports various interconnection solutions for the next level of assembly. It can be manufactured before further assembly steps to shorten the manufacturing cycle time. Incorporated into the manufacturing process and cost-effective.

雖然已特定地參考本發明的示例性實施例展示且描述了本發明，但所屬技術領域中具有通常知識者將理解，可進行形式及細節上的多種改變，而不脫離所附申請專利範圍第書所界定的本發明的精神及範圍。 Although the present invention has been specifically shown and described with reference to the exemplary embodiments of the present invention, those skilled in the art will understand that various changes in form and details can be made without departing from the scope of the appended application. The spirit and scope of the present invention defined by the book.

如所附申請專利範圍第書所反映，本發明的方面可在於單個前述揭示的實施例的不到全部的特徵。因此，所附申請專利範圍在此明確地併入到此具體實施方式中，其中每一申請專利範圍本身獨立地作為本發明的單獨實施例。此外，雖然本文中所描述的一些實施例包含其它實施例 中所包含的一些但非全部其它特徵，但如所屬技術領域中具有通常知識者將理解，不同實施例的特徵的組合意圖在本發明的範圍內且意圖形成不同的實施例。 As reflected in the appended claims, aspects of the present invention may lie in less than all the features of a single previously disclosed embodiment. Therefore, the scope of the attached patent application is hereby expressly incorporated into this specific embodiment, wherein each scope of the patent application independently serves as a separate embodiment of the present invention. In addition, although some embodiments described herein include other embodiments Some but not all of the other features included in, but as those skilled in the art will understand, the combination of features of different embodiments is intended to be within the scope of the present invention and is intended to form different embodiments.

100:半導體裝置 100: Semiconductor device

101:可路由囊封的傳導基板/可路由的模制引線框架 101: routable encapsulated conductive substrate / routable molded lead frame

110:第一層壓層/第一囊封層 110: The first laminate layer / the first encapsulation layer

111:第一表面修整層/第一接合層/第一可線接合修整層 111: first surface finishing layer/first bonding layer/first wire bonding finishing layer

112:第一傳導圖案 112: The first conductive pattern

113:導通孔/傳導導通孔/傳導柱 113: Via/Conducting Via/Conducting Post

114:第一樹脂層 114: The first resin layer

120:第二層壓層/第二囊封層 120: second laminate layer/second encapsulation layer

121:第二傳導圖案 121: second conductive pattern

122:凸塊墊 122: bump pad

123:第二樹脂層 123: second resin layer

130:半導體晶粒 130: semiconductor die

135:黏著劑 135: Adhesive

140:傳導連接結構/導線 140: Conductive connection structure/wire

150:囊封物 150: Encapsulation

160:傳導凸塊 160: Conductive bump

Claims (12)

一種半導體裝置，其包括：第一層壓層，其包括：第一表面修整層；多個第一傳導圖案，其包括連接到所述第一表面修整層的多個第一部分及與所述多個第一部分側向地隔開的多個第二部分，其中所述多個第二部分沒有所述第一表面修整層；多個傳導導通孔，其連接到所述多個第一傳導圖案的所述多個第一部分；及第一樹脂層，其覆蓋所述多個第一傳導圖案、所述多個傳導導通孔及所述第一表面修整層的一部分，其中所述第一表面修整層暴露在所述第一樹脂層的第一表面中且所述多個傳導導通孔暴露在所述第一樹脂層的第二表面中；第二層壓層，其鄰近於所述第一層壓層且包括：多個第二傳導圖案，其連接到所述多個傳導導通孔；多個傳導墊，其連接到所述多個第二傳導圖案；及第二樹脂層，其覆蓋所述第一樹脂層、所述多個第二傳導圖案及所述多個傳導墊的至少一部分，其中所述多個傳導墊暴露在所述第二樹脂層的第一表面中；半導體晶粒，其電耦合到所述第一表面修整層；及囊封物，其覆蓋所述第一層壓層及所述半導體晶粒的至少一部分。 A semiconductor device includes: a first laminate layer, including: a first surface trimming layer; a plurality of first conductive patterns, including a plurality of first portions connected to the first surface trimming layer and the plurality of A plurality of second portions laterally separated by a first portion, wherein the plurality of second portions do not have the first surface finishing layer; a plurality of conductive vias, which are connected to the plurality of first conductive patterns The plurality of first portions; and a first resin layer covering the plurality of first conductive patterns, the plurality of conductive vias, and a part of the first surface finishing layer, wherein the first surface finishing layer Exposed in the first surface of the first resin layer and the plurality of conductive vias are exposed in the second surface of the first resin layer; a second laminate layer, which is adjacent to the first laminate Layer and includes: a plurality of second conductive patterns connected to the plurality of conductive vias; a plurality of conductive pads connected to the plurality of second conductive patterns; and a second resin layer covering the first A resin layer, the plurality of second conductive patterns, and at least a part of the plurality of conductive pads, wherein the plurality of conductive pads are exposed in the first surface of the second resin layer; semiconductor die, electrical Coupled to the first surface finishing layer; and an encapsulant covering at least a part of the first laminate layer and the semiconductor die. 根據申請專利範圍第1項所述的半導體裝置，其中： 所述多個傳導墊的多個表面在所述第二樹脂層中的多個開口內凹陷；且所述半導體裝置進一步包括連接到所述多個傳導墊的多個傳導凸塊。 The semiconductor device according to item 1 of the scope of patent application, wherein: A plurality of surfaces of the plurality of conductive pads are recessed in a plurality of openings in the second resin layer; and the semiconductor device further includes a plurality of conductive bumps connected to the plurality of conductive pads. 根據申請專利範圍第1項所述的半導體裝置，其中：所述第一表面修整層包括鎳/金(Ni/Au)、銀(Ag)或銅(Cu)中的一或多者；所述第一表面修整層及所述半導體晶粒由導線電耦合；所述半導體裝置進一步包括連接到所述多個傳導墊的第二表面修整層；且所述第二表面修整層包括鎳/金(Ni/Au)、銀(Ag)或錫(Sn)中的一或多者。 The semiconductor device according to claim 1, wherein: the first surface modification layer includes one or more of nickel/gold (Ni/Au), silver (Ag), or copper (Cu); the The first surface modification layer and the semiconductor die are electrically coupled by wires; the semiconductor device further includes a second surface modification layer connected to the plurality of conductive pads; and the second surface modification layer includes nickel/gold ( One or more of Ni/Au), silver (Ag), or tin (Sn). 根據申請專利範圍第1項所述的半導體裝置，其中：所述第一表面修整層包括銅(Cu)；且所述第一表面修整層及所述半導體晶粒由多個傳導凸塊電耦合；且所述第一樹脂層、所述第二樹脂層及所述囊封物包括模制化合物材料。 The semiconductor device according to claim 1, wherein: the first surface modification layer includes copper (Cu); and the first surface modification layer and the semiconductor die are electrically coupled by a plurality of conductive bumps And the first resin layer, the second resin layer and the encapsulant include molding compound materials. 根據申請專利範圍第1項所述的半導體裝置，其中：所述第一樹脂層、所述第二樹脂層及所述囊封物包括具有相似熱膨脹係數的多個模制化合物材料；所述第一表面修整層基本上與所述第一樹脂層共面；且所述第一傳導圖案的所述第二部分的表面在所述第一樹脂層的所述第一表面下方凹陷。 The semiconductor device according to claim 1, wherein: the first resin layer, the second resin layer, and the encapsulant include a plurality of molding compound materials having similar thermal expansion coefficients; A surface finishing layer is substantially coplanar with the first resin layer; and the surface of the second portion of the first conductive pattern is recessed below the first surface of the first resin layer. 一種經封裝半導體裝置，其包括： 可路由囊封的傳導基板，其包括：第一傳導結構，其囊封在第一樹脂層內；第二傳導結構，其電耦合到所述第一傳導結構且囊封在第二樹脂層內；及第一表面修整層，其安置在所述第一傳導結構的至少部分上，其中：所述第一表面修整層暴露在所述第一樹脂層中；且所述第二傳導結構的至少部分暴露在所述第二樹脂層中；半導體晶粒，其電耦合到所述第一表面修整層；及囊封物，其囊封所述半導體晶粒及所述第一表面修整層。 A packaged semiconductor device, which includes: A routable encapsulated conductive substrate includes: a first conductive structure encapsulated in a first resin layer; a second conductive structure electrically coupled to the first conductive structure and encapsulated in a second resin layer And a first surface finishing layer disposed on at least part of the first conductive structure, wherein: the first surface finishing layer is exposed in the first resin layer; and at least the second conductive structure Partially exposed in the second resin layer; a semiconductor die, which is electrically coupled to the first surface modification layer; and an encapsulant, which encapsulates the semiconductor die and the first surface modification layer. 根據申請專利範圍第6項所述的經封裝半導體裝置，其中：所述第一傳導結構包括連接到第一傳導圖案的多個傳導導通孔；所述第二傳導結構包括連接到傳導凸塊的第二傳導圖案；且所述第一表面修整層連接到所述第一傳導圖案的至少部分。 The packaged semiconductor device according to claim 6, wherein: the first conductive structure includes a plurality of conductive vias connected to a first conductive pattern; the second conductive structure includes a conductive bump connected to A second conductive pattern; and the first surface finishing layer is connected to at least part of the first conductive pattern. 根據申請專利範圍第6項所述的經封裝半導體裝置，其中：所述第一傳導結構包括多個傳導導通孔；所述第一表面修整層經配置為第一傳導圖案；所述第一傳導圖案的至少一部分連接到所述多個傳導導通孔；所述第一表面修整層包括銀(Ag)或銅(Cu)中的一或多者；且所述經封裝半導體裝置進一步包括連接到所述第二傳導結構的多個傳導凸塊。 The packaged semiconductor device according to claim 6, wherein: the first conductive structure includes a plurality of conductive vias; the first surface finishing layer is configured as a first conductive pattern; the first conductive At least a part of the pattern is connected to the plurality of conductive vias; the first surface finishing layer includes one or more of silver (Ag) or copper (Cu); and the packaged semiconductor device further includes a connection to the The plurality of conductive bumps of the second conductive structure. 一種製造具有可路由囊封的傳導基板的半導體裝置的方法，其包括： 提供包括以下各者的所述可路由囊封的傳導基板：第一傳導結構，其囊封在第一樹脂層內；第二傳導結構，其電耦合到所述第一傳導結構且囊封在第二樹脂層內；及第一表面修整層，其安置在所述第一傳導結構的至少部分上，其中：所述第一表面修整層暴露在所述第一樹脂層中；且所述第二傳導結構的至少部分暴露在所述第二樹脂層中；將半導體晶粒電耦合到所述第一表面修整層；及形成覆蓋所述半導體晶粒及所述第一表面修整層的囊封物。 A method of manufacturing a semiconductor device with a routable encapsulated conductive substrate, which includes: Provide the routable encapsulated conductive substrate including: a first conductive structure encapsulated in a first resin layer; a second conductive structure electrically coupled to the first conductive structure and encapsulated in And a first surface finishing layer disposed on at least part of the first conductive structure, wherein: the first surface finishing layer is exposed in the first resin layer; and the first surface finishing layer At least part of the two conductive structures are exposed in the second resin layer; electrically coupling the semiconductor die to the first surface trimming layer; and forming an encapsulation covering the semiconductor die and the first surface trimming layer Things. 根據申請專利範圍第9項所述的方法，其中提供所述可路由囊封的傳導基板包括：在載體上提供所述第一表面修整層；提供在所述載體及所述第一表面修整層中的每一者上包括多個第一傳導圖案且在所述多個第一傳導圖案的至少部分上包括多個傳導導通孔的所述第一傳導結構；提供覆蓋所述載體、所述第一表面修整層、所述多個第一傳導圖案及所述多個傳導導通孔的所述第一樹脂層；提供包括連接到所述多個傳導導通孔的多個第二傳導圖案及多個傳導墊的所述第二傳導結構；提供覆蓋所述第一樹脂層、所述多個第二傳導圖案及所述多個傳導墊的所述第二樹脂層；及移除所述載體。 The method according to item 9 of the scope of patent application, wherein providing the routable encapsulated conductive substrate includes: providing the first surface finishing layer on a carrier; providing the carrier and the first surface finishing layer Each of the first conductive structure includes a plurality of first conductive patterns and includes a plurality of conductive vias on at least a part of the plurality of first conductive patterns; providing covering the carrier, the first conductive structure A surface finishing layer, the first resin layer of the plurality of first conductive patterns and the plurality of conductive vias; providing a plurality of second conductive patterns connected to the plurality of conductive vias and a plurality of The second conductive structure of the conductive pad; providing the second resin layer covering the first resin layer, the plurality of second conductive patterns, and the plurality of conductive pads; and removing the carrier. 根據申請專利範圍第10項所述的方法，其進一步包括：在提供所述第二傳導結構之前移除所述第一樹脂層的一部分以將所述多個傳導導通孔暴露於外部；及將多個傳導凸塊連接到所述多個傳導墊，其中：所述第一表面修整層包括鎳/金(Ni/Au)、銀(Ag)或銅(Cu)中的一或多者；在橫截面圖中所述多個第一傳導圖案的至少部分的多個表面在所述第一樹脂層的主表面下方凹陷；且所述第一表面修整層基本上與所述第一樹脂層的所述主表面共面。 The method according to claim 10, further comprising: removing a part of the first resin layer to expose the plurality of conductive vias to the outside before providing the second conductive structure; and A plurality of conductive bumps are connected to the plurality of conductive pads, wherein: the first surface finishing layer includes one or more of nickel/gold (Ni/Au), silver (Ag), or copper (Cu); In the cross-sectional view, at least part of the plurality of surfaces of the plurality of first conductive patterns are recessed below the main surface of the first resin layer; and the first surface finishing layer is substantially the same as the first resin layer The major surfaces are coplanar. 根據申請專利範圍第10項所述的方法，其進一步包括：移除所述第二樹脂層的一部分以將所述多個傳導墊暴露於外部；及形成連接到所述多個傳導墊的第二表面修整層，其中：所述第二表面修整層包括鎳/金(Ni/Au)、銀(Ag)或錫(Sn)中的一或多者；且所述第二表面修整層基本上與所述第二樹脂層的主表面共面。 The method according to claim 10, further comprising: removing a part of the second resin layer to expose the plurality of conductive pads to the outside; and forming a first portion connected to the plurality of conductive pads Two surface finishing layers, wherein: the second surface finishing layer includes one or more of nickel/gold (Ni/Au), silver (Ag) or tin (Sn); and the second surface finishing layer is basically It is coplanar with the main surface of the second resin layer.
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