201112640 六、發明說明： 【發明所屬之技術領域】 所揭示之實施例係關於鎖相迴路（PLL)，且更特定言 之，係關於可在無線電接收器及傳輸器内之本地振盪器中 使用之PLL。 本申請案係有關2009年6月30日申請之題為「Continuous-Time Oversampled Delta-Sigma ADC And Charge Pump Based Mixed-Mode Digital PLL」的美國臨時專利申請案第 61，222,035號且主張該申請案之優先權。 【先前技術】 鎖相迴路（PLL)用於許多應用中，包括在蜂巢式電話接 收器及傳輸器之本地振盪器中使用。存在可用以實現此種 PLL之不同電路。用於實現本地振盪器之PLL的可能選項 包括類比PLL及所謂的「全數位」PLL(ADPLL)。一種類 型之ADPLL為時間至數位轉換器全數位鎖相迴路（TDC ADPLL)。圖1(先前技術）為TDC ADPLL 1之圖式。TDC ADPLL 1包括一累加器2、一時間至數位轉換器（TDC)3、 一求和器4、一數位迴路濾波器5及一數位控制振盪器 (DCO)6。第二類型之ADPLL為相位至數位轉換器全數位 鎖相迴路（PDC ADPLL)。圖2(先前技術）為相位至數位轉換 器全數位鎖相迴路（PDC ADPLL)7之圖式。PDC ADPLL 7 包括一相位至數位轉換器（PDC)8、一數位迴路濾波器9、 一 DCO 10及一數位迴路除頻器η。在兩個ADPLL架構 中，使用延遲線來量測時域中之時序，且將信號邊緣之間 149467.doc 201112640 的時差轉換成數位值。控制迴路常對參考時脈抖動、對大 量參考時脈之抖動及/或對其他㈣_。^ 擾鑛LL適當操作之機制可能是複雜的。可能難㈣= 線進行適當的控制與校準。時序控制電路之設計亦是複雜 的0 用於實現本地振盪器之PLL的另一可能選項為類比 PLL。圖3(先前技術）為分數_比似12之圓式。類比 PLL 12包括一相位债測器13、—類比電荷泉14、—類比滤 波器15、一壓控振盪器（VCO)16及一除頻器17。在此實例 且包括一三角積分調變器201112640 VI. Description of the Invention: [Technical Field] The disclosed embodiments relate to phase-locked loops (PLLs) and, more particularly, to local oscillators that can be used in radio receivers and transmitters. PLL. The present application is related to U.S. Provisional Patent Application No. 61,222,035, entitled "Continuous-Time Oversampled Delta-Sigma ADC And Charge Pump Based Mixed-Mode Digital PLL", filed on June 30, 2009, and claims Priority. [Prior Art] Phase-locked loops (PLLs) are used in many applications, including in local oscillators for cellular telephone receivers and transmitters. There are different circuits that can be used to implement such a PLL. Possible options for implementing a local oscillator PLL include an analog PLL and a so-called "full digital" PLL (ADPLL). One type of ADPLL is a time-to-digital converter full digital phase-locked loop (TDC ADPLL). Figure 1 (previous technique) is a diagram of TDC ADPLL 1. The TDC ADPLL 1 includes an accumulator 2, a time to digital converter (TDC) 3, a summer 4, a digital loop filter 5, and a digitally controlled oscillator (DCO) 6. The second type of ADPLL is a phase-to-digital converter full digital phase-locked loop (PDC ADPLL). Figure 2 (previous technique) is a diagram of a phase-to-digital converter full digital phase-locked loop (PDC ADPLL) 7. The PDC ADPLL 7 includes a phase to digital converter (PDC) 8, a digital loop filter 9, a DCO 10, and a digital loop divider η. In both ADPLL architectures, a delay line is used to measure the timing in the time domain and the time difference between the edges of the signal is converted to a digital value of 149467.doc 201112640. Control loops often have jitter on the reference clock, jitter on a large number of reference clocks, and/or on other (4) _. ^ The mechanism by which the disturbance LL is properly operated may be complicated. It may be difficult (4) = line to perform proper control and calibration. The timing control circuit is also designed to be complex. Another possible option for implementing a PLL for the local oscillator is the analog PLL. Figure 3 (previous technique) is a round-point with a score of -12. The analog PLL 12 includes a phase debt detector 13, an analog charge spring 14, an analog filter 15, a voltage controlled oscillator (VCO) 16, and a frequency divider 17. In this example and including a triangular integral modulator
中，類比PLL 12為分數N PLL 18。在蜂巢式電話應用中，此種類比pLL電路拓撲之設 計 '建置及除錯通常比ADPLL的簡單，但此種類比pLL電 路拓撲包含一類比電荷泵及一類比迴路濾波器。歸因於類 比電荷泵之上動態餘量及下動態餘量的限制性要求， ADPLL通常不能在低供電電壓下操作。此外，在蜂巢式電 話應用中，單一積體PLL電路將能夠在多個不同頻帶中操 作。與係數可改變的數位迴路濾波器不同，類比迴路渡波 器通常不很靈活。有時難以使或不可能使單一 ADPLL電路 在所述多個不同頻帶（如蜂巢式電話應用中所需要的）中進 行的操作達成令人滿意的效果。此外，實施類比迴路濾波 器可能需要大量的晶粒空間，因此花費很大且可能需要使 用晶片外組件。 【發明内容】 本文中被稱作「以ADC為基礎的混合模式數位鎖相迴 149467.doc 201112640 路」之PLL包括一相位至數位轉換器（Pr)C)、一數位迴路 濾波器、一數位控制振盪器（DC0)及一迴路除頻器。在 PDC内，相位/時序資訊由電荷泵及類比至數位轉換器 (ADC)轉換成數位值流。如由ADC輸出之數位值流供應至 該數位迴路濾波器，且該數位迴路濾波器又將一數位調諧 字流供應至該DCO。自該DC0輸出之一振盪信號由該迴路 除頻器進行頻率除法運算以產生一供應至該p D c之一第二 輸入端的回饋信號DIV_〇UT。該PDC之一第一輸入端接收 一參考時脈信號XO。 該PDC内之該ADC可為許多不同合適類型的ADC中之一 者，包括（但不限於）連續時間三角積分過取樣數位ADC、 另一類型之連續時間ADC、另一類型之過取樣ADc、連續 漸近ADC(S AR ADC)、另—類型之離散時間ADC、開關電 容器ADC或快閃ADC。 在一第-實施例中，該ADC為—連續時間三角積分過取 樣數位就。電荷泵之輸出節點上的電壓信^小振幅中 段電壓。由於電荷泵輸出信號被供應至主動積分器之虛擬 接地輸：節點上’因此該電屋信號為小振幅中段電壓信 唬。電何泵之輪出端上的小振幅中段電壓產生眾多優勢， 包括電荷栗線性的改良、電荷㈣訊的減少及允許自較低 的供電電壓操作整個PLL。自電絲輸出之信號中的緩慢 變化之相位誤差資訊被過取樣，因為就在較高頻率（例 如，參考輸入時脈信號頻率)下取樣。與此取樣相關聯之 量化雜訊移動至較高頻率且被據出。獄之連續時間操作 149467.doc 201112640 放鬆對ADC内之運算放大器的回轉率及頻寬的要求，藉此 與包含習知離散時間ADC之實施例相比，電力消耗減少。 在習知TDC ADPLL中，在時域中處理相位/時序資訊以使 得時序控制可為困難@，而在以ADC為基礎的混合模式數 位^中，相位/時序資訊轉換成電荷資訊。接著便處理此 電荷資訊。此使時序控制電路相對簡單。在一實例中，電 荷泵具有可控制增益。當PLL不處於鎖定狀態時，電荷泵 之增益被設定至較低值，而當PLL處於鎖定狀態時，電荷 泵之增益被設定至較高值。數位迴路濾波器係可程式化 的，且其係數在PLL回饋迴路之操作頻率改變時改變。當 蜂巢式電話正在第一頻帶中進行接收時，則數位迴路濾波 器使用第一組係數，而當蜂巢式電話正在第二頻帶中進行 接收時’則數位迴路濾波器使用第二組係數。 在一第二實施例中’ ADC為一離散時間s AR ADC。在 SAR ADC實施例中，與連續時間三角積分過取樣ADc實施 例相同’來自電荷泵之輸出信號為小振幅且中段電壓信 號。在一貫例中’ S AR ADC之僅有的重要類比組件為比較 器’且與對三角積分過取樣ADC之積分器内的運算放大器 之線性要求相比’對此比較器之線性要求有所放鬆。歸因 於減少之線性要求’與連續時間三角積分過取樣Adc實施 例相比’可使SAR Adc實施例具有較低電力消耗.減少之 線性要求亦允許SAR ADC在較低供電電壓下操作。 前述内容為[發明内容]，且因此必定含有細節之簡化、 概括及省略；因此，熟習此項技術者應瞭解，[發明内容] 149467.doc 201112640 僅為說明性的’且並非旨在以任—方式進行限制。在本文 中所閣明之非限制性[實施方式]中，如僅藉由申請專利範 圍定義的本文中所描述之裝置及/或程序之其他態樣、發 明性特徵及優勢將變得顯而易見。 【實施方式】 圖4為根據一新穎態樣的一特定類型之行動通信裝置ι〇〇 之極簡化之高階方塊圖。在此實例中，行動通信裝置1〇〇 為使用分碼多重存取（CDMA)蜂巢式電話通信協定之蜂巢 式電話。蜂巢式電話包括（除了未說明之若干其他零件外） 一天線102及兩個積體電路1〇3及1〇4。積體電路1〇4被稱為 「數位基頻積體電路」或「基頻處理器積體電路」。積體 電路103為射頻（RF)收發器積體電路。RF收發器積體電路 1〇3被稱為「收發器」，因為其包括一傳輸器以及一接收 器。 圖5為圖4之RF收發器積體電路ι〇3之更詳細的方塊圖。 接收器包括所謂的「接收鏈」1 〇5以及一本地振盡器 (LO)106。當蜂巢式電話正接收時，在天線1〇2上接收到— 高頻RF信號107。來自信號1〇7之資訊穿過雙工器1〇8、匹 配網路109，且穿過接收鏈105。信號1〇7由低雜訊放大器 (LNA)l 10放大，且由混頻器丨丨丨降頻轉換。所得之經降頻 轉換之信號由基頻濾波器112濾波，且傳送至數位基頻積 體電路104。數位基頻積體電路1 〇4中之類比至數位轉換器 113將信號轉換成數位形式，且所得之數位資訊由數位基 頻積體電路104中之數位電路處理。數位基頻積體電路1〇4 149467.doc 201112640 藉由控制在本地振盪讀出端ιΐ4上供應至混頻器⑴的本 地振盡器錢⑽）之頻率來調㈣接收器。 右蜂巢式電話正傳輸’則待傳輸之資訊由數位基頻積體 電路104中之數位至類比轉換器（dac)i η轉換成類比形 式’且供應至「傳輸鍵」116。基頻濾波器ιΐ7渡出由數位 至類比轉換程序產生之雜訊。在本地振廬器119之控制 下混頻器區塊118接著將信號升頻轉換成高頻信號。驅 動器放大器120及外部功率放大器121放大該高頻信號以驅 動天線102，以使得自天線1〇2傳輸高頻尺1?信號122 ^數位 基頻積體電路104藉由控制在本地振盪器輸出端123上供應 至混頻器11 8的本地振盪器信號之頻率來控制該傳輸器。 數位基頻積體電路104藉由跨越數位匯流排124經由匯流排 介面125及控制線126及127發送適當之控制資訊來控制本 地振盪器106及119。 圖6為更詳細地展示圖5之本地振盪器ι〇6之電路圖。本 地振蘯器106包括參考時脈信號χ〇之源128及以ADC為基 礎的混合模式數位PLL 129。源128可為晶體振盪器或一振 蘆器之一部分，或參考時脈信號χ〇之另一源（諸如，傳遞 參考時脈信號XO之導線）。源12 8將參考時脈信號χ〇供應 至相位頻率偵測器（PFD)138之第一輸入引線144上。藉由 設定經由導線132供應至三角積分調變器131之分數F除數 值（N，f)，經由導線126及控制介面電路130所接收之控制資 訊控制以ADC為基礎的混合模式數位PLL 129。 以ADC為基礎的混合模式數位PLL 129包括一相位至數 149467.doc -10- 201112640 位轉換器（PDC)133、一數位迴路濾波器134、一數位控制 振盪器（DCO)135、一迴路除頻器136、三角積分調變器 131、控制介面130及一鎖定偵測器電路137。pDc 133又包 括PFD 138、一差分電荷泵139及一類比至數位轉換器 (ADC)140。DCO 135自數位迴路濾波器134接收十六位元 數位調諧字流。在給定時間，由Dc〇 i35接收之十六位元 數位調諧字判定由DCO 135輸出至導線1上的本地振盪 器輸出信號LO之頻率。本地振盪器輸出信號L〇在此實例 中為4 GHz範圍中之數位信號。輸出信號[〇可為單端或差 分信號。 迴路除頻器136以經由導線141自三角積分調變器131接 收之夕位元數位除數值對單位元本地振盈器輸出信號L〇 進行頻率除法運算，且將所得之經除法運算之單位元回饋 k唬DIV—OUT輸出至導線142上且輸出至PFD 138之第二輸 入引線143。三角積分調變器131隨著時間之流逝將除數值 在整數值N與下一個整數值N+1之間來回改變，以使得隨 著時間之流逝LO之頻率除以分。分數1?值「Nf」 中之「N」表示整數，而分數值「N f」中之「f」表示分 數值。如上所述’迴路除頻器136除法運算中之分數值Nf 在自數位基頻積體電路！ 〇4被接收後被本地振盪器i 〇6獲 知。 PFD 138在其第一輸入端144上接收參考時脈信號χ〇， 且在其第二輸入端143上接收回饋div_〇UT信號。自此等 k號’ PFD 138產生向上電荷泵控制信號（up)及向下電荷 149467.doc 201112640 泵控制信號（DN)。分別經由導線145及146將UP及DN信號 供應至電荷泵139。 圖7為PFD 138之一實施方案之圖式。PFD 138包括一第 一正反器147、一第二正反器148及一 AND閘149。若信號 XO及DIV_OUT兩者最初處於數位邏輯低值，且若正反器 147及148兩者經重設且正輸出數位邏輯低值，則AND閘 149正輸出數位邏輯低值且正反器147及148不處於經重設 之條件下。若信號XO接著轉變至數位邏輯高值，則正反 器147經設定且UP信號確證為數位邏輯高值。此條件持 續，直至信號DIV—OUT轉變至高為止。當信號DIV_OUT 轉變至高時，則正反器148經設定且信號DN確證為高。當 DN轉變至高時，則供應至AND閘149之輸入端上的UP及 DN信號兩者為高。AND閘1 49因此輸出一數位邏輯高值， 其非同步地重設正反器147及148兩者。接著快速撤銷確證 兩個信號UP及DN以使其具有數位邏輯低值。在信號DNS 生低至高轉變後不久的時間點，PFD 138處於重設條件 下，且準備量測另一上升邊緣條件之相位。確證信號DN 之時間量為需要用來經由AND閘149及正反器之非同步重 設輸入端非同步地重設正反器147及148之時間量。然而， 信號UP確證為高之時間量取決於XO之上升邊緣與 DIV_OUT之上升邊緣之間的相位差而變化。相位差愈大， 則信號UP確證為高之時間量愈長。 若信號XO及DIV_OUT兩者最初處於數位邏輯低值，且 若正反器147及148兩者經重設且正輸出數位邏輯低值，且 149467.doc -12- 201112640 若在信號XO前信號DIV—OUT因而轉變至數位邏輯高值， 則正反器148經設定。DN信號確證為高。此條件持續，直 至信號XO轉變至高為止。當信號XO轉變至高時，則正反 器147經設定且信號UP確證為高。在此點，兩個信號UP及 DN為高。AND閘149因此輸出一數位邏輯高值，其非同步 地重設正反器147及148兩者。撤銷確證兩個信號UP及DN 以具有數位邏輯零值。PFD 138接著準備量測另一上升邊 緣條件。確證信號UP之時間量為需要用來經由AND閘149 及正反器之非同步重設輸入端非同步地重設正反器147及 1 48之時間量。然而，信號DN確證為高之時間量取決於 DIV-OUT之上升邊緣與XO之上升邊緣之間的相位差而變 化。相位差愈大，則DN確證為高之時間量愈長。 圖8為差分電荷泵139之更詳細圖式。電荷泵139包括一 供電電壓選擇器150、一第一開關151及P通道UP電流源電 晶體152、一第二開關153及一 N通道DN電流源電晶體 154。供電電壓選擇器150可（例如）為包含傳輸閘極之類比 多工器。P通道UP電流源電晶體152之閘極由閘極偏壓電 壓VBIASP加偏壓。N通道DN電流源電晶體154之閘極由閘 極偏壓電壓VBIASN加偏壓。此等偏壓電壓經設定以使得 UP及DN電流具有所要的量值。當經由導線145接收之控制 信號UP具有數位邏輯高值時，UP電流流動。當經由導線 146接收之控制信號DN具有數位邏輯高值時，DN電流流 動。若在相位量測上升XO/DIV—OUT邊緣條件期間，信號 UP處於高之時間比信號DN處於高之時間長，則有淨值的 149467.doc -13- 201112640 UP電流流動。另一方面，若在相位量測上升X0/DIV_0UT 邊緣條件期間，信號DN處於高之時間比信號UP處於高之 時間長’則有淨值的DN電流流動。 若輸入引線155上之信號IN-LOCK處於數位邏輯高值， 則供電電壓選擇器1 50將供電電壓V2供應至開關1 5 1，而當 輸入端155上之信號IN-LOCK處於數位邏輯低值時，則供 電電壓選擇器150將供電電壓VI供應至開關151。供電電壓 V2為比供電電壓VI大之正電壓。當供電電壓V2供應至開 關1 5 1時，由電荷泵1 39輸出的ICP電流脈衝之振幅量值（例 如，1 0 mA)比當將較小供電電壓V 1供應至開關1 5 1時（例 如，1 mA)大。因此，當確證信號IN-LOCK時電荷泵之增 益比當未確證信號IN-LOCK時電荷泵的增益大。UP電流之 脈衝供應至導線及節點1 56上。自導線及節點1 56汲取DN 電流脈衝。UP與DN電流脈衝一起構成脈衝串ICP。 圖9為圖6之ADC 140之更詳細圖式。ADC 140可實現為 任一類型之合適的ADC，包括（但不限於）連續時間ADC、 離散時間ADC、過取樣ADC、連續時間三角積分過取樣 ADC、離散時間SAR ADC、離散時間開關電容器ADC及快 閃ADC。圖9說明ADC 140為連續時間三角積分過取樣 ADC(CT三角積分過取樣ADC)之一實例。ADC 140包括兩 個級、帶隙基準電壓157及ADC 158。第一級包括一運算 放大器159、一電容器160及一回饋控制電流源161。第二 級包括一電阻器162、一運算放大器163、一電容器164及 一回饋控制電流源165。第一級與第二級構成主動積分器 149467.doc -14- 201112640 一起操作，其中節點156為積分器之輸入信號節點。若第 一級為主要雜訊源，則可藉由將截波器置放於第一級周圍 應用截波器穩定化。 積分器對節點156上之電壓求積分，且將平滑化之結果 供應至ADC 158之輸入端167上。ADC 158將輸入端167上 之電壓與基準電壓VREF比較。為此，ADC 158之輸入端 168接收量值為比較電壓vref之兩倍的基準電麼2vref。 ADC 1S8在參考時脈XO之每一循環將三位元數位值 ADC一OUT[l:3]輸出至輸出導線189上。每一連續數位值 ADC_OUT[l:3]為一數位相位誤差字，其為在輸入端167上 自積分器接收之電壓信號與電壓VREF(在輸入端168上接 收的電壓2VREF之一半）之間的電壓差之數值的量度。此 電壓差愈大，ADC_OUT[l:3]之絕對值愈大。最高有效位 元ADC 一 OUT[3]指示輸入端167上之積分器輸出信號比 VREF高或是比VREF低。所得數位相位誤差字 ADC-0UT[1:3]之流控制回饋控制電流源161及165。若積 分器輸出號與VREF之間的電壓差較大，則回饋控制電 流源161及165經控制以流出或流入較多電流，而若積分器 輸出彳5號與VREF之間的電壓差較小，則回饋控制電流源 161及165經控制以流出或流入較少電流。結果為使積分器 及ADC穩定之負回饋。隨著時間之流逝，由電荷果丨39供 應至節點156上之平均電荷等於由回饋控制電流源161自節 點156移除之平均電荷。運算放大器159並不自節點156汲 取可觀的電流’因為其柄接至節點15 6之非反相輸入端具 149467.doc 15 201112640 有高輸入阻抗。 圖10為圖9之ADC 158之更詳細圖式。有許多方法可實 現ADC 158。圖10僅說明一實例。ADC 158包括一快閃類 比至數位轉換器，其包含電阻器梯169至173及一組對應的 比較器1 74至1 77。比較電壓VREF為大致在沿著該梯之中 途處的梯分接節點上之電壓。此快閃轉換器之多位元輸出 供應至數位邏輯編碼器178。編碼器178將快閃轉換器之多 位元輸出轉換成對應的三位元數位值。如由編碼器178輸 出之三位元數位值在參考時脈信號x〇之上升邊緣上鎖存 至二位元暫存器179至181中。如由三位元暫存器179至181 輸出的三位元值流為信號ADC_OUT[l :3]。 圖11為圖9之一回饋電流源161之更詳細電路圖。p通道 UP開關電晶體SU1 1 82及SU2 183經定大小以使得若最高 有效位元ADC_OUT[ 1 ]為數位邏輯低，則該等電晶體按由 兩位元值ADC一ΟϋΤ[2:3]判定之量使電流流出至節點ι56 上。此流出之電流自供電電壓節點i 84經由並聯連接之電 曰曰體182及183而流動至節點156上。類似地，n通道DOWN 開關電晶體SD1 185及SD2 186經定大小以使得若最高有效 位兀ADC_OUT[l]為數位邏輯高，則該等電晶體按由兩位 兀值ADC_〇UT[2:3]判定之量自節點ι56流入電流。此電流 自節點156經由並聯連接之電晶體185及186而流動至接地 即點187。在圖11之左侧上說明的載運信號adc_〇ut[2:3] 及ADC一OUT[3]之k號導線為延伸至圖9中之ado 158之輸 出端之相同信號導·線。 149467.doc -16 - 201112640 圖12為說明ADC 158及圖11之回饋電流源1 6 1之操作之 表格。如該表格所指示，若VREF(在沿著圖1 0之電阻器梯 之中途處的電壓）與輸入節點167上之電壓VIN(自圖9之兩 級積分器接收之電壓）之間的電壓差處於_〇1伏特與+〇1伏 特之間’則ADC—OUT[l:3]值為「000」。開關電晶體 SD1、SD2、SU1及SU2皆控制為關斷。回饋控制電流源 161既不將電流供應至節點15 6上，亦不自節點15 6汲取電 流。此電流在圖式中表示為IFB。然而，若VREF與VIN之 間的電壓差為正’則電晶體SU1及/或SU2控制為開啟，以 使得電流IFB為正。電流流出至節點1 5 6上。若VREF與VIN 之間的電壓差為負，則電晶體SU1及/或SU2控制為開斷， 以使得電流IFB為負。電流自節點156流入。信號極性經設 定’以使得負回饋使圖9之回饋迴路穩定。 因此’如圖6中所說明，ADC 140將三位元數位值 ADC_OUT[l:3]流供應至數位迴路濾波器134。此三位元值 ADC_OUT[l:3]流之資訊内容的量值指示在PFd 136之第一 輸入引線144上之參考信號χ〇與pFD 136之第二輸入引線 143上之回饋信號DIV—OUT之間的相位誤差量。在一實例 t ’由電荷泵139輸出之信號具有約1 〇〇 kHz之有用頻寬， 但ADC 140在高得多的參考時脈頻率（例如，2〇 mHz)下過 取樣此信號。量化雜訊經成形為具有較高頻率且被濾出。 迴路濾波器134具有1〇 kHz之頻寬。雖然由ADC 140輸出之 ADC_OUT[l:3]值為僅三位元值，但取決於取樣率，歸因 於過取樣及渡波的有效解析度為十至二十位元之解析度。 149467.doc 17 201112640 在一有利態樣中’迴路濾波器丨34為靈活且可程式化之 數位濾波器，其係數可在軟體控制下改變。由數位迴路濾 波器1 34使用之濾波器係數係經由控制介面13〇及導線丨88 並行地供應。若使用以ADC為基礎的混合模式數位pLL 129產生用於在第一射頻通信頻帶中接收蜂巢式通信之^〇 仏號，則使用第一組濾波器係數，而若使用以AD(：為基礎 的混合棋式數位PLL 129產生用於在第二射頻通信頻帶中 接收蜂巢式通信之LO，則使用第二組濾波器係數。 在另一有利態樣中，與PLL常規操作且處於鎖定之情況 相比，在PLL處於獲取狀態且正試圖鎖定之情況下，pLL 電荷泵會獲得較小增益。在獲取期間，將電荷供應至節點 156或供應至節點156以外之速率在電荷泵增益沒有減少的 情況下大到使得ADC 14〇内的積分器之負回饋遭受壓製。 積分器輸出可能飽和。為了防止發生此情況，在獲取期間 電荷泵139之增益經控制在具有較小增益值，而在常規操 作（〃中PLL 129鎖定）中電荷泵139之增益為較大增益值。 藉由適當地設定圖8中之電壓¥1及乂2來設定相對增益值。 PLL是否處於鎖定由圖6之鎖定偵測器電路137判定。 在另一有利態樣中，與習知ADPLL之電荷系相比，pLL 電何系’、有改良之線性。在圖6及圖9之pll中，受pll電 荷栗驅動之積分器輸入節點156為「虛擬接地」節點156。 歸因於圖9之主動兩級積分器，節點159為虛擬接地，且在 常規PLL操作期間節點159上之電壓信號為小振幅中段電壓 信號。輸入ct三角積分過取樣ADC之輸入阻抗大於丨河歐 149467.doc 201112640 姆術s吾厂小振幅」在本文中γ、+. + a 頂本文中&迷有關於在電荷泵139之 頁4處的供電電壓VI及V2盥雷尸石， 位之H“r 心與電何果⑼之底部處的接地電 位之間的電壓差之關係。在一 當V2為1.3伏特時，「 ’ <於鎖定且 田」具有峰至峰的約〇.〇5伏特 °上動態餘量㈣為約〇.4伏特，且下動態餘 壓為約〇_4伏特。術語「中 ‘、、 中奴」係相對於在電荷泵139之頂 錢的供電電W與電荷系m之底部處的接地電位 之間的電壓範圍而言。 隨者時間之流逝，歸因於電流ICP脈衝而供應至節點156 上之電荷與歸因於電流IFB而離開節點156之電荷相同。在 習知類比電荷聚電路中，電荷粟之增益根據電荷泉輸出端 上之電壓而改變。此變化的增益被認為是非線性的。隨著 輸出電壓接近電荷泵之正供電電壓，電荷栗之線性進一步 降,、因為電荷泵之up電流源内的p通道電晶體進入三極 體區域操作。此情況有時被稱作「上動態餘量」問題。正 供電電1與此三極體區域操作開始之輸出電壓之間的電壓 差可被稱作「上動態餘量」電壓。類似地，隨著輸出電壓 接近接地電位，電荷泵之線性嚴重降級，因為DN電流源 内的N通道電晶體進入三極體區域操作。接地電位與三極 體區域操作開始之此電壓之間的電壓差可被稱作「下動態 餘量」電壓。在包含圖9之CT三角積分過取樣八〇(： 14〇的 圖6之PLL 129中，電荷泵丨39具有改良之線性，因為在節 "”占15 6處之其輸出j而上的電壓信號為小振幅中段電壓信 號。 149467.doc 201112640 在另一有利態樣中’與具有類似效能之習知ADPLL相 比，PLL可在較低供電電壓下操作。歸因於電荷泵驅動節 點156之電壓改變在Pll在鎖定狀態下操作時極小，理想狀 況下節點156上之電壓可設定為稍高於下動態餘量電壓。 供電電壓可低至稍大於上動態餘量與下動態餘量電壓之總 和的電壓。由於當PLL處於鎖定狀態時電荷泵之輸出端上 的電壓信號為小振幅信號，因此電荷泵之輸出電壓可保持 處於小電壓操作範圍中，在該情況下up電流源或DN電流 源均不在三極體區域中操作。The analog PLL 12 is a fractional N PLL 18. In cellular applications, this type of design than the pLL circuit topology is generally simpler than ADPLL, but this type contains an analog charge pump and an analog loop filter than the pLL circuit topology. Due to the limitations of dynamic headroom and lower headroom on analog charge pumps, ADPLLs typically cannot operate at low supply voltages. In addition, in cellular telephone applications, a single integrated PLL circuit will be able to operate in multiple different frequency bands. Unlike digital loop filters where the coefficients can be changed, analog loop ferrites are usually not very flexible. It is sometimes difficult or impossible to achieve a satisfactory effect on the operation of a single ADPLL circuit in the plurality of different frequency bands, as required in a cellular telephone application. In addition, implementing an analog loop filter may require a large amount of die space and is therefore expensive and may require the use of off-chip components. SUMMARY OF THE INVENTION The PLL referred to herein as "ADC-based mixed mode digital phase-locked back 149467.doc 201112640" includes a phase-to-digital converter (Pr) C), a digital loop filter, and a digital bit. Control oscillator (DC0) and primary loop divider. Within the PDC, phase/timing information is converted to a digital value stream by a charge pump and analog to digital converter (ADC). A digital bit stream, such as output by the ADC, is supplied to the digital loop filter, and the digital loop filter supplies a digitally tuned word stream to the DCO. An oscillating signal from the DC0 output is frequency-divided by the loop divider to generate a feedback signal DIV_〇UT supplied to a second input of the dc. A first input of the PDC receives a reference clock signal XO. The ADC within the PDC can be one of many different suitable types of ADCs including, but not limited to, continuous time delta-sigma oversampling digital ADCs, another type of continuous time ADC, another type of oversampled ADc, Continuous Asymptotic ADC (S AR ADC), another type of discrete-time ADC, switched capacitor ADC, or flash ADC. In a first embodiment, the ADC is - continuous time delta-sigma over-sampling digits. The voltage on the output node of the charge pump is a small amplitude mid-segment voltage. Since the charge pump output signal is supplied to the virtual ground input of the active integrator: node, the house signal is a small amplitude mid-segment voltage signal. The small amplitude mid-segment voltage on the output of the electric pump produces numerous advantages, including improved linearity of the charge pump, reduced charge (tetra), and the ability to operate the entire PLL from a lower supply voltage. The slowly varying phase error information in the signal output from the wire is oversampled because it is sampled at a higher frequency (e. g., reference input clock signal frequency). The quantized noise associated with this sampling moves to a higher frequency and is derived. Continuous Time Operation of Prisons 149467.doc 201112640 Relaxes the slew rate and bandwidth requirements of the op amps in the ADC, thereby reducing power consumption compared to embodiments that include conventional discrete-time ADCs. In the conventional TDC ADPLL, phase/timing information is processed in the time domain to make timing control difficult*, while in ADC-based mixed mode bits, phase/timing information is converted into charge information. This charge information is then processed. This makes the timing control circuit relatively simple. In one example, the charge pump has a controllable gain. When the PLL is not in the locked state, the gain of the charge pump is set to a lower value, and when the PLL is in the locked state, the gain of the charge pump is set to a higher value. The digital loop filter is programmable and its coefficients change as the operating frequency of the PLL feedback loop changes. When the cellular telephone is receiving in the first frequency band, the digital loop filter uses the first set of coefficients, and when the cellular telephone is receiving in the second frequency band, the digital loop filter uses the second set of coefficients. In a second embodiment, the ADC is a discrete time s AR ADC. In the SAR ADC embodiment, the same as the continuous time delta-sigma oversampling ADc embodiment, the output signal from the charge pump is a small amplitude and mid-segment voltage signal. In the usual example, the only important analog component of the 'S AR ADC is the comparator' and the linearity requirement of the comparator is relaxed compared to the linearity requirement of the op amp in the integrator of the delta-sigma oversampling ADC. . The linearity requirement due to reduced 'compared to the continuous-time delta-sigma over-sampling Adc embodiment' enables the SAR Adc embodiment to have lower power consumption. The reduced linearity requirement also allows the SAR ADC to operate at lower supply voltages. The foregoing is [invention], and thus must contain simplifications, generalizations, and omissions of the details; therefore, those skilled in the art should understand that [invention] 149467.doc 201112640 is merely illustrative and is not intended to be - Ways to limit. Other aspects, inventive features and advantages of the devices and/or procedures described herein will be apparent from the scope of the invention. [Embodiment] FIG. 4 is a highly simplified high-order block diagram of a specific type of mobile communication device according to a novel aspect. In this example, the mobile communication device 1 is a cellular telephone using a code division multiple access (CDMA) cellular telephone communication protocol. The cellular telephone includes (with the exception of several other components not illustrated) an antenna 102 and two integrated circuits 1〇3 and 1〇4. The integrated circuit 1〇4 is referred to as a "digital base frequency integrated circuit" or a "base frequency processor integrated circuit". The integrated circuit 103 is a radio frequency (RF) transceiver integrated circuit. The RF transceiver integrated circuit 1 〇 3 is called a "transceiver" because it includes a transmitter and a receiver. FIG. 5 is a more detailed block diagram of the RF transceiver integrated circuit ι 3 of FIG. 4. The receiver includes a so-called "receiving chain" 1 〇 5 and a local oscillating unit (LO) 106. When the cellular telephone is receiving, the high frequency RF signal 107 is received on the antenna 1〇2. Information from signal 1〇7 passes through duplexer 1〇8, matching network 109, and passes through receive chain 105. Signal 1〇7 is amplified by a low noise amplifier (LNA) 10 and downconverted by a mixer. The resulting downconverted signal is filtered by a baseband filter 112 and passed to a digital baseband integrated circuit 104. The analog to digital converter 113 in the digital baseband integrated circuit 1 〇4 converts the signal into a digital form and the resulting digital information is processed by a digital circuit in the digital base product circuit 104. The digital base frequency integrated circuit 1 〇 4 149467.doc 201112640 adjusts the (four) receiver by controlling the frequency of the local oscillator (10) supplied to the mixer (1) at the local oscillation sense terminal ι4. The right cellular phone is transmitting 'the information to be transmitted is converted into analogy by the digits in the digital base product circuit 104 to the analog converter (dac) i η and supplied to the "transfer key" 116. The fundamental frequency filter ιΐ7 takes out the noise generated by the digital to analog conversion program. The mixer block 118 then upconverts the signal to a high frequency signal under the control of the local oscillator 119. The driver amplifier 120 and the external power amplifier 121 amplify the high frequency signal to drive the antenna 102 such that the high frequency scale 1 is transmitted from the antenna 1〇2. The signal 122 is digitally controlled by the local oscillator output 104. The frequency of the local oscillator signal supplied to the mixer 11 8 is controlled by 123 to control the transmitter. The digital baseband integrated circuit 104 controls the local oscillators 106 and 119 by transmitting appropriate control information via the busbar interface 125 and control lines 126 and 127 across the digital bus 124. Figure 6 is a circuit diagram showing the local oscillator ι6 of Figure 5 in more detail. The local oscillator 106 includes a source 128 of reference clock signals and an ADC-based mixed mode digital PLL 129. Source 128 can be part of a crystal oscillator or a vibrator, or another source of reference clock signals (such as a wire that carries reference clock signal XO). Source 12 8 supplies the reference clock signal χ〇 to the first input lead 144 of phase frequency detector (PFD) 138. The ADC-based mixed mode digital PLL 129 is controlled via the control information received by the conductors 126 and the control interface circuit 130 by setting the fractional F divisor (N, f) supplied to the delta-sigma modulator 131 via the conductor 132. The ADC-based mixed mode digital PLL 129 includes a phase to 149467.doc -10- 201112640 bit converter (PDC) 133, a digital loop filter 134, a digitally controlled oscillator (DCO) 135, a primary circuit The frequency converter 136, the triangular integral modulator 131, the control interface 130 and a lock detector circuit 137. The pDc 133 in turn includes a PFD 138, a differential charge pump 139, and an analog to digital converter (ADC) 140. DCO 135 receives a sixteen bit digit tuning word stream from digital loop filter 134. At a given time, the sixteen-bit digit tuning word received by Dc 〇 i35 determines the frequency of the local oscillator output signal LO output by the DCO 135 to conductor 1. The local oscillator output signal L〇 is a digital signal in the 4 GHz range in this example. The output signal [〇 can be a single-ended or differential signal. The loop frequency divider 136 performs frequency division on the unit local local oscillator output signal L〇 by the octave digit division value received from the triangular integral modulator 131 via the wire 141, and the obtained unit cell of the division operation is obtained. The feedback k唬DIV_OUT is output to the conductor 142 and output to the second input lead 143 of the PFD 138. The delta-sigma modulator 131 changes the divisor value back and forth between the integer value N and the next integer value N+1 as time passes, so that the frequency of the LO is divided by the fraction as time elapses. The "N" in the score "?" value "Nf" represents an integer, and the "f" in the fraction value "Nf" represents a fractional value. As described above, the fractional value Nf in the division of the circuit divider 136 is in the self-digit baseband integrated circuit! 〇4 is received and is known by the local oscillator i 〇6. The PFD 138 receives the reference clock signal 在 on its first input 144 and the feedback div_〇 UT signal on its second input 143. From this k number ' PFD 138 produces an up charge pump control signal (up) and a downward charge 149467.doc 201112640 pump control signal (DN). The UP and DN signals are supplied to the charge pump 139 via wires 145 and 146, respectively. FIG. 7 is a diagram of one embodiment of PFD 138. The PFD 138 includes a first flip flop 147, a second flip flop 148, and an AND gate 149. If both signals XO and DIV_OUT are initially at a digital logic low value, and if both flip-flops 147 and 148 are reset and a digital logic low value is being output, AND gate 149 is outputting a digital logic low value and flip-flop 147 And 148 are not under reset conditions. If signal XO then transitions to a digital logic high value, flip flop 147 is set and the UP signal is asserted as a digital logic high value. This condition continues until the signal DIV-OUT transitions high. When the signal DIV_OUT transitions high, the flip flop 148 is set and the signal DN is asserted high. When the DN transitions high, both the UP and DN signals supplied to the input of the AND gate 149 are high. The AND gate 1 49 thus outputs a digital logic high value that resets both flip-flops 147 and 148 asynchronously. The two signals UP and DN are then quickly revoked to have a digital logic low value. At a point in time shortly after the signal DNS low to high transition, the PFD 138 is in a reset condition and is ready to measure the phase of another rising edge condition. The amount of time to confirm the signal DN is the amount of time required to reset the flip-flops 147 and 148 asynchronously via the AND gate 149 and the non-synchronous reset input of the flip-flop. However, the amount of time that the signal UP is asserted high depends on the phase difference between the rising edge of XO and the rising edge of DIV_OUT. The larger the phase difference, the longer the amount of time that the signal UP is confirmed to be high. If both signals XO and DIV_OUT are initially at a digital logic low value, and if both flip-flops 147 and 148 are reset and are outputting a digital logic low value, and 149467.doc -12- 201112640 if the signal XV is before the signal DIV - OUT thus transitions to a digital logic high value, and the flip flop 148 is set. The DN signal is confirmed to be high. This condition continues until the signal XO transitions high. When signal XO transitions high, flip-flop 147 is set and signal UP is asserted high. At this point, the two signals UP and DN are high. The AND gate 149 thus outputs a digital logic high value that resets both flip-flops 147 and 148 asynchronously. Undo confirms the two signals UP and DN to have a digital logic zero value. The PFD 138 is then ready to measure another rising edge condition. The amount of time for which the signal UP is asserted is the amount of time required to reset the flip-flops 147 and 148 asynchronously via the AND gate 149 and the non-synchronous reset input of the flip-flop. However, the amount of time that the signal DN is confirmed to be high depends on the phase difference between the rising edge of DIV-OUT and the rising edge of XO. The larger the phase difference, the longer the DN is confirmed to be high. FIG. 8 is a more detailed diagram of differential charge pump 139. The charge pump 139 includes a supply voltage selector 150, a first switch 151 and a P-channel UP current source transistor 152, a second switch 153, and an N-channel DN current source transistor 154. Supply voltage selector 150 can be, for example, an analog multiplexer that includes a transmission gate. The gate of the P-channel UP current source transistor 152 is biased by the gate bias voltage VBIASP. The gate of the N-channel DN current source transistor 154 is biased by the gate bias voltage VBIASN. These bias voltages are set such that the UP and DN currents have the desired magnitude. When the control signal UP received via the wire 145 has a digital logic high value, the UP current flows. When the control signal DN received via wire 146 has a digital logic high value, the DN current flows. If during the phase measurement rise XO/DIV-OUT edge condition, the signal UP is high for a longer time than the signal DN is high, then the net current 149467.doc -13- 201112640 UP current flows. On the other hand, if the signal DN is high for a period of time higher than the signal UP during the phase measurement rising X0/DIV_0UT edge condition, the net DN current flows. If the signal IN-LOCK on the input lead 155 is at a digital logic high value, the supply voltage selector 150 supplies the supply voltage V2 to the switch 153, and when the signal IN-LOCK at the input 155 is at the digital logic low value At this time, the supply voltage selector 150 supplies the supply voltage VI to the switch 151. The supply voltage V2 is a positive voltage greater than the supply voltage VI. When the supply voltage V2 is supplied to the switch 151, the amplitude magnitude (for example, 10 mA) of the ICP current pulse outputted by the charge pump 139 is higher than when the smaller supply voltage V1 is supplied to the switch 151 ( For example, 1 mA) is large. Therefore, the gain of the charge pump when the signal IN-LOCK is confirmed is greater than the gain of the charge pump when the signal IN-LOCK is not confirmed. A pulse of UP current is supplied to the conductor and node 156. A DN current pulse is drawn from the wire and node 1 56. The UP and DN current pulses together form a pulse train ICP. 9 is a more detailed diagram of the ADC 140 of FIG. The ADC 140 can be implemented as any suitable ADC of any type including, but not limited to, continuous time ADCs, discrete time ADCs, oversampled ADCs, continuous time delta-sigma oversampled ADCs, discrete time SAR ADCs, discrete time switched capacitor ADCs, and Flash ADC. Figure 9 illustrates an example of ADC 140 being a continuous time delta-sigma oversampling ADC (CT delta-sigma oversampling ADC). The ADC 140 includes two stages, a bandgap reference voltage 157 and an ADC 158. The first stage includes an operational amplifier 159, a capacitor 160, and a feedback control current source 161. The second stage includes a resistor 162, an operational amplifier 163, a capacitor 164, and a feedback control current source 165. The first stage and the second stage constitute an active integrator 149467.doc -14- 201112640, wherein node 156 is the input signal node of the integrator. If the first stage is the main source of noise, the chopper can be stabilized by placing the chopper around the first stage. The integrator integrates the voltage on node 156 and supplies the smoothed result to input 167 of ADC 158. The ADC 158 compares the voltage at input 167 to the reference voltage VREF. To this end, the input 168 of the ADC 158 receives a reference value of 2vref which is twice the comparison voltage vref. The ADC 1S8 outputs a three-bit value ADC-OUT[l:3] to the output conductor 189 in each cycle of the reference clock XO. Each successive digital value ADC_OUT[l:3] is a digital phase error word that is between the voltage signal received from the integrator at input 167 and the voltage VREF (one half of the voltage received at input 168, 2VREF). A measure of the value of the voltage difference. The larger the voltage difference, the larger the absolute value of ADC_OUT[l:3]. The most significant bit ADC, OUT[3], indicates that the integrator output signal at input 167 is higher or lower than VREF. The resulting digital phase error word ADC-0UT[1:3] flows control feedback current sources 161 and 165. If the voltage difference between the integrator output number and VREF is large, the feedback control current sources 161 and 165 are controlled to flow or flow more current, and if the voltage difference between the integrator output 彳5 and VREF is small, The feedback control current sources 161 and 165 are controlled to flow or flow less current. The result is a negative feedback that stabilizes the integrator and the ADC. Over time, the average charge supplied by charge fruit 39 to node 156 is equal to the average charge removed from node 156 by feedback control current source 161. The operational amplifier 159 does not draw a significant current from node 156 because its handle is connected to the non-inverting input of node 156. 149467.doc 15 201112640 has a high input impedance. 10 is a more detailed diagram of the ADC 158 of FIG. There are many ways to implement ADC 158. Figure 10 illustrates only one example. The ADC 158 includes a flash analog to digital converter that includes resistor ladders 169 through 173 and a corresponding set of comparators 1 74 through 1 77. The comparison voltage VREF is a voltage substantially across the ladder tap node at the middle of the ladder. The multi-bit output of this flash converter is supplied to a digital logic encoder 178. Encoder 178 converts the multi-bit output of the flash converter to a corresponding three-bit value. The three-bit digit value as output by encoder 178 is latched into binary register 179-181 on the rising edge of reference clock signal x. The three-bit value stream output by the three-bit register 179 to 181 is the signal ADC_OUT[l:3]. Figure 11 is a more detailed circuit diagram of one of the feedback current sources 161 of Figure 9. The p-channel UP switch transistors SU1 1 82 and SU2 183 are sized such that if the most significant bit ADC_OUT[ 1 ] is digitally low, then the transistors are scaled by a two-element ADC [2:3] The amount determined determines that current flows to node ι56. This outflow current flows from the supply voltage node i 84 to the node 156 via the parallel connected electrodes 182 and 183. Similarly, the n-channel DOWN switch transistors SD1 185 and SD2 186 are sized such that if the most significant bit 兀 ADC_OUT[l] is digitally logic high, then the transistors are scaled by the two-bit ADC_〇UT[2 :3] The amount of judgment flows into the current from node ι56. This current flows from node 156 to ground, point 187, via transistors 185 and 186 connected in parallel. The carrier signals adc_〇ut[2:3] and the ADC-OUT[3] conductors illustrated on the left side of Fig. 11 are the same signal conductors extending to the output of ado 158 in Fig. 9. 149467.doc -16 - 201112640 Figure 12 is a table illustrating the operation of ADC 158 and the feedback current source 161 of Figure 11. As indicated in the table, if VREF (the voltage at the middle of the resistor ladder along Figure 10) and the voltage VIN at the input node 167 (the voltage received from the two-stage integrator of Figure 9) The difference is between _〇1 volt and +〇1 volt', then the ADC-OUT[l:3] value is "000". The switching transistors SD1, SD2, SU1 and SU2 are all controlled to be turned off. The feedback control current source 161 neither supplies current to the node 156 nor draws current from the node 156. This current is represented in the figure as IFB. However, if the voltage difference between VREF and VIN is positive, then transistors SU1 and/or SU2 are controlled to be turned on so that current IFB is positive. The current flows out to node 1 5 6 . If the voltage difference between VREF and VIN is negative, transistor SU1 and/or SU2 is controlled to be off so that current IFB is negative. Current flows from node 156. The signal polarity is set 'so that the negative feedback stabilizes the feedback loop of Figure 9. Thus, as illustrated in Figure 6, ADC 140 supplies a three-bit digital value ADC_OUT[l:3] stream to digital loop filter 134. The magnitude of the information content of the three-bit value ADC_OUT[l:3] stream indicates the reference signal χ〇 on the first input lead 144 of the PFd 136 and the feedback signal DIV-OUT on the second input lead 143 of the pFD 136. The amount of phase error between. The signal output by charge pump 139 in an example t' has a useful bandwidth of about 1 〇〇 kHz, but ADC 140 oversamples this signal at a much higher reference clock frequency (e.g., 2 〇 mHz). The quantization noise is shaped to have a higher frequency and is filtered out. Loop filter 134 has a bandwidth of 1 〇 kHz. Although the ADC_OUT[l:3] value output by the ADC 140 is only a three-bit value, depending on the sampling rate, the effective resolution due to oversampling and crossing is a resolution of ten to twenty bits. 149467.doc 17 201112640 In an advantageous aspect, the 'loop filter 丨 34 is a flexible and programmable digital filter whose coefficients can be changed under software control. The filter coefficients used by the digital loop filter 134 are supplied in parallel via the control interface 13 and the lead 丨88. If an ADC-based mixed mode digital pLL 129 is used to generate a nucleus for receiving cellular communication in the first RF communication band, the first set of filter coefficients is used, and if used based on AD(: The hybrid chess-type digital PLL 129 generates an LO for receiving cellular communication in the second RF communication band, and then uses a second set of filter coefficients. In another advantageous aspect, the PLL is normally operated and locked. In contrast, the pLL charge pump achieves a small gain when the PLL is in the acquisition state and is attempting to lock. During the acquisition, the charge is supplied to the node 156 or the rate other than the supply to the node 156 is not reduced at the charge pump gain. The situation is so large that the negative feedback of the integrator in the ADC 14〇 is suppressed. The integrator output may be saturated. To prevent this from happening, the gain of the charge pump 139 is controlled to have a smaller gain value during acquisition, while conventional The gain of the charge pump 139 in the operation (〃 PLL 129 lock) is a larger gain value. The relative gain value is set by appropriately setting the voltages ¥1 and 乂2 in Fig. 8. The lock is determined by the lock detector circuit 137 of Figure 6. In another advantageous aspect, the pLL is improved in linearity compared to the charge of the conventional ADPLL. Figure 6 and Figure 9 In pll, the integrator input node 156 driven by the pll charge is a "virtual ground" node 156. Due to the active two-stage integrator of Figure 9, node 159 is a virtual ground and is on node 159 during normal PLL operation. The voltage signal is a small amplitude mid-segment voltage signal. The input impedance of the input ct delta-sigma over-sampling ADC is greater than that of the 丨 River Europe 149467.doc 201112640 姆, s, the small amplitude of the factory. γ, +. + a in this article & It is related to the voltage difference between the supply voltage VI at the page 4 of the charge pump 139 and the V2 盥 尸 , ,, the position of the H "r heart and the ground potential at the bottom of the electric (9). When V2 is 1.3 volts, " ' < in lock and field" has a peak-to-peak value of about 〇. 〇 5 volts. The dynamic headroom (4) is about 〇.4 volts, and the lower dynamic residual pressure is about 〇4 volts. The term "中中,中中" is compared to the power supply W in the charge pump 139. In terms of the voltage range between the ground potential at the bottom of the charge system m. The charge supplied to the node 156 due to the current ICP pulse and the charge leaving the node 156 due to the current IFB are passed over time. In the conventional analog charge collector circuit, the gain of the charge mill varies according to the voltage at the output of the charge spring. The gain of this change is considered to be non-linear. As the output voltage approaches the positive supply voltage of the charge pump, the charge pump The linearity is further reduced because the p-channel transistor in the up current source of the charge pump enters the triode region operation. This condition is sometimes referred to as the "upper headroom" problem. The voltage difference between the positive power supply 1 and the output voltage at which the triode region operation begins can be referred to as the "upper headroom" voltage. Similarly, as the output voltage approaches ground potential, the linearity of the charge pump is severely degraded because the N-channel transistor in the DN current source enters the triode region operation. The voltage difference between the ground potential and the voltage at which the triode region operation begins can be referred to as the "lower dynamic margin" voltage. In the PLL 129 of Figure 6, which includes the CT delta-sigma oversampling gossip of Figure 9, the charge pump 丨39 has an improved linearity because the section "" The voltage signal is a small amplitude mid-section voltage signal. 149467.doc 201112640 In another advantageous aspect, the PLL can operate at a lower supply voltage than a conventional ADPLL with similar performance. Due to the charge pump drive node 156 The voltage change is extremely small when P11 is operating in the locked state. Under ideal conditions, the voltage on node 156 can be set slightly higher than the lower headroom voltage. The supply voltage can be as low as slightly above the upper headroom and the lower headroom voltage. The sum of the voltages. Since the voltage signal at the output of the charge pump is a small amplitude signal when the PLL is in the locked state, the output voltage of the charge pump can remain in the small voltage operating range, in which case the up current source or DN The current sources are not operated in the triode region.
在另一有利態樣中，可使用與原本在具有類似效能之習 知ADPLL中需要之電荷泵相比能將較少雜訊引入至pLL内 之電荷泵。改良電荷泵線性之習知做法為使用更具線性的 電荷泵。不幸的是，更具線性的電荷泵亦通常將較多雜訊 引入至電荷泵輸出信號内。在包含圖9之CT三角積分過取 樣ADC 140的圖6之PLL 129中，歸因於節點156上之電壓 在书規PLL操作期間保持大體上固定，電荷泵〖39不需要為 问線性電荷泵。節點i 5 6上之電壓信號為小振幅中段電壓 乜號電荷泵13 9可因此為與具有類似效能之習知ADPLL 的電荷系相比能將較少雜訊引人至電荷系輸出信號内的較 不具線性之類型。 圖13 A為說明圖6之以ADC為基礎的混合模式數位pLL之 操作之波形圖。在說明於左側之時間週期中及在說明於右 側之時間週期中，參考時脈信號χ〇與回饋信號mv—⑽τ 之間的相位差為正（亦即，在mv一〇υτ轉變至 χ〇 149467.doc •20· 201112640 變至高）。電荷泵輸出電流ICP之脈衝因此為正脈衝。電流 ICP之脈衝正供應至節點156上。與說明於右側之週期中之 相位差相比，在說明於圖13Α中之左側之時間週期中，相 位差較大。左側之時間週期中的ICP脈衝之寬度因此 側之時間週期中的ICP脈衝之寬度寬。左側之時間週期中 的供應至節點156上之電荷量因此比右側之時間週期中的 供應至節點156上之電荷量大。回饋電壓IFB由三位元值 ADC一OUT[l:3]設定。電流IFB之量值因此在左側之時間週 期中比其在右側之時間週期中大。在兩個時間週期中之每 者中，由電流ICP之量值與脈衝寬度相乘表示之總電荷 等於由IFB之量值與IFB電流流動的時間週期（電流IFB遍及 整個時間週期流動）相乘表示之總電荷。 圖13B為說明圖6之以ADC為基礎的混合模式數位pLL之 操作之波形圖。在說明於左側之時間週期中及在說明於右 側之時間週期中，參考時脈信號χ〇與回饋信號mv_〇UT 之間的相位差為負（亦即，在DIV_〇UT轉變至高後，χ〇轉 變至高）。ICP電流脈衝之量值因此為負。在相位差較大 (如由說明於圖13B中之左側之時間週期指示）之情況下， ICP之脈衝寬度較寬，且回饋電流IFB具有較大負量值。 圖14為說明圖6之以ADC為基礎的混合模式數位pll之另 一有利態樣之圖。諸如圖1之TDC ADPLL的習知TDC ADPLL通常對參考時脈抖動敏感。如由線2〇〇指示，隨著 參考時脈抖動增加，圖1之習知TDC ADPLL展現，當此抖 動之量值達到300皮秒相位雜訊明顯增加。相比而言，如 149467.doc -21- 201112640 由線201指示，圖6之以ADC為基礎的混合模式數位PLl對 參考時脈抖動較不敏感，且展現相位雜訊未明顯增加。In another advantageous aspect, a charge pump capable of introducing less noise into the pLL can be used as compared to a charge pump that would otherwise be required in a conventional ADPLL having similar performance. A well-known practice for improving charge pump linearity is to use a more linear charge pump. Unfortunately, more linear charge pumps also typically introduce more noise into the charge pump output signal. In the PLL 129 of FIG. 6 including the CT delta-sigma oversampling ADC 140 of FIG. 9, the charge pump 390 does not need to be a linear charge pump due to the voltage on the node 156 remaining substantially fixed during the book PLL operation. . The voltage signal on node i 5 6 is a small amplitude mid-segment voltage. The charge pump 13 9 can therefore introduce less noise into the charge system output signal than the charge system of a conventional ADPLL with similar performance. Less linear type. Figure 13A is a waveform diagram illustrating the operation of the ADC-based mixed mode digital pLL of Figure 6. In the time period illustrated on the left side and in the time period illustrated on the right side, the phase difference between the reference clock signal χ〇 and the feedback signal mv_(10)τ is positive (that is, the transition from mv to 〇υτ to χ〇) 149467.doc •20· 201112640 becomes high). The pulse of the charge pump output current ICP is therefore a positive pulse. The pulse of current ICP is being supplied to node 156. The phase difference is large in the time period illustrated on the left side in Fig. 13A as compared with the phase difference in the period illustrated on the right side. The width of the ICP pulse in the time period on the left side is therefore wider than the width of the ICP pulse in the time period on the side. The amount of charge supplied to node 156 in the time period on the left is therefore greater than the amount of charge supplied to node 156 in the time period on the right. The feedback voltage IFB is set by the three-bit value ADC-OUT[l:3]. The magnitude of the current IFB is therefore greater in the time period on the left side than in the time period on the right side. In each of the two time periods, the total charge represented by the magnitude of the current ICP multiplied by the pulse width is equal to the time period between the magnitude of the IFB and the time period during which the IFB current flows (current IFB flows throughout the entire time period) Indicates the total charge. Figure 13B is a waveform diagram illustrating the operation of the ADC-based mixed mode digital pLL of Figure 6. In the time period illustrated on the left side and in the time period illustrated on the right side, the phase difference between the reference clock signal χ〇 and the feedback signal mv_〇UT is negative (ie, after the DIV_〇UT transitions to high) , χ〇 change to high). The magnitude of the ICP current pulse is therefore negative. In the case where the phase difference is large (as indicated by the time period indicated on the left side in Fig. 13B), the pulse width of the ICP is wide, and the feedback current IFB has a large negative value. Figure 14 is a diagram showing another advantageous aspect of the ADC-based mixed mode digital bit p11 of Figure 6. A conventional TDC ADPLL such as the TDC ADPLL of Figure 1 is typically sensitive to reference clock jitter. As indicated by line 2〇〇, as the reference clock jitter increases, the conventional TDC ADPLL of Figure 1 exhibits a significant increase in phase noise when the amount of jitter reaches 300 picoseconds. In contrast, as indicated by line 201, 149467.doc -21-201112640, the ADC-based mixed mode digital PL1 of Figure 6 is less sensitive to reference clock jitter and exhibits no significant increase in phase noise.
圖15展示圖6之以ADC為基礎的混合模式數位pll之ADCFigure 15 shows the ADC-based mixed mode digital pll ADC of Figure 6.
140為連續漸近ADC(SAR ADC)之實例。SAR ADC並非為 過取樣ADC ’而是為奈奎斯（Nyquist)速率ADC。SAR ADC 140包括電容C之第一電容器301、電容C/2之第二電容器 302、電容C/4之第三電容器303、一比較器304、大量數位 連續漸近邏輯305及三個開關306至308。最初，電荷泵139 將大里電何供應至郎點15 6上或將大量電荷拉離節點15 6， 如上文結合圖9、圖13A及圖13B所解釋。將電荷整合至節 點1 56之電容上開始於信號x〇或DIV_〇uT中之一者的上升 邊緣，且當信號XO或DIV一OUT中之另一者具有上升邊緣 時止，如上文結合圖丨3 a及圖13 B所解釋。此時，開關 306至308處於如藉由先前類比至數位轉換所判定之狀態 下。二進位加權之電容器中之每一者的底板因此耦接至去 地電位節點或耦接至參考電壓VREF節點或耦接至參考$ 壓2VREF節.點。在一有利態樣中，開關3〇6至3〇8保持於》 在先前進行之類比至數位轉換結束時所處之狀態下，以右 得當電荷系正對節點156充電或放電時，節點156上之電遲 為中段電壓。當電荷泵正對節點156充電或放電時將節黑 156上之電壓保持在中段電壓可維持電荷泵之線性。 -旦已完成對節點156之充電或放電，則電荷泵之购 DN電机源實際上與節點156隔離，且SAR ADC 14G接著f 仃類比至數位轉換。數位SAR邏輯3〇5控制所有三個開职 149467.doc -22- 201112640 306至308 ’以使得電容器301至303之底板耦接至vREf節 點。比較器304判定節點156上之電壓比比較器3〇4之非反 相輸入引線上之電壓VREF高或是低。若節點156上之電壓 比VREF高’則ADC_OUT[l:3]之最高有效位元 ADC_OUT[l] s史疋至數位「1」，且開關3〇6經控制以將電 容器301之底板耦接至接地電位節點。另一方面，若節點 156上之電壓比VREF低’則最高有效位元ad c 〇UT[l]^ 定至數位「0」，且開關306經控制以將電容器3〇丨之底板 耗接至2VREF節點。接下來’判定第二位元adc 〇UT[2} 之值。比較器304再次判定郎點156上之電壓比vref高咬 疋低。右郎點15 6上之電壓比VREF高，則數位sar邏輯 305控制開關307將電容器302之底板耦接至接地電位節 點’且位元ADC_0UT[2]設定至數位「1」，否則開關3〇7 經控制以將電容器302之底板輕接至2VREF節點且 ADC_0UT[2]設定至數位「0」。接下來，判定第三位元 ADC_0UT[3]之值。比較器304再次判定節點156上之電壓 比VREF高或是低。若節點1 56上之電壓比VREF高，則數 位SAR邏輯305控制開關308將電容器3〇3之底板柄接至接 地電位節點，且位元ADC_0UT[3]設定至數位「1j ，否則 開關308經控制以將電容器303之底板耦接至2VREF節點且 ADC—0UT[3]設定至數位「0」。 因此，三位元數位值ADC_0UT[1:3]中之最高有致位元 ADC_0UT[1]指示節點156上之樣本電壓比VREF高或是 低。另兩個位元ADC_〇UT[2:3]指示VREF與節點156上之 149467.doc -23- 201112640 樣本電壓之間的電壓差之量值。參考時脈信號χ〇之每一 循環執行一個此數位化操作。 圖16為展示在參考時脈信號又〇之一循環期間電荷泵何 時對節點156充電/放電及在該循環期間SAR ADC何時將節 點156上之電壓轉換成數位值ADC_〇UT[l:3]之波形圖。在 先前循環之最後部分期間及/或在該循環之第一部分3〇9期 間，電荷泵對節點156充電/放電》無關於div_OUT在相位 上在XO之前或是之後，在信號χ〇之下降邊緣出現前完成 電荷栗對節點1 56之充電或放電。在開始於信號χ〇之下降 邊緣的ΧΟ信號循環之第二部分3 1 〇期間，SAR ADC將節點 156上之電壓轉換成數位值ADC_OUT[l:3]。使用信號Χ〇 之延遲之版本起始開關306、307及308之三個連續比較及 操縱。延遲之版本由數位SAR邏輯區塊305内之延遲線產 生。第一次的下降邊緣311用以起始由比較器304進行之第 一比較及開關306之相關聯的開關操作。第二次的χ〇之延 遲之版本之下降邊緣3 12用以起始由比較器304進行之第二 比較及開關307之相關聯的開關操作《第三次的χ〇之進一 步延遲之版本之下降邊緣313用以起始由比較器304進行之 第三比較及開關308之相關聯的開關操作。 圖15之SAR ADC 140中的僅有類比電路為比較器304。 所有其他組件為數位邏輯組件或被動電路組件。以ADC為 基礎的混合模式ADC之SAR ADC實施例因此通常具有比以 ADC為基礎的混合模式ADC之CT三角積分ADC實施例低的 電力消耗。由於僅有的類比組件為可按實質非線性操作之 149467.doc -24- 201112640 比較器（與必須具有優越線性之運算放大器相反），因此以 ADC為基礎的混合模式adC之SAR ADC實施例亦可在比以 ADC為基礎的混合模式ADC之CT三角積分ADC實施例低的 供電電壓下操作。 圖17為根據一新穎態樣的方法4〇〇之流程圖。將參考信 號及回饋信號接收至相位至數位轉換器（PDC)上（步驟 401) ° PDC内之電荷泵用以驅動節點。pdc内之類比至數 位轉換器（ADC)將該節點上之信號轉換成第一多位元數位 值流（步驟402)。在一實例中，該信號為小振幅中段電壓信 號’且s玄節點為「虛擬接地」節點。數位迴路濾波器對第 一夕位元數位值流濾波’藉此產生第二多位元數位值流 (步驟403)。數位控制振盪器（DC0)接收第二多位元數位值 "il且輸出對應的DCO輸出信號（步驟4〇4)。迴路除頻器對 DCO輸出信號進行頻率除法運算，藉此產生回饋信號（步 驟405)。 雖然在上文中出於指導目的描述某些具體實施例，但本 專利文獻之教示具有普遍的可應用性，且不限於上文所描 述之具體實施例。因此，在不脫離下文闡明之申請專利範 圍的範疇之情況下，可實踐所描述之具體實施例的各種特 徵之各種修改、改編及組合。 【圖式簡單說明】 ’ 圖1(先前技術)為習知時間至數位轉換器全數位鎖相迴 路（TDCADPLL)之方塊圖； 圖2 (先前技術)為習知相位至數位轉換器全數位鎖相迴 149467.doc •25· 201112640 路（PDCADPLL)之方塊圖； 圖3(先前技術）為一習知類比PLL之方塊圖； 圖4為根據一新穎態樣的使用以ADC為基礎的混合模式 數位P L L之一特定類型之行動通信裝置！ 〇 〇之極簡化的高階 方塊圖； 圖5為圖4之RF收發器積體電路1〇3之更詳細的方塊圖； 圖6為圖5之本地振盪器内1〇6的以ADC為基礎的混合模 式數位PLL 129之更詳細的方塊圖； 圖7為圖6之PFD 13 8之電路圖； 圖8為圖6之電荷果139之電路圖； 圖9為展示以下實例之圖式，即在該實例中圖6之以adc 為基礎的混合模式數位PLL之ADC 140為一 CT三角積分過 取樣ADC ; 圖10為圖9之CT二角積分過取樣ADC 14〇之ADC 158之 圖式； 圖11為圖9之CT三角積分過取樣ADC 14〇之回饋控制電 流源中的一者之電路圖； 圖12為說明圖1G之ADC與圖&回饋控制電流源如何— 起操作之表格； 圖13A為說明在參考時脈信號χ〇與回饋信號之 間的相位差為正之情形下圖6之以ADC為基礎的混合模式 數位PLL·之操作之波形圖； 圖13 B為說明在參考時脈产喻v ^ a T于脈4唬XO與回饋信號Div_OUT之 間的相位差為負之情形下国A七 肜下圖6之以AOC為基礎的混合模式 149467.doc •26- 201112640 數位PLL之操作之波形圖； 圖Μ為說明圖6之以ADC為基礎的混合模式數位以之有 利態樣之圖； 圖15為可用於圖6之PLL内之ADP , , Α Α < ι4〇的連續漸近 ADC(SAR ADC)之圖式； 圖16為說明圖15之SAR ADC之操作之处，. 夜形圖；及 圖17為根據一新穎態樣的方法之簡化流程圖。 【主要元件符號說明】 1 時間至數位轉換器全數位鎖相迴路(tdc adpll) 2 累加器 3 時間至數位轉換器（TDC) 4 求和器 5 數位迴路濾波器 6 數位控制振盪器（DCO) 7 相位至數位轉換器全數位鎖相迴路(pDC ADPLL) 8 相位至數位轉換器（PDC) 9 數位迴路濾波器 10 數位控制振盪器（DCO) 11 數位迴路除頻器 12 分數N類比鎖相迴路 13 相位偵測器 14 類比電荷泵 15 類比濾波器 16 壓控振盪器（vcc〇 149467.doc -27- 201112640 17 除頻器 18 三角積分調變器 100 行動通信裝置 102 天線 103 RF收發器積體電路 104 數位基頻積體電路 105 接收鏈 106 本地振盪器（LO) 107 高頻RF信號 108 雙工器 109 匹配網路 110 低雜訊放大器（LNA) 111 混頻器 112 基頻渡波裔 113 類比至數位轉換器 114 本地振盪器輸出端/導線 115 數位至類比轉換器（DAC) 116 傳輸鏈 117 基頻渡波益 118 混頻器 119 本地振盪器 120 驅動器放大器 121 外部功率放大器 122 高頻RF信號 149467.doc -28- 201112640 123 本地振盪器輸出端 124 數位匯流排 125 匯流排介面 126 控制線/導線 127 控制線 128 參考時脈信號XO之源 129 以ADC為基礎的混合模式數位鎖相迴路 130 控制介面電路 131 三角積分調變器 132 導線 133 相位至數位轉換器（PDC) 134 數位迴路濾波器 135 數位控制振盪器（DCO) 136 迴路除頻器 137 鎖定偵測器電路 138 相位頻率偵測器（PFD) 139 差分電荷泵 140 類比至數位轉換器（ADC) 141 導線 142 導線 143 第二輸入引線 144 第一輸入引線 145 導線 146 導線 149467.doc -29- 201112640 147 正反器 148 正反器 149 AND閘 150 供電電壓選擇器 151 開關 152 P通道UP電流源電晶體 153 第二開關 154 N通道DN電流源電晶體 155 輸入引線/輸入端 156 節點 157 帶隙基準電壓 158 類比至數位轉換器（ADC) 159 運算放大器 160 電容器 161 回饋控制電流源 162 電阻器 163 運算放大器 164 電容器 165 回饋控制電流源 167 輸入端/輸入節點 168 輸入端 169 電阻器梯 170 電阻器梯 171 電阻器梯 149467.doc -30- 201112640 172 電阻器梯 173 電阻器梯 174 比較器 175 比較器 176 比較器 177 比較器 178 數位邏輯編碼器 179 三位元暫存器 180 三位元暫存器 181 三位元暫存器 182 P通道UP開關電晶體SU1 183 P通道UP開關電晶體SU2 184 供電電壓節點 185 N通道DOWN開關電晶體SD1 186 N通道DOWN開關電晶體SD2 187 接地節點 188 導線 189 輸出導線 200 線 201 線 301 第一電容器 302 電容C/2之第二電容器 303 電容C/4之第三電容器 304 比較器 149467.doc -31 - 201112640 305 數位連續漸近邏輯 306 開關 307 開關 308 開關 309 XO信號循環之第一部分 310 XO信號循環之第二部分 311 下降邊緣 312 下降邊緣 313 下降邊緣 149467.doc -32-140 is an example of a continuous asymptotic ADC (SAR ADC). The SAR ADC is not an oversampled ADC' but a Nyquist rate ADC. The SAR ADC 140 includes a first capacitor 301 of capacitor C, a second capacitor 302 of capacitor C/2, a third capacitor 303 of capacitor C/4, a comparator 304, a plurality of digits of continuous asymptotic logic 305, and three switches 306 to 308. . Initially, the charge pump 139 supplies a large amount of electricity to the point 15 6 or pulls a large amount of charge away from the node 15 6 as explained above in connection with Figures 9, 13A and 13B. Integrating the charge onto the capacitance of node 1 56 begins at the rising edge of one of the signals x〇 or DIV_〇uT, and when the other of the signal XO or DIV-OUT has a rising edge, as described above Figure 3a and Figure 13B explain. At this time, the switches 306 to 308 are in a state as determined by the previous analog to digital conversion. The bottom plate of each of the binary weighted capacitors is thus coupled to the ground potential node or to the reference voltage VREF node or to the reference voltage 2VREF node. In an advantageous aspect, the switches 3〇6 to 3〇8 are held in a state in which the analogy to the end of the digital conversion is performed, and the node 156 is charged or discharged with the right-handed charge system. The upper power is delayed in the middle voltage. Maintaining the voltage on blackout 156 at the mid-section voltage while the charge pump is charging or discharging node 156 maintains the linearity of the charge pump. Once the charging or discharging of node 156 has been completed, the source of the charge pump's DN motor is actually isolated from node 156, and SAR ADC 14G is then f 仃 analog to digital converted. The digital SAR logic 3〇5 controls all three of the 149467.doc -22- 201112640 306 to 308' to couple the bottom plates of the capacitors 301 to 303 to the vREf node. Comparator 304 determines that the voltage on node 156 is higher or lower than the voltage VREF on the non-inverting input lead of comparator 3〇4. If the voltage on node 156 is higher than VREF', then the most significant bit ADC_OUT[l] of ADC_OUT[l:3] is 疋" to the digit "1", and switch 3〇6 is controlled to couple the bottom plate of capacitor 301. To the ground potential node. On the other hand, if the voltage on node 156 is lower than VREF, then the most significant bit ad c 〇 UT[l] is determined to digit "0", and switch 306 is controlled to draw the bottom plate of capacitor 3 to 2VREF node. Next, the value of the second bit adc 〇UT[2} is determined. Comparator 304 again determines that the voltage at Lang 156 is higher than vref. The voltage on the right point 15 6 is higher than VREF, then the digital sar logic 305 controls the switch 307 to couple the bottom plate of the capacitor 302 to the ground potential node 'and the bit ADC_0UT[2] is set to the digit "1", otherwise the switch 3〇 7 Controlled to lightly connect the bottom plate of capacitor 302 to the 2VREF node and ADC_0UT[2] to the digital "0". Next, the value of the third bit ADC_0UT[3] is determined. Comparator 304 again determines if the voltage on node 156 is higher or lower than VREF. If the voltage on node 1 56 is higher than VREF, digital SAR logic 305 controls switch 308 to connect the bottom handle of capacitor 3〇3 to the ground potential node, and bit ADC_0UT[3] is set to digit "1j, otherwise switch 308 passes Control is to couple the bottom plate of capacitor 303 to the 2VREF node and ADC_OUT[3] to the digital "0". Therefore, the highest significant bit of the three-bit value ADC_0UT[1:3] ADC_0UT[1] indicates that the sample voltage on node 156 is higher or lower than VREF. The other two bits ADC_〇UT[2:3] indicate the magnitude of the voltage difference between VREF and the 149467.doc -23- 201112640 sample voltage on node 156. This digitalization operation is performed every cycle of the reference clock signal. Figure 16 is a diagram showing when the charge pump charges/discharges node 156 during one cycle of the reference clock signal and during which the SAR ADC converts the voltage on node 156 to a digital value ADC_〇UT[l:3 Waveform diagram. During the last part of the previous cycle and/or during the first part of the cycle 3〇9, the charge pump charges/discharges the node 156 regardless of whether the div_OUT is in phase before or after XO, at the falling edge of the signal χ〇 Charging or discharging the node 1 56 is completed before the occurrence of the charge. During the second portion 3 1 ΧΟ of the chirp signal cycle beginning at the falling edge of the signal chirp, the SAR ADC converts the voltage at node 156 into a digital value ADC_OUT[l:3]. Three consecutive comparisons and manipulations of the start switches 306, 307 and 308 using the delayed version of the signal 。 are used. The delayed version is generated by a delay line within the digital SAR logic block 305. The first falling edge 311 is used to initiate the first comparison by comparator 304 and the associated switching operation of switch 306. The falling edge 3 12 of the second delayed version is used to initiate the second comparison by comparator 304 and the associated switching operation of switch 307. The third delayed version of the further delay The falling edge 313 is used to initiate a third comparison by the comparator 304 and an associated switching operation of the switch 308. The only analog circuit in the SAR ADC 140 of Figure 15 is the comparator 304. All other components are digital logic components or passive circuit components. The SAR ADC embodiment of an ADC-based mixed mode ADC therefore typically has lower power consumption than the CT delta-sigma ADC embodiment of an ADC-based mixed mode ADC. Since the only analog component is the 149467.doc -24-201112640 comparator that can operate in substantial nonlinearity (as opposed to an op amp that must have superior linearity), the ADC-based hybrid mode adC SAR ADC embodiment is also It can operate at a lower supply voltage than the CT delta-sigma ADC embodiment of an ADC-based mixed mode ADC. Figure 17 is a flow diagram of a method 4 in accordance with a novel aspect. The reference signal and the feedback signal are received to the phase to digital converter (PDC) (step 401). The charge pump in the PDC is used to drive the node. An analog to digital converter (ADC) within pdc converts the signal on the node into a first multi-bit digit value stream (step 402). In one example, the signal is a small amplitude mid-segment voltage signal and the s-think node is a "virtual ground" node. The digital loop filter filters the first octet digit value stream' thereby generating a second multi-bit digit value stream (step 403). The digitally controlled oscillator (DC0) receives the second multi-bit digital value "il and outputs the corresponding DCO output signal (step 4〇4). The loop divider divides the DCO output signal by frequency division, thereby generating a feedback signal (step 405). Although certain specific embodiments have been described above for instructional purposes, the teachings of this patent document have general applicability and are not limited to the specific embodiments described above. Accordingly, various modifications, adaptations and combinations of the various features of the described embodiments may be practiced without departing from the scope of the invention. [Simple diagram of the diagram] 'Figure 1 (previous technique) is a block diagram of a conventional time-to-digital converter full digital phase-locked loop (TDCADPLL); Figure 2 (previous technique) is a conventional phase-to-digital converter full digital lock Figure ternary diagram 149467.doc •25·201112640 (PDCADPLL); Figure 3 (previous technique) is a block diagram of a conventional analog PLL; Figure 4 is an ADC-based hybrid mode according to a novel aspect. A specific type of mobile communication device for digital PLLs! Figure 5 is a more detailed block diagram of the RF transceiver integrated circuit 1〇3 of Figure 4; Figure 6 is an ADC based on the 1〇6 of the local oscillator of Figure 5. FIG. 7 is a circuit diagram of the PFD 13 8 of FIG. 6; FIG. 8 is a circuit diagram of the charge fruit 139 of FIG. 6; FIG. 9 is a diagram showing the following example, that is, In the example, the ADC 140 of the adc-based mixed mode digital PLL of FIG. 6 is a CT delta-sigma oversampling ADC; FIG. 10 is a diagram of the CT 158 of the CT two-corner integral oversampling ADC of FIG. 9; FIG. Figure 12 is a circuit diagram of one of the feedback control current sources of the CT delta-sigma oversampling ADC 14 of Figure 9; Figure 12 is a table illustrating how the ADC of Figure 1G and the Figure & feedback control current source operate; Figure 13A is A waveform diagram illustrating the operation of the ADC-based mixed mode digital PLL in FIG. 6 in the case where the phase difference between the reference clock signal 回 and the feedback signal is positive; FIG. 13B is a diagram illustrating the reference clock generation. v ^ a T is the case where the phase difference between the pulse 4唬XO and the feedback signal Div_OUT is negative. The AOC-based hybrid mode of Figure 6 is 149467.doc •26- 201112640 The waveform diagram of the operation of the digital PLL; Figure Μ is a diagram illustrating the advantageous mode of the ADC-based mixed mode digit of Figure 6; Figure 15 is a diagram of a continuous asymptotic ADC (SAR ADC) that can be used for the ADP, Α Α < ι4〇 in the PLL of Figure 6; Figure 16 is a diagram illustrating the operation of the SAR ADC of Figure 15; And Figure 17 is a simplified flow diagram of a method in accordance with a novel aspect. [Main component symbol description] 1 Time to digital converter full digital phase-locked loop (tdc adpll) 2 Accumulator 3 time to digital converter (TDC) 4 Summer 5 digital loop filter 6 Digitally controlled oscillator (DCO) 7 Phase to Digital Converter Full Digital Phase-Locked Loop (pDC ADPLL) 8 Phase-to-Digital Converter (PDC) 9 Digital Loop Filter 10 Digitally Controlled Oscillator (DCO) 11 Digital Loop Divider 12 Fractional N-Type Phase-Locked Loop 13 Phase detector 14 Analog charge pump 15 Analog filter 16 Voltage controlled oscillator (vcc〇149467.doc -27- 201112640 17 Frequency divider 18 Triangular integral modulator 100 Mobile communication device 102 Antenna 103 RF transceiver integrated body Circuit 104 Digital Base Product Circuit 105 Receive Chain 106 Local Oscillator (LO) 107 High Frequency RF Signal 108 Duplexer 109 Matching Network 110 Low Noise Amplifier (LNA) 111 Mixer 112 Fundamental Frequency Waves 113 Analogy To digital converter 114 local oscillator output / conductor 115 digital to analog converter (DAC) 116 transmission chain 117 base frequency crossing wave benefit 118 mixer 119 local oscillation 120 Driver amplifier 121 External power amplifier 122 High frequency RF signal 149467.doc -28- 201112640 123 Local oscillator output 124 Digital bus 125 Bus interface 126 Control line / conductor 127 Control line 128 Reference clock signal XO source 129 ADC-Based Mixed Mode Digital Phase-Locked Circuit 130 Control Interface Circuitry 131 Delta Integral Modulator 132 Wire 133 Phase-to-Digital Converter (PDC) 134 Digital Loop Filter 135 Digitally Controlled Oscillator (DCO) 136 Circuit Divided 137 Locked Detector Circuitry 138 Phase Frequency Detector (PFD) 139 Differential Charge Pump 140 Analog to Digital Converter (ADC) 141 Wire 142 Wire 143 Second Input Lead 144 First Input Lead 145 Conductor 146 Conductor 149467.doc -29- 201112640 147 Reactor 148 Reactor 149 AND gate 150 Supply voltage selector 151 Switch 152 P channel UP current source transistor 153 Second switch 154 N channel DN current source transistor 155 Input lead / input 156 node 157 Bandgap Reference 158 Analog to Digital Converter (ADC) 159 Operation Generator 160 Capacitor 161 Feedback Control Current Source 162 Resistor 163 Operational Amplifier 164 Capacitor 165 Feedback Control Current Source 167 Input/Input Node 168 Input 169 Resistor Ladder 170 Resistor Ladder 171 Resistor Ladder 149467.doc -30- 201112640 172 resistor ladder 173 resistor ladder 174 comparator 175 comparator 176 comparator 177 comparator 178 digital logic encoder 179 three-bit register 180 three-bit register 181 three-bit register 182 P channel UP Switching transistor SU1 183 P channel UP switch transistor SU2 184 Supply voltage node 185 N channel DOWN switch transistor SD1 186 N channel DOWN switch transistor SD2 187 Ground node 188 Wire 189 Output wire 200 Line 201 Line 301 First capacitor 302 Capacitor C/2 second capacitor 303 capacitor C/4 third capacitor 304 comparator 149467.doc -31 - 201112640 305 digital continuous asymptotic logic 306 switch 307 switch 308 switch 309 XO signal cycle first part 310 XO signal cycle Two parts 311 falling edge 312 falling edge 313 falling edge 149467.doc -32-