CN115473527A - Fractional sampling phase-locked loop based on multi-stage quantization noise compensation - Google Patents

Fractional sampling phase-locked loop based on multi-stage quantization noise compensation Download PDF

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CN115473527A
CN115473527A CN202210996978.2A CN202210996978A CN115473527A CN 115473527 A CN115473527 A CN 115473527A CN 202210996978 A CN202210996978 A CN 202210996978A CN 115473527 A CN115473527 A CN 115473527A
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quantization noise
voltage
noise compensation
compensation circuit
bit
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丁瑞雪
黄林国
孙德鹏
步枫
刘术彬
朱樟明
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Xidian University
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Xidian University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop

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Abstract

The invention provides a fractional sampling phase-locked loop based on multi-level quantization noise compensation, which comprises: the two-step quantization noise compensation circuit performs 2 times of compensation on quantization noise caused by the quantization error of the DSM in the fractional sampling phase-locked loop by using a mode of N1-bit phase interpolator PI and N2-bit numerical control switch capacitor array DCCA combined compensation; the N1-bit phase interpolator compensation of the first step quantization noise compensation circuit can reduce quantization noise by 6 x (N1 + 2) dB, and the N2-bit capacitor array compensation of the second step quantization noise compensation circuit can reduce quantization noise by 6 x N2dB, so that the quantization noise and integer boundary stray of the fractional phase-locked loop are greatly reduced.

Description

Fractional sampling phase-locked loop based on multi-stage quantization noise compensation
Technical Field
The invention belongs to the field of digital-analog hybrid integrated circuit design, and particularly relates to a fractional sampling phase-locked loop based on multi-level quantization noise compensation.
Background
For a phase-locked loop system, performance indexes such as phase noise, spurious, power consumption and area are all important. The conventional phase-locked loop is a charge pump phase-locked loop, and the charge pump phase-locked loop needs to increase power consumption and the area of a chip to optimize phase noise and clock jitter, so that the conventional phase-locked loop is limited in practical use.
The phase difference of an input reference signal and a feedback signal of a phase-locked loop is converted into voltage by using a Sampling Phase Detector (SPD) in the conventional sampling phase-locked loop in a sampling and holding mode, and then the converted voltage is compared to improve in-band gain, so that the optimization of phase noise is realized.
However, in the fractional mode of the existing sampling phase-locked loop, the linearity of the sampling phase detector SPD is worse than that of the phase frequency detector of the traditional charge pump phase-locked loop, which causes the quantization noise of DSM to be aliasing to low frequency after passing through a nonlinear system, thereby causing higher integer boundary stray and in-band phase noise to appear at the output end of the phase-locked loop, and reducing the performance of the phase-locked loop system.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a fractional sampling phase-locked loop based on multi-level quantization noise compensation. The technical problem to be solved by the invention is realized by the following technical scheme:
the invention provides a fractional sampling phase-locked loop based on multi-stage quantization noise compensation, which comprises a two-step quantization noise compensation circuit,
the first step quantization noise compensation circuit is composed of an orthogonal frequency divider QDIV, a multi-stage cascade frequency divider MMDIV and an N1-bit phase interpolator PI which are sequentially connected;
the control end of the MMDIV is connected with an interpolation integral modulator DSM, the control end of the N1-bit phase interpolator PI is connected with an accumulator ACC, the input end of the accumulator ACC is connected with an adder ADD, the input end of the interpolation integral modulator DSM is connected with the positive input end of the adder ADD, and the output end of the interpolation integral modulator DSM is connected with the negative input end of the adder ADD;
the second step of quantization noise compensation circuit is composed of a sampling phase discriminator SPD, two groups of N2-bit capacitor arrays DCCA, a transconductance amplifier GM, a low pass filter LPF and a voltage controlled oscillator VCO which are sequentially connected;
the first-step quantization noise compensation circuit and the second-step quantization noise compensation circuit form a feedback loop, the input end of a sampling phase discriminator SPD in the feedback loop is connected with the output end of an N1-bit phase interpolator PI, the output end of a voltage-controlled oscillator VCO is connected with the input end of an orthogonal frequency divider QDIV, and the control end of an N2-bit capacitor array DCCA is connected with the output end of an accumulator ACC;
the first-step quantization noise compensation circuit reduces quantization noise by reducing the range of the sampling edge generated by the orthogonal frequency divider QDIV and feeds the reduced quantization noise back to the second-step quantization noise compensation circuit;
and the second step of quantization noise compensation circuit further compensates quantization noise through two groups of N2-bit capacitor arrays DCCA.
Optionally, the first-step quantization noise compensation circuit reduces quantization noise by reducing a sampling edge range generated by the quadrature frequency divider QDIV, and feeds back the reduced quantization noise to the second-step quantization noise compensation circuit, where the first-step quantization noise compensation circuit includes:
the quadrature frequency divider QDIV receives a sine wave voltage signal input by the voltage-controlled oscillator VCO, carries out quadrature frequency division on the sine wave voltage signal, generates four quadrature frequency division voltage signals FQP, FQN, FIP and FIN and inputs the four quadrature frequency division voltage signals to the multistage cascade frequency divider MMDIV;
an interpolation integral modulator DSM for receiving the fractional division ratio N and generating a variable integer division ratio N to a multi-stage cascade divider MMDIV according to the fractional division ratio N;
the multi-stage cascade frequency divider MMDIV is used for respectively carrying out N frequency division on four orthogonal frequency-halved voltage signals FQP, FQN, FIP and FIN according to the variable integer frequency division ratio N to obtain signals F1, F2, F3 and F4 which are output to the N1-bit phase interpolator PI;
the N1-bit phase interpolator PI is used for respectively carrying out phase interpolation on input signals F1, F2, F3 and F4, and obtaining two voltage signals Fdiv1 and Fdiv2 which can generate various phases and feeding the two voltage signals Fdiv1 and Fdiv2 back to the sampling phase discriminator SPD under the control of the first N1+2 digital code of an output digital code KA < N1+ N2+2> of N1+ N2+2 bits of an accumulator ACC;
the difference between Fdiv1 and Fdiv2 is one-fourth of the period of the orthogonal frequency divider QDIV, and the number of phases of the voltage signal is positively correlated with the number of averaging times of phase interpolation.
Optionally, the step two quantization noise compensation circuit further compensates the quantization noise through two sets of N2-bit capacitor arrays DCCA, and includes:
sampling phase discriminator SPD for respectively obtaining input reference signals F ref The instantaneous phase errors of the voltage signal Fdiv1 and the voltage signal Fdiv2 are respectively converted into voltage signals V1 and V2 with different amplitudes in a sampling and holding mode;
the two groups of capacitor arrays DCCA are used for performing voltage compensation on the voltage signal V1 and the voltage signal V2 under the control of a post-N2-bit digital code of an output digital code KA < N1+ N2+2> of the accumulator ACC to obtain stable direct-current voltage V3;
the transconductance amplifier GM is used for generating output current I1 and outputting the output current I1 to the low-pass filter LPF after the direct-current voltage V3 and the external fixed voltage Vdc are input so as to charge and discharge the low-pass filter LPF;
the low pass filter LPF is used for filtering the self-charged voltage and outputting a filtered voltage signal to the voltage-controlled oscillator VCO;
and the voltage-controlled oscillator VCO is used for controlling the working frequency of the VCO according to the voltage signal VC so as to output a sine wave voltage signal FVCO.
Optionally, each capacitor array in the two capacitor arrays DCCA includes four capacitors, one end of each capacitor is connected to a power ground, and the other end of each capacitor is connected to one end of each of two switches, wherein one switch has a dc voltage V3 whose other end tends to be stable, and the other end of the other switch is connected to an input voltage signal V1 or a voltage signal V2;
the voltage signals input by the two groups of capacitor arrays DCCA are different.
The invention has the beneficial effects that:
the invention provides a fractional sampling phase-locked loop based on multi-level quantization noise compensation, which comprises: the first quantization noise compensation circuit reduces quantization noise in a mode of reducing the range of a sampling edge generated by the orthogonal frequency divider (QDIV) and feeds the quantization noise back to the second quantization noise compensation circuit, and the second quantization noise compensation circuit further compensates the quantization noise through two groups of N2-bit capacitor arrays (DCCA). The invention uses the combined compensation mode of the N1-bit phase interpolator PI and the N2-bit numerical control switch capacitor array DCCA to compensate the quantization noise caused by the quantization error of the DSM in the fractional sampling phase-locked loop for 2 times; the N1-bit phase interpolator compensation of the first step quantization noise compensation circuit can reduce quantization noise by 6 x (N1 + 2) dB, and the N2-bit capacitor array compensation of the second step quantization noise compensation circuit can reduce quantization noise by 6 x N2dB, so that the quantization noise and integer boundary stray of the fractional phase-locked loop are greatly reduced.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic structural diagram of a fractional sampling phase-locked loop based on multi-level quantization noise compensation according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of input and output signals of an oscillator, a quadrature divider and a phase interpolator according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating a compensation process of a first-step quantization noise compensation circuit according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of two N2-bit capacitor arrays (DCCA) according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a second step of quantization noise compensation circuit compensation according to an embodiment of the present invention.
Fig. 6 is a schematic diagram of a compensation process of a fractional sampling phase-locked loop based on multi-level quantization noise compensation according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
As shown in fig. 1, the fractional sampling phase-locked loop based on multi-level quantization noise compensation provided by the present invention includes: a two-step quantization noise compensation circuit for performing a quantization noise compensation,
the first step quantization noise compensation circuit is composed of an orthogonal frequency divider QDIV, a multi-stage cascade frequency divider MMDIV and an N1-bit phase interpolator PI which are sequentially connected;
the control end of the multi-stage cascade frequency divider MMDIV is connected with an interpolation integral modulator DSM; the control end of the N1-bit phase interpolator PI is connected with an accumulator ACC, the input end of the accumulator ACC is connected with an adder ADD, the input end of an interpolation integral modulator DSM is connected with the positive input end of the adder ADD, and the output end of the interpolation integral modulator DSM is connected with the negative input end of the adder ADD;
the second step of quantization noise compensation circuit is composed of a sampling phase discriminator SPD, two groups of N2-bit capacitor arrays DCCA, a transconductance amplifier GM, a low pass filter LPF and a voltage controlled oscillator VCO which are sequentially connected;
the first-step quantization noise compensation circuit and the second-step quantization noise compensation circuit form a feedback loop, the input end of a sampling phase discriminator SPD in the feedback loop is connected with the output end of an N1-bit phase interpolator PI, and the output end of a voltage controlled oscillator VCO is connected with the input end of an orthogonal frequency divider QDIV; the control ends of the two groups of N2-bit capacitor arrays DCCA are connected with the output end of an accumulator ACC;
the first-step quantization noise compensation circuit reduces quantization noise by reducing the range of the sampling edge generated by the orthogonal frequency divider QDIV and feeds the reduced quantization noise back to the second-step quantization noise compensation circuit;
the first-step quantization noise compensation circuit reduces quantization noise by reducing a range of a sampling edge generated by the quadrature frequency divider QDIV and feeds back the reduced range to the second-step quantization noise compensation circuit, and the first-step quantization noise compensation circuit includes:
the quadrature frequency divider QDIV receives a sine wave voltage signal input by the voltage-controlled oscillator VCO, performs quadrature frequency division on the sine wave voltage signal to generate four quadrature frequency division voltage signals FQP, FQN, FIP and FIN which are input to the multistage cascade frequency divider MMDIV;
an interpolation integral modulator DSM for receiving the fractional division ratio N and generating a variable integer division ratio N to a multistage cascade divider MMDIV according to the fractional division ratio N;
the input end of the interpolation accumulator ACC is connected with an adder ADD, and the output end of the interpolation accumulator ACC is connected with an N1-bit phase interpolator PI and two groups of N2-bit capacitor arrays DCCA;
the adder ADD is used for performing difference calculation on the input signal fractional division ratio N and the output signal integer division ratio N of the DSM to obtain a quantization error M.
The accumulator ACC is used for accumulating the quantization error M generated by the adder ADD and outputting an N1+ N2+ 2-bit digital control code KA < N1+ N2+2>, wherein the first N1+ 2-bit digital control code is used for controlling the phase output by the N1-bit phase interpolator PI, and the second N2-bit digital control code is used for controlling the opening or closing of a switch in the N2-bit capacitor array DCCA;
it is worth mentioning that: the interpolation integral modulator DSM controls the frequency dividing ratio N of the multi-stage cascade divider MMDIV to convert to different integer values in different reference clock periods, and implements the fractional frequency dividing function by averaging different integer frequency dividing ratios N in multiple reference clock periods.
The multi-stage cascade frequency divider MMDIV is used for respectively carrying out N frequency division on four orthogonal frequency-halved voltage signals FQP, FQN, FIP and FIN according to the variable integer frequency division ratio N to obtain signals F1, F2, F3 and F4 which are output to the N1-bit phase interpolator PI;
the N1-bit phase interpolator PI is used for respectively carrying out phase interpolation on input signals F1, F2, F3 and F4 to obtain two voltage signals Fdiv1 and Fdiv2 which can generate various phases and feeding the two voltage signals back to the sampling phase discriminator SPD;
the difference between Fdiv1 and Fdiv2 is one-fourth of the period of the orthogonal frequency divider QDIV, and the number of phases of the voltage signal is positively correlated with the number of averaging times of phase interpolation.
The following are exemplary: the quadrature frequency divider QDIV performs quadrature processing on the signal output by the oscillator to obtain signals of 0 °, 90 °, 180 °, and 270 °, and then the phase interpolator PI performs phase interpolation on one of four groups of 0 °, 90 °, 180 °, 270 °, and 0 °, so that the output signal can arbitrarily output a certain phase between the pair of input signals.
Fig. 2 shows a schematic diagram of input and output signals of an oscillator, a quadrature frequency divider and a phase interpolator. The orthogonal frequency divider carries out orthogonal processing on the oscillator signals to obtain signals of 0 degrees, 90 degrees, 180 degrees and 270 degrees; the phase interpolator performs phase interpolation on the 0-degree and 90-degree signals according to the binary control code to obtain five phase signals of 0 degrees, 22.5 degrees, 45 degrees, 67.5 degrees and 90 degrees. Referring to fig. 3, the phase interpolator implementation of the quadrature dividers QDIV and N1 bit will be one vco period T VCO Conversion to T VCO /2 N1+2 And the output of PI is used as the sampling signal of SPD, and the input reference signal F is ref Sampling to realize feedback signal F div1 ，F div2 And input reference signal F ref The instantaneous phase error between the two phases is compensated, so that the quantization noise is compensated, and the quantization noise is reduced by 6 x (N1 + 2) dB.
And the second step of quantization noise compensation circuit further compensates quantization noise through two groups of N2-bit capacitor arrays DCCA.
The second step quantization noise compensation circuit further compensates the quantization noise through two groups of N2-bit capacitor arrays DCCA, and comprises the following steps:
a sampling phase discriminator SPD for respectively calculating input reference signals F ref The instantaneous phase errors of the voltage signal Fdiv1 and the voltage signal Fdiv2 are respectively converted into voltage signals V1 and V2 with different amplitudes in a sampling and holding mode;
it is worth mentioning that: due to the fact that the frequency dividing ratios N in different reference clock periods are different, constantly-changing instantaneous phase errors exist between the signals Fdiv1 and Fdiv2 and the input reference signal Fref, namely quantization errors are generated by a quantizer, and quantization noise is introduced to the output end of the MMDIV.
Two groups of capacitor arrays DCCA are used for performing voltage compensation on a voltage signal V1 and a voltage signal V2 under the control of a post-N2-bit digital code of an output digital code KA < N1+ N2+2> of an accumulator ACC to obtain a direct current voltage V3 tending to be stable;
the transconductance amplifier GM is used for generating output current I1 and outputting the output current I1 to the low pass filter LPF after the direct-current voltage V3 and the external fixed voltage Vdc are input so as to charge and discharge the low pass filter LPF;
the low pass filter LPF is used for filtering the self-charged voltage and outputting a filtered voltage signal to the voltage-controlled oscillator VCO;
and the voltage-controlled oscillator VCO is used for controlling the working frequency of the VCO according to the voltage signal VC so as to output a sine wave voltage signal FVCO.
It is worth mentioning that: the phase-locked loop circularly works according to the process of the two-step quantization noise compensation circuit through negative feedback until the phases of the output voltage FVCO of the voltage-controlled oscillator VCO and the input reference signal Fref are equal, and the phase-locked function of the phase-locked loop is finished.
Referring to fig. 4, each of the two capacitor arrays DCCA of the present invention includes four capacitors, one end of each capacitor is grounded, and one end of each capacitor is connected to one end of two switches, wherein one switch has a stable dc voltage V3 at the other end, and the other switch has an input voltage signal V1 or a voltage signal V2 at the other end;
the voltage signals input by the two groups of capacitor arrays DCCA are different.
The two capacitor arrays DCCA are numerical control switch capacitor arrays DCCA capacitors, and the compensation principle is as follows:
illustratively, take 3-bit digital control switch capacitor array DCCA as an example, wherein the capacitor C of DCCA1 A0 ：C A1 ：C A2 ：C A3 =1:1:2:4; and the capacitance C of DCCA2 B0 ：C B1 ：C B2 ：C B3 ＝1：1：2：4。
(1) In the initial sampling stage, the sampling phase discriminator transmits the two acquired voltages V1 and V2 to DCCA1 and DCCA2;
(2) In the compensation output stage, the DCCA1 and the DCCA2 open and close KA <0:3> and KB <0:3> according to the binary codes output by the DSM to obtain voltage V3;
in the initial stage, the numerical control switch capacitor arrays DCCA1 and DCCA2 are respectively charged to V 1 And V 2 (ii) a Capacitor C A0 、C A1 、C A2 、C A3 Has a voltage of V 1 (ii) a At this time, the capacitor C B0 、C B1 、C B2 、C B3 Has a voltage of V 2 。
And (3) compensation stage:
when the binary code is 000, KB<0>、KB<1>、KB<2>、KB<3>Opening; KA (KA)<0>、KA<1>、KA<2>、KA<3>And closing. Two numerical control switch capacitor arrays DCCA combined new capacitor array, voltage magnitude is V 3 ＝(0*V 1 +8*V 2 ) A voltage of/8;
when the binary code is 001, KB<0>、KB<2>、KB<3>Open, KB<1>Closing; KA (KA)<0>、KA<2>、KA<3>Closure, KA<1>And (4) opening. Two numerical control switch capacitor arrays DCCA combined new capacitor array, voltage magnitude is V 3 ＝(1*V 1 +7*V 2 ) A voltage of/8;
when the binary code is 010, KB<0>、KB<1>、KB<3>Open, KB<2>Closing; KA (KA)<0>、KA<1>、KA<3>Closure, KA<2>And (4) opening. Two numerical control switch capacitor arrays DCCA combined new capacitor array, voltage magnitude is V 3 ＝(2*V 1 +6*V 2 ) A voltage of/8;
when the binary code is 011, KB<0>、KB<3>Open, KB<1>、KB<2>Closing; KA (KA)<0>、KA<3>Closure, KA<1>、KA<2>And (4) opening. Two numerical control switch capacitor arrays DCCA combined new capacitor array, voltage magnitude is V 3 ＝(3*V 1 +5*V 2 ) A voltage of/8;
when the binary code is 111, KB<0>Open, KB<1>、KB<2>、KB<3>Closing; KA (KA)<0>Closure, KA<1>、KA<2>、KA<3>And (4) opening. Two numerical control switch capacitor arrays DCCA combined new capacitor array, voltage magnitude is V 3 ＝(7*V 1 +1*V 2 ) A voltage of/8;
referring to fig. 5, the N2 bit digitally controlled switched capacitor array DCCA adjusts the variation of the output voltage of the sampler by adjusting the charge sharing, thereby implementing the output T of the N1 bit phase interpolator PI VCO /2 N1+2 Conversion to T VCO /2 N1+N2+2 And compensating the instantaneous phase error, thereby realizing the compensation of quantization noise, and continuously reducing the quantization noise by 6 × N2dB.
Referring to fig. 6, the present invention reduces quantization noise in 2 steps by using a method of combining the quadrature frequency divider QDIV, the phase interpolator PI, and the digitally controlled switched capacitor array DCCA capacitance compensation. Firstly, a mode of an orthogonal frequency divider QDIV and a phase interpolator PI of N1-bit is adopted to reduce the range of the sampling edge generated by the frequency divider from Tvco to Tvco/2 N1+2 Thus theoretically reducing the quantization noise by 6 x (N1 + 2) dB. And secondly, further compensating the quantization noise through the N2-bit numerical control switch capacitor array, and reducing the quantization noise by 6X N2dB. By the two-step quantization compensation method, the quantization noise generated by DSM is greatly reduced, and therefore small integer boundary spurs are obtained.
The invention provides a fractional sampling phase-locked loop based on multi-level quantization noise compensation, which comprises: the first quantization noise compensation circuit reduces quantization noise in a mode of reducing the range of a sampling edge generated by the orthogonal frequency divider QDIV and feeds the reduced quantization noise back to the second quantization noise compensation circuit, and the second quantization noise compensation circuit further compensates the quantization noise through two groups of n-bit capacitor arrays DCCA. The invention uses the combined compensation mode of the phase interpolator PI of N1-bit and the numerical control switch capacitor array DCCA of N2-bit to compensate the quantization noise caused by the quantization error of DSM in the fractional sampling phase-locked loop for 2 times; the N1-bit phase interpolator compensation of the first step quantization noise compensation circuit can reduce quantization noise by 6 x (N1 + 2) dB, and the N2-bit capacitor array compensation of the second step quantization noise compensation circuit can reduce quantization noise by 6 x N2dB, so that the quantization noise and integer boundary stray of the fractional phase-locked loop are greatly reduced.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
While the present application has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, numerous simple deductions or substitutions may be made without departing from the spirit of the invention, which shall be deemed to belong to the scope of the invention.

Claims (4)

1. A fractional sampling phase-locked loop based on multi-level quantization noise compensation, comprising: a two-step quantization noise compensation circuit for performing a quantization noise compensation,
the first step quantization noise compensation circuit is composed of an orthogonal frequency divider (QDIV), a multi-stage cascade frequency divider (MMDIV) and an N1-bit Phase Interpolator (PI) which are sequentially connected;
the control end of the multi-stage cascade frequency divider (MMDIV) is connected with an interpolation integral modulator (DSM), the control end of the N1-bit Phase Interpolator (PI) is connected with an Accumulator (ACC), the input end of the Accumulator (ACC) is connected with an Adder (ADD), the input end of the interpolation integral modulator (DSM) is connected with the positive input end of the Adder (ADD), and the output end of the interpolation integral modulator (DSM) is connected with the negative input end of the Adder (ADD);
the second step of quantization noise compensation circuit is composed of a Sampling Phase Discriminator (SPD), two groups of N2-bit capacitor arrays (DCCA), a transconductance amplifier (GM), a Low Pass Filter (LPF) and a Voltage Controlled Oscillator (VCO) which are sequentially connected;
the first-step quantization noise compensation circuit and the second-step quantization noise compensation circuit form a feedback loop, the input end of the Sampling Phase Discriminator (SPD) in the feedback loop is connected with the output end of the N1-bit Phase Interpolator (PI), the output end of the voltage-controlled oscillator (VCO) is connected with the input end of the quadrature frequency divider (QDIV), and the control end of the N2-bit capacitor array (DCCA) is connected with the output end of the Accumulator (ACC);
the first-step quantization noise compensation circuit reduces quantization noise by reducing a sampling edge range generated by the quadrature frequency divider (QDIV) and feeds back the reduced quantization noise to the second-step quantization noise compensation circuit;
and the second-step quantization noise compensation circuit further compensates quantization noise through two groups of N2-bit capacitor arrays (DCCA).
2. The fractional-sampling phase-locked loop based on multi-stage quantization noise compensation of claim 1, wherein the first-stage quantization noise compensation circuit reduces quantization noise by reducing a range of sampling edges generated by the quadrature frequency divider (QDIV), and the feedback to the second-stage quantization noise compensation circuit comprises:
a quadrature frequency divider (QDIV) which receives a sine wave voltage signal input by a Voltage Controlled Oscillator (VCO), performs quadrature frequency division on the sine wave voltage signal, generates four quadrature frequency division voltage signals FQP, FQN, FIP and FIN and inputs the four quadrature frequency division voltage signals to a multi-stage cascade frequency divider (MMDIV);
-said interpolating integral modulator (DSM) for receiving a fractional division ratio N and generating a varying integer division ratio N to a multistage cascaded divider (MMDIV) in dependence on the fractional division ratio N;
the multi-stage cascade frequency divider (MMDIV) is used for respectively carrying out N frequency division on four orthogonal frequency-halved voltage signals FQP, FQN, FIP and FIN according to the variable integer frequency division ratio N to obtain signals F1, F2, F3 and F4 which are output to the N1-bit Phase Interpolator (PI);
the N1-bit Phase Interpolator (PI) is used for respectively carrying out phase interpolation on input signals F1, F2, F3 and F4, and obtaining two voltage signals Fdiv1 and Fdiv2 which can generate various phases and feeding the voltage signals Fdiv1 and Fdiv2 back to the Sampling Phase Discriminator (SPD) under the control of the first N1+2 digital codes of the output digital codes KA < N1+ N2+2> of N1+ N2+2 bits of an Accumulator (ACC);
the difference between Fdiv1 and Fdiv2 is one quarter of the period of the orthogonal frequency divider (QDIV), and the number of phases of the voltage signal is positively correlated with the number of averaging times of phase interpolation.
3. The fractional-sampling pll based on multi-stage quantization noise compensation of claim 2, wherein the second step quantization noise compensation circuit further compensates quantization noise through two N2-bit capacitor arrays (DCCA) comprising:
the Sampling Phase Discriminator (SPD) is used for respectively calculating the input reference signals F ref The instantaneous phase errors of the voltage signal Fdiv1 and the voltage signal Fdiv2 are respectively converted into voltage signals V1 and V2 with different amplitudes in a sampling and holding mode;
the two groups of capacitor arrays (DCCA) are used for carrying out voltage compensation on the voltage signal V1 and the voltage signal V2 under the control of a post-N2-bit digital code of an output digital code KA < N1+ N2+2> of the Accumulator (ACC) to obtain stable direct current voltage V3;
the transconductance amplifier (GM) is used for generating an output current I1 and outputting the output current I1 to the Low Pass Filter (LPF) after the direct-current voltage V3 and the external fixed voltage Vdc are input so as to charge and discharge the Low Pass Filter (LPF);
the low-pass filter (LPF) is used for filtering the self-charged voltage and outputting a filtered voltage signal to the voltage-controlled oscillator (VCO);
and the Voltage Controlled Oscillator (VCO) is used for controlling the working frequency of the VCO according to the voltage signal VC so as to output a sine wave voltage signal FVCO.
4. The fractional sampling pll according to claim 3, wherein each of the two capacitor arrays (DCCA) comprises four capacitors, one end of each capacitor is connected to ground, and the other end of each capacitor is connected to one end of two switches, wherein the other end of one switch is biased to a stable dc voltage V3, and the other end of the other switch is connected to an input voltage signal V1 or a voltage signal V2;
wherein, the voltage signals input by the two groups of capacitor arrays (DCCA) are different.
CN202210996978.2A 2022-08-18 2022-08-18 Fractional sampling phase-locked loop based on multi-stage quantization noise compensation Pending CN115473527A (en)

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