TW201110549A - Input/output circuit and integrated circuit apparatus including the same - Google Patents
Input/output circuit and integrated circuit apparatus including the same Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0278—Arrangements for impedance matching
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- General Engineering & Computer Science (AREA)
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Abstract
Description
201110549 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種積體電路（ic)裝置，且更特定言之， ^ 係關於一種用於介接具有不同操作電壓之裝置的混合電壓 輸入/輸出（I/O)電路’及一種包括該混合電壓輸入/輸出 ' (I/O)電路之1C裝置。 本申請案根據35 U.S.C. § 119之規定主張2009年4月22日 向韓國智慧財產局申請之韓國專利申請案第10-2009- 〇 0034870號的優先權及權利，該案之全部内容以引用的方 式併入本文中。 【先前技術】 在互補金屬氧化物半導體（CM〇s)技術中，按比例減小 供電電壓以減少功率消耗，且亦按比例減小電晶體之尺寸 以改良電路效能及面積效率。微電子系統中之一些半導體 晶片係使用不同CMOS技術來實施且不可能使用相同電 〇 壓，且因此，需要一混合電壓I/O介面。舉例而言，動態 隨機存取記憶體（DRAM)晶片之讀取電壓對於8〇奈米之 DRAM半間距而言為2.5 V，而對於6G奈米之⑽鹰半間距 - 而言為2.0 V。 當在混合電Μ系統中使用f知非混合介接方法時，可能 發生非吾人所樂見之漏電流之產生、間極氧化物之可靠性 之減小及熱載子注入。 在用於接收外部信號之接收模;式中，1/〇墊之電麼可能 高於電源供應電麼，且因此，可能自該"〇墊通過_上拉； 147730.doc 201110549 型金屬氧化物半導體（PM0S)電晶體至—電源供應器形成 一非吾人所樂見之漏電流路徑。已研究了用於防止上拉 PMOS電晶體之漏電流的方法。然而，此等習知方法需要 以複雜方式連接之額外墊或電晶體。此外，該等習知方法 中之一些方法增加1/0墊負載及上拉閘極負載，此可減小 I/O介接速度。 因為在閘極氧化物處形成一過高電場，所以閘極氧化物 之可靠性減小。雖然雙氧化物法（dual_oxide process)可解 決該可靠性問題，但具有厚閘極氧化物之電晶體可減小 I/O介接速度。已引入閘極追蹤來提供上 極氧化物可靠性同時不減小1/0介接速度。通常使用中= 連接額外N型金屬氧化物半導體（NM〇s)電晶體之方法來避 免與下拉電晶體及接收器有關的可靠性問題，該等額外N 型NMOS電晶體之閘極連接至電源供應器 ，在低電 源供應電壓環境或低電壓操作環境中，日益難以限制該等 額外NM〇S電晶體令之接收信號的擺動位準（swing level)。 當波極與源極之間存在大電壓差時，發生熱載子注入。 堆疊式NMOS電晶體及阻隔電晶體（blGeking加以叫（其 中之每一者與一下拉電晶體串聯連接)防止至該下拉電晶 體之熱載子注人H當將接收模式轉換成傳輸模式 時，此等電晶體可能經受熱載子注入。因此，為了減少在 接收模式中累積於1/0塾處之過高電壓或高電位電荷，需 要一熱載子防護電路。 為了解決可能在混合介面S統中發生的上文所描述之擔 147730.doc 201110549 憂問題且為了支援低操作電壓，需要新的混合電壓介接。 【發明内容】 本發明之發明概念之例示性實施例提供一種甚至在高電 壓或低電壓操作條件下亦傳輸輸入資料之輸入/輸出（I/O) 電路。 本發明之發明概念之例示性實施例亦提供 少低電壓操作條件下之漏電流之〗/〇電路 Ο ❹ 本發明之發明概念之例示性實施例亦提供一種甚至在伯 電壓操作條件下亦減少一電晶體之一閘極氧化物的可靠招 之減小的I/O電路。 本發明之發明概念之例示性實施例亦提供一種防止低電 左操作條件下之熱載子注入的I/O電路。 根據例不性貫施例，一種輸入/輸出電路包括一〗/〇節 點’其連接i包含-上拉電晶體及一下拉電晶體之一上拉 與下拉電路’該I/O節.點經組態以自一1/0墊接收一資料輸 入且將一資料輸出發送至兮τ/η轨. 山设^:主；I 1/0墊，一位準移位器，其經 組態以提供包括一供雷曾蔽n 併電電壓及一尚電壓之各種電壓，該高 電壓處於高於該供電電壓之—電壓；及—信號控制電路， 其經組態以控制施加至該上拉與下拉電路之—電壓位準。 在一資料輸入模式期間，在兮 任I/O郎點處自該I/O塾接收資 料並在該高電壓下對該上杈雪曰 上报1：日日體％加偏壓以斷開該上拉201110549 VI. Description of the Invention: [Technical Field] The present invention relates to an integrated circuit (IC) device, and more particularly to a hybrid voltage input for interfacing devices having different operating voltages /output (I/O) circuit 'and a 1C device including the mixed voltage input/output' (I/O) circuit. The present application claims the priority and the rights of the Korean Patent Application No. 10-2009- 0034870, filed on Apr. 22, 2009, to the Korean Intellectual Property Office, the entire contents of which are incorporated by reference. Incorporated herein. [Prior Art] In the complementary metal oxide semiconductor (CM 〇s) technology, the supply voltage is proportionally reduced to reduce power consumption, and the size of the transistor is also scaled down to improve circuit efficiency and area efficiency. Some semiconductor wafers in microelectronic systems are implemented using different CMOS technologies and it is not possible to use the same electrical voltage and, therefore, a mixed voltage I/O interface is required. For example, the read voltage of a dynamic random access memory (DRAM) chip is 2.5 V for a DRAM half pitch of 8 nanometers, and 2.0 V for a 6G nanometer (10) eagle half pitch. When a non-mixed dielectric method is used in a hybrid electric system, generation of leakage current, reduction in reliability of the interpole oxide, and hot carrier injection may occur. In the receiving mode for receiving an external signal; in the formula, the power of the 1/〇 pad may be higher than the power supply, and therefore, may be pulled from the "〇 pad; 147730.doc 201110549 type metal oxide The semiconductor (PM0S) transistor to the power supply forms a leakage current path that is not forgotten. A method for preventing leakage current of a pull-up PMOS transistor has been studied. However, such conventional methods require additional pads or transistors that are connected in a complicated manner. In addition, some of these conventional methods increase the I/O pad load and pull up the gate load, which reduces the I/O interface speed. Since an excessive electric field is formed at the gate oxide, the reliability of the gate oxide is reduced. Although the dual_oxide process solves this reliability problem, a transistor with a thick gate oxide can reduce the I/O interface speed. Gate tracking has been introduced to provide upper oxide reliability without reducing the 1/0 interface speed. The use of additional N-type metal oxide semiconductor (NM〇s) transistors is often used to avoid reliability issues associated with pull-down transistors and receivers. The gates of these additional N-type NMOS transistors are connected to the power supply. The supply, in a low power supply voltage environment or a low voltage operating environment, is increasingly difficult to limit the swing level of the received signals by the additional NM〇S transistors. Hot carrier injection occurs when there is a large voltage difference between the wave and the source. Stacked NMOS transistors and blocking transistors (blGeking is called (each of which is connected in series with a pull-down transistor) to prevent hot carriers from being pulled into the pull-down transistor. When converting the receive mode to the transfer mode, These transistors may be subjected to hot carrier injection. Therefore, in order to reduce the excessive voltage or high potential charge accumulated in the receiving mode at 1/0 ,, a hot carrier protection circuit is required. To solve the possible problem in the hybrid interface S The problem described above is 147,730.doc 201110549 and in order to support low operating voltages, a new hybrid voltage interface is required. [SUMMARY OF THE INVENTION An exemplary embodiment of the inventive concept provides an even high Input/output (I/O) circuits for input data are also transmitted under voltage or low voltage operating conditions. Exemplary embodiments of the inventive concept of the present invention also provide leakage currents under low voltage operating conditions. An exemplary embodiment of the inventive concept of the present invention also provides a reliable method for reducing a gate oxide of a transistor even under a primary voltage operating condition. Small I/O Circuits Illustrative embodiments of the inventive concept also provide an I/O circuit that prevents hot carrier injection under low power left operating conditions. According to an exemplary embodiment, an input/output The circuit includes a 〇/〇 node' whose connection i includes a pull-up transistor and a pull-up and pull-down circuit of the pull-up transistor. The I/O section is configured to receive a data from a 1/0 pad. Input and send a data output to 兮τ/η rail. Mountain set ^: main; I 1 / 0 pad, a quasi-shifter, configured to provide a lightning supply and electrical voltage and a voltage of a voltage that is higher than the voltage of the supply voltage; and a signal control circuit configured to control the voltage level applied to the pull-up and pull-down circuits. During the mode, the data is received from the I/O 兮 at the I/O 朗点 and the upper sleigh is reported at the high voltage. 1: The Japanese body is biased to disconnect the pull-up.
電晶體，且在一資料輪4 M 将出模式期間，在該I/O節點處輸出 資料’且當該輸出資料為低時， r 啟動s亥下拉電晶體以將該 I/O綠點下拉至接地，日告兮认 ^讀出資料為高時，啟動該上 147730.doc 201110549 拉電晶體。 資料輸出模式期間’該信號控制電路可經組態以將 該供電電欠壓施加於該上拉電晶體之基板處。 資料輸出模式期間，該信號控制電路可經組態以將 在該供電雷壓_ 低位準之間擺動的閘極電壓施加至該上 拉電晶體，以在兮·於山^ ^輸出負料電壓為高時啟動該上拉電晶 體。 =貝料輸人模式期間，該信號控制電路可經組態以將 该南電虔施加至該上拉電晶體之該基板。 一=號控制電路可經組態以將等於或大於該供電電麼之 曰電壓施加至該下拉電晶體之閘極。a transistor, and during a data wheel 4 M output mode, at the I/O node output data 'and when the output data is low, r starts the s-down transistor to drop the I/O green dot To grounding, the day tells you that the read data is high, start the 147730.doc 201110549 pull-up crystal. During the data output mode, the signal control circuit can be configured to apply the supply undervoltage to the substrate of the pull-up transistor. During the data output mode, the signal control circuit can be configured to apply a gate voltage that swings between the supply voltage _low level to the pull-up transistor to output a negative voltage at 兮·山山The pull-up transistor is activated when it is high. During the beaker input mode, the signal control circuit can be configured to apply the south electric power to the substrate of the pull-up transistor. A = control circuit can be configured to apply a voltage equal to or greater than the supply voltage to the gate of the pull-down transistor.
該信號控制電路可、，I 資料徐屮^ I 該資料輸人模式㈣至該 貝科輸出杈式時施加一 仞進石2 遲以使在該1/0節點處自一高 位準至一低位準的—電壓擺動延遲。 根據一例示性實施例，一 且右、查拉狄 U電路包括一傳輸器，盆 八有連接於—第一電源供應器與— 、 上把雷曰麯U <間的至少一 拉包曰曰體及連接於該1/0節點與—第二電塵節 至少一下拉電晶體，以經由 ，間的 -外部器件；-接收写m 輸出貝枓傳輸至 料；及一時庠/你n 由該"〇節點接收輸入資 ㈣ 制器’其經組態以在-傳輸桓★φ 選擇性地將該第一電;% _ 得輸镇式中 $ $源供應裔之―電壓施加 拉電晶體之一主體（bulk)筋赴 〇 ^ 主忒至 >—上 該主體節點以使其具有 ：準控制器控制 一電壓。 丨馬态之该電壓的 147730.doc 201110549 聯連接之一第一下拉電晶 下拉電晶體連接至該第二 該至少一下拉電晶體可包括串 體及一第二下拉電晶體，該第二 電壓節點。 該至少一上拉電晶體可句 J包括串聯連接之一第一上拉雷曰 體；5 —筮- 矛工？51黾日日 骽及第一上拉電晶體，該第_The signal control circuit can, I data Xu Wei ^ I the data input mode (4) to the Beca output 杈 type when applying a 石 stone 2 late so that at the 1/0 node from a high level to a low level Quasi-voltage swing delay. According to an exemplary embodiment, the one-and-right, Charard U circuit includes a transmitter, and the basin eight has at least one pull package connected between the first power supply and the upper thunder bend U < The body is connected to the 1/0 node and the second electric dust node at least pulls the transistor at a time to pass the inter-external device; the receiving write m output is transmitted to the material; and the time is 庠/你n The "〇 node receives the input resource (4) controller's configured to selectively transfer the first power in the -桓桓φ; _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ One of the bulks of the crystal goes to the main node to the main node so that it has a quasi-controller to control a voltage. 147730.doc 201110549 of the voltage state of the humming state, the first pull-down transistor pull-down transistor is connected to the second, the at least one pull-down transistor may include a string body and a second pull-down transistor, the second Voltage node. The at least one pull-up transistor can include one of the first series of pull-up scorpions connected in series; 5 - 筮 - spearman? 51黾日骽 and the first pull-up transistor, the first _
節點。 χ弟一上拉電晶體耦接至該I/O β亥時序/位準控制器可經 m t U在該資料輸入模式切換node. The younger brother is connected to the I/O. The timing/level controller can be switched in the data input mode via m t U.
至该育料輸出模式時施加— _ 延遲’以使在該I/O節點處自 间位準至-低位準的—電麗擺動延遲。 該I/O電路可進_步句枯— 括—電晶體，其耦接於該至少一 上拉電晶體之該主體節點與-開極之間；及一個二極體， 其相接於該電晶體之一閉極與一第二電壓節點之間。該二 極體可經組態以防止該電晶體之該閘極與源極之間的—電 堅差曰加且防止該電晶體之—閑極電壓高於該第—電源 供應器之該電壓。 該至少一下拉電晶體可包括串聯連接之一第一下拉電晶 體及第一下拉電晶體，且該電晶體可耦接於該第一上拉 電晶體之該主體節點與該閘極之間。 一接收開關電晶體可連接於該I/C)節點與該接收器之 間，該接收開關電晶體經組態以控制該接收器處之一電壓 擺動。 該時序/位準控制器可進一步包括一上拉開關電晶體， 該上拉開關電晶體連接至該第一上拉電晶體之該閘極及該 第二上拉電晶體之該閘極。 147730.doc 201110549 該時序/位準控制器可進一步包括一第一位準移位器， 該第-位準移位器轉換藉由對一輸出啟用信號與一延遲之 輸出啟用信號執行一邏輯運算而獲得的一信號之一位準， 該延遲之輸出啟用信號係由於使該輪出啟用信號延遲而產 〇第位準移位器將一經位準移位之信號輸出至該 主體節點。 該至少-下拉電晶體可包括串聯連接之—第—下拉電晶 體及-。第二下拉電晶體，且該1/〇電路可進一步包括一前 置驅動器，該前詈 徐出延遲之輸出啟用信號及該 输出貝料而產生—上赵 拉k號及一下拉信號，且分別將該上 拉4號及该下拉信號輸出至一 伐即點及一下拉節點，該 上拉即點對應於該至少— 徂冤日日體之一閘極，該下拉節 點對應於該第二下拉電晶體之一閘極。 該第一位準移位器可經組態以將該第二電屢節點… 壓位準轉換成該第一電 电 供應益之該電壓位準，且將該第The _delay is applied to the feed output mode to delay the oscillating motion from the inter-level to the low-level at the I/O node. The I/O circuit can be coupled to the transistor and coupled between the body node and the open electrode of the at least one pull-up transistor; and a diode connected to the One of the transistors is closed between the pole and a second voltage node. The diode can be configured to prevent an electrical differential between the gate and the source of the transistor and prevent the voltage of the transistor from being higher than the voltage of the first power supply . The at least one pull-down transistor may include a first pull-down transistor and a first pull-down transistor connected in series, and the transistor may be coupled to the body node of the first pull-up transistor and the gate between. A receive switch transistor can be coupled between the I/C) node and the receiver, the receive switch transistor configured to control a voltage swing at the receiver. The timing/level controller can further include a pull-up switch transistor coupled to the gate of the first pull-up transistor and the gate of the second pull-up transistor. 147730.doc 201110549 The timing/level controller can further include a first level shifter that performs a logic operation by an output enable signal and a delayed output enable signal. And obtaining one of the signals, the delayed output enable signal is outputted to the body node by the first level shifter due to delaying the turn-on enable signal. The at least - pull-down transistor can include - a pull-down transistor and - connected in series. a second pull-down transistor, and the 1/〇 circuit may further include a pre-driver, the output enable signal of the front-end delay delay and the output of the output-------------------------- Outputting the pull-up No. 4 and the pull-down signal to a point-and-point pull-down node, the pull-up point corresponding to the gate of the at least one day, the pull-down node corresponding to the second pull-down One of the gates of the transistor. The first level shifter can be configured to convert the second electrical node to a voltage level of the first electrical supply, and the
一電源供應器之一電I< I +轉換成—高電 — 準，且該高電壓可高於該 乐 4 /原供應窃之一電遷。 該第二電壓節點可處於一接地電塵。 該I/O電路可進一步句杠 n . 括連接於該1 / 〇節點與該接收器之 間的一接收開關電晶體， 叹。°之 丑β接收開關電晶體經 制該接收器處之一電壓擺動。 、.、心以控 該I/O電路可進一步句扛 傳輸控制器，該傳輪 連接於該前置驅動器與該至少—上拉電晶體及h 拉電晶體之間’以控制經由該1/0節點至：:：至少-下 即砧至该外部器件之輸 147730.doc •10- 201110549 出資料傳輪。 置=:::接於該至少，電晶雜與該前 爻間的—上拉開關。 門:=/位準控制器可包括-開關控制位準移位器，談 *工制位準移位器經組態以控制該上 該⑽節點將該輪出資料傳輸至該外部器件d用於經由 Ο Ο :控制位準移位器可經組態以將該第 π轉換成大於該第-電源供應器之該電二 =電，位準，且將該第二_點之-：:： 換成该第—電源供應II之n位準。 該上拉開關可為一傳輸閘。 該時序/位準控制器可包括一傳輸閉位 器經組態以控制該傳輸閘以用於經由= 即點將該輸“料傳輸至該外部器件。 ，傳輪閘位準移位器可經組態以將該第二電 第电壓:準轉換成該第—電源供應器之該電壓位準，且將該 :一毛源供應器之-電壓位準轉換成一高電壓之一電墨位 準’且該高㈣可高於該第-電源供應器之-電壓。 根據-例示性實施例，一種記憶體系統包括— 制器’其具有-記憶體介面；及一記憶體器件，直且有： 記憶體及與該記憶體介面通信之一輸入/輪出電路。該輸 =輸出電路包括一傳輪器’其包含連接於—第一電源供 广、-I/O即點之間的至少—上拉電晶體及連接於該㈤ 即點與-第二電壓節點之間的至少一下拉電晶體，以經由 147730.doc 201110549 該I/O節點將輪出資料傳輸至該記憶體介面；―接收器， 其經由該I/O節點自該記憶體介面接收輸入資料；及一時 序/位準控制器，其經組態以在一傳輸模式中選擇性地將 該第-電源供應器之-電壓施加至該至少一上拉電晶體之 -主體節,點’且該時序/位準控制器控制該主體節點以使 其具有高於該第一電源供應器之該電壓的一電壓。 可將該輸出資料傳輸至該記憶體器件中之一晶片控制 器，且可自該記憶體器件中之該晶片控制器接收該輸入資 料。 根據一例示性實施例，計算系統包括一中央處理單元； 及:記憶體系統，其經由一系統匯流排與該中央處理單元 通信。該記憶體系統包括一記憶體控制器，其具有一記憶 體介面；及一記憶體器株，欲g 士 /、八有一圮憶體及與該記憶體 /1面通j5之 輸入/截}'屮*政 土人 叛出電路。該輸入/輸出電路包括一傳 輸益，其包含連接於一第一電源供應器與一1/0節點之間 的至少-上拉電晶體及連接於該1/0節點與一第二電屡節 點之間的至少一下把雷曰躺 電日日體，以經由該I/O節點將輸出資 料傳輸至該系統匯流排；一技 。 、 ^ 饼接收态’其經由該I/O節點自 一 頁料，及一時序/位準控制器，其 經組態以在一傳輸模式中選擇 ’、 Τ、伴性地將6亥弟—電源供應器之 :電壓施加至該至少—上拉電晶體之一主體節點，且該時 序位準控制器控制該主體節點以使其具有高於該第1 源供應杰之遠電壓的_電壓。 根據一例示性實施例，一種操作具有-1/0墊之—1/0緩 147730.doc •12- 201110549 衝器的方法包括在用於將輸出資料傳輸至一外部器件之— 傳輪模式巾，回應於具有—邏輯高錢之第-輪出資料而 選擇性地接通耦接至該1/0墊之一上拉電晶體，或回應於 具有-邏輯低信號之第二輸出資料而選擇性地接通耦接至 «亥I/O墊之一下拉電晶體；在一第一電源供應電壓之電壓 下驅動該UO墊以用於該第一輸出資料傳輸；在—第二電 壓節點之-電壓下驅動該1/0塾以用於該第二輸出資料傳 Ο 輸’及選擇性地將該第一電源供應電壓或高於該第一電源 供應器之該電壓的-電射之—者施加至該上拉電晶體二 一主體節點。 η亥方法可進一步包括在用於自一外部器件接收輸入資料 商體，且將經由該1/0墊所接收之輸入資料提供至一接 之-接收模式中，斷開該傳輸器之該上拉電晶體及該下拉 電晶… 收器 祀據例示性貫施例，一種防止一 緩衝器之一 I/O塾 〇 纟之熱載子注入的方法，該方法係當於一接收模式中接收 到-外部高電虔信號且在自該接收模式轉變至一傳輸模式 之一模式轉t之後⑨該傳輸模4中將4於一邏輯低位準之 、L 5虎輸出至-外部&件時進行，該方法包括當該接收模 式轉換成該傳輪拉式時，在自啟動一輸出啟用信號開始直 /成通過下拉電晶體之一下拉路徑為止的一延遲時間 1 ’’’二由上拉電晶體降低該I/O墊處之一電麼，以用 於邏輯低位準輸出信號傳輸。 【實施方式】 147730.doc •13- 201110549 藉由參看附加圖式詳細地描述例示性實施例，本發明之 發明概念之以下及其他特徵及優點將變得更加顯而易見。 在下文中’將參看展示例示性實施例之隨附圖式更完全 地描述本發明之發明概念。然而，本發明之發明概念可以 許多不同形式體現，且不應被解釋為限於本文中所闡述之 例示性實施例。在該等圖式中，相同數字始終指代相同元 件。 應理解’當一元件被稱作「連接至」或「耦接至」另一 元件呀，其可直接連接至或耦接至另一元件，或可存在介 0 入元件。 亦應理解，雖然本文中可能使用術語「第—」'「第二」 等來描述各種元件，但此等元件不應受此等術語限制。此 等術浯僅用以區別一個元件與另一元件。舉例而言，可將 第一信號稱為第二信號，且類似地，可將第二信號稱為第 一信號’而不偏離本發明之教示。 圖1為根據本發明之發明概念之一例示性實施例的輸入/ 輸出（1/〇)電路100的電路圖。I/O電路100包括傳輸器u〇、 ❹ 接收器120、前置驅動器130、時序/位準控制器140及傳輸 控制器150。 傳輸器110為用於經由一 1/〇節點N〇及一 1/〇墊將輸出資 料DOUT傳輸至一外部器件之電路，且包括上拉電晶體 MP〇、第—下拉電晶體ΜΝ0及第二下拉電晶體MN1。上拉 電晶體ΜΡ0連接於第一電源供應器VDD與該ι/〇節點之 間。上拉電晶體MP〇之—閘極（亦即，上拉節點pu)經由一 147730.doc -14- 201110549 上拉開關電晶體MN2與前置驅動器130之一輸出連接。第 一下拉電晶體ΜΝ0與第二下拉電晶體MN1串聯連接於該 I/O節點NO與一第二電壓節點GND之間。第一下拉電晶體 ΜΝ0之一閘極連接至一中間電壓VDDM，且第二下拉電晶 體MN1之一閘極（亦即，下拉節點PD)與前置驅動器130之 另一輸出連接。 接收器120與一接收器輸入節點IR連接，且經由I/O墊及 I/O節點NO接收資料輸入。接收器輸入節點IR連接於第一 下拉電晶體ΜΝ0與第二下拉電晶體MN1之間。 前置驅動器130基於一延遲之輸出啟用信號OED及輸出 資料DOUT而產生一上拉信號（在下文中，稱作第一輸出資 料）及一下拉信號（在下文中，稱作第二輸出資料），且分別 將其輸出至上拉節點PU及下拉節點PD。在用於輸出該輸 出資料DOUT之一傳輸模式中，第一輸出資料與第二輸出 資料具有相同邏輯位準，以使得上拉電晶體ΜΡ0與第二下 拉電晶體MN1之間僅一者接通。在用於接收輸入資料之一 接收模式中，第一輸出資料及第二輸出資料具有使得能夠 將上拉電晶體ΜΡ0與第二下拉電晶體MN1兩者斷開之邏輯 位準。 前置驅動器130包括反及（NAND)閘ND1、反或（NOR)閘 NOR1及反相器INV1。NAND閘ND1對輸出資料DOUT與延 遲之輸出啟用信號0ED執行一 NAND運算，以輸出第一輸 出資料。NOR閘N0R1對延遲之輸出啟用信號0ED之一反 相信號及輸出資料DOUT執行一 NOR運算，以輸出第二輸 147730.doc -15- 201110549 出資料。 時序/位準控制器140包括延遲單元141、NOR閘NORO、 第一位準移位器LC1、第二位準移位器LC2及反相器 INV2。當接收模式轉換成傳輸模式時，時序/位準控制器 140控制上拉電晶體ΜΡ0之一主體節點PB(或基板）以使其 在一預定時段（例如，延遲單元14 1之延遲時間）内具有第一 電源供應器VDD之電壓，以便將在接收模式中累積於I/O 節點NO處之高電位電荷傳輸至第一電源供應器VDD，且 接著經由I/O節點NO將輸出資料DOUT傳輸至一外部器 件。本文中將在下文中更詳細地描述此操作。 延遲單元141使輸出啟用信號OE延遲達一預定延遲時間 (例如，第一延遲時間），且輸出延遲之輸出啟用信號 OED。NOR閘NORO對輸出啟用信號OE與延遲之輸出啟用 信號OED執行一NOR運算，且輸出一信號，該信號具有大 於輸入信號OE及OED之脈寬的一脈寬。將NOR閘NORO之 輸出信號輸入至第一位準移位器LC 1，且經由反相器INV2 將其輸入至第二位準移位器LC2。亦將延遲之輸出啟用信 號OED輸入至前置驅動器130。 如圖12B中所說明，第二位準移位器LC2分別將第二電 壓節點GND之電壓位準（在下文中，稱作接地位準）及第一 電源供應器VDD之電壓位準轉換成第一電源供應器VDD之 電壓位準及中間電壓VDDM之電壓位準。中間電壓VDDM 之電壓位準等於或高於第一電源供應器VDD之電壓位準。 舉例而言，中間電壓VDDM可為「第一電源供應器VDD之 147730.doc -16- 201110549 電壓+NMOS電晶體之臨限電壓Vthn」，亦即， 「VDD+Vthn」。 如圖12A中所說明’第一位準移位器LC1分別將接地位 • 準及第一電源供應器VDD之電壓位準轉換成第一電源供應 器VDD之電壓位準及高電壓vdDH之位準。高電壓VDDH 高於第一電源供應器VDD之電壓。舉例而言，高電壓 VDDH可為第一電源供應器VDD之電壓的兩倍，或類似於 0 由1/0電路100介接之外部器件的一高電壓。 同於第一電源供應器VDD之電壓的中間電壓vddm及高 電壓VDDH可由一内部電壓產生器（圖中未展示）來產生。 d内部電壓產生器可包括—電荷栗。在接收模式中，使用 高電麼VDDH來上拉主體節點pB及上拉冑點⑼，藉此防止 自I/O節點NO通過上拉電晶體Mp〇至主體節點形成一非 口人所樂見之電流路徑。使用中間電壓VDDM來上拉第一 下拉電晶體ΜΝ0及上拉開關電晶體顧2之閑極，藉此增加 〇 帛收11輪人節點1R之擺動位準。因此，甚至在-低電壓操 作％ i兄中亦可可靠地確保接收資料mN之電壓，且因此， 可減少接收資料DIN中之錯誤的發生。換言之，使用中間 电壓VDDM來控制第—下拉電晶體MN〇及上拉開關電晶體 • MN2之閘極，以增加受限之擺動位準。 傳輪控制器150包括與下拉節點PD連接之反相器INV0、 PMOS電晶體MP1，及上拉開關電晶體應2。上拉節點印 I由PAios電晶體MPi與主體節點PB連接。pM〇s電晶體 MP1之〜閘極連接至反相器丨請之―輸出，且回應於一下 147730.doc -17. 201110549 拉信號之一反相信號PDB而操作。 上拉開關電晶體MN2之一閘極（亦即，節點G2)係受控於 一第二經位準移位之輸出啟用信號，該第二經位準移位之 輸出啟用信號係藉由使用第二位準移位器LC2對反相器 INV2之輸出信號進行位準移位而獲得。如上文所描述，第 二位準移位器LC2係用於控制上拉開關電晶體MN2，且因 此被稱作開關控制位準移位器。 上拉電晶體ΜΡ0及PMOS電晶體MP1之基板（亦即，主體 節點PB)係受控於一第一經位準移位之輸出啟用信號，該 第一經位準移位之輸出啟用信號係藉由使用第一位準移位 器LC 1對NOR閘NORO之輸出信號進行位準移位而獲得。如 上文所描述，第一位準移位器LC 1係用於控制主體節點 PB，且因此被稱作主體節點位準移位器。 PMOS電晶體MP1係受控於反相器INV0之輸出信號 PDB，以使得上拉節點PU在傳輸模式中完全自第二電壓節 點GND之電壓擺動至第一電源供應器VDD之電壓，且在接 收模式中維持在高電壓VDDH之電壓位準。在接收模式 中，將處於一邏輯低位準之第二輸出資料施加至下拉節點 PD。因此，信號PDB處於一邏輯高位準（或第一電源供應 器VDD之電壓位準）。此時，主體節點PB具有高電壓 VDDH，且因此，PMOS電晶體MP1接通，且上拉節點PU 亦維持在高電壓VDDH。因此，防止了在接收模式中形成 一漏電流路徑。在傳輸模式中，PMOS電晶體MP 1僅在下 拉節點PD處於邏輯高位準時才接通，從而使得上拉節點 147730.doc -18- 201110549 PU能夠具有第一電源供應器VDD之電壓。 其間，PMOS電晶體MP1之閘極可連接至第一電源供應 器VDD。在此狀況下，PMOS電晶體MP1在接收模式中接 通以將上拉節點PU維持在高電壓VDDH，但在傳輸模式中 斷開。 在具有複數個I/O墊之一多重I/O系統中，時序/位準控制 器140可供所有I/O墊共同使用。因此，減小了必要區域。 下文將描述I/O電路100之操作。 在用於將輸出資料DOUT傳輸至一外部器件之傳輸模式 中，上拉節點PU與下拉節點PD兩者均處於一邏輯高位準 或一邏輯低位準，以便將輸出資料DOUT傳輸至I/O墊。當 上拉節點PU與下拉節點PD兩者均處於邏輯高位準時，在 第二電壓節點GND之電壓下驅動I/O墊。當上拉節點PU與 下拉節點PD兩者均處於邏輯低位準時，在第一電源供應器 VDD之電壓下驅動I/O墊。 在傳輸模式中，將輸出啟用信號OE啟動至一邏輯高位 準。因此，第二位準移位器LC2之輸出具有中間電壓 VDDM之電壓位準，第一位準移位器LC1之輸出具有第一 電源供應器VDD之電壓位準，且主體節點PB具有第一電源 供應器VDD之電壓位準。另外，上拉開關電晶體MN2之閘 極G2具有中間電壓VDDM，且上拉開關電晶體MN2接通， 藉此將前置驅動器130之第一輸出資料傳輸至上拉節點PU 而不產生失真。換言之，因為將高於第一電源供應器VDD 之電壓的一電壓施加至上拉開關電晶體MN2之閘極G2，所 147730.doc -19- 201110549 以甚至在前置驅動器130之第一輸出資料為一邏輯高信號 時，亦將第一輸出資料傳輸至上拉節點PU。 將前置驅動器130之第二輸出資料傳輸至下拉節點PD。 因此，在傳輸模式中，回應於第一輸出資料及第二輸出資 料而選擇性地接通上拉電晶體ΜΡ0及第二下拉電晶體 MN1，藉此在第一電源供應器VDD之電壓下驅動I/O節點 NO(或經由I/O節點NO將電流供應至一外部器件），或在第 二電壓節點GND之電壓下驅動I/O節點NO(或使電流自I/O 節點NO沈降至接地）。 其間，在用於自一外部器件接收輸入資料之接收模式 中，斷開傳輸器110之上拉電晶體ΜΡ0及第二下拉電晶體 MN1，以將經由I/O墊所接收之輸入資料傳輸至接收器 120。上拉開關電晶體MN2之閘極G2具有中間電壓 VDDM，且因此，接收器輸入節點IR在第一電源供應器 VDD之電壓與第二電壓節點GND之電壓之間擺動。因此， 相比於以下習知技術而言，擺動位準已得以增加：在習知 技術中，接收器輸入節點IR在藉由自第一電源供應器VDD 之電壓減去NMOS電晶體之臨限電壓Vthn(亦即，「VDD-Vthn」）而獲得的一電壓與第二電壓節點GND之電壓之間 擺動。 在接收模式中，將輸出啟用信號OE撤銷啟動至一邏輯 低位準。因此，第二位準移位器LC2之輸出具有第一電源 供應器VDD之電壓位準，且第一位準移位器LC1之輸出具 有高電壓VDDH之電壓位準。因此，主體節點PB及上拉節 147730.doc -20- 201110549 點PU具有高電壓VDDH。因此，防止了可能自I/O節點NO 至上拉電晶體ΜΡ0發生之漏電流。當自外部器件所接收之 一信號具有一高電壓時，I/O節點NO處之電壓可能高於第 一電源供應器VDD之電壓（例如，類似於高電壓VDDH)。 甚至在此狀況下，因為主體節點PB具有高電壓VDDH，所 以亦可使一接面漏電流路徑中斷，該接面漏電流路徑可能 自I/O節點NO至上拉電晶體ΜΡ0之基板而形成。另外，因 為上拉節點PU亦具有高電壓VDDH，所以上拉電晶體ΜΡ0 未接通，且因此，可防止通過上拉電晶體MP 0之一漏電流 路徑。 上拉開關電晶體MN2之閘極G2歸因於第二位準移位器 LC2而具有第一電源供應器VDD之電壓，且上拉開關電晶 體MN2之源極（亦即，前置驅動器130之第一輸出資料）亦具 有第一電源供應器VDD之電壓，且因此，上拉開關電晶體 MN2保持在一斷開狀態中。 可使用一時序控制方法來防止熱載子注入，該時序控制 方法使用具有擴展之脈寬的一輸出啟用信號與延遲之輸出 啟用信號OED之間的時間差。將在下文中更詳細地描述此 方法。 尤其當在接收模式中接收到一外部高電壓信號且接著將 處於邏輯低位準之一信號輸出至外部器件（亦即，在模式 轉變之後，在傳輸模式中在第二電壓節點GND之電壓下驅 動I/O節點NO)時，熱載子注入變得成問題。當接收到高電 壓信號時，在I/O墊處存在大量高電位電荷。若在此狀態 147730.doc -21- 201110549 下形成一下拉路徑，則在第一下拉電晶體mno之汲極與源 極之間產生一大電壓差，從而引起熱載子注入。 根據本發明之發明概念之一例示性實施例，在形成一下 拉路徑之前，上拉開關電晶體MN2之閘極G2及主體節點 PB分別變成具有中間電壓VDDM及第一電源供應器VDD之 電壓。因此，I/O墊處之大量高電位電荷經由上拉電晶體 ΜΡ0而傳輸至主體節點PB或第一電源供應器VDD，且上拉 節點PU處之大量高電位電荷經由上拉開關電晶體MN2及 PMOS電晶體MP 1而傳輸至第一電源供應器VDD。當接收 模式轉換成傳輸模式時，在自啟動輸出啟用信號OE開始 直至形成下拉路徑為止之一延遲時間期間，I/O墊處之電 壓經由上拉電晶體MP0而降低，以使得即使在形成下拉路 徑之情況下亦可防止在第一下拉電晶體MN0處發生熱載子 注入。換言之，當資料輸入模式切換至資料輸出模式時， I/O節點處之自高位準至低位準之電壓擺動得以延遲。 可使用可變化之中間電壓VDDM來解決閘極氧化物可靠 性問題。更詳言之，可根據第一電源供應器VDD之電壓位 準而改變中間電壓VDDM。舉例而言，當第一電源供應器 VDD之電壓位準相對較高（例如，高於一預定位準）時，將 中間電壓VDDM設定為類似於第一電源供應器VDD之電 壓。當第一電源供應器VDD之電壓位準相對較低（例如， 低於一預定位準）時（亦即，在低電壓操作條件下），將中間 電壓VDDM設定為等於第一電源供應器VDD之電壓或高於 第一電源供應器VDD之電壓（例如，VDD+Vthn)。 147730.doc -22- 201110549 如上文所描述，根據本發明之發明概念之一例示性實施 例上拉電曰曰體ΜΡ0之基板（亦即，主體節點pB)具有高 壓VDDH，藉此防止一漏電流路徑。另外，根據一操作電 ⑽即’第-電源供應器卿之電麼)而改變中間電塵 VDDM卩增加低電壓操作條件下的接收器輸人節點JR之 擺動位準，藉此減少接收資料中之錯誤之發生。又，在自 接收模式轉變至傳輸模式時，在將輸出資料傳輸至外部器One of the power supplies is electrically I<I+ converted to - high power, and the high voltage can be higher than the one of the music/original supply. The second voltage node can be in a grounded electrical dust. The I/O circuit may further include a receiving switch transistor connected between the 1 / 〇 node and the receiver, sighing. The ugly beta receiving switch transistor passes through a voltage swing at the receiver. And controlling the I/O circuit to further transmit a controller, the transfer wheel being connected between the pre-driver and the at least-pull-up transistor and the h-pull transistor to control via the 1/ 0 node to ::: at least - the next anvil to the external device loses 147730.doc •10- 201110549 Data transfer. Set =::: to the at least, the pull-up switch between the electric crystal and the front turn. The door:=/ level controller may include a switch control level shifter, and the control level shifter is configured to control the (10) node to transmit the round-trip data to the external device d. The control level shifter can be configured to convert the third π to be greater than the electric power of the first power supply, and the second _ point is -:: : Change to the n-level of the first power supply II. The pull-up switch can be a transmission gate. The timing/level controller can include a transmission locker configured to control the transmission gate for transmitting the input material to the external device via a = point. The transfer gate position shifter can be Configuring to convert the second electrical voltage to a voltage level of the first power supply, and converting the voltage level of a source to a high voltage 'and the high (four) may be higher than the voltage of the first power supply. According to an exemplary embodiment, a memory system includes a memory device; and a memory device, straight and : a memory and an input/round-out circuit in communication with the memory interface. The output=output circuit includes a wheel finder that includes at least a connection between the first power supply and the -I/O point a pull-up transistor and at least a pull-up transistor connected between the (5) point and the -second voltage node to transmit the wheeled data to the memory interface via the 147730.doc 201110549; a receiver that receives input data from the memory interface via the I/O node; and a timing/level controller configured to selectively apply a voltage of the first power supply to a body section of the at least one pull-up transistor in a transmission mode, the point 'and the timing/ The level controller controls the body node to have a voltage higher than the voltage of the first power supply. The output data can be transmitted to a wafer controller in the memory device and can be self-remembered The wafer controller in the body device receives the input data. According to an exemplary embodiment, the computing system includes a central processing unit; and: a memory system that communicates with the central processing unit via a system bus. The system includes a memory controller having a memory interface; and a memory device, the input/cutting of the memory/1 surface and the input/cutting of the memory. The traitor circuit rebels the circuit. The input/output circuit includes a transmission benefit including at least a pull-up transistor connected between a first power supply and a 1/0 node and connected to the 1/0 node Between a second electrical node At least one time, the Thunder is placed in the solar cell to transmit the output data to the system bus via the I/O node; a technology receiving, a pie receiving state, which is self-sampling via the I/O node, and A timing/level controller configured to select ', Τ, and companionally apply a voltage to a body node of the at least one pull-up transistor in a transmission mode And the timing level controller controls the body node to have a voltage greater than a voltage of the first source supply. According to an exemplary embodiment, an operation has a -1/0 pad-1/ 0 147,730.doc •12- 201110549 The method of the punch includes selectively transmitting the output data to an external device, the transfer mode towel, in response to the first-round data with the logic high money Passing a pull-up transistor to one of the 1/0 pads, or selectively turning on a pull-down transistor coupled to one of the I/O pads in response to a second output data having a logic low signal; Driving the UO pad at a voltage of a first power supply voltage for the first output data Transmitting the 1/0塾 at the voltage of the second voltage node for the second output data transmission and selectively supplying the first power supply voltage to or higher than the first power supply The voltage-of-voltage is applied to the pull-up transistor two-body node. The 亥海 method may further include receiving the input data provider from an external device, and providing the input data received via the 1/0 pad to the connected-receive mode, disconnecting the transmitter Pull-pull transistor and the pull-down transistor... Receiver, according to an exemplary embodiment, a method of preventing hot carrier injection of one I/O 一 of a buffer, which is received in a receiving mode To the -external high-power signal and after switching from the receiving mode to one of the transmission modes, after the mode t, the transmission mode 4 outputs 4 to a logic low level, and the L 5 tiger outputs to the - external & The method includes: when the receiving mode is converted into the roller pull type, a delay time 1 ''' is pulled up by a pull-down path of one of the pull-down transistors from the start of an output enable signal. The transistor lowers one of the I/O pads for logic low level output signal transmission. The following and other features and advantages of the inventive concept will become more apparent from the detailed description of exemplary embodiments. The inventive concept of the present invention will be described more fully hereinafter with reference to the accompanying drawings. However, the inventive concept of the invention may be embodied in many different forms and should not be construed as being limited to the illustrative embodiments set forth herein. In these figures, the same numbers always refer to the same elements. It will be understood that when an element is referred to as "connected to" or "coupled to" another element, it can be directly connected or coupled to the other element, or a component can be present. It should also be understood that although the terms "first", "second", and the like may be used herein to describe various elements, such elements are not limited by the terms. These procedures are only used to distinguish one component from another. For example, a first signal may be referred to as a second signal, and similarly, a second signal may be referred to as a first signal without departing from the teachings of the present invention. 1 is a circuit diagram of an input/output (1/〇) circuit 100 in accordance with an exemplary embodiment of the inventive concepts of the present invention. The I/O circuit 100 includes a transmitter u, a receiver 120, a pre-driver 130, a timing/level controller 140, and a transmission controller 150. The transmitter 110 is a circuit for transmitting the output data DOUT to an external device via a 1/〇 node N〇 and a 1/〇 pad, and includes a pull-up transistor MP〇, a pull-down transistor ΜΝ0, and a second Pull down the transistor MN1. The pull-up transistor ΜΡ0 is connected between the first power supply VDD and the ι/〇 node. The pull-up transistor MP—the gate (i.e., the pull-up node pu) is connected to one of the pre-drivers 130 via a 147730.doc -14-201110549 pull-up switch transistor MN2. The first pull-down transistor ΜΝ0 and the second pull-down transistor MN1 are connected in series between the I/O node NO and a second voltage node GND. One of the first pull-down transistors ΜΝ0 is connected to an intermediate voltage VDDM, and one of the gates of the second pull-down transistor MN1 (i.e., the pull-down node PD) is connected to the other output of the pre-driver 130. The receiver 120 is coupled to a receiver input node IR and receives data input via the I/O pad and I/O node NO. The receiver input node IR is coupled between the first pull-down transistor ΜΝ0 and the second pull-down transistor MN1. The pre-driver 130 generates a pull-up signal (hereinafter, referred to as a first output data) and a pull-down signal (hereinafter, referred to as a second output data) based on a delayed output enable signal OED and an output data DOUT, and It is output to the pull-up node PU and the pull-down node PD, respectively. In a transmission mode for outputting the output data DOUT, the first output data and the second output data have the same logic level, so that only one of the pull-up transistor ΜΡ0 and the second pull-down transistor MN1 are connected. . In a receiving mode for receiving input data, the first output data and the second output data have logic levels that enable both the pull-up transistor ΜΡ0 and the second pull-down transistor MN1 to be disconnected. The pre-driver 130 includes a (NAND) gate ND1, a reverse (NOR) gate NOR1, and an inverter INV1. The NAND gate ND1 performs a NAND operation on the output data DOUT and the delayed output enable signal 0ED to output the first output data. The NOR gate N0R1 performs a NOR operation on one of the delayed output enable signal 0ED and the output data DOUT to output the second output 147730.doc -15- 201110549. The timing/level controller 140 includes a delay unit 141, a NOR gate NORO, a first bit shifter LC1, a second level shifter LC2, and an inverter INV2. When the receive mode is switched to the transfer mode, the timing/level controller 140 controls one of the body nodes PB (or the substrate) of the pull-up transistor 以0 to be within a predetermined period of time (eg, the delay time of the delay unit 14 1) Having a voltage of the first power supply VDD to transfer the high potential charge accumulated at the I/O node NO in the receiving mode to the first power supply VDD, and then transmitting the output data DOUT via the I/O node NO To an external device. This operation will be described in more detail below herein. The delay unit 141 delays the output enable signal OE for a predetermined delay time (e.g., the first delay time) and outputs the delayed output enable signal OED. The NOR gate NORO performs a NOR operation on the output enable signal OE and the delayed output enable signal OED, and outputs a signal having a pulse width greater than the pulse width of the input signals OE and OED. The output signal of the NOR gate NORO is input to the first level shifter LC1, and is input to the second level shifter LC2 via the inverter INV2. The delayed output enable signal OED is also input to the pre-driver 130. As illustrated in FIG. 12B, the second level shifter LC2 converts the voltage level of the second voltage node GND (hereinafter, referred to as the ground level) and the voltage level of the first power supply VDD into the first The voltage level of a power supply VDD and the voltage level of the intermediate voltage VDDM. The voltage level of the intermediate voltage VDDM is equal to or higher than the voltage level of the first power supply VDD. For example, the intermediate voltage VDDM can be "147730.doc -16-201110549 voltage of the first power supply VDD + threshold voltage Vthn of the NMOS transistor", that is, "VDD+Vthn". As illustrated in FIG. 12A, the first level shifter LC1 converts the ground level and the voltage level of the first power supply VDD into the voltage level of the first power supply VDD and the high voltage vdDH, respectively. quasi. The high voltage VDDH is higher than the voltage of the first power supply VDD. For example, the high voltage VDDH can be twice the voltage of the first power supply VDD, or a high voltage similar to 0 of the external device interfaced by the 1/0 circuit 100. The intermediate voltage vddm and the high voltage VDDH, which are the same as the voltage of the first power supply VDD, can be generated by an internal voltage generator (not shown). d The internal voltage generator may include a charge pump. In the receive mode, the high-power VDDH is used to pull up the body node pB and the pull-up point (9), thereby preventing the self-I/O node NO from forming a non-speaking person through the pull-up transistor Mp〇 to the body node. Current path. The intermediate voltage VDDM is used to pull up the first pull-down transistor ΜΝ0 and the pull-up switch transistor to take the idle pole of the transistor 2, thereby increasing the swing level of the 11-wheel human node 1R. Therefore, even in the -low voltage operation % i brother, the voltage of the received data mN can be reliably ensured, and therefore, the occurrence of an error in the received data DIN can be reduced. In other words, the intermediate voltage VDDM is used to control the gate of the pull-down transistor MN〇 and the pull-up transistor transistor MN2 to increase the limited swing level. The transfer controller 150 includes an inverter INV0 connected to the pull-down node PD, a PMOS transistor MP1, and a pull-up switch transistor 2. The pull-up node print I is connected to the body node PB by the PAios transistor MPi. pM〇s transistor MP1 ~ gate is connected to the inverter 丨 please output, and in response to the next 147730.doc -17. 201110549 pull signal one of the inverted signal PDB operation. One of the gates of the pull-up switch transistor MN2 (ie, node G2) is controlled by a second level-shifted output enable signal, and the second level-shifted output enable signal is used by The second level shifter LC2 obtains a level shift of the output signal of the inverter INV2. As described above, the second level shifter LC2 is used to control the pull-up switch transistor MN2 and is therefore referred to as a switch control level shifter. The substrate of the pull-up transistor ΜΡ0 and the PMOS transistor MP1 (ie, the body node PB) is controlled by a first level-shifted output enable signal, and the first level-shifted output enable signal system Obtained by level shifting the output signal of the NOR gate NORO using the first level shifter LC1. As described above, the first level shifter LC 1 is used to control the body node PB and is therefore referred to as a body node level shifter. The PMOS transistor MP1 is controlled by the output signal PDB of the inverter INV0 such that the pull-up node PU swings completely from the voltage of the second voltage node GND to the voltage of the first power supply VDD in the transmission mode, and receives The voltage level at the high voltage VDDH is maintained in the mode. In the receive mode, a second output data at a logic low level is applied to the pull-down node PD. Therefore, the signal PDB is at a logic high level (or the voltage level of the first power supply VDD). At this time, the body node PB has a high voltage VDDH, and therefore, the PMOS transistor MP1 is turned on, and the pull-up node PU is also maintained at the high voltage VDDH. Therefore, a leakage current path is prevented from being formed in the receiving mode. In the transmission mode, the PMOS transistor MP1 is turned on only when the pull-down node PD is at the logic high level, so that the pull-up node 147730.doc -18-201110549 PU can have the voltage of the first power supply VDD. Meanwhile, the gate of the PMOS transistor MP1 can be connected to the first power supply VDD. In this case, the PMOS transistor MP1 is turned on in the receiving mode to maintain the pull-up node PU at the high voltage VDDH, but is turned off in the transmission mode. In a multiple I/O system with multiple I/O pads, the timing/level controller 140 can be used in conjunction with all I/O pads. Therefore, the necessary area is reduced. The operation of the I/O circuit 100 will be described below. In the transmission mode for transmitting the output data DOUT to an external device, both the pull-up node PU and the pull-down node PD are at a logic high level or a logic low level to transfer the output data DOUT to the I/O pad. . When both the pull-up node PU and the pull-down node PD are at a logic high level, the I/O pad is driven at the voltage of the second voltage node GND. When both the pull-up node PU and the pull-down node PD are at a logic low level, the I/O pad is driven at the voltage of the first power supply VDD. In the transfer mode, the output enable signal OE is activated to a logic high level. Therefore, the output of the second level shifter LC2 has a voltage level of the intermediate voltage VDDM, the output of the first level shifter LC1 has the voltage level of the first power supply VDD, and the body node PB has the first The voltage level of the power supply VDD. In addition, the gate G2 of the pull-up switch transistor MN2 has an intermediate voltage VDDM, and the pull-up switch transistor MN2 is turned on, whereby the first output data of the pre-driver 130 is transmitted to the pull-up node PU without distortion. In other words, since a voltage higher than the voltage of the first power supply VDD is applied to the gate G2 of the pull-up switching transistor MN2, 147730.doc -19-201110549 to even the first output data of the pre-driver 130 is When a logic high signal is transmitted, the first output data is also transmitted to the pull-up node PU. The second output data of the pre-driver 130 is transmitted to the pull-down node PD. Therefore, in the transmission mode, the pull-up transistor ΜΡ0 and the second pull-down transistor MN1 are selectively turned on in response to the first output data and the second output data, thereby driving at the voltage of the first power supply VDD I/O node NO (or supply current to an external device via I/O node NO), or drive I/O node NO at voltage of second voltage node GND (or sink current from I/O node NO to Ground). Meanwhile, in the receiving mode for receiving input data from an external device, the transistor ΜΡ0 and the second pull-down transistor MN1 are disconnected from the transmitter 110 to transmit the input data received via the I/O pad to Receiver 120. The gate G2 of the pull-up switch transistor MN2 has an intermediate voltage VDDM, and therefore, the receiver input node IR swings between the voltage of the first power supply VDD and the voltage of the second voltage node GND. Therefore, the wobble level has been increased compared to the prior art: in the prior art, the receiver input node IR is subtracted from the threshold of the NMOS transistor by the voltage from the first power supply VDD. A voltage obtained by the voltage Vthn (that is, "VDD-Vthn") swings between the voltage of the second voltage node GND. In the receive mode, the output enable signal OE is deactivated to a logic low level. Therefore, the output of the second level shifter LC2 has the voltage level of the first power supply VDD, and the output of the first level shifter LC1 has the voltage level of the high voltage VDDH. Therefore, the main node PB and the pull-up 147730.doc -20- 201110549 point PU have a high voltage VDDH. Therefore, leakage current that may occur from the I/O node NO to the pull-up transistor ΜΡ0 is prevented. When a signal received from an external device has a high voltage, the voltage at the I/O node NO may be higher than the voltage of the first power supply VDD (e.g., similar to the high voltage VDDH). Even in this case, since the body node PB has a high voltage VDDH, it is also possible to interrupt a junction leakage current path which may be formed from the I/O node NO to the substrate of the pull-up transistor ΜΡ0. In addition, since the pull-up node PU also has a high voltage VDDH, the pull-up transistor ΜΡ0 is not turned on, and therefore, a leakage current path through one of the pull-up transistors MP 0 can be prevented. The gate G2 of the pull-up switch transistor MN2 has a voltage of the first power supply VDD due to the second level shifter LC2, and the source of the pull-up switching transistor MN2 (ie, the pre-driver 130) The first output data) also has the voltage of the first power supply VDD, and therefore, the pull-up switch transistor MN2 remains in an off state. A timing control method can be used to prevent hot carrier injection, which uses a time difference between an output enable signal having an extended pulse width and a delayed output enable signal OED. This method will be described in more detail below. In particular, when an external high voltage signal is received in the receive mode and then a signal at a logic low level is output to the external device (ie, after the mode transition, the voltage is driven at the voltage of the second voltage node GND in the transmit mode). At the I/O node NO), hot carrier injection becomes a problem. When a high voltage signal is received, there is a large amount of high potential charge at the I/O pad. If a pull-down path is formed under this state 147730.doc -21- 201110549, a large voltage difference is generated between the drain and the source of the first pull-down transistor mno, thereby causing hot carrier injection. According to an exemplary embodiment of the inventive concept, the gate G2 of the pull-up switching transistor MN2 and the body node PB become voltages having an intermediate voltage VDDM and a first power supply VDD, respectively, before forming a pull-down path. Therefore, a large amount of high potential charge at the I/O pad is transferred to the body node PB or the first power supply VDD via the pull-up transistor ΜΡ0, and a large amount of high-potential charge at the pull-up node PU via the pull-up switch transistor MN2 And the PMOS transistor MP 1 is transmitted to the first power supply VDD. When the reception mode is switched to the transmission mode, during a delay time from the start of the enable output enable signal OE until the pull-down path is formed, the voltage at the I/O pad is lowered via the pull-up transistor MP0, so that even when the pull-down is formed In the case of the path, hot carrier injection can also be prevented from occurring at the first pull-down transistor MN0. In other words, when the data input mode is switched to the data output mode, the voltage swing from the high level to the low level at the I/O node is delayed. The gate oxide reliability problem can be solved using a variable intermediate voltage VDDM. More specifically, the intermediate voltage VDDM can be changed according to the voltage level of the first power supply VDD. For example, when the voltage level of the first power supply VDD is relatively high (e.g., above a predetermined level), the intermediate voltage VDDM is set to be similar to the voltage of the first power supply VDD. When the voltage level of the first power supply VDD is relatively low (eg, below a predetermined level) (ie, under low voltage operating conditions), the intermediate voltage VDDM is set equal to the first power supply VDD The voltage is either higher than the voltage of the first power supply VDD (for example, VDD+Vthn). 147730.doc -22- 201110549 As described above, according to an exemplary embodiment of the inventive concept, the substrate of the pull-up body (0 (that is, the body node pB) has a high voltage VDDH, thereby preventing a leak Current path. In addition, according to an operating power (10), that is, 'the first power supply device', the intermediate electric dust VDDM 改变 increases the swing level of the receiver input node JR under the low voltage operating condition, thereby reducing the received data. The error occurred. Also, when the self-receiving mode is changed to the transmission mode, the output data is transmitted to the external device.
件之月|J使用時序控制方法對1/〇塾處剩餘之高電位電荷 進行放電’藉此防止熱載子注入。 圖2為圖i中所說明之1/〇電路1〇〇之修改i〇〇a的電路圖。 參看圖2’卯電路_包括傳輸器11〇、接收器12〇、前置 驅動器13G、時序/位準控制η術及傳輸控制器⑽。ι/〇 電路100a中所包括之傳輸器11〇、接收器12〇及前置驅動器 130與I/O電路1〇〇中所包括之彼等元件相同，但ι/〇電路 l〇〇a中所包括之時序/位準控制器14〇a及傳輸控制器15(^不 同於I/O電路1〇〇中所包括之對應元件14〇、15〇。因此將 主要描述I/O電路100與I/O電路100a之間的差別。 在圖1中所說明之I/O電路100中，上拉開關電晶體MN2 之閘極G2連接至第二位準移位器LC2之輸出，但在圖2中 所說明之I/O電路l〇〇a中，上拉開關電晶體河]^2之閘極G2 連接至第一電源供應器vdd。因此，在圖1中所說明之i/o 電路100中’在傳輸模式中將中間電壓VDDM施加至上拉 開關電晶體MN2之閘極G2，而在圖2中所說明之I/O電路 100a中’在傳輸模式中上拉開關電晶體MN2之閘極G2處的 147730.doc -23- 201110549 電壓固定至第一電源供應器VDD之電壓。在圖1中，第二 位準移位器LC2之輸出（亦即，中間電壓VDDM)連接至上 拉開關電晶體MN2之閘極G2以在上拉節點pu處達成完全 擺動操作.，而在圖2中，雖然上拉開關電晶體MN2之閘極 G2處的電壓固定至第一電源供應器VDD之電壓，但反相器 INV0及PMOS電晶體MP1使得能夠在上拉節點pu處達成完 全擺動操作。 圖3為圖1中所說明之1/0電路1〇〇之另一修改1〇〇b的電路 圖。參看圖3，I/O電路l〇〇b包括傳輸器110、接收器12〇、 前置驅動器130、時序/位準控制器140b及傳輸控制器 150b。I/O電路100b中所包括之傳輸器11〇、接收器12〇及 前置驅動器130與I/O電路1〇〇中所包括之彼等元件相同， 但I/O電路l〇〇b中所包括之時序/位準控制器14汕及傳輸控 制器150b不同於I/O電路1〇〇中所包括之對應元件、 150。因此’將主要描述1/0電路1〇〇與1/〇電路1〇讥之間的 差別。 相比於時序/位準控制器14〇而言，時序/位準控制器14此 進一步包括反相器INV2,、NAND閘ND2、pM〇s電晶於 MP2及二極體01。二極體〇1防止pM〇s電晶體]^1>2之閘極 與源極之間的電壓差增加，藉此防止PMOS電晶體MP2之 閘極電壓高於第一電源供應器VDD之電壓。 反相器INV2,使延遲之輸出啟用信號〇ED反相。nand^ ND2對反相器INV2,之輸出信號與輸出啟用信號〇e執行— NAND運算，且將一所得信號輸出至PM〇s電晶體Mp2之閘 147730.doc -24· 201110549 ° PMOS電晶體ΜΡ2之-節點（亦即，源極或沒極）及其主體 (或基板）共同連接至第一位準移位器LC1之輪出。pM〇s電 晶體MP2之另-節點（亦即，沒極或源極）與上拉節點抓連 接。因此’在自接收模式轉變至傳輸模式時，上拉節點叫 處之高電位電荷經由PM0S電晶體Mp2而傳輸至主體節點 PB ’以使得上拉節點PU具有第一電源供應器之電 ΟThe month of the device|J uses the timing control method to discharge the remaining high potential charge at 1/〇塾, thereby preventing hot carrier injection. Figure 2 is a circuit diagram of the modification i〇〇a of the 1/〇 circuit 1〇〇 illustrated in Figure i. Referring to Fig. 2', the circuit _ includes a transmitter 11 接收, a receiver 12 〇, a pre-driver 13G, a timing/level control η, and a transmission controller (10). The transmitter 11 〇, the receiver 12 〇 and the pre-driver 130 included in the ι/〇 circuit 100a are the same as those included in the I/O circuit 1 ,, but the ι/〇 circuit l 〇〇 a The included timing/level controller 14A and the transfer controller 15 are different from the corresponding elements 14A, 15A included in the I/O circuit 1A. Therefore, the I/O circuit 100 will be mainly described. The difference between the I/O circuits 100a. In the I/O circuit 100 illustrated in Fig. 1, the gate G2 of the pull-up switching transistor MN2 is connected to the output of the second level shifter LC2, but in the figure In the I/O circuit 10a described in 2, the gate G2 of the pull-up switch transistor is connected to the first power supply vdd. Therefore, the i/o circuit illustrated in FIG. In the transmission mode, the intermediate voltage VDDM is applied to the gate G2 of the pull-up switching transistor MN2, and in the I/O circuit 100a illustrated in FIG. 2, the gate of the pull-up switching transistor MN2 is in the transmission mode. 147730.doc -23- 201110549 at pole G2 is fixed to the voltage of the first power supply VDD. In Figure 1, the output of the second level shifter LC2 (ie, the intermediate voltage) VDDM) is connected to the gate G2 of the pull-up switch transistor MN2 to achieve a full swing operation at the pull-up node pu. In FIG. 2, although the voltage at the gate G2 of the pull-up switch transistor MN2 is fixed to the first The voltage of the power supply VDD, but the inverter INV0 and the PMOS transistor MP1 enable a full swing operation at the pull-up node pu. Figure 3 is another modification of the 1/0 circuit 1 illustrated in Figure 1. 1电路b. Referring to Fig. 3, the I/O circuit 10b includes a transmitter 110, a receiver 12A, a pre-driver 130, a timing/level controller 140b, and a transmission controller 150b. I/O The transmitter 11 〇, the receiver 12 〇 and the pre-driver 130 included in the circuit 100b are identical to the components included in the I/O circuit 1 ,, but are included in the I/O circuit 10b The timing/level controller 14A and the transmission controller 150b are different from the corresponding components included in the I/O circuit 1A, 150. Therefore, the 1/0 circuit 1〇〇 and the 1/〇 circuit 1〇 will be mainly described. The difference between 讥. Compared to the timing/level controller 14〇, the timing/level controller 14 further includes an inverter I NV2, NAND gate ND2, pM〇s electro-crystal in MP2 and diode 01. Diode 〇1 prevents the voltage difference between the gate and source of pM〇s transistor]^1>2, This prevents the gate voltage of the PMOS transistor MP2 from being higher than the voltage of the first power supply VDD. The inverter INV2 inverts the delayed output enable signal 〇ED. nand^ ND2 pairs the inverter INV2, the output signal is The output enable signal 〇e performs a NAND operation, and outputs a resultant signal to the gate of the PM〇s transistor Mp2 147730.doc -24·201110549 ° PMOS transistor ΜΡ2-node (ie, source or immersion) And its body (or substrate) is connected in common to the wheel of the first level shifter LC1. The other node (i.e., the pole or source) of the pM〇s transistor MP2 is connected to the pull-up node. Therefore, when transitioning from the reception mode to the transmission mode, the high potential charge called by the pull-up node is transmitted to the body node PB' via the PMOS transistor Mp2 so that the pull-up node PU has the power of the first power supply.
G 歷。 圖4為圖1中所說明之1/0電路⑽之另一修改100c的電路 圖。參看圖4，I/O電路i00c包括傳輸器u〇a、接收器m 接收開關電晶體MN3、前置驅動器13〇、時序/位準控制器 !40及傳輸控制器15G。1/〇電路脈_所包括之缝器 120、則置驅動器130、時序/位準控制器刚及 150與1/〇電路⑽中所包括之彼等元件相同，㈣電路 100C中戶斤包括之傳輸器110a不同於1/〇電路1〇〇中所包括之 傳輸器1H)，且相比於1/〇電路100而言，1/〇電路聽進一 步包括接收開關電晶體则。因此，將主要描述卯電路 100與I/O電路l〇〇c之間的差別。 接收開關電晶體咖連接於1/〇節點N〇與接收器12〇之 間’且具有受控於中間電麼卿处一閘極。因為接收開 關電曰曰體MN3之閘極具有_間電屢vddm，所 入，—電源供應器卿之電壓與第二電㈣點= 之'屢，間擺動。其間，圖4中所說明之I/O電路跡中所 包括的第一下拉電晶體咖在接收模式中不使用，且因 J47730.doc •25· 201110549 此，將第一電源供應器VDD之電壓而非中間電壓VDDM施 加至第一下拉電晶體ΜΝ0之閘極。 圖5為圖1中所說明之I/O電路100之另一修改100d的電路 圖。參看圖5，I/O電路100d包括傳輸器110b、接收器 120、前置驅動器130、時序/位準控制器140及傳輸控制器 150。I/O電路100d中所包括之接收器120、前置驅動器 130、時序/位準控制器140及傳輸控制器150與I/O電路100 中所包括之彼等元件相同，但I/O電路l〇〇d中所包括之傳 輸器110b不同於I/O電路100中所包括之傳輸器110。 傳輸器ll〇b包括串聯連接於第一電源供應器VDD與I/O 節點NO之間的第一上拉電晶體ΜΡ0及第二上拉電晶體 MP2。換言之，傳輸器11 0b具有一結構，在該結構中，多 個上拉電晶體堆疊。第二上拉電晶體MP2連接於第一上拉 電晶體ΜΡ0與I/O節點NO之間。第二上拉電晶體MP2之閘 極與前置驅動器130之一輸出節點連接，且第二上拉電晶 體MP2之主體（或基板）與第一上拉電晶體ΜΡ0之主體節點 PB連接。 當在接收模式中將處於0 V之邏輯低位準之資料輸入至 圖1中所說明之I/O電路100中所包括的I/O節點NO時，上拉 電晶體ΜΡ0之閘極電壓與I/O節點NO處之電壓之間的電壓 差類似於高電壓VDDH之電壓位準。然而，在圖5中所說明 之I/O電路100d(其中第二上拉電晶體MP2***於第一上拉 電晶體ΜΡ0與I/O節點NO之間）中，第二上拉電晶體MP2之 閘極電壓與I/O節點NO處之電壓之間的電壓差類似於第一 147730.doc -26- 201110549 電源供應器VDD之電壓位準（其小於高電壓vdDH之電壓位 準）。 如上文所描述’可以各種方式來修改根據本發明之發明 概念之一例示性實施例的1/0電路1〇〇。雖然未展示，但可 藉由組合圖2至圖5中所說明之修改而產生其他修改。 圖6為根據本發明之發明概念之一例示性實施例的"〇電 路200的電路圖。1/〇電路2〇〇包括傳輸器21〇、接收器G calendar. Figure 4 is a circuit diagram of another modification 100c of the 1/0 circuit (10) illustrated in Figure 1. Referring to FIG. 4, the I/O circuit i00c includes a transmitter u〇a, a receiver m receiving switch transistor MN3, a pre-driver 13A, a timing/level controller !40, and a transmission controller 15G. 1/〇 circuit pulse_included the stitcher 120, the set driver 130, the timing/level controller just and 150 are identical to the components included in the 1/〇 circuit (10), and (4) the circuit 100C includes The transmitter 110a is different from the transmitter 1H) included in the 1/〇 circuit 1A, and the 1/〇 circuit is further included to receive the switching transistor as compared to the 1/〇 circuit 100. Therefore, the difference between the 卯 circuit 100 and the I/O circuit 10c will be mainly described. The receiving switch transistor is connected between the 1/〇 node N〇 and the receiver 12〇 and has a gate controlled by the intermediate power. Because the gate of the receiving switch body MN3 has _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Meanwhile, the first pull-down transistor included in the I/O circuit trace illustrated in FIG. 4 is not used in the receiving mode, and the first power supply VDD is used as described in J47730.doc • 25· 201110549 A voltage, rather than an intermediate voltage VDDM, is applied to the gate of the first pull-down transistor ΜΝ0. Figure 5 is a circuit diagram of another modification 100d of the I/O circuit 100 illustrated in Figure 1. Referring to FIG. 5, the I/O circuit 100d includes a transmitter 110b, a receiver 120, a pre-driver 130, a timing/level controller 140, and a transmission controller 150. The receiver 120, the pre-driver 130, the timing/level controller 140, and the transmission controller 150 included in the I/O circuit 100d are the same as those included in the I/O circuit 100, but the I/O circuit The transmitter 110b included in l〇〇d is different from the transmitter 110 included in the I/O circuit 100. The transmitter 11b includes a first pull-up transistor ΜΡ0 and a second pull-up transistor MP2 connected in series between the first power supply VDD and the I/O node NO. In other words, the transmitter 110b has a structure in which a plurality of pull-up transistors are stacked. The second pull-up transistor MP2 is connected between the first pull-up transistor ΜΡ0 and the I/O node NO. The gate of the second pull-up transistor MP2 is connected to one of the output nodes of the pre-driver 130, and the body (or substrate) of the second pull-up transistor MP2 is connected to the body node PB of the first pull-up transistor ΜΡ0. When the data of the logic low level of 0 V is input to the I/O node NO included in the I/O circuit 100 illustrated in FIG. 1 in the receiving mode, the gate voltage of the pull-up transistor ΜΡ0 and I are The voltage difference between the voltages at the /O node NO is similar to the voltage level of the high voltage VDDH. However, in the I/O circuit 100d illustrated in FIG. 5 (wherein the second pull-up transistor MP2 is interposed between the first pull-up transistor ΜΡ0 and the I/O node NO), the second pull-up transistor MP2 The voltage difference between the gate voltage and the voltage at the I/O node NO is similar to the voltage level of the power supply VDD of the first 147730.doc -26-201110549 (which is less than the voltage level of the high voltage vdDH). The 1/0 circuit 1 根据 according to an exemplary embodiment of the inventive concept of the present invention can be modified in various ways as described above. Although not shown, other modifications can be made by combining the modifications illustrated in Figures 2 through 5. FIG. 6 is a circuit diagram of a "〇 circuit 200 in accordance with an exemplary embodiment of the inventive concepts of the present invention. 1/〇 circuit 2〇〇 includes transmitter 21〇, receiver
220廂置驅動器230、時序/位準控制器240及傳輸控制器 25〇。傳輸器210、前置驅動器23〇及接收器22〇與圖i中所 說明之傳輸器no、前置驅動器130及接收器12()相同。因 此，將省略其描述。 時序/位準控制器24〇包括延 憋早兀、NOR閘nuxw、 反相器INV2、NAND閘刪、第一位準移位器lci及第三 位準移位IILC3。延遲單元241使輸出啟用信號⑽延遲達 一預定延遲時間（例如，第—延遲時間），且輸出延遲之輸 出啟用信細D。職間職晴輸出啟用信號娜延遲 啟用信號咖執行—職運算，且將—所得信號作 為一輸入提供至第-位準移位器LC1。因此，職間N〇r〇 :輸出信號為具有擴展之脈寬之一輸出啟用信號的反相信 二。。亦將延遲之輸出啟用信號咖輸人至前置驅動器 反相器INV2使延遲之輪出 斟^山仏 由驭用1口唬0ED反相。NAND閘 咖對輪歧时號崎反相㈣ NAND運算，m〜 m號執灯一 建异且將所得信號作為—輸人提供至第三位準 147730.doc -27- 201110549 移位器LC3。 圖6中所說明之第一位準移位器LC1與圖1中所說明之彼 第一位準移位器LC 1相同。因此，將省略其描述。如同第 一位準移位器LC1，第三位準移位器LC3分別將接地位準 及第一電源供應器VDD之電壓位準轉換成第一電源供應器 VDD之電壓位準及高電壓VDDH之電壓位準（如圖12C中所 說明）。 傳輸控制器250包括連接於上拉節點Pu與前置驅動器 230之一輸出節點之間的一上拉開關。該上拉開關可藉由 包括一 NMOS電晶體MN2及一 PMOS電晶體MP2之一傳輸閘 來實施。 傳輸控制器250亦包括PMOS電晶體MP1，其連接於上拉 筇點PU與I/O節點NO之間；PMOS電晶體MP3，其連接於 PMOS電晶體MP2之閘極與I/O節點；^〇之間；及NM〇s電晶 體MN3，其連接於連接節點（亦即，第一下拉電晶體MN〇 與第二下拉電晶體MN1之間的一接收器輸入節點IR)與 PMOS電晶體MP2之閘極之間。 第三位準移位器LC3控制傳輪控制器25〇中所包括之上 拉開關之NMOS電晶體MN2的間極，且因此被稱作開關控 制位準移位器。PM〇s電晶體Μρι及Mp3之閘極連接至第 一電源供應器VDD，且NM0S電晶體MN3之閘極連接至反 相器INV2之輸出。 日守序/位準控制器240亦可包括兩個NM〇s電晶體MN4及 MN5，其串聯連接於上拉開關之pM〇s電晶體之問極 147730.doc -28 - 201110549 與第二電壓節點GND之間。NMOS電晶體MN4之一閘極連 接至第一電源供應器VDD，且將延遲之輸出啟用信號OED 輸入至NMOS電晶體MN5之閘極。該兩個NMOS電晶體 MN4及MN5用以將節點GP2保持在接地位準。 根據本發明之發明概念之當前實施例，在接收模式中將 上拉電晶體ΜΡ0之主體節點PB上拉至高電壓VDDH之電壓 位準，藉此防止形成通過上拉電晶體ΜΡ0的非吾人所樂見 之一電流路徑。另外，在接收模式中將第一下拉電晶體 ΜΝ0之閘極上拉至中間電壓VDDM之電壓位準，藉此增加 I/O節點NO之擺動位準。因此，甚至在低電壓操作條件 下，輸入資料之擺動位準亦不受限制。在自接收模式轉變 至傳輸模式時，節點GN2(亦即，上拉開關之NMOS電晶體 MN2之閘極）處的電壓轉變至高電壓VDDH之電壓位準，藉 此將上拉節點PU處之高電位電荷傳輸至第一電源供應器 VDD。 圖7為圖6中所說明之I/O電路200之修改200a的電路圖。 I/O電路200a類似於圖6中所說明之I/O電路200，且因此， 將主要描述I/O電路200a與I/O電路200之間的差別。 圖7中所說明之時序/位準控制器140與圖1中所說明之時 序/位準控制器140相同。因此，上拉開關之NMOS電晶體 MN2係受控於第二位準移位器LC2之輸出。在圖6中所說明 之I/O電路200中，NMOS電晶體MN3之閘極連接至反相器 INV2之輸出，但在圖7中所說明之I/O電路200a中，NMOS 電晶體MN3之閘極連接至第一電源供應器VDD。 147730.doc -29- 201110549 可如將圖1中所說明之I/O電路H)〇修改為圖4中所說明之 1/〇電路敝來修改1/〇電路彻 '雇。換言之下拉電晶 體ΜΝ0之閘極可連拯$结 ^ — 曰 供至第一電源供應器VDD，且I/O電路 200 200a亦可。括〜接收開關電晶體，該接收開關電晶 體連接於I/O節點N〇礙拉丨> 0。一 n 日日 >、接收器220之間且具有一接收中間電 壓VDDM之閘極。在勵。山_ 牧圈8中說明此修改之一實例。 圖8為圖6中所說明夕τ/〇带妨。。〇 & 之I/O電路200之另一修改200b的電路 圖。相比於圖6中所兮的〜τ μ ^ 味明之I/O電路200而言，I/O電路2〇〇b 包括與圖6中所說明之& μ — α <彼等兀件相同的前置驅動器23〇、傳 輸控制器25〇及時序^ & 位準控制器240，及一不同於圖6中所 說明之傳輸器210的值於„。^ ^ 辱輸盗21 〇 a ’且進—'步包括一接收開 關電晶體。該接收開關φ 听關電晶體連接於I/O節點NO與接收器 220之間，且具有受扣 。 人疫於中間電壓VDDM之一閘極。因為 接收開關電晶體之閘朽 J極具有中間電壓VDDM之電壓位準， 所以接收益輸入即點IR在第—電源供應器之電壓與第 二電壓節點GND之電壓之間擺動。 、 其間’圖8中戶斤成明之1/〇電路2嶋中所包括的第一下拉 電晶體函在接收模式中不Μ，且因此，將第-電源供 應器VDD之電壓電壓vddm施加至第一下拉電晶 體ΜΝ0之閘極。如上文所描述，中間電壓vddm可隨第— 電源供應器VDD之電壓位準而變化。 圖9為根據本發明之發明概念之其他實施例的1/〇電路 300的電路圖。I/O電路300包括傳輸器31〇、接收器32〇、 前置驅動器330及時序/位準控制器34〇。前置驅動器33〇及 147730.doc •30· 201110549 接收器320與圖1中所說明之前置驅動器130及接收器120相 同。因此，將省略其描述。 傳輸器310包括第一上拉電晶體ΜΡ0、第二上拉電晶體 MP1、第一下拉電晶體ΜΝ0及第二下拉電晶體MN1。第一 上拉電晶體ΜΡ0與第二上拉電晶體MP1串聯連接於第一電 源供應器VDD與I/O節點NO之間。第二上拉電晶體MP1之 一閘極（亦即，上拉節點PU)連接至前置驅動器330之一輸 出。第一上拉電晶體ΜΡ0及第二上拉電晶體MP1之基板（亦 即，共同主體節點PB)連接至第一位準移位器LC1之輸 出。 第一下拉電晶體ΜΝ0與第二下拉電晶體MN1串聯連接於 I/O節點NO與第二電壓節點GND之間。第一下拉電晶體 ΜΝ0之一閘極連接至中間電壓VDDM，且第二下拉電晶體 MN1之一閘極連接至前置驅動器330之另一輸出。 時序/位準控制器340包括延遲單元341、NOR閘NR0、 NAND閘ND0、反相器INV2、位準移位器LC1、NMOS電晶 體MN2及PMOS電晶體MP2。 在自接收模式轉變至傳輸模式時，時序/位準控制器340 控制第一上拉電晶體ΜΡ0及第二上拉電晶體MP1之共同主 體節點PB以使其在一預定延遲時間内具有第一電源供應器 VDD之電壓，以便將I/O節點NO處之高電位電荷傳輸至第 一電源供應器VDD且接著經由I/O節點NO將輸出資料 DOUT傳輸至一外部器件。在接收模式中，時序/位準控制 器340控制共同主體節點PB以使其具有高電壓VDDH。因 147730.doc •31 - 201110549 此，防止了發生通過第一上拉電晶體ΜΡ0及第二上拉電晶 體MP1之漏電流。 延遲單元341使輸出啟用信號OE延遲達一預定延遲時間 (例如，第一延遲時間），且輸出延遲之輸出啟用信號 OED。反相器INV2使延遲之輸出啟用信號OED反相。 NAND閘ND0對由延遲單元341(延遲單元341使輸出啟用 信號OE延遲達一第二延遲時間）產生之一信號與反相器 INV2之一輸出信號執行一 NAND運算。此時，藉由使輸出 啟用信號OE延遲達第二延遲時間而產生之該信號的相位 可不同於延遲之輸出啟用信號OED之相位。 PMOS電晶體MP2係受控於NAND閘ND0之輸出信號，且 連接於第一上拉電晶體ΜΡ0之閘極（亦即，節點GO)與共同 主體節點PB之間。NMOS電晶體MN2連接於反相器INV2與 節點G0(亦即，第一上拉電晶體ΜΡ0之閘極）之間，且具有 連接至第一電源供應器VDD之一閘極。 位準移位器LC 1與上文所描述之第一位準移位器LC 1相 同。換言之，位準移位器LC1分別將第二電壓節點GND之 電壓位準（亦即，接地位準）及第一電源供應器VDD之電壓 位準轉換成第一電源供應器VDD之電壓位準及高電壓 VDDH之電壓位準，如圖12A中所說明。高電壓VDDH可為 第一電源供應器VDD之電壓的兩倍，或類似於由I/O電路 3 00介接之外部器件的一高電壓。高於第一電源供應器 VDD之電壓的中間電壓VDDM及高電壓VDDH可由一内部 電壓產生器（圖中未展示）來產生。該内部電壓產生器可包 147730.doc -32· 201110549 括一電荷泵。 在接收模式中使用高電壓VDDH來上拉主體節點PB，藉 此防止形成通過第一上拉電晶體ΜΡ0及第二上拉電晶體 MP1的非吾人所樂見之一電流路徑。換言之，在接收模式 中防止形成通過第一上拉電晶體ΜΡ0及第二上拉電晶體 MP1之一漏電流路徑。使用中間電壓VDDM來上拉第一下 拉電晶體ΜΝ0之閘極，藉此達成低電壓操作條件。換言 ^ 之，使用中間電壓VDDM來控制第一下拉電晶體ΜΝ0之閘 〇 極以增加受限之擺動位準。 如上文所描述，可取決於閘極氧化物之可靠性及低電壓 操作而使中間電壓VDDM變化。舉例而言，當第一電源供 應器VDD之電壓相對較高時，可將中間電壓VDDM設定為 類似於第一電源供應器VDD之電壓以減小閘極氧化物上之 應力。當第一電源供應器VDD之電壓相對較低時（亦即， 在低電壓操作條件下），將中間電壓VDDM設定為等於第一 Q 電源供應器VDD之電壓或高於第一電源供應器VDD之電壓 (例如，VDD+Vthn)。另外，如上文所描述，使用時序控 制方法來防止可能在自接收模式轉變至傳輸模式時發生的 " 熱載子注入。換言之，當接收模式轉換成傳輸模式時，在 - 貢料傳輸之前’對I / 0塾處剩餘之雨電位電荷進行放電’ 藉此防止熱載子注入。 在具有複數個I/O墊之一多重I/O系統中，時序/位準控制 器340可供所有I/O墊共同使用。因此，減小了必要區域。 下文將描述I/O電路300之操作。 147730.doc •33- 201110549 在用於將輸出資料DOUT傳輸至一外部器件之傳輸模式 中，上拉節點PU與下拉節點PD兩者均處於一邏輯高位準 或一邏輯低位準，以便將輸出資料DOUT傳輸至I/O墊。當 上拉節點PU與下拉節點PD兩者均處於邏輯高位準時，在 第二電壓節點GND之電壓下驅動I/O墊。當上拉節點PU與 下拉節點PD兩者均處於邏輯低位準時，在第一電源供應器 VDD之電壓下驅動I/O墊。 位準移位器LC 1之輸出具有第一電源供應器VDD之電壓 位準，且主體節點PB因此具有第一電源供應器VDD之電壓 位準。因此，防止了第一上拉電晶體ΜΡ0及第二上拉電晶 體MP 1之體效應。輸出啟用信號OE處於一邏輯高位準，且 因此反相器INV2之輸出信號處於一邏輯低位準。因此，第 一上拉電晶體MP0之閘極（亦即，節點G0)經由NMOS電晶 體MN2而保持具有第二電壓節點GND之電壓。 將前置驅動器330之第二輸出資料傳輸至下拉節點PD。 因此，回應於第一輸出資料及第二輸出資料而選擇性地接 通第二上拉電晶體MP1及第二下拉電晶體MN1，藉此在第 一電源供應器VDD之電壓下驅動I/O節點NO(或經由I/O節 點NO將電流供應至外部器件），或在第二電壓節點GND之 電壓下驅動I/O節點NO(或使電流自I/O節點NO沈降至接 地）。 其間，在用於自一外部器件接收輸入資料之接收模式 中，斷開傳輸器3 10之第一上拉電晶體ΜΡ0及第二上電晶 體MP1以及第二下拉電晶體MN1，以將經由I/O墊所接收之 147730.doc -34- 201110549 輸入資料傳輸至接收器320。主體節點PB處之電壓具有高 電壓VDDH之電壓位準，且並不根據輸入資料而改變。因 為主體節點PB處之電壓維持在高電壓VDDH之電壓位準， 所以防止了發生通過第一上拉電晶體ΜΡ0及第二上拉電晶 體MP1之一漏電流（亦即，非吾人所樂見之電流）。節點G0 亦經由PMOS電晶體MP2而變成具有高電壓VDDH，以使得 防止發生通過第一上拉電晶體ΜΡ0及第二上拉電晶體MP1 之一漏電流。 上拉節點PU及節點S2具有第一電源供應器VDD之電 壓，且下拉節點PD處之電壓處於一低位準。因此，第二下 拉電晶體MN1斷開。第一下拉電晶體ΜΝ0之閘極具有中間 電壓VDDM，且因此，接收器輸入節點IR在第一電源供應 器VDD之電壓與第二電壓節點GND之電壓之間擺動。 此後，當啟動輸出啟用信號OE並進入傳輸模式中時， 主體節點PB具有第一電源供應器VDD之電壓，且節點G2 處之電壓在一延遲時間内處於一邏輯低位準。此時，節點 G2處之電壓歸因於NAND閘ND0及連接於NAND閘ND0與 接地之間的二極體D1而處於約一臨限電壓位準。因此， PMOS電晶體MP2處之閘極氧化物應力得以減小。因此， 儲存於I/O墊及節點G0處之高電位電荷經由PMOS電晶體 ΜΡ0、MP1及MP2而傳輸至第一電源供應器VDD。 如上文所描述，根據本發明之發明概念之當前實施例， 第一上拉電晶體ΜΡ0及第二上拉電晶體MP1之基板（亦即， 共同主體節點PB)具有高電壓VDDH，藉此防止一漏電流 147730.doc -35- 201110549 路徑。另夕卜，中間電壓VDDhm據—操作電壓（亦即，第一 電源供應器侧之電歷）而改變，以增加低電壓操作停件 下的接收器輸入節點IR之擺動位準，藉此減少接收資料中 之錯㈡之發生。又，在自接收模式轉變至傳輸模式時，使 用時序控制方法對1/0塾處剩餘之高電位電荷進行放電， 藉此防止熱載子注入。 圖10為圖9中所說明之1/0電路3〇〇之修改3〇〇a的電路 圖。t看圖10,1/0電路300a包括傳輸器310、接收器 320、月置驅動器33〇及時序/位準控制器鳩a。ι/〇電路 3〇〇a中所包括之傳輸器3 1〇、接收器咖及前置驅動器咖 與圖9中所說明之1/〇電路3〇〇中所包括的彼等元件相同， 仁I/O電路30〇a中所包括之時序/位準控制器3他不同於"。 電路300中所包括之時序/位準控制器34〇。因此，將主要 描述I/O電路300與1/〇電路3〇〇a之間的差別。 時序/位準控制器3術中所包括之腿⑽電晶體連接 於上拉節點PU與第一上拉電晶體ΜΡ0之閘極（亦即，節點 G〇)之間’且具有連接至第—電源供應器VDD之-間極。 可如將圖1中所說明之1/〇電路1〇〇修改為圖4中所說明之 I/O電路iOOc來修改1/〇電路3〇〇、3_。換言之下拉電晶 體ΜΝ0之閘極可連接至第一電源供應器，且"〇電路 00 300a亦可包括一接收開關電晶體，該接收開關電晶 體連接於I / Ο節點N 〇與接收器3 2 〇之間且具有一接收中間= 壓VDDM之閘極。在圖u中說明此修改之―實例。如上文 所描述，可以各種方式來修改根據本發明之發明概念之一 I47730.doc -36- 201110549 例示性實施例的I/O電路。 圖13及圖14說明根據本發明之發明概念之至少一例示性 實施例的積體電路（1C)裝置的實例，該積體電路（1C)裝置 使用一I/O電路。220 compartment drive 230, timing/level controller 240 and transmission controller 25A. The transmitter 210, the pre-driver 23A, and the receiver 22 are the same as the transmitter no, the pre-driver 130, and the receiver 12() illustrated in FIG. Therefore, the description thereof will be omitted. The timing/level controller 24 includes an extension, a NOR gate, an inverter INV2, a NAND gate, a first level shifter lci, and a third level shift IILC3. The delay unit 241 delays the output enable signal (10) by a predetermined delay time (e.g., the first delay time), and the output of the output delay enables the letter D. The inter-service job output enable signal delay is enabled to enable the signal-to-service operation and the resulting signal is provided as an input to the level-shifter LC1. Therefore, the job N〇r〇: the output signal is an anti-trust II with one of the extended pulse width output enable signals. . The delayed output enable signal is also input to the pre-driver. The inverter INV2 causes the delay to be turned out. 斟^山仏 By using 1 port 唬0ED inversion. The NAND gate is in reverse phase (4) NAND operation, and the m~m lamp is built and the resulting signal is provided as the input to the third level 147730.doc -27- 201110549 shifter LC3. The first level shifter LC1 illustrated in Fig. 6 is identical to the first bit shifter LC1 illustrated in Fig. 1. Therefore, the description thereof will be omitted. Like the first level shifter LC1, the third level shifter LC3 converts the ground level and the voltage level of the first power supply VDD into the voltage level of the first power supply VDD and the high voltage VDDH, respectively. The voltage level (as illustrated in Figure 12C). The transmission controller 250 includes a pull-up switch coupled between the pull-up node Pu and one of the output nodes of the pre-driver 230. The pull-up switch can be implemented by a transmission gate including an NMOS transistor MN2 and a PMOS transistor MP2. The transmission controller 250 also includes a PMOS transistor MP1 connected between the pull-up point PU and the I/O node NO; a PMOS transistor MP3 connected to the gate and I/O node of the PMOS transistor MP2; Between the 〇; and the NM〇s transistor MN3, which is connected to the connection node (ie, a receiver input node IR between the first pull-down transistor MN〇 and the second pull-down transistor MN1) and the PMOS transistor Between the gates of MP2. The third level shifter LC3 controls the interpole of the NMOS transistor MN2 included in the flywheel controller 25A, and is therefore referred to as a switch control level shifter. The gate of the PM〇s transistor Μρι and Mp3 is connected to the first power supply VDD, and the gate of the NMOS transistor MN3 is connected to the output of the inverter INV2. The cyber sequence/level controller 240 may also include two NM 〇s transistors MN4 and MN5 connected in series to the pM 〇s transistor of the pull-up switch 147730.doc -28 - 201110549 and the second voltage Between nodes GND. One of the gates of the NMOS transistor MN4 is connected to the first power supply VDD, and the delayed output enable signal OED is input to the gate of the NMOS transistor MN5. The two NMOS transistors MN4 and MN5 are used to maintain the node GP2 at the ground level. According to the current embodiment of the inventive concept of the present invention, the body node PB of the pull-up transistor ΜΡ0 is pulled up to the voltage level of the high voltage VDDH in the receiving mode, thereby preventing the formation of the non-going person through the pull-up transistor ΜΡ0. See one of the current paths. In addition, in the receiving mode, the gate of the first pull-down transistor ΜΝ0 is pulled up to the voltage level of the intermediate voltage VDDM, thereby increasing the swing level of the I/O node NO. Therefore, even under low voltage operating conditions, the swing level of the input data is not limited. When transitioning from the receive mode to the transmit mode, the voltage at node GN2 (ie, the gate of NMOS transistor MN2 of the pull-up switch) transitions to the voltage level of high voltage VDDH, thereby bringing the pull-up node PU high The potential charge is transferred to the first power supply VDD. FIG. 7 is a circuit diagram of a modification 200a of the I/O circuit 200 illustrated in FIG. The I/O circuit 200a is similar to the I/O circuit 200 illustrated in FIG. 6, and therefore, the difference between the I/O circuit 200a and the I/O circuit 200 will be mainly described. The timing/level controller 140 illustrated in Figure 7 is identical to the timing/level controller 140 illustrated in Figure 1 . Therefore, the NMOS transistor MN2 of the pull-up switch is controlled by the output of the second level shifter LC2. In the I/O circuit 200 illustrated in FIG. 6, the gate of the NMOS transistor MN3 is connected to the output of the inverter INV2, but in the I/O circuit 200a illustrated in FIG. 7, the NMOS transistor MN3 The gate is connected to the first power supply VDD. 147730.doc -29- 201110549 The I/O circuit H) can be modified as shown in Figure 1 to modify the 1/〇 circuit to modify the 1/〇 circuit. In other words, the gate of the pull-down transistor ΜΝ0 can be connected to the first power supply VDD, and the I/O circuit 200 200a can also be used. Including the receiving switch transistor, the receiving switch transistor is connected to the I/O node N 丨 丨 丨 > 0. A n-day >, between the receivers 220 and having a gate that receives the intermediate voltage VDDM. Inspiration. An example of this modification is illustrated in Mountain _ Shepherd 8 Fig. 8 is a τ/〇 说明 illustrated in Fig. 6. . A circuit diagram of another modification 200b of the I/O circuit 200 of 〇 & The I/O circuit 2〇〇b includes the & μ — α < 兀 说明 说明 相比 相比 相比 相比 相比 〜 〜 相比 相比 相比 相比 相比 相比 相比 相比 相比 相比 相比 相比 相比The same pre-driver 23〇, transmission controller 25〇 and timing ^ & level controller 240, and a different value than the transmitter 210 illustrated in Fig. 6 is in the „.^^ The 'and-in' step includes a receiving switch transistor. The receiving switch φ is connected between the I/O node NO and the receiver 220 and has a buckle. The plague is one of the gates of the intermediate voltage VDDM. Because the gate of the receiving switch transistor has the voltage level of the intermediate voltage VDDM, the receiving benefit input point IR swings between the voltage of the first power supply and the voltage of the second voltage node GND. In FIG. 8, the first pull-down transistor function included in the 1/〇 circuit 2嶋 of the household is not in the receiving mode, and therefore, the voltage voltage vddm of the first power supply VDD is applied to the first pull-down. The gate of the transistor ΜΝ0. As described above, the intermediate voltage vddm can follow the voltage of the first power supply VDD Figure 9 is a circuit diagram of a 1/〇 circuit 300 in accordance with another embodiment of the inventive concept of the present invention. The I/O circuit 300 includes a transmitter 31, a receiver 32, a pre-driver 330, and timing/ The level controller 34. The pre-driver 33A and 147730.doc • 30·201110549 The receiver 320 is the same as the pre-driver 130 and the receiver 120 illustrated in Fig. 1. Therefore, the description thereof will be omitted. The first pull-up transistor ΜΡ0, the second pull-up transistor MP1, the first pull-down transistor ΜΝ0, and the second pull-down transistor MN1 are included. The first pull-up transistor ΜΡ0 and the second pull-up transistor MP1 are connected in series Between the first power supply VDD and the I/O node NO. One of the gates of the second pull-up transistor MP1 (ie, the pull-up node PU) is connected to one of the outputs of the pre-driver 330. The first pull-up The substrate of the crystal ΜΡ0 and the second pull-up transistor MP1 (that is, the common body node PB) is connected to the output of the first level shifter LC1. The first pull-down transistor ΜΝ0 is connected in series with the second pull-down transistor MN1. Between the I/O node NO and the second voltage node GND. The first pull-down One of the gates of the body 0 is connected to the intermediate voltage VDDM, and one of the gates of the second pull-down transistor MN1 is connected to the other output of the pre-driver 330. The timing/level controller 340 includes a delay unit 341, a NOR gate NR0, NAND gate ND0, inverter INV2, level shifter LC1, NMOS transistor MN2, and PMOS transistor MP2. When transitioning from the receive mode to the transfer mode, the timing/level controller 340 controls the first pull-up transistor共同0 and the common body node PB of the second pull-up transistor MP1 to have a voltage of the first power supply VDD for a predetermined delay time to transmit the high potential charge at the I/O node NO to the first power source The supplier VDD and then the output data DOUT is transmitted to an external device via the I/O node NO. In the receive mode, the timing/level controller 340 controls the common body node PB to have a high voltage VDDH. Since 147730.doc •31 - 201110549, the leakage current through the first pull-up transistor ΜΡ0 and the second pull-up transistor MP1 is prevented from occurring. The delay unit 341 delays the output enable signal OE for a predetermined delay time (e.g., the first delay time) and outputs the delayed output enable signal OED. The inverter INV2 inverts the delayed output enable signal OED. The NAND gate ND0 performs a NAND operation on one of the signals generated by the delay unit 341 (the delay unit 341 delays the output enable signal OE for a second delay time) and one of the output signals of the inverter INV2. At this time, the phase of the signal generated by delaying the output enable signal OE by the second delay time may be different from the phase of the delayed output enable signal OED. The PMOS transistor MP2 is controlled by the output signal of the NAND gate ND0 and is connected between the gate of the first pull-up transistor ΜΡ0 (i.e., the node GO) and the common body node PB. The NMOS transistor MN2 is connected between the inverter INV2 and the node G0 (i.e., the gate of the first pull-up transistor ΜΡ0) and has a gate connected to the first power supply VDD. The level shifter LC 1 is the same as the first level shifter LC 1 described above. In other words, the level shifter LC1 converts the voltage level of the second voltage node GND (ie, the ground level) and the voltage level of the first power supply VDD into the voltage level of the first power supply VDD. And the voltage level of the high voltage VDDH, as illustrated in Figure 12A. The high voltage VDDH may be twice the voltage of the first power supply VDD or a high voltage similar to the external device interfaced by the I/O circuit 300. The intermediate voltage VDDM and the high voltage VDDH which are higher than the voltage of the first power supply VDD can be generated by an internal voltage generator (not shown). The internal voltage generator can include a charge pump in 147730.doc -32· 201110549. The high voltage VDDH is used in the receiving mode to pull up the body node PB, thereby preventing the formation of a current path through the first pull-up transistor ΜΡ0 and the second pull-up transistor MP1. In other words, the leakage current path through one of the first pull-up transistor ΜΡ0 and the second pull-up transistor MP1 is prevented from being formed in the receiving mode. The intermediate voltage VDDM is used to pull up the gate of the first pull-down transistor ,0, thereby achieving a low voltage operating condition. In other words, the intermediate voltage VDDM is used to control the gate of the first pull-down transistor ΜΝ0 to increase the limited swing level. As described above, the intermediate voltage VDDM can be varied depending on the reliability of the gate oxide and the low voltage operation. For example, when the voltage of the first power supply VDD is relatively high, the intermediate voltage VDDM can be set to be similar to the voltage of the first power supply VDD to reduce the stress on the gate oxide. When the voltage of the first power supply VDD is relatively low (that is, under low voltage operating conditions), the intermediate voltage VDDM is set equal to or higher than the voltage of the first Q power supply VDD or higher than the first power supply VDD. The voltage (for example, VDD+Vthn). Additionally, as described above, a timing control method is used to prevent "hot carrier injection that may occur when transitioning from the receive mode to the transmit mode. In other words, when the reception mode is switched to the transmission mode, the remaining rain potential charge at I / 0 is discharged before the transmission of the tribute', thereby preventing hot carrier injection. In a multiple I/O system with multiple I/O pads, the timing/level controller 340 can be used in conjunction with all I/O pads. Therefore, the necessary area is reduced. The operation of the I/O circuit 300 will be described below. 147730.doc •33- 201110549 In the transmission mode for transmitting the output data DOUT to an external device, both the pull-up node PU and the pull-down node PD are at a logic high level or a logic low level in order to output data. DOUT is transferred to the I/O pad. When both the pull-up node PU and the pull-down node PD are at a logic high level, the I/O pad is driven at the voltage of the second voltage node GND. When both the pull-up node PU and the pull-down node PD are at a logic low level, the I/O pad is driven at the voltage of the first power supply VDD. The output of the level shifter LC 1 has the voltage level of the first power supply VDD, and the body node PB thus has the voltage level of the first power supply VDD. Therefore, the bulk effects of the first pull-up transistor ΜΡ0 and the second pull-up transistor MP1 are prevented. The output enable signal OE is at a logic high level, and thus the output signal of the inverter INV2 is at a logic low level. Therefore, the gate of the first pull-up transistor MP0 (i.e., node G0) maintains the voltage having the second voltage node GND via the NMOS transistor MN2. The second output data of the pre-driver 330 is transmitted to the pull-down node PD. Therefore, the second pull-up transistor MP1 and the second pull-down transistor MN1 are selectively turned on in response to the first output data and the second output data, thereby driving the I/O at the voltage of the first power supply VDD The node NO (or supplies current to the external device via the I/O node NO) or drives the I/O node NO (or sinks current from the I/O node NO to ground) at the voltage of the second voltage node GND. Meanwhile, in the receiving mode for receiving input data from an external device, the first pull-up transistor ΜΡ0 and the second upper transistor MP1 and the second pull-down transistor MN1 of the transmitter 3 10 are disconnected to pass through the I. The input data is transmitted to the receiver 320 by the 147730.doc -34- 201110549 received by the /O pad. The voltage at the body node PB has a voltage level of a high voltage VDDH and does not change according to the input data. Since the voltage at the main node PB is maintained at the voltage level of the high voltage VDDH, leakage current through one of the first pull-up transistor ΜΡ0 and the second pull-up transistor MP1 is prevented from occurring (ie, it is not desirable for us) Current). The node G0 also becomes a high voltage VDDH via the PMOS transistor MP2, so that leakage current through one of the first pull-up transistor ΜΡ0 and the second pull-up transistor MP1 is prevented from occurring. The pull-up node PU and node S2 have a voltage of the first power supply VDD, and the voltage at the pull-down node PD is at a low level. Therefore, the second pull-down transistor MN1 is turned off. The gate of the first pull-down transistor ΜΝ0 has an intermediate voltage VDDM, and therefore, the receiver input node IR swings between the voltage of the first power supply VDD and the voltage of the second voltage node GND. Thereafter, when the output enable signal OE is activated and enters the transmission mode, the body node PB has the voltage of the first power supply VDD, and the voltage at the node G2 is at a logic low level for a delay time. At this time, the voltage at the node G2 is at about a threshold voltage level due to the NAND gate ND0 and the diode D1 connected between the NAND gate ND0 and the ground. Therefore, the gate oxide stress at the PMOS transistor MP2 is reduced. Therefore, the high potential charge stored at the I/O pad and node G0 is transferred to the first power supply VDD via the PMOS transistors ΜΡ0, MP1, and MP2. As described above, according to the current embodiment of the inventive concept of the present invention, the substrate of the first pull-up transistor ΜΡ0 and the second pull-up transistor MP1 (that is, the common body node PB) has a high voltage VDDH, thereby preventing A leakage current 147730.doc -35- 201110549 path. In addition, the intermediate voltage VDDhm is changed according to the operating voltage (ie, the electrical history of the first power supply side) to increase the swing level of the receiver input node IR under the low voltage operation stop, thereby reducing The occurrence of the error (2) in the received data. Further, during the transition from the reception mode to the transmission mode, the remaining high potential charge at 1/0 进行 is discharged using the timing control method, thereby preventing hot carrier injection. Fig. 10 is a circuit diagram showing a modification 3〇〇a of the 1/0 circuit 3A illustrated in Fig. 9. Referring to Figure 10, the 1/0 circuit 300a includes a transmitter 310, a receiver 320, a monthly driver 33A, and a timing/level controller 鸠a. The transmitter 3 1〇, the receiver coffee, and the pre-driver included in the ι/〇 circuit 3〇〇a are the same as those included in the 1/〇 circuit 3〇〇 illustrated in FIG. 9, The timing/level controller 3 included in the I/O circuit 30A is different from ". The timing/level controller 34A included in circuit 300. Therefore, the difference between the I/O circuit 300 and the 1/〇 circuit 3〇〇a will be mainly described. The leg (10) transistor included in the timing/level controller 3 is connected between the pull-up node PU and the gate of the first pull-up transistor (0 (ie, node G〇) and has a connection to the first power source Supply VDD - the pole. The 1/〇 circuit 3〇〇, 3_ can be modified by modifying the 1/〇 circuit 1〇〇 illustrated in Fig. 1 to the I/O circuit iOOc illustrated in Fig. 4. In other words, the gate of the pull-down transistor ΜΝ0 can be connected to the first power supply, and the 〇 circuit 00 300a can also include a receiving switch transistor connected to the I / Ο node N 〇 and the receiver 3 Between 2 且 and with a gate that receives the intermediate = voltage VDDM. An example of this modification is illustrated in Figure u. As described above, the I/O circuit of the exemplary embodiment in accordance with one of the inventive concepts of the present invention, I47730.doc-36-201110549, can be modified in various ways. 13 and 14 illustrate an example of an integrated circuit (1C) device in accordance with at least one exemplary embodiment of the inventive concept, the integrated circuit (1C) device using an I/O circuit.
圖13為根據本發明之發明概念之一例示性實施例的記憶 體系統500的方塊圖。該記憶體系統包括記憶體器件52〇， 及控制記憶體器件520之記憶體控制器51 〇。記憶體控制器 510包括經由一匯流排5 15通信之SRAM 511、CPU 512、主 機介面513及記憶體介面514 ^記憶體器件包括記憶體核心 530，記憶體核心530與晶片控制器540通信，晶片控制器 540又與I/O電路550通信，I/O電路55〇可藉由本文中所描述 的發明之發明概念之例示性實施例中的至少一者來實施。 根據本發明之發明概念之一例示性實施例的半導體記憶 體器件或記憶體模組亦可用於一計算系統（例如，行動設 備或桌上型電腦）中。在圖14中說明計算系統之一實例。 參看圖14，計算系統700包括根據本發明之發明概念之一 例示性實施例的記憶體系統500、電源供應器71〇、中央處 理單元（CPU)720、隨機存取記憶體（RAM)73〇及使用者介 面740，該等元件經由一系統匯流排75〇而彼此電連接。 如上文所描述，根據本發明之發明概念之一例示性實施 例，一上拉電晶體之基板（亦即，主體節點）具有一高電 壓’藉此防止-漏電流路徑。另外，一中間電壓根據—操 作電壓而改變，以增加低電壓操作條件下的接❹輪入二 點之擺動位準，以使得甚至在低電壓操作環境中亦可； 147730.doc -37· 201110549 地確保接收資料之電塵。因此，可減少接收資料 的發生。此外，在自接收模式轉變至傳輸模式時，在將 t 出資料傳輸至外部器件之前，使用時序控制方法 處剩餘之高電位電荷進行放電，以便防止熱载子注入= 此，甚至在低電屢操作環境中，亦可防止接收模 電，、自接收模式轉變至傳輸模式時的熱載子注入= 極氧化物之可靠性的減小。 甲 然已參考本發明之發明概念之例示性實施例來特別展 不及描述本發明之發明概念，但—般熟習 :广偏離如藉由以下申請專利㈣定義的:::： ==之精神及範嘴的情況下，在本文中作出形式及細 即上的各種改變。 【圖式簡單說明】 圖1為根據本發明之於人 _ 考月概心之一例不性實施例的輸入/ 輸出d/ο)電路的電路圖； 圖2為圖1中所說明之1/0電路之修改的電路圖； 圖3為圖!中所說明之1/〇電路之另一修改的電路圖； 圖4為圖1中所說明之1/0電路之另-修改的電路圖； 圖5為圖1中所說明之1/〇電路之另一修改的電路圖； 沾為根據本發明之發明概念之一例示性實施例的而電 路的電路圖； 8為圖6中所説明之1/〇電路之修改的電路圖； 圖9為圖6中所說明之1/〇電路之另一修改的電路圖； '、據本發明之發明概念之一例示性實施例的I/O電 147730.doc •38- 201110549 路的電路圖， 圖10為圖9中所說明之I/O電路之修改的電路圖； 圖11為圖9中所說明之I/O電路之另一修改的電路圖； 圖12A、圖12B及圖12C分別為說明第一位準移位器、第 一位準移位器及第二位準移位器中之1/〇信號之位準的示 意圖；及 圖U及圖14說明根據本發明之發明概念之一例示性實施 ΟFIG. 13 is a block diagram of a memory system 500 in accordance with an exemplary embodiment of the inventive concepts of the present invention. The memory system includes a memory device 52A, and a memory controller 51 that controls the memory device 520. The memory controller 510 includes an SRAM 511, a CPU 512, a host interface 513, and a memory interface 514 that communicate via a bus 515. The memory device includes a memory core 530, and the memory core 530 communicates with the wafer controller 540. Controller 540 is in turn in communication with I/O circuitry 550, which may be implemented by at least one of the illustrative embodiments of the inventive concepts described herein. A semiconductor memory device or memory module in accordance with an exemplary embodiment of the inventive concept may also be used in a computing system (e.g., a mobile device or a desktop computer). An example of a computing system is illustrated in FIG. Referring to Figure 14, a computing system 700 includes a memory system 500, a power supply 71, a central processing unit (CPU) 720, and a random access memory (RAM) 73 in accordance with an exemplary embodiment of the inventive concept of the present invention. And the user interface 740, the components are electrically connected to each other via a system bus bar 75 。. As described above, according to an exemplary embodiment of the inventive concept of the present invention, a substrate (i.e., a body node) of a pull-up transistor has a high voltage ' thereby preventing a leakage current path. In addition, an intermediate voltage is changed according to the operating voltage to increase the swing level of the two-point turn in the low-voltage operating condition, so that even in a low-voltage operating environment; 147730.doc -37· 201110549 Ensure the reception of electrical dust. Therefore, the occurrence of received data can be reduced. In addition, during the transition from the receive mode to the transfer mode, the high-potential charge remaining at the timing control method is used to discharge the t-out data before the data is transferred to the external device to prevent hot carrier injection = this, even in low-voltage In the operating environment, it is also possible to prevent the reception of the mode, and the hot carrier injection when the mode is changed from the reception mode to the transmission mode = the reliability of the electrode oxide is reduced. The exemplary embodiments of the inventive concept of the present invention have been specifically described with reference to the inventive concept of the present invention, but it is generally understood that the broad deviation from the spirit of::::== as defined by the following patent application (d) In the case of Fan Mouth, various changes in form and detail are made in this paper. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of an input/output d/o circuit according to an embodiment of the present invention; FIG. 2 is a 1/0 illustrated in FIG. Figure 3 is a circuit diagram of another modification of the 1/〇 circuit illustrated in Figure!; Figure 4 is a further modified circuit diagram of the 1/0 circuit illustrated in Figure 1; Figure 5 is a diagram A circuit diagram of another modification of the 1/〇 circuit illustrated in FIG. 1; a circuit diagram of a circuit according to an exemplary embodiment of the inventive concept; 8 is a modification of the 1/〇 circuit illustrated in FIG. FIG. 9 is a circuit diagram of another modification of the 1/〇 circuit illustrated in FIG. 6; 'I/O 147730.doc • 38- 201110549 road according to an exemplary embodiment of the inventive concept of the present invention FIG. 10 is a circuit diagram showing a modification of the I/O circuit illustrated in FIG. 9. FIG. 11 is a circuit diagram showing another modification of the I/O circuit illustrated in FIG. 9. FIG. 12A, FIG. 12B, and FIG. Schematic diagram for explaining the level of the 1/〇 signal in the first level shifter, the first level shifter, and the second level shifter FIG. 1 and FIG. 14 illustrate an exemplary implementation of an inventive concept in accordance with the present invention.
例的積體電路（IC)裝置的實例，該積體電路⑽裝置使用 一 I/O電路。 【主要元件符號說明】 100 l〇〇a l〇〇b 10〇c l〇〇d 110 ll〇a 110b 120 130 140 140a 140b 141 輸入/輸出（I/O)電路 I/O電路 I/O電路 I/O電路 I/O電路 傳輸器 傳輪器 傳輸器 接收器 月!J置驅動器 時序/位準控制器 時序/位準控制器 時序/位準控制器 延遲單元 147730.doc -39- 201110549 150 傳輸控制器 150a 傳輸控制器 150b 傳輸控制器 200 I/O電路 200a I/O電路 200b I/O電路 210 傳輸器 210a 傳輸器 220 接收器 230 前置驅動器 240 時序/位準控制器 241 延遲單元 250 傳輸控制器 300 I/O電路 300a I/O電路 300b I/O電路 310 傳輸器 320 接收器 330 前置驅動器 340 時序/位準控制器 340a 時序/位準控制器 341 延遲單元 500 記憶體系統 510 記憶體控制器 147730.doc -40- 201110549An example of an integrated circuit (IC) device of the example, the integrated circuit (10) device uses an I/O circuit. [Main component symbol description] 100 l〇〇al〇〇b 10〇cl〇〇d 110 ll〇a 110b 120 130 140 140a 140b 141 Input/output (I/O) circuit I/O circuit I/O circuit I/ O circuit I / O circuit transmitter passer transmitter receiver month! J set driver timing / level controller timing / level controller timing / level controller delay unit 147730.doc -39- 201110549 150 transmission control Transmitter 150a transmission controller 150b transmission controller 200 I/O circuit 200a I/O circuit 200b I/O circuit 210 transmitter 210a transmitter 220 receiver 230 pre-driver 240 timing/level controller 241 delay unit 250 transmission control 300 I/O circuit 300a I/O circuit 300b I/O circuit 310 transmitter 320 receiver 330 pre-driver 340 timing/level controller 340a timing/level controller 341 delay unit 500 memory system 510 memory Controller 147730.doc -40- 201110549
D ❹ 511 SRAM 512 CPU 513 主機介面 514 記憶體介面 515 匯流排 520 記憶體器件 530 記憶體核心 540 晶片控制器 550 I/O電路 700 計算系統 710 電源供應 720 中央處理單元（CPU) 730 隨機存取記憶體（RAM) 740 使用者介面 750 系統匯流排 D1 二極體 DIN 接收資料 DOUT 輸出資料 GO 節點 G2 節點 GN2 節點 GND 第二電壓節點 GP2 節點 INYO 反相器 147730.doc -41 - 201110549 IN VI 反相器 INV2 反相器 INV2f 反相器 IR 接收器輸入節點 LC1 第一位準移位器 LC2 第二位準移位器 LC3 第三位準移位器 MNO 第一下拉電晶體 MN1 第二下拉電晶體 MN2 上拉開關電晶體 MN3 接收開關電晶體 MPO 第一上拉電晶體 MP1 第二上拉電晶體 MP2 第二上拉電晶體 MP3 PMOS電晶體 NDO NAND 閘 ND1 NAND 閘 ND2 NAND 閘 NO I/O節點 NORO NOR閘 NOR1 NOR閘 NRO NOR閘 OE 輸出啟用信號 OED 延遲之輸出啟用信號 147730.doc -42· 201110549D ❹ 511 SRAM 512 CPU 513 Host Interface 514 Memory Interface 515 Bus 520 Memory Device 530 Memory Core 540 Chip Controller 550 I/O Circuit 700 Computing System 710 Power Supply 720 Central Processing Unit (CPU) 730 Random Access Memory (RAM) 740 User Interface 750 System Bus D1 Diode DIN Receive Data DOUT Output Data GO Node G2 Node GN2 Node GND Second Voltage Node GP2 Node INYO Inverter 147730.doc -41 - 201110549 IN VI Phase INV2 Inverter INV2f Inverter IR Receiver Input Node LC1 First Bit Quasi-Shifter LC2 Second Level Shifter LC3 Third Level Shifter MNO First Pulldown Transistor MN1 Second Pulldown Transistor MN2 Pull-up switch transistor MN3 Receive switch transistor MPO First pull-up transistor MP1 Second pull-up transistor MP2 Second pull-up transistor MP3 PMOS transistor NDO NAND gate ND1 NAND gate ND2 NAND gate NO I/ O node NORO NOR gate NOR1 NOR gate NRO NOR gate OE output enable signal OED delayed output enable signal 147730.doc -42· 201110 549
PB 主體節點 PD 下拉節點 PDB 下拉信號之反相信號 PU 上拉節點 S2 節點 VDD 第一電源供應器 VDDH 高電壓 VDDM 中間電壓PB body node PD pull-down node PDB pull-down signal inversion signal PU pull-up node S2 node VDD first power supply VDDH high voltage VDDM intermediate voltage
147730.doc 43-147730.doc 43-
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020090034870A KR20100116253A (en) | 2009-04-22 | 2009-04-22 | Input/output circuit and integrated circuit apparatus including the same |
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| Publication Number | Publication Date |
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| TW201110549A true TW201110549A (en) | 2011-03-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| TW099112719A TW201110549A (en) | 2009-04-22 | 2010-04-22 | Input/output circuit and integrated circuit apparatus including the same |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US8004311B2 (en) |
| KR (1) | KR20100116253A (en) |
| DE (1) | DE102010016422A1 (en) |
| TW (1) | TW201110549A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI570720B (en) * | 2013-09-27 | 2017-02-11 | Ａｒｍ股份有限公司 | Integrated circuit with signal assist circuitry and method of operating the circuit |
| CN110121227A (en) * | 2018-02-07 | 2019-08-13 | 义隆电子股份有限公司 | The integrated circuit of imput output circuit with multistage output electric current |
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| US10164635B2 (en) * | 2011-12-16 | 2018-12-25 | Intel Corporation | Low voltage transmitter with variable output swing |
| JP5594546B2 (en) * | 2012-03-02 | 2014-09-24 | 横河電機株式会社 | Input protection circuit |
| KR20140025012A (en) * | 2012-08-20 | 2014-03-04 | 에스케이하이닉스 주식회사 | Semiconductor memory device |
| US9000799B1 (en) * | 2013-10-01 | 2015-04-07 | Texas Instruments Incorporated | Method to achieve true fail safe compliance and ultra low pin current during power-up sequencing for mobile interfaces |
| TWI752898B (en) * | 2014-03-25 | 2022-01-21 | 日商新力股份有限公司 | Signaling devices and communication systems |
| US9910482B2 (en) | 2015-09-24 | 2018-03-06 | Qualcomm Incorporated | Memory interface with adjustable voltage and termination and methods of use |
| CN107196639B (en) * | 2017-05-25 | 2020-09-29 | 湖南工学院 | Multi-path parallel bidirectional level conversion circuit |
| KR102311490B1 (en) * | 2017-05-26 | 2021-10-13 | 에스케이하이닉스 주식회사 | Memory device and memory system having input buffer circuit |
| KR102514241B1 (en) | 2017-12-05 | 2023-03-27 | 삼성전자주식회사 | Level shifter circuit |
| US10812138B2 (en) | 2018-08-20 | 2020-10-20 | Rambus Inc. | Pseudo-differential signaling for modified single-ended interface |
| US10389358B1 (en) * | 2018-09-07 | 2019-08-20 | Apple Inc. | Transmit-receive switch |
| EP3644501B1 (en) * | 2018-10-24 | 2021-12-15 | ams International AG | Output driver with reverse current blocking capabilities |
| US11677399B1 (en) * | 2022-01-04 | 2023-06-13 | Nanya Technology Corporation | Interface circuit |
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| US5144165A (en) * | 1990-12-14 | 1992-09-01 | International Business Machines Corporation | CMOS off-chip driver circuits |
| JP3031195B2 (en) * | 1995-02-28 | 2000-04-10 | 株式会社日立製作所 | I / O buffer circuit device |
| DE69621576T2 (en) * | 1995-12-26 | 2002-12-19 | Kabushiki Kaisha Toshiba, Kawasaki | Integrated semiconductor circuit |
| KR100223744B1 (en) | 1995-12-29 | 1999-10-15 | 김영환 | Mixed voltage input buffer |
| US6838908B2 (en) * | 2003-03-28 | 2005-01-04 | Industrial Technology Research Institute | Mixed-voltage I/O design with novel floating N-well and gate-tracking circuits |
| WO2008010482A1 (en) | 2006-07-19 | 2008-01-24 | Keio University | Optical elasticity measuring method and its device |
| TW200828806A (en) * | 2006-12-29 | 2008-07-01 | Univ Nat Chiao Tung | Mixed voltage input/output buffer |
-
2009
- 2009-04-22 KR KR1020090034870A patent/KR20100116253A/en not_active Application Discontinuation
-
2010
- 2010-03-01 US US12/714,878 patent/US8004311B2/en active Active
- 2010-04-13 DE DE102010016422A patent/DE102010016422A1/en not_active Withdrawn
- 2010-04-22 TW TW099112719A patent/TW201110549A/en unknown
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI570720B (en) * | 2013-09-27 | 2017-02-11 | Ａｒｍ股份有限公司 | Integrated circuit with signal assist circuitry and method of operating the circuit |
| CN110121227A (en) * | 2018-02-07 | 2019-08-13 | 义隆电子股份有限公司 | The integrated circuit of imput output circuit with multistage output electric current |
| TWI687130B (en) * | 2018-02-07 | 2020-03-01 | 義隆電子股份有限公司 | Integrated circuit with a multi-output-current input and output circuit |
| CN110121227B (en) * | 2018-02-07 | 2021-08-27 | 义隆电子股份有限公司 | Integrated circuit having multi-stage output current I/O circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| US20100271069A1 (en) | 2010-10-28 |
| KR20100116253A (en) | 2010-11-01 |
| DE102010016422A1 (en) | 2010-11-18 |
| US8004311B2 (en) | 2011-08-23 |
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