201036134 六、發明說明： 【發明所屬之技術領域】 本發明係有關具銅凸塊之堆疊結構，尤其是最上層具有銅柱接腳 之銅凸塊的電路基板。 【先前技術】 晶圓焊錫凸塊技術(Solder Bumping)是先利用薄膜、黃光及電鍍 製程或印刷技術於晶片鋁墊上製作焊錫凸塊，在於後段1C封裝製程 0 上，利用熱能將凸塊熔融，與電路基版上之錫墊進行封裝(assembly)。 此技術可大幅縮小1C封裝的體積，並具有密度大、低感應、低成本、 散熱能力佳等優點。 參閱第一圖，焊鉛凸塊技術之積體電路結構示意圖，其中積體電 路板1包含一晶粒層10以及一電路基板20，此晶粒層10上具有複數 個晶粒接腳12藉著焊料30與電路基板20上的基板接腳22相接合， 其中晶粒接腳12與基板接腳22的凸塊間距dl製作極限為15〇〜18〇um。 參閱第二圖，焊鉛凸塊技術之積體電路結構的另一示意圖，其中 〇每個晶粒接腳12與晶粒接腳之間以及每個基板接腳22與基板接腳 22之間排列較密而使凸塊間距d2縮小，當藉著焊料3〇使晶粒層ι〇 與電路基板20相接合時，則會產生焊料3〇短路的風險。 【發明内容】 本發明之主要目的在提供—種油凸塊之堆疊結構，係包括複數個導 電銅層、複數個絕緣層以及複數個銅凸塊，其中複數個導電銅層與複 數個絕緣層相互堆位於最上層的為第-導電銅層，並在第— ^上形成=數個鋼凸塊，用以焊接到晶粒接腳。藉著銅凸塊表面與 ;:間的内聚力’使得焊料形狀為長條狀而非球體狀，因此減少焊料 3 201036134 之間的距離’進而使晶粒接腳之間的間距設計以及銅凸塊之間的間距 設計得以縮小，使得整體積體電路板結構也可跟著縮小或在相同面積 内可設計更多接腳數量。 因此本發明可解決上述習知技術的缺失，利用第一導電銅層上具 有一定高度的銅凸塊與焊料的特性，使得接腳可排列得更密集，且可 以降低焊接時焊料短路的風險。 【實施方式】 以下配合圖式及元件符號對本發明之實施方式做更詳細的說明， 俾使熟習該項技藝者在研讀本說明書後能據以實施。 參閱弟三圖，本發明第一實施例之示意圖，此具銅凸塊之堆疊 結構2係包括第一導電銅層40、銅凸塊41、第一絕緣層5〇以及第一 綠漆層60,其中第一導電銅層4〇具有一電路圖案（圖中未顯示），該電 路圖案係覆蓋該第一絕緣層40的部份上表面，該電路圖案具有複數個 銅凸塊41。該些銅凸塊41各具有一底部4ib以及一凸起部4la，該凸 起部41a位於該底部41b的上方，該凸起部4ia具有一寬度與一高度 以及該底部41b具有-寬度與-高度，而該凸起部41a的寬度比該底 部41b的寬度小。帛-綠漆層60係、覆蓋第一、絕緣層5〇的上表面中未 被電路_覆㈣部份以及覆蓋魏路圖案巾未被該物凸塊41覆蓋 的部份。 參閱第四®，本發明第二實施例之示意圖，此具銅凸塊之堆疊結 構3係包括第-導電銅層40、銅凸塊4卜第二導電銅層42、第三導電 銅層44、第-絕緣層50、第二絕緣層52、第一綠漆層6〇卩及第二綠 漆層62’其中第-導電銅層40具有一電路圖案（圖中未顯示），該電路 圖案係覆蓋該第-絕緣層4G的部份上表面，該魏圖案具有複數個銅 凸塊41。該些銅凸塊41各具有-底部41b以及一凸起部仙，該凸起 4 201036134 4 41a位於該底揭上方，該凸起部仙具有一寬度與一高度以及該 底部仙具有一寬度與—高度，且該凸起部41a的寬度比該底部41b 的寬度小。第—綠漆層60倾蓋第-職層50的上表面中未被電路 圖案覆蓋的部份以及覆蓋該電路圖案中未被該等銅凸塊41覆蓋的部 伤該第一導電銅層42具有一電路圖案，且該電路圖案係位於該第一 絕緣層50的部分下表面與該第二絕緣層犯的部分上表面之間。該第 二導電銅層44具有-f闕案，且該電關案餘_第二絕緣層52 的部分下表面，第二綠漆層62係覆蓋該第二絕緣層52的下表面。 〇 錢第五® ’本發明的具鋼凸塊之堆疊結構與晶粒接觸焊接示 意圖，在此示意圖中將位於具銅凸塊之堆疊結構3上的銅凸塊41與晶 粒層10上的晶粒接腳12藉著焊接相接合。由於銅凸塊41的凸起部4ia 八疋尚度因而與日日粒接腳12之間的距離縮短，可減少焊接時所需 的焊料30 ’且藉著銅凸塊41表面與焊料3〇間的内聚力，使得焊料3〇 形狀為長條狀而非球體狀，因此減少焊料3〇之間的距離，進而使晶粒 接腳12之間的間距以及銅凸塊41之間的間距縮小到低於一般凸塊間 距製作極限150〜180um以下，因而使得整體積體電路板1結構也跟著 〇、缩小。 以上所述者僅為用以解釋本發明之較佳實施例，並非企圖據以對 本發明做任何形式上之限制，是以，凡有在相同之發明精神下所作有 關本發明之任何修飾或變更，皆仍應包括在本發明意圖保護之範疇。 201036134 【圖式簡單說明】 第一圖為焊鉛凸塊技術之積體電路結構示意圖。 第二圖為焊鉛凸塊技術之積體電路結構的另一示意圖。 第三圖為本發明第一實施例之示意圖。 第四圖為本發明第二實施例之示意圖。 第五圖為本發明的具銅凸塊之堆疊結構與晶粒接腳的焊接示意圖。 【主要元件符號說明】 1積體電路板 〇 2具銅凸塊之堆疊結構 3具銅凸塊之堆疊結構 10晶粒層 12晶粒接腳 20電路基板 22基板接腳 30焊料 40第一導電銅層 〇 41銅凸塊 41a凸起部 41b底部 42第二導電銅層 44第三導電銅層 50第一絕緣層 52第二絕緣層 60第一綠漆層 62第二綠漆層201036134 VI. Description of the Invention: [Technical Field] The present invention relates to a stacked structure having copper bumps, and more particularly to a circuit substrate having copper bumps of the uppermost copper posts. [Prior Art] Solder bumping technology (Solder Bumping) is to use the film, yellow light and electroplating process or printing technology to make solder bumps on the wafer aluminum pad. In the back 1C package process 0, the bumps are melted by thermal energy. , with the tin pad on the circuit board for assembly. This technology can greatly reduce the size of the 1C package, and has the advantages of high density, low induction, low cost, and good heat dissipation. Referring to the first figure, a schematic diagram of the integrated circuit structure of the lead-lead bump technology, wherein the integrated circuit board 1 comprises a seed layer 10 and a circuit substrate 20, the seed layer 10 having a plurality of die pins 12 The solder 30 is bonded to the substrate pin 22 on the circuit substrate 20, wherein the bump pitch dl of the die pad 12 and the substrate pin 22 is set to be 15 〇 18 〇 um. Referring to the second figure, another schematic diagram of the integrated circuit structure of the lead-lead bump technology, wherein between each of the die pins 12 and the die pins, and between each of the substrate pins 22 and the substrate pins 22 The arrangement is dense and the bump pitch d2 is reduced. When the die layer is bonded to the circuit substrate 20 by the solder 3, there is a risk that the solder 3 is short-circuited. SUMMARY OF THE INVENTION The main object of the present invention is to provide a stack structure of oil bumps, comprising a plurality of conductive copper layers, a plurality of insulating layers, and a plurality of copper bumps, wherein the plurality of conductive copper layers and the plurality of insulating layers The first conductive layer is stacked on top of each other, and a plurality of steel bumps are formed on the first layer for soldering to the die pins. By the cohesion between the copper bump surface and the ': the shape of the solder is elongated rather than spherical, thus reducing the distance between the solder 3 201036134' and thus the spacing between the die pins and the copper bumps The spacing between the designs is reduced, so that the entire bulk board structure can be reduced or more pins can be designed in the same area. Therefore, the present invention can solve the above-mentioned shortcomings of the prior art by utilizing the characteristics of the copper bumps and the solder having a certain height on the first conductive copper layer, so that the pins can be arranged more densely, and the risk of solder short circuit during soldering can be reduced. [Embodiment] Hereinafter, the embodiments of the present invention will be described in more detail with reference to the drawings and the reference numerals, which can be implemented by those skilled in the art after studying this specification. Referring to the third embodiment of the present invention, the stacked structure 2 of the copper bumps includes a first conductive copper layer 40, copper bumps 41, a first insulating layer 5, and a first green lacquer layer 60. The first conductive copper layer 4 has a circuit pattern (not shown) covering a portion of the upper surface of the first insulating layer 40. The circuit pattern has a plurality of copper bumps 41. The copper bumps 41 each have a bottom portion 4ib and a convex portion 41a. The convex portion 41a is located above the bottom portion 41b. The convex portion 4ia has a width and a height, and the bottom portion 41b has a width-and- The height of the convex portion 41a is smaller than the width of the bottom portion 41b. The upper layer of the 帛-green lacquer layer 60 covering the first and insulating layers 5 未 is not covered by the circuit (four) portion and the portion covering the Wei road pattern towel not covered by the object bumps 41. Referring to the fourth embodiment, a schematic diagram of a second embodiment of the present invention includes a first conductive copper layer 40, a copper bump 4, a second conductive copper layer 42, and a third conductive copper layer 44. , the first insulating layer 50, the second insulating layer 52, the first green lacquer layer 6 〇卩 and the second green lacquer layer 62 ′, wherein the first conductive copper layer 40 has a circuit pattern (not shown), the circuit pattern A portion of the upper surface of the first insulating layer 4G is covered, and the Wei pattern has a plurality of copper bumps 41. The copper bumps 41 each have a bottom portion 41b and a convex portion. The protrusion 4 201036134 4 41a is located above the bottom surface, and the convex portion has a width and a height, and the bottom portion has a width and - height, and the width of the raised portion 41a is smaller than the width of the bottom portion 41b. The first green copper layer 60 covers the portion of the upper surface of the first-level layer 50 that is not covered by the circuit pattern and covers the portion of the circuit pattern that is not covered by the copper bumps 41 to damage the first conductive copper layer 42. There is a circuit pattern, and the circuit pattern is located between a portion of the lower surface of the first insulating layer 50 and a portion of the upper surface of the second insulating layer. The second conductive copper layer 44 has a -f case, and the second green lacquer layer 62 covers a lower surface of the second insulating layer 52. 〇钱五® 'The schematic diagram of the contact structure of the steel bumps of the present invention and the die contact welding, in this schematic view, the copper bumps 41 on the stacked structure 3 with copper bumps and the grain layer 10 The die pins 12 are joined by soldering. Since the distance between the convex portion 4ia of the copper bump 41 and the sunday pin 12 is shortened, the solder 30' required for soldering can be reduced and the surface of the copper bump 41 and the solder 3 can be reduced. The cohesive force between the solders causes the shape of the solder 3 to be elongated rather than spherical, thereby reducing the distance between the solders 3〇, thereby narrowing the pitch between the die pins 12 and the pitch between the copper bumps 41 to Below the general bump pitch production limit of 150~180um, the structure of the whole bulk circuit board 1 is also reduced and reduced. The above is only a preferred embodiment for explaining the present invention, and is not intended to limit the present invention in any way, and any modifications or alterations to the present invention made in the spirit of the same invention. All should still be included in the scope of the intention of the present invention. 201036134 [Simple description of the diagram] The first figure is a schematic diagram of the integrated circuit structure of the lead-lead bump technology. The second figure is another schematic diagram of the integrated circuit structure of the lead-lead bump technology. The third figure is a schematic view of the first embodiment of the present invention. The fourth figure is a schematic view of a second embodiment of the present invention. The fifth figure is a schematic diagram of the welding structure of the copper bumps and the die of the die of the present invention. [Main component symbol description] 1 integrated circuit board 〇 2 stacked structure of copper bumps 3 stacked structure of copper bumps 10 crystal layer 12 die pin 20 circuit substrate 22 substrate pin 30 solder 40 first conductive Copper layer 〇41 copper bump 41a raised portion 41b bottom portion 42 second conductive copper layer 44 third conductive copper layer 50 first insulating layer 52 second insulating layer 60 first green lacquer layer 62 second green lacquer layer