201030854 六、發明說明： 【發明所屬之技術領域】 本發明之實施例係關於半導體元件（例如太陽能電 池）。該些實施例係特別關於半導體元件製造方法、半導 體元件與半導體元件製造設備。 【先前技術】 半導體元件在數種工業領域中具有許多功能，包括但 不限於諸如電晶體和光伏電池（例如太陽能電池）之電子 元件的製造。個別的光伏電池係用於例如提供功率予小 裝置（例如電子計算機）。光伏陣列係用於例如遠距區域 功率系統、繞地球之衛星與太空探測器、遠距無線電話 及泵水應用中。 運作一含p-n接面之太陽能電池的原理係如以下所概 略描述。太陽能電池吸收光且因所吸收的光能而產生電 子/電洞電荷對。由於接面電場和擴散所造成的漂移，電 子移動朝向接面的n_層側，並且電洞移動朝向p_層侧。 對於太陽能電池製造，可以利用所謂的塊體（bulk)技術 或薄膜技術’前者係使用塊體半導體晶圓，後者係造成 薄膜太陽能電池。太陽能電池之大部分普遍的塊體材料 是節晶矽’例如單晶矽（c-Si)或多晶矽（mc-Si)。 典'型的使用mc_Si的太陽能電池製造過程可以包括例 如下述步驟中的一些步驟：藉由蝕刻從mc_Si晶圓移除 3 201030854 鋸-損壞；藉由在POC13環境中進行熱處理以形成射極； 移除產生的磷矽玻璃（PSG);鈍化前側與/或背側；藉由 例如電聚增強化學氣相沉積（PECVD)來沉積前側抗反射 塗層；進行後側金屬化與前接觸格線的網印；以及退火 以造成後侧金屬相互擴散且引發前接觸格線。 多晶矽晶圓可以含有高密度之再結合中心，例如晶格 缺陷（諸如像是鐵（Fe)或鎳（Ni)的雜質）^這造成了不希望 之電荷載子的再結合，因而影響了太陽能電池的電氣性 質。為了改善使用mc-Si之太陽能電池的性質，可以執 行所謂的雜質的吸附（gettering) ’並且藉此執行雜質的失 活（inactivation)，其典型地包括在高溫下的磷擴散。蛾 可以保留射極與/或太陽能電池的表面中的Fe和其他金 屬雜質’減少了因這些雜質的再結合。在碟擴散期間， 一磷矽玻璃係形成，磷矽玻璃必須被移除以進行後續的 太陽能電池製造過程步驟。 【發明内容】 鑑於前述，本發明提供了根據申請專利範圍第1項之 一種半導體元件製造方法、根據申請專利範圍第1 5項之 一種半導體元件、以及根據申請專利範圍第16項之一種 半導體元件製造設備。 根據一實施例’本發明提供一種半導體元件製造方 法’其包括.提供一半導體基材；在該半導體基材上形 4 201030854 成一包括半導體化合物與掺雜添加物的層；以及接著形 成一射極區域’並且藉由將包括該層的該半導體基材予 以退火以吸附（getter)雜質。 根據另一實施例’本發明提供一種半導體元件，其可 藉由一半導體元件製造方法來獲得，該方法包括：提供 一半導體基材；在該半導體基材上形成一包括半導體化 合物與摻雜添加物的層；以及接著形成一射極區域，並 且藉由將包括該層的該半導體基材予以退火以吸附雜 9 質。 根據進一步實施例，本發明提供一種半導體元件製造 設備，其包括：一塗覆裝置，其適於塗覆一半導體基材； 一加熱裝置，其適於將該經塗覆之半導體基材予以退 火；以及一控制裝置，其適於控制該塗覆裝置與該加熱 裝置，並適於執行一半導體元件製造方法，該方法包括： 提供一半導體基材；在該半導體基材上形成一包括半導 Φ 體化合物與掺雜添加物的層；以及接著形成一射極區 域，並且藉由將包括該層的該半導體基材予以退火以吸 附雜質。 本發明之進一步特徵及細節可由附屬項、詳細說明和 圖式瞭解。 實施例亦涉及用來實施所揭露方法的設備，並且涉及 包括多個設備部件以執行所述方法步驟的設備。又，實 施例亦涉及所述設備藉以運作或所述設備藉以製造的方 法。其可以包括用於實施設備功能或用於製造設備部件 201030854 的方法步驟。方法 _ ☆步驟可以藉由硬體構件、韌體、軟體、 經程式化以適當姑 軟體之電腦、前述任何組合、或以任何 其他方式來執行。 •、瞭解 實施例的元件可以有利地被用到其他實施 例中，而不需贅述。 【實施方式】 # 下述說明將涉及各種實施例’該些實施例的一或多個 實例係緣不在圖式中。各實例是以解釋的方式來提供， 並且沒有意圖要限制本發明。 、 it中半導體元件將示範性地被稱為太陽能電 池’其不會限制範圍。此外，半導體元件之基材將示範 地被稱為曰曰圓或矽晶圓，也被稱為矽基材，其不會限 制範圍°然、而’本文揭露的實施例的實例也可以被應用 J其他類型的半導體元件（例如薄膜太陽能電池）。又， _ 可以想出其他不是石夕的半導體或半導體材料。再者， 在下述中，矽晶圓將示範性地被稱為多晶Ρ-型矽晶圓， 其不會限制範圍 '然而，可以使用其他類型的石夕晶圓， 例如單曰曰矽晶圓與/或本質矽晶圓（諸如實質上純的矽晶 圓又，在下述中，一 Ρ_η太陽能電池的製造係被描述， 其中η-型射極係形成在ρ_型矽基材中。然而，本文描述 之實施例的方法的原理可以對應地用於具有相反ρ_η結 構之太陽能電池的製造。此外，在下述中，磷被提及作 201030854 為用來形成射極之η-摻質的實例。然而，可以使用其他 η-摻質（例如砷）。 在以下的圖式說明中’相同的元件符號係指稱相同的 元件。通常，僅描述個別實施例的不同處。 本文描述之多個實施例的一典型應用是太陽能電池 (例如使用me-Si的太陽能電池）的製造。 根據一實施例，本發明提供一種半導體元件製造方 φ 法，其包括：提供一半導體基材；在該半導體基材上形 成一包括半導體化合物與摻雜添加物的層；以及接著形 成一射極區域，並且藉由將包括該層的該半導體基材予 以退火以吸附（getter)雜質。因此，射極區域的形成與雜 質的吸附疋執行於一步驟中，典型地為同時。雜質可以 被摻雜添加物所吸附》 第la-lc圖係繪示，根據實施例之一實例，一半導體 元件製造方法的步驟。在此實例之第一步驟中，提供一 • P-型矽晶圓10形式的矽基材（顯示於第U圖）以作為一半 導體基材’其具有一前側12與一背側14。晶圓1〇包括 散佈在塊體晶圓10内的金屬雜質16。例如，可以使用 P-型（典型地為硼摻雜）之多晶矽晶圓以作為一矽基材，其 具有0.2-10 Ohm-cm之電阻率（典型地為1 〇hm cm)及厚 達500 μηι之厚度（典型地為2〇〇 μπι)。 在第lb圖繪示的第二步驟中，可以沉積一矽化合物與 -摻雜添加物於矽基材上。目此，一非晶矽化合物層 2〇(其包括摻質22’例如磷）形成在晶圓1〇之前侧12上。 7 201030854 矽化合物可以是例如氮化矽或碳化矽。在實施例之一實 中第—步驟可以藉由濺射該矽化合物與該摻雜添加 物(例如藉由濺射一含有該矽化合物與該摻雜添加物之 標乾）來執行。在賤射期間，可以提供一氣體，其中該氣 體包括選自由ch4、Nh3及其他適當成分所構成群組之 至y者。在實施例之另一實例中，第二步驟是藉由一 氣體混合物的PECVD來執行，其中該氣體混合物包括 SiH4與選自由NHyCH4及PH3所構成群組之至少一者。 例如，在第二步驟中，可以沉積一磷摻雜鈍化層在晶 圓10之前側12上。產生的鈍化層可以具有抗反射性質、 70-95 nm的厚度、及在622 nm波長下之1 95 2 〇5的折 射率。沉積可以如下述來執行：在一第一實例中，可以 藉由PECVD來沉積一碳化矽層SiCx(n):H於晶圓1〇之 前側上。在塗覆腔室中，可以建立^⑹至之總 壓力與約200 C至約500°C之晶圓溫度。為了產生電漿， • 可以使用提供約3 Hz至約300 Hz範圍之RF的功率源， 典型地為約300 kHz至30〇〇 kHz範圍的中等頻率 (Medium Frequency，MF)。可以將 SiH4、CH4、及 pH〗氣 體導入塗覆腔室内《沉積時間可為約丨分鐘至約1〇分 鐘。在一替代性實施例中，可以藉由濺射一磷掺雜矽標 靶來沉積例如一氮化矽層SiNx(n)於晶圓1〇之前側12 上。在塗覆腔至中，可以建立j 至6々訂之總壓力 與約200 C至約500°C之晶圓溫度。可以將Ar、Nh3、仏、 及選擇性地PH3(若標靶未經磷摻雜）導入塗覆腔室内。 201030854 為了產生電漿’可以使用提供DC、RF、或mf的功率源。 在進-步實施例中，可以藉㈣射—料雜標乾且使用 Α與〇2作為反應性氣體於晶圓上生長一包括磷摻雜氮 氧化石夕的層2 0。 選擇性地，在第二步驟之後，可以執行以本質或棚換 雜之鈍化層（未示出）對晶圓1〇之背侧進行鈍化。這可以 使用類似於第二步驟之條件的沉積條件在不存在磷摻質 下來實現。在完成製造方法之後，此層必須保持鈍化性 質。當選擇一硼摻雜層時，在晶圓（例如太陽能電池）之 背側處存在有經鈍化之高低接面的額外優點。 然後，在第1 c圖繪示之第三步驟中，經塗覆之晶圓 10被退火於約600°C至約12〇〇。(：的退火溫度長達約！分 鐘至約100分鐘。可以藉由使用一管狀爐、一帶狀爐、 一電阻式加熱爐、一紅外線爐、一利用鹵素燈的爐、與/ 或快速熱處理（RTP)之加熱程序來執行該退火。經塗覆之 晶圓ίο的退火可以進行於惰性氛圍下（例如n2)或反應性 氛圍下（例如Ni/H2)在約700。(：至約950。(：的退火溫度長 達約15分鐘至約30分鐘。因此，磷22會擴散到晶圓 10内’並且吸附一實質量的雜質16。又，一量的磷在矽 晶圓1 〇與矽化合物層20之間的介面處會擴散到晶圓i 〇 内，而不會吸附。藉此，一 n_型射極區域3〇形成在靠近 化合物層20與晶圓1〇的介面處。進一步地，晶圓之 前侧12被塗覆以一石夕化合物層20 ’其中該；ε夕化合物層 20可以實質上耗盡碟。由於氮化砍或碳化石夕可以作為發 9 201030854 化合物，包含射極區域30之晶圓10的表面可以被層2〇 鈍化。此外’層20可以作為一抗反射塗層。又，退火溫 度可以位在約9501：至約12001之範圍中，典型地為約 1100C。因此’可以額外地執行化合物層2〇的熱氧化。 在第三步驟中，由於磷的活化和擴散到晶圓内，形成 了射極。再者，在此步驟中，可以藉由存在磷的輔助來 在層中查成金屬雜質的吸附。故，藉由根據實施例的方 _ 法’一半導體晶圓之表面區域中與/或塊體區域中金屬雜 質的吸附及射極形成係在一步驟中同時來執行。又，可 以達到表面鈍化與/或抗反射塗覆。 在實施例之其他實例中，退火溫度可以典型地位在約 600°C至約1200°C之範圍中，更典型地為位在約650°c至 約780°C之範圍中或約750¾至約830。(：之範圍中，最典 型地為位在約7〇〇°C至約800。(：之範圍中。 在實施例之進一步實例中，退火時間可以典型地位在 ❿ 約1分鐘至約100分鐘之範圍中’更典型地為位在約 75分鐘至約1〇〇分鐘之範圍中或約8〇分鐘至約9〇 分鐘之範圍中’最典型地為位在約15分鐘至約30分 鐘之範圍中或約20分鐘至約30分鐘之範圍中。 在一些實施例中，於沉積一矽化合物與一摻雜添加物 於石夕基材上之步驟的期間，可以形成兩層（例如兩層相同 的組成）。在實施例之其他實例中，於沉積一矽化合物與 一摻雜添加物於矽基材上之步驟的期間，可以形成兩層 不同的組成。這樣的實施例的一實例係緣示在第2a_2d 201030854 圖。此實例與第la-lc圖所纷示的方 實例在第二步称期間係執行兩 =在：此 填作為摻質…化合物2"塗覆：序。首先，包含 D物20係沉積在晶圓10之前側 上’如第2b圖所示。額外的塗覆程序係如第2。圖所 :’其顯不-沒有摻雜嶙的梦化合物層24係形成在包含 構之石夕化合物層20上。因此， 在第2d圖之第三步驟期 間，一量之麟會在石夕晶圓10與石夕化合物層2〇之介面處 擴散到晶圓内。故，射極區域3〇的形成和晶㈣之雜 質16的吸附係、同時執行。此外，同時12〇可以提供 一表面鈍化’而層24可以提供抗反射性質。 在上述第2a-2d圖顯示之實例的變化中，在第二步驟 之後’層20可以包括就化石夕與磷，而層^包括氮切 而未經摻雜鱗。根據此實例之另m 2g可以包括 碳化石夕與填’而層24包括氮化梦而未經掺雜鱗。在此實 ❿ 例之又進-步變化中120可以包括氮切與填，而層 24包括碳化矽而未經摻雜磷。再者，層2〇可以包括碳 化石夕與麟’而層24包括碳切而未經摻雜麟。 如别所述，在執行退火步驟之前，層2〇可以包括氮化 石夕與填’或碳切與I在第3a_3d圖繪示之進一步實 例中’可以形成-經塗覆之晶圓1G，其中在退火之前層 24可以具有與層20相同的成分，層24中摻質22的濃 度係實質上等於或低於層2〇中摻質22的濃度。在替代 性實例中（未示出）’| 24中摻質22的漠度可以甚至高 於層20中摻質22的濃度。因此，層2〇可以包括磷摻雜 201030854 氮化矽或磷摻雜碳化矽，而層24也包括磷摻雜氮化矽或 磷摻雜碳化矽。這些實例具有與第la_lc圖所解釋之實 例相同的效果：可以在一步驟中同時執行在一半導體晶 圓之表面區域中與/或塊體區域中金屬雜質的吸附、射極 形成、及在一些情況中表面鈍化和抗反射塗覆。 在第2a-2d圖與第3a-3d圖各自顯示之實例的變化中 (未示出），可以藉由先在半導體基材上沉積此兩半導體 化&物層之一層且接著使用前述退火溫度和退火時間進 # 行退火，以及沉積另—層且接著使用前述退火溫度和退 火時間進行退火，以形成此兩半導體化合物層。又，在 第2a-2d圖顯示之實例的變化中（未示出），在個別層 與24的兩者或各者進行退火之前，半導體化合物層2〇 可以不經摻質來摻雜，而層24可以包括摻質22。在這 些變化中，於退火之後，可以產生如第2d圖或第3d圖 所示之相同的結構。 • 層2〇與層24的典型實例是a-SiCx* a-SiyCx (例如 a-Si〇.8C〇.2)以及 a_SiNx* a_SiyNx，其中 χ 典型地位在 〇 至約1範圍中，並且y典型地位在超過〇至約丨範圍中。 所形成之層的厚度可以位在約3〇分鐘至約12〇11〇1範圍 t。此外，適當量的氫與/或氧或其他成分可以被包括在 層20和24中，以提供合適的鈍化與/或抗反射性質。包 含氫之層20或24的一實例係為經氫化之磷摻雜之非晶 碳化矽a-SiCx(n):H，其係藉由從SiH4、Ch4、及PH3執 行PECVD來形成。包含氧之層20或24的一實例係為磷 12 201030854 掺雜之氮氧切，其係藉由_ n_摻雜之石夕標乾且利用 &和〇2作為反應性氣體來生長。 根據一些實施例，矽基材可以選自由結晶矽基材多 晶矽基材、具有結晶矽表面層之基材、及具有多晶矽表 面層之基材所構成群組。 如則所述，根據一些實施例，矽基材可以是p型矽基 材。在其他實施例中，矽基材可以是本質矽基材，即未 經摻雜之矽晶圓1 〇。又，根據一些實施例，此方法可以 包括形成一本質矽材料層於矽晶圓1 0之背側上的步 驟。因此，在一些實施例中’晶圓1〇之前側能夠被提供 以一經摻雜之a-矽化合物層，而背側可以由本質材料所 構成。故，在執行此方法的期間，可以避免在背側處的 射極形成。在其他實施例中，此方法可以包括形成一經 摻雜（例如p-摻雜）之材料層於矽晶圓1 〇之背側上的步 驟。所形成的背側層可以是例如一經领摻雜石夕表面層。 這會在經塗覆之晶圓（例如太陽能電池）的背側處導致鈍 化的高低接面。 如前所述，藉由本文描述的實施例，可以在一步驟中 同時執行一半導體晶圓之表面區域中與/或塊體區域中 金屬雜質或其他晶格缺陷的吸附以及射極形成。再者， 當形成射極及吸附雜質時，可以達成表面鈍化。在相同 的步驟中，可以完成一抗反射塗層的形成。此外，不需 要移除磷矽玻璃，這是因為本文實施例所提供的麟擴散 不會造成PSG區域的形成。又，所製造之半導體元件或 13 201030854 太陽能電池的經改善射極輪廓可以為更陡。故，本文揭 露之實施例的方法允許射極輪廓的更佳控制。這可取決 於磷擴散到晶圓基材内之慢速度（由於半導體化合物和 掺質的選擇以及退火溫度和退火時間的選擇）。所以，能 夠以一簡單的製造過程來製造一改善射極區域、改善表 面鈍化、減少電荷載子再結合與/或改善抗反射性質的半 導體元件（例如太陽能電池）。故，可以顯著地降低太陽 能電池生產成本。 在下文中，將描述實施例的進一步實例。 在第一實例中，使用P-型之硼摻雜多晶矽晶圓作為— 基材’其具有1 Ohm-cm之電阻率200 μηι之厚度。晶圓 具有在結晶生長期間所導入的金屬雜質。 在第二步驟中’兩個磷摻雜之非晶碳化矽鈍化層 a-SiCx(n):H的堆疊沉積在晶圓之前侧上。沉積條件為如 下：反應器：PECVD，直接電漿，運作於RF頻率（13 % MHz)，反應器腔室中的真空壓力低於i〇e5 hpa ;氣 流：SiH4(95%)+PH3(5%):3 seem ; CH4:32 seem ;總壓力：3 pbar ;溫度：300°C ;沉積時間（靜態）：12分鐘；功率密 度：0.086 W/m2。所形成的a_SiCx(n):H雙層具有抗反射性 質、80 nm的厚度、及在622 nm波長下之2.00的折射率。 在第二步驟中，經塗覆之晶圓係在ν2氛圍下於 的溫度下進行長達20分鐘退火時間的退火。太陽能電 池的前驅物被形成了。僅需要施加多個接點。 第二實例與第一實例的不同點在於第二實例在第二步 201030854 驟之後且在第三步驟的退火之前，以a SiCx⑴：H的本質 非aa碳化石夕膜來執行晶圓之背側的鈍化。沉積條件係對 應於第二步驟的沉積條件，而不存在有磷摻質。反應 器：PECVD，直接電漿，運作於RF頻率（13.56 MHz);反應 器腔室中的真空壓力低於l〇e_5 hPa ;氣 流.SiH4(95 /ό)+ΡΗ3(5%):3 seem ; CH4:32 seem ;總壓力：3 pbar ;溫度：30(TC ;沉積時間（靜態乃12分鐘；功率密 度：0.086 W/m2。 在第二實例中，執行第一實例的三個步驟，但第三步 驟被更改成經塗覆之晶圓被退火於780 的溫度長達75 分鐘。 在第四實例中，第三實例被更改成經塗覆之晶圓被退 火於780°C的溫度長達20分鐘。 根據一實施例，本發明提供一種半導體元件製造方 法，其包括：提供一半導體基材；在該半導體基材上形 • 成一包括半導體化合物與摻雜添加物的層；以及接著形 成一射極區域，並且藉由將包括該層的該半導體基材予 以退火以吸附（getter)雜質。因此’射極區域的形成與雜 質的吸附是執行於一步驟中，典型地為同時。雜質可以 被摻雜添加物所吸附。雜質可以是金屬雜質或其他晶格 缺陷。 在一可以與本文中任何其他實施例結合的實施例中， 該半導體基材是一矽基材且該半導體化合物是一妙化合 物’並且退火係藉由加熱於約6〇〇。〇至約120〇°C的退火 15 201030854 溫度長達約1分鐘至約i 〇〇分鐘的退火時間來執行。 在一可以與本文中任何其他實施例結合的實施例中， 在形成該層的步驟中，一經摻雜之半導體化合物層係被 形成在半導體基材的表面上。經摻雜之半導體層可以是 非晶的。 在一可以與本文中任何其他實施例結合的實施例中， 在形成該層的步驟中，至少兩個相同或不同組成的層係 被形成。 在一可以與本文中任何其他實施例結合的實施例中， 在形成該層的步驟中，形成至少兩層，該些層的至少兩 層包括相同的半導體化合物或不同的半導體化合物。 在一可以與本文中任何其他實施例結合的實施例中， 至少一半導體化合物包括選自由矽化合物、碳化矽及氮 化矽所構成群組之至少一者。 在一可以與本文中任何其他實施例結合的實施例中， 該摻雜添加物包括選自由一 p_型摻質、一 n型摻質、磷 及砷所構成群組之至少一者。 在一可以與本文中任何其他實施例結合的實施例中， 形成該層的步驟係藉由濺射該半導體化合物與該掺雜添 加物來執行。典型地，可以濺射一包括該半導體化合物 與該摻雜添加物的標靶。 在一可以與本文中任何其他實施例結合的實施例中， 形成該層的步驟係藉由一氣體混合物的PEcvd來執 行，其中該氣體混合物包括SiH4與選自由NH3、CH4及 201030854 PH3所構成群組之至少一者。 在一可以與本文中任何其他實施例結合的實施例中， 在退火的步驟中，該半導體基材的表面係被氧化。 在一可以與本文中任何其他實施例結合的實施例中， 該半導體基材係、為選自由—碎基材一結晶石夕基材、一 多ro石夕基材、一具有結晶矽表面層之基材及一具有多 晶碎表面層之基材所構成群組之一者。201030854 6. Description of the Invention: TECHNICAL FIELD Embodiments of the present invention relate to semiconductor elements (e.g., solar cells). These embodiments are particularly related to a semiconductor device manufacturing method, a semiconductor device, and a semiconductor device manufacturing apparatus. [Prior Art] Semiconductor components have many functions in several industrial fields including, but not limited to, the manufacture of electronic components such as transistors and photovoltaic cells (e.g., solar cells). Individual photovoltaic cells are used, for example, to provide power to small devices (e.g., electronic computers). Photovoltaic arrays are used in, for example, remote area power systems, satellite and space probes around the earth, remote radiotelephones, and pumping applications. The principle of operating a solar cell with a p-n junction is as outlined below. Solar cells absorb light and generate electron/hole charge pairs due to the absorbed light energy. Due to the drift caused by the electric field and diffusion of the junction, the electrons move toward the n_layer side of the junction, and the holes move toward the p_ layer side. For solar cell manufacturing, so-called bulk technology or thin film technology can be utilized. The former uses bulk semiconductor wafers, and the latter forms thin film solar cells. The most common bulk material for solar cells is the interstitial 矽' such as single crystal germanium (c-Si) or polycrystalline germanium (mc-Si). The solar cell manufacturing process using mc_Si may include, for example, some of the following steps: removing from the mc_Si wafer by etching 3 201030854 saw-damage; forming an emitter by heat treatment in a POC13 environment; Removing the produced phosphorous bismuth glass (PSG); passivating the front side and/or the back side; depositing the front side anti-reflective coating by, for example, electropolymerization enhanced chemical vapor deposition (PECVD); performing backside metallization and front contact grid lines Screen printing; and annealing to cause the backside metal to diffuse and cause the front contact grid. Polycrystalline germanium wafers may contain high density recombination centers, such as lattice defects (such as impurities such as iron (Fe) or nickel (Ni)). This causes undesirable recombination of charge carriers, thus affecting solar energy. The electrical properties of the battery. In order to improve the properties of the solar cell using mc-Si, so-called gettering of impurities' can be performed and thereby the inactivation of impurities is performed, which typically involves phosphorus diffusion at high temperatures. Moths can retain Fe and other metal impurities in the surface of the emitter and/or solar cell' to reduce recombination due to these impurities. During the diffusion of the disc, a phosphorous glass system is formed and the phosphorous glass must be removed for subsequent solar cell manufacturing process steps. In view of the foregoing, the present invention provides a semiconductor device manufacturing method according to the first aspect of the patent application, a semiconductor device according to claim 15 of the patent application, and a semiconductor device according to claim 16 of the patent application. Manufacturing Equipment. According to an embodiment, the present invention provides a method of fabricating a semiconductor device comprising: providing a semiconductor substrate; forming a layer on the semiconductor substrate 4 201030854 into a layer comprising a semiconductor compound and a doping additive; and subsequently forming an emitter The region 'and by annealing the semiconductor substrate including the layer to getter impurities. According to another embodiment, the present invention provides a semiconductor device obtainable by a method of fabricating a semiconductor device, the method comprising: providing a semiconductor substrate; forming a semiconductor compound and doping addition on the semiconductor substrate a layer of the object; and then an emitter region is formed and the dopant is adsorbed by annealing the semiconductor substrate comprising the layer. According to a further embodiment, the present invention provides a semiconductor device manufacturing apparatus comprising: a coating device adapted to coat a semiconductor substrate; a heating device adapted to anneal the coated semiconductor substrate And a control device adapted to control the coating device and the heating device, and adapted to perform a semiconductor device manufacturing method, the method comprising: providing a semiconductor substrate; forming a semiconducting layer on the semiconductor substrate a layer of the Φ bulk compound and the dopant additive; and then an emitter region is formed and the impurity is adsorbed by annealing the semiconductor substrate including the layer. Further features and details of the invention are apparent from the dependent items, the detailed description and the drawings. Embodiments also relate to apparatus for implementing the disclosed method, and to apparatus comprising a plurality of equipment components to perform the method steps. Moreover, embodiments also relate to methods by which the device operates or by which the device is manufactured. It may include method steps for implementing device functions or for manufacturing device component 201030854. Method _ ☆ steps can be performed by hardware components, firmware, software, computer programmed with appropriate software, any combination of the foregoing, or in any other manner. It will be appreciated that the elements of the embodiments may be used in other embodiments without further recitation. [Embodiment] The following description will refer to various embodiments. One or more examples of the embodiments are not in the drawings. The examples are provided by way of explanation and are not intended to limit the invention. The semiconductor component in it will be exemplarily referred to as a solar cell' which does not limit the range. Furthermore, the substrate of the semiconductor component will be exemplarily referred to as a round or germanium wafer, also referred to as a germanium substrate, which does not limit the scope, and examples of the embodiments disclosed herein may also be applied. J other types of semiconductor components (such as thin film solar cells). Also, _ can think of other semiconductor or semiconductor materials that are not Shi Xi. Furthermore, in the following, germanium wafers will be exemplarily referred to as polysilicon-type germanium wafers, which do not limit the range. However, other types of stone wafers, such as single twins, may be used. Circular and/or essentially germanium wafers (such as substantially pure germanium wafers, in addition, in the following, a fabrication of a solar cell, wherein the n-type emitter is formed in a p-type germanium substrate. However, the principles of the methods of the embodiments described herein can be used correspondingly for the fabrication of solar cells having opposite ρ_η structures. Further, in the following, phosphorus is referred to as 201030854 as the η-doped material used to form the emitter. Examples. However, other η-doped species (e.g., arsenic) may be used. In the following description of the drawings, the same elements are referred to as the same elements. In general, only the differences of the individual embodiments are described. A typical application of an embodiment is the manufacture of a solar cell, such as a solar cell using me-Si. According to an embodiment, the present invention provides a method of fabricating a semiconductor device, comprising: providing a semiconductor substrate; Forming a layer including a semiconductor compound and a doping additive on the semiconductor substrate; and then forming an emitter region, and by annealing the semiconductor substrate including the layer to getter impurities. The formation of the polar regions and the adsorption of the impurities are performed in one step, typically at the same time. The impurities may be adsorbed by the doping additive, a la-lc diagram, according to an example of an embodiment, a semiconductor device fabrication Step of the method. In the first step of the example, a ruthenium substrate (shown in Figure U) in the form of a P-type 矽 wafer 10 is provided as a semiconductor substrate having a front side 12 and a back Side 14. The wafer 1 includes metal impurities 16 dispersed in the bulk wafer 10. For example, a P-type (typically boron doped) polysilicon wafer can be used as a germanium substrate having 0.2. a resistivity of -10 Ohm-cm (typically 1 〇hm cm) and a thickness of 500 μηι (typically 2 〇〇μπι). In the second step depicted in Figure lb, a 可以 can be deposited Compound and doping additive on ruthenium substrate To this end, an amorphous germanium compound layer 2, which includes a dopant 22' such as phosphorus, is formed on the front side 12 of the wafer. 7 201030854 The germanium compound may be, for example, tantalum nitride or tantalum carbide. The first step can be performed by sputtering the germanium compound and the doping additive (for example, by sputtering a stem containing the germanium compound and the doping additive). During sputtering, A gas may be provided, wherein the gas comprises a group selected from the group consisting of ch4, Nh3, and other suitable components to y. In another example of the embodiment, the second step is performed by PECVD of a gas mixture, Wherein the gas mixture comprises at least one of SiH4 and a group selected from the group consisting of NHyCH4 and PH3. For example, in a second step, a phosphorous doped passivation layer can be deposited on the front side 12 of the wafer 10. The resulting passivation layer can have antireflective properties, a thickness of 70-95 nm, and a refractive index of 1 95 2 〇 5 at a wavelength of 622 nm. The deposition can be performed as follows: In a first example, a tantalum carbide layer SiCx(n):H can be deposited by PECVD on the front side of the wafer. In the coating chamber, a total pressure of from (6) to a wafer temperature of from about 200 C to about 500 °C can be established. To generate plasma, • A power source that provides RF in the range of about 3 Hz to about 300 Hz can be used, typically a medium frequency (MF) in the range of about 300 kHz to 30 kHz. The SiH4, CH4, and pH gases can be introduced into the coating chamber. The deposition time can range from about 丨 minutes to about 1 〇 minutes. In an alternative embodiment, for example, a tantalum nitride layer SiNx(n) may be deposited on the front side 12 of the wafer 1 by sputtering a phosphorous-doped target. In the coating chamber to the middle, a total pressure of j to 6 Å and a wafer temperature of about 200 C to about 500 ° C can be established. Ar, Nh3, yttrium, and optionally PH3 (if the target is not doped with phosphorus) can be introduced into the coating chamber. 201030854 A power source providing DC, RF, or mf can be used to generate plasma. In a further embodiment, a layer 20 comprising a phosphorus-doped nitrous oxide oxide may be grown on the wafer by a (four) shot-and-charge dry and using ruthenium and osmium 2 as reactive gases. Alternatively, after the second step, passivation of a back side of the wafer 1 can be performed with an intrinsic or shed-modified passivation layer (not shown). This can be achieved using deposition conditions similar to those of the second step in the absence of phosphorus dopants. This layer must remain passivated after the manufacturing process is completed. When a boron doped layer is selected, there is an additional advantage of passivated high and low junctions on the back side of the wafer (e.g., solar cell). Then, in a third step, depicted in Figure 1c, the coated wafer 10 is annealed at about 600 ° C to about 12 Torr. (: The annealing temperature is as long as about! minutes to about 100 minutes. It can be used by using a tubular furnace, a belt furnace, a resistance heating furnace, an infrared furnace, a furnace using a halogen lamp, and/or rapid heat treatment. The annealing process is performed by a heating process (RTP). The annealing of the coated wafer ί can be performed under an inert atmosphere (for example, n2) or a reactive atmosphere (for example, Ni/H2) at about 700. (: to about 950) (: The annealing temperature is as long as about 15 minutes to about 30 minutes. Therefore, phosphorus 22 will diffuse into the wafer 10' and adsorb a substantial amount of impurities 16. Again, a quantity of phosphorus is on the wafer 1 The interface between the germanium compound layers 20 is diffused into the wafer i without being adsorbed. Thereby, an n-type emitter region 3 is formed near the interface between the compound layer 20 and the wafer 1 . Further, the front side 12 of the wafer is coated with a layer of stone compound 20' wherein the layer of the compound compound 20 can substantially deplete the dish. Since the nitriding or carbonization of the stone can be used as a compound of the genus 9 201030854, including the shot The surface of the wafer 10 of the polar region 30 can be passivated by the layer 2 。. Layer 20 can serve as an anti-reflective coating. Again, the annealing temperature can be in the range of from about 9501: to about 12001, typically about 1100 C. Thus, thermal oxidation of compound layer 2 can be additionally performed. In the step, an emitter is formed due to activation and diffusion of phosphorus into the wafer. Further, in this step, adsorption of metal impurities can be detected in the layer by the presence of phosphorus. The adsorption and emitter formation of metal impurities in the surface region of the semiconductor wafer and/or the bulk region are performed simultaneously in one step. Furthermore, surface passivation and/or anti-reflection can be achieved. In other examples of embodiments, the annealing temperature may typically be in the range of from about 600 °C to about 1200 °C, more typically in the range of from about 650 °C to about 780 °C or about From 7503⁄4 to about 830. (of the range, most typically in the range of from about 7 ° C to about 800. (in the range of: in a further example of the embodiment, the annealing time can be typically in the range of about 1 In the range of minutes to about 100 minutes, 'more typically The position is in the range of from about 75 minutes to about 1 minute or in the range of from about 8 minutes to about 9 minutes, most typically in the range of from about 15 minutes to about 30 minutes or from about 20 minutes to about In the range of 30 minutes. In some embodiments, two layers (eg, two layers of the same composition) may be formed during the step of depositing a ruthenium compound and a doping additive on the shixi substrate. In other examples, two different compositions may be formed during the step of depositing a ruthenium compound and a doping additive on the ruthenium substrate. An example of such an embodiment is shown in Figure 2a_2d 201030854. This example and the party example shown in the la-lc diagram are executed during the second step of the two = in: this is filled as a dopant... compound 2 " coating: sequence. First, the inclusion of the D material 20 is deposited on the front side of the wafer 10 as shown in Fig. 2b. The additional coating procedure is as in the second. Fig.: 'It is shown that the dream compound layer 24 which is not doped with antimony is formed on the layer of the compound compound 20 of the inclusion structure. Therefore, during the third step of Figure 2d, a quantity of Lin will diffuse into the wafer at the interface between Shixi wafer 10 and Shixia compound layer. Therefore, the formation of the emitter region 3〇 and the adsorption of the impurity 16 of the crystal (4) are simultaneously performed. In addition, 12 turns can provide a surface passivation while layer 24 can provide anti-reflective properties. In the variation of the examples shown in the above 2a-2d diagram, after the second step, the layer 20 may include fossils and phosphorus, and the layer includes nitrogen cut without undoped scales. Another m 2g according to this example may include carbon stone and fill and the layer 24 includes a dream of nitriding without being doped. The further step 120 in this example may include nitrogen cutting and filling, while layer 24 includes tantalum carbide without undoped phosphorus. Further, layer 2 can include carbon carbide and lining and layer 24 includes carbon cut without being doped. As noted, prior to performing the annealing step, layer 2 may comprise a nitride nitride and fill or carbon cut and I may form a coated wafer 1G in a further example depicted in FIG. 3a-3d, wherein Layer 24 may have the same composition as layer 20 prior to annealing, and the concentration of dopant 22 in layer 24 is substantially equal to or lower than the concentration of dopant 22 in layer 2 . In an alternative example (not shown), the indifference of the dopant 22 may be even higher than the concentration of the dopant 22 in layer 20. Thus, layer 2 can include phosphorus doping 201030854 tantalum nitride or phosphorus doped tantalum carbide, while layer 24 also includes phosphorus doped tantalum nitride or phosphorus doped tantalum carbide. These examples have the same effect as the example explained in the la_lc diagram: the adsorption, the emitter formation, and some of the metal impurities in the surface region and/or the bulk region of a semiconductor wafer can be simultaneously performed in one step. Surface passivation and anti-reflective coating in the case. In a variation of the examples shown in Figures 2a-2d and 3a-3d, respectively (not shown), one of the two layers of the semiconductor layer can be deposited on the semiconductor substrate and then the aforesaid annealing is used. The temperature and the annealing time are annealed, and another layer is deposited and then annealed using the aforementioned annealing temperature and annealing time to form the two semiconductor compound layers. Further, in the variation of the example shown in the 2a-2d diagram (not shown), the semiconductor compound layer 2 can be doped without doping before the annealing of either or both of the individual layers and 24 Layer 24 can include dopants 22. In these variations, after annealing, the same structure as shown in Fig. 2d or Fig. 3d can be produced. • Typical examples of layer 2 and layer 24 are a-SiCx* a-SiyCx (eg, a-Si〇.8C〇.2) and a_SiNx* a_SiyNx, where χ is typically in the range of 〇 to about 1, and y is typical The status is in the range of more than 〇 to about 。. The thickness of the layer formed can range from about 3 minutes to about 12 〇 11 〇 1 range. Additionally, a suitable amount of hydrogen and/or oxygen or other components may be included in layers 20 and 24 to provide suitable passivation and/or anti-reflective properties. An example of the hydrogen-containing layer 20 or 24 is hydrogenated phosphorus-doped amorphous lanthanum a-SiCx(n):H which is formed by performing PECVD from SiH4, Ch4, and PH3. An example of a layer 20 or 24 comprising oxygen is phosphorus 12 201030854 doped oxynitride which is grown by _n-doped stone and dried using & and 〇2 as reactive gases. According to some embodiments, the ruthenium substrate may be selected from the group consisting of a crystalline ruthenium substrate polycrystalline ruthenium substrate, a substrate having a crystalline ruthenium surface layer, and a substrate having a polycrystalline ruthenium surface layer. As noted, in accordance with some embodiments, the tantalum substrate can be a p-type tantalum substrate. In other embodiments, the tantalum substrate can be an intrinsic tantalum substrate, i.e., an undoped tantalum wafer 1 . Still further, in accordance with some embodiments, the method can include the step of forming an intrinsic germanium material layer on the back side of the germanium wafer 10. Thus, in some embodiments, the front side of the wafer 1 can be provided with a layer of doped a-antimony compound, while the back side can be composed of an intrinsic material. Therefore, the emitter formation at the back side can be avoided during the execution of this method. In other embodiments, the method can include the step of forming a doped (e.g., p-doped) material layer on the back side of the tantalum wafer 1 . The back side layer formed may be, for example, a collar doped stone surface layer. This can result in a passivated high and low junction at the back side of the coated wafer (e.g., solar cell). As previously discussed, with the embodiments described herein, adsorption and emitter formation of metal or other lattice defects in the surface region and/or bulk regions of a semiconductor wafer can be performed simultaneously in one step. Furthermore, surface passivation can be achieved when the emitter is formed and the impurities are adsorbed. In the same step, the formation of an anti-reflective coating can be completed. In addition, it is not necessary to remove the phosphorous silicate glass because the lining diffusion provided by the embodiments herein does not cause the formation of the PSG region. Moreover, the improved emitter profile of the fabricated semiconductor component or 13 201030854 solar cell can be steeper. Thus, the method of the embodiments disclosed herein allows for better control of the emitter profile. This can depend on the slow rate at which phosphorus diffuses into the wafer substrate (due to the choice of semiconductor compound and dopant and the choice of annealing temperature and annealing time). Therefore, it is possible to fabricate a semiconductor element (e.g., a solar cell) that improves the emitter region, improves surface passivation, reduces charge carrier recombination, and/or improves antireflection properties in a simple manufacturing process. Therefore, the solar cell production cost can be significantly reduced. In the following, further examples of the embodiments will be described. In the first example, a P-type boron doped polysilicon wafer was used as a substrate to have a resistivity of 200 μηι of 1 Ohm-cm. The wafer has metal impurities introduced during crystal growth. In the second step, a stack of two phosphorus-doped amorphous tantalum carbide passivation layers a-SiCx(n):H is deposited on the front side of the wafer. The deposition conditions were as follows: Reactor: PECVD, direct plasma, operating at RF frequency (13 % MHz), vacuum pressure in the reactor chamber was lower than i〇e5 hpa; gas flow: SiH4 (95%) + PH3 (5 %): 3 seem ; CH4: 32 seem ; total pressure: 3 pbar ; temperature: 300 ° C; deposition time (static): 12 minutes; power density: 0.086 W/m 2 . The formed a_SiCx(n):H double layer has antireflective properties, a thickness of 80 nm, and a refractive index of 2.00 at a wavelength of 622 nm. In the second step, the coated wafer is annealed at a temperature of ν2 atmosphere for an annealing time of up to 20 minutes. The precursor of the solar cell was formed. Only multiple contacts need to be applied. The second example differs from the first example in that the second example performs the backside of the wafer with an essentially non-aa carbonized fossil film of a SiCx(1):H after the second step 201030854 and before the annealing of the third step. Passivation. The deposition conditions correspond to the deposition conditions of the second step, and there is no phosphorus dopant. Reactor: PECVD, direct plasma, operating at RF frequency (13.56 MHz); vacuum pressure in the reactor chamber is less than l〇e_5 hPa; gas flow. SiH4 (95 / ό) + ΡΗ 3 (5%): 3 seem CH4:32 seem; total pressure: 3 pbar; temperature: 30 (TC; deposition time (static is 12 minutes; power density: 0.086 W/m2. In the second example, the first step of the first example is performed, but The third step was changed to a temperature at which the coated wafer was annealed at 780 for up to 75 minutes. In the fourth example, the third example was changed to a temperature at which the coated wafer was annealed at 780 °C. Up to 20 minutes. According to an embodiment, the present invention provides a method of fabricating a semiconductor device, comprising: providing a semiconductor substrate; forming a layer comprising a semiconductor compound and a doping additive on the semiconductor substrate; and subsequently forming An emitter region, and by annealing the semiconductor substrate including the layer to getter impurities. Therefore, the formation of the emitter region and the adsorption of the impurities are performed in one step, typically simultaneously. Can be adsorbed by doping additives. The metal may be a metal impurity or other lattice defect. In an embodiment that may be combined with any of the other embodiments herein, the semiconductor substrate is a germanium substrate and the semiconductor compound is a wonderful compound' and the annealing is performed by Heating at about 6 Torr. 〇 to an annealing of about 120 ° C 15 201030854 The temperature is extended from about 1 minute to an annealing time of about i 〇〇 minutes. An embodiment that can be combined with any of the other embodiments herein. In the step of forming the layer, a doped semiconductor compound layer is formed on the surface of the semiconductor substrate. The doped semiconductor layer may be amorphous. In one can be combined with any other embodiment herein. In an embodiment, in the step of forming the layer, at least two layers of the same or different composition are formed. In an embodiment that can be combined with any of the other embodiments herein, in the step of forming the layer, Forming at least two layers, at least two of the layers comprising the same semiconductor compound or different semiconductor compounds. One can be combined with any of the other embodiments herein. In an embodiment, the at least one semiconductor compound comprises at least one selected from the group consisting of ruthenium compounds, ruthenium carbide, and tantalum nitride. In an embodiment that can be combined with any of the other embodiments herein, the doping is added The article comprises at least one selected from the group consisting of a p-type dopant, an n-type dopant, phosphorus, and arsenic. In an embodiment that can be combined with any of the other embodiments herein, the step of forming the layer This is performed by sputtering the semiconductor compound with the doping additive. Typically, a target comprising the semiconductor compound and the doping additive can be sputtered. In one can be combined with any of the other embodiments herein. In an embodiment, the step of forming the layer is performed by PEcvd of a gas mixture comprising at least one of SiH4 and a group selected from the group consisting of NH3, CH4, and 201030854 PH3. In an embodiment that can be combined with any of the other embodiments herein, the surface of the semiconductor substrate is oxidized during the annealing step. In an embodiment that can be combined with any of the other embodiments herein, the semiconductor substrate is selected from the group consisting of a crystalline substrate, a crystalline substrate, a multi-ro substrate, and a crystalline germanium surface layer. One of a group consisting of a substrate and a substrate having a polycrystalline surface layer.
在一可以與本文中任何其他實施例結合的實施例中， 該半導體基材係為選自由一 n_型半導體基材、—p型半 導體基材、一本質半導體基材、-卜型矽基材、一卜型 矽基材、及一本質矽基材所構成群組之至少一者。 在一可以與本文中任何其他實施例結合的實施例中， 該退火溫度係位於約㈣。c至約78Gt範圍中或位於約 950°C至約1200°C範圍中。 、 在一可以與本文中任何其他實施例結合的實施例中， 該退火時間係位於約75分鐘至約1〇〇 I鐘範圍中或位 於約15分鐘至約3〇分鐘範圍中。 在一可以與本文中任何其他實施例結合的實施例中，In an embodiment that can be combined with any of the other embodiments herein, the semiconductor substrate is selected from the group consisting of an n-type semiconductor substrate, a p-type semiconductor substrate, an intrinsic semiconductor substrate, At least one of a material, a ruthenium substrate, and an intrinsic ruthenium substrate. In an embodiment that can be combined with any of the other embodiments herein, the annealing temperature is at about (four). From c to about 78 Gt or in the range of from about 950 ° C to about 1200 ° C. In an embodiment that may be combined with any of the other embodiments herein, the annealing time is in the range of from about 75 minutes to about 1 〇〇 I or in the range of from about 15 minutes to about 3 minutes. In an embodiment that can be combined with any of the other embodiments herein,
該半導體基材包括—前側與-背側，並且該半導體化合 物層形成在該前側上》 Q 在一可以與本文中任何其他實施例結合的實施例中， 該方法更包含在該背側上形成一層的一步驟該層包含 -本質或-經摻雜之半導體化合物。該經摻雜之 化合物可以是摻雜或p_摻雜（例如硼摻雜卜 17 201030854 在一可以與本文中任何其他實施例結合的實施例中， 退火是藉由一加熱程序來執行，該加熱程序係使用選自 由一管狀爐、一帶狀爐、一電阻式加熱爐、一紅外線爐、 及多個鹵素燈所構成群組之至少一者。 在另一實施例中，本發明提供一種半導體元件，其可 藉由一半導體元件製造方法來獲得，該方法包括：提供 一半導體基材；在該半導體基材上形成一包括半導體^ 合物與摻雜添加物的層；以及接著形成一射極區域，並 且藉由將包括該層的該半導體基材予以退火以吸附雜 質。 ’ 在進一步實施例中，本發明提供一種半導體元件，其 係藉由一半導體元件製造方法來獲得，該方法包括：提 供一半導體基材；在該半導體基材上形成一包括半導體 化合物與摻雜添加物的層；以及接著形成一射極區域， 並且藉由將包括該層的該半導體基材予以退火以吸附雜 質。 ’ 根據又進一步實施例，本發明提供一種半導體元件製 造方法，該方法實質上由下列步驟構成：提供一半導體 基材；在該半導體基材上形成一包括半導體化合物與摻 雜添加物的層；以及接著形成一射極區域，並且藉由將 包括該層的該半導體基材予以退火以吸附雜質。 根據另一實施例，本發明提供一種半導體元件，其可 藉由任何前述實施例之方法來獲得。 根據另一實施例，本發明提供一種半導體元件，其係 18 201030854 藉由任何前述實施例之方法來獲得。The semiconductor substrate includes a front side and a back side, and the semiconductor compound layer is formed on the front side. In an embodiment that can be combined with any of the other embodiments herein, the method further includes forming on the back side. One step of a layer This layer comprises an intrinsic or - doped semiconductor compound. The doped compound can be doped or p-doped (eg, boron doped). In an embodiment that can be combined with any of the other embodiments herein, annealing is performed by a heating process. The heating program uses at least one selected from the group consisting of a tubular furnace, a belt furnace, a resistance heating furnace, an infrared furnace, and a plurality of halogen lamps. In another embodiment, the present invention provides a a semiconductor device obtainable by a method of fabricating a semiconductor device, the method comprising: providing a semiconductor substrate; forming a layer comprising a semiconductor compound and a doping additive on the semiconductor substrate; and then forming a An emitter region, and adsorbing impurities by annealing the semiconductor substrate including the layer. In a further embodiment, the present invention provides a semiconductor device obtained by a method of fabricating a semiconductor device, the method The method includes: providing a semiconductor substrate; forming a layer including a semiconductor compound and a doping additive on the semiconductor substrate; and then forming a layer a polar region, and by adsorbing the semiconductor substrate including the layer to adsorb impurities. According to still further embodiments, the present invention provides a method of fabricating a semiconductor device, the method consisting essentially of: providing a semiconductor based Forming a layer including a semiconductor compound and a doping additive on the semiconductor substrate; and then forming an emitter region, and adsorbing the semiconductor substrate by annealing the layer to adsorb impurities. By way of example, the present invention provides a semiconductor device obtainable by the method of any of the preceding embodiments. According to another embodiment, the present invention provides a semiconductor device, which is obtained by the method of any of the preceding embodiments, 18 201030854 .
根據進一步實施例，本發明提供一種半導體元件製造 設備’其包括：-塗覆裝置’其適於塗覆一半導體基材； 一加熱裝置，其適於將該經塗覆之半導體基材予以退 火’以及一控制裝置’其適於控制該塗覆裝置與該加熱 裝置，並適於執行一半導體元件製造方法，該方法包括： 提供-半導體基材；在該半導體基材上形成一包括半導 體化合物與摻雜添加物的層；以及接著形成—射極區 域’並且藉由將包括該層的該半導體基材予以退火以吸 附雜質。為了執行該提供—半導體基材的步驟，可以在 該製造設備中包括一由該控制裝置控制之基材支撐件， 例如用於在該塗覆裝置前面傳送基材之一傳送系統。 詳細說明係使用實例來揭露本發明（包括最佳實施 例）’並且也可使任何熟習此技藝之人士使用且利用本發 明。儘管本發明係'以各種特定實施例來描4，任何熟習 此技藝之人士將可瞭解的是，在不脫離申請專利範圍的 精神和範圍下’可以實施具有變化的本發明。尤其，前 述實施例之彼此非獨佔特徵可以互相結合。本發明之可 專利範圍是由中請專利範圍來界^，並且可以包括熟習 此技藝之人士所旎设想的其他實例。這樣的其他實例被 涵蓋在申請專利範圍的範嗜内。 雖然前述說明是著重在本發明的實施例，在不脫離本 發明的基本範圍下’可以設想出本發明之其他與進一步 實施例’並且本發明的範圍是由隨附中請專利範圍所決 201030854 定0 【圖式簡單說明】 本發明之前述特徵、詳細說明可以藉由參照實施例來 詳細地瞭解。附圖係關於本發明之實施例並且在下述中 被描述。一些實施例係藉由參照以下附圖而更詳細地被 描述在「實施方式」，其中： 第la-lc圖係繪示，根據實施例之一實例，一半導體 元件製造方法的步驟。 第2a-2d圖係繪示，根據實施例之另一實例，一半導 體元件製造方法的步驟。 第3a-3d圖係繪示’根據實施例之進一步實例，一半 導體元件製造方法的步雜。 【主要元件符號說明】 10 晶圓 12 前側 14 背側 16 金屬雜質 20 層 22 摻質 24 層 30 射極區域 20According to a further embodiment, the present invention provides a semiconductor device manufacturing apparatus comprising: a coating device adapted to coat a semiconductor substrate; a heating device adapted to anneal the coated semiconductor substrate And a control device adapted to control the coating device and the heating device, and adapted to perform a semiconductor device manufacturing method, the method comprising: providing a semiconductor substrate; forming a semiconductor compound on the semiconductor substrate And a layer doped with an additive; and then an emitter region is formed and the impurity is adsorbed by annealing the semiconductor substrate including the layer. In order to perform the step of providing a semiconductor substrate, a substrate support controlled by the control device may be included in the manufacturing apparatus, for example, a transfer system for transporting a substrate in front of the coating device. DETAILED DESCRIPTION OF THE INVENTION The present invention is intended to be illustrative of the invention, including the preferred embodiments thereof Although the present invention has been described in terms of various specific embodiments, it will be understood by those skilled in the art that the present invention may be practiced without departing from the spirit and scope of the invention. In particular, the mutually exclusive features of the foregoing embodiments may be combined with one another. The patentable scope of the present invention is defined by the scope of the claims, and may include other examples contemplated by those skilled in the art. Such other examples are covered by the scope of the patent application. While the foregoing is a description of the embodiments of the present invention, the invention may be construed as the <Desc/Clms Page number> [Brief Description of the Drawings] The foregoing features and detailed description of the present invention can be understood by referring to the embodiments. The drawings are related to embodiments of the invention and are described below. Some embodiments are described in more detail in the "embodiment" by referring to the following drawings, wherein: a la-lc diagram shows the steps of a method of fabricating a semiconductor device according to an example of an embodiment. 2a-2d are diagrams showing the steps of a method of fabricating a half conductor element, according to another example of an embodiment. Figures 3a-3d are diagrams showing the steps of a half conductor element fabrication method, according to further examples of embodiments. [Main component symbol description] 10 Wafer 12 Front side 14 Back side 16 Metal impurity 20 layers 22 Doping 24 layers 30 Emitter area 20