201025567 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體裝置，祥細而言係關於一種高 耐壓半導體裝置。 【先前技術】 電源用IC(Integrated Circuit，積幾：電路）中所使用之起動 電路中，一般而言係使用高对麼之MOSFET(Metallic Oxide Semiconductor Field Effect Transistor，金屬氧化物 半導體場效應電晶體），例如LDMOS(Laterally Diffused MOS，橫向擴散金屬氧化物半導體）。先前之起動電路如 圖32A所示，係於LDMOS 411之汲極-閘極間連接數ΜΩ之 電阻R，以控制LDMOS 4 11之驅動及斷開時之偏壓電流。 該電路構成中，當藉由主電源之導通而對起動端子T施 加高位準之電壓時，高位準之電壓經由電阻R被施加至 LDMOS 411之閘極，從而LDMOS 41 1導通，電流被供給至 内部電路412。 其後，當内部電路412動作而將LDMOS之閘極電壓設為 低位準時，LDMOS 411斷開，朝向内部電路412之電流之 供給停止。 該起動電路中，經由電阻R而始終流動有與電源電壓相 應之偏壓電流。因此，不適合低功耗化。又，因LDMOS 411 之汲極係直接打線接合於1C封裝之插腳，故而於施加有靜 電等之情形時，電阻有時會被破壞。 因此，考慮採用圖328所示之電各構成，由吓£丁413進 143695.doc 201025567 行LDMOS 411之驅動及洩漏電流之控制，藉此改善上述之 問題。藉由該電路構成，LDMOS 411斷開之期間之偏壓電 流被規定為JFET 413之飽和電流，相對於電壓之電流成為 固定值。又，因未使用對突波電壓較弱之高電阻，故破壞 變強。 然而，若將該起動電路直接IC化，則需要2個高耐壓元 件’從而會佔據較廣之晶片面積。 又，眾所周知有使用JFET進行起動用元件之高耐壓化與 低導通電阻化之技術。然而，若採用如此之1!?]£11之構成則 件面積會增大，並且需要2個獨立之高耐壓元件，就此 點而言並無改變。 【發明内容】 [發明所欲解決之問題] 本發明係鐾於上述實際情況而完成者，其目的在於提供 -種具有作為起動電路之優異特性並且適合積體化之半導 艎電路。 又，本發明另—目的在於使用單—之半導體元件構成起 動電路，或者提供舍合JL古h 伢匕3具有較小之佔有面積的半導體元件 之起動電路。 [解決問題之技術手段] 為了達成上述目的，本發明之半導體裝置之特徵在於包 括： 第1導電型之層（Π)，· 第2導電型之層〇2)，其形成於上述第！導電型之層⑼ 143695.doc 201025567 第1導電型之元件分離區域（13)’其自上述第2導電型之 層（12)之表面區域到達上述第丨導電型之層（11)，規定作為 第2導電型之汲極區域（121)而發揮功能之元件區域； 第1導電型之第1區域（15)，其形成於上述元件區域； 第2導電型之第1源極區域（16)，其形成於該第〗導電型 之第1區域（15); 第1閘極電極（20)，其於上述第〗導電型之第〗區域（15) 内，形成於位於上述汲極區域（121)與上述第丨源極區域 (16)之間的區域之上；以及 第2源極區域（23)，其於上述第2導電型之層（12)内，形 成於在逆偏壓時藉由自上述元件分離區域（】3)、上述第1導 電型之層（11)、及上述第}導電型之第i區域（ls)中之至少 任一者延伸之空乏層而控制與上述汲極區域（ΐ2ι)之間之通 道的位置處。 較好的是，上述第1導電型之元件分離區域包括： 圈狀部（131)，其一部分形成有開口部（133)，且規定上述 汲極區域（121);以及部分（132)，其規定經由上述開口部 (133)連接於上述汲極區域（121)之第2導電型之延伸區域 (122)； 上述第2導電型之第2源極區域（23)係形成於上述第2導 電型之延伸區域（122)。 較好的是，上述第2導電型之延伸區域（122)係沿著上述 圈狀部（131)形成。 143695.doc 201025567 較好的是，上述半導體裝置包括對上述第1導電型之元 件分離區域（13)施加特定之電壓之機構。 較好的是’上述開口部（133)設置於上述元件分離區域 (13)之上述圈狀部（Mi)之一部分。 較好的是，規定上述第2導電型之延伸區域（122)之部分 (132)係形成為圓弧狀，上述第2導電型之延伸區域係 於上述圈狀部（131)與規定上述第2導電型之延伸區域（122) φ 之部分（132)之間形成為圓弧狀。 較好的是，於上述開口部（133)上形成絕緣膜（35)，於該 閘極絕緣膜（3 5)上配置閘極電極（36)，且可設定或調整施 加至該閘極電極（3 6)之閘極電壓。 較好的是，於上述開口部（133)内之上述第1導電型之層 (11)與上述第2導電型之層（12)之間，形成濃度比上述開口 部（13 3)内之上述第2導電型之層（12)之雜質濃度高之第2導 電型之第2區域（37)。 φ 較好的是，上述第2導電型之第2區域（37)係形成於上述 開口部（133)及上述第2導電型之延伸區域（122)内。 較好的是，上述第2導電型之第2源極區域（23)係於上述 第1導電型之第1區域（15)與規定上述汲極區域（121)之上述 元件分離區域（13)之間，形成於上述汲極區域（121)之表面 區域。 較好的是，上述第2導電型之第2源極區域（23)係比上述 第1導電型之第1區域（15)及上述元件分離區域（13)形成為 更淺。 143695.doc 201025567 較好的是，於上述第2導電型之汲極區域（121)之中央部 形成有沒極引出區域（14)，且上述第1導電型之第1區域 (15)以包圍該汲極引出區域（14)之方式而形成為圈狀。 較好的是’上述第1導電型之層（U)之表面區域上形成有 雜質濃度可調整之第2導電型之第1區域（22)。 較好的是，上述第2導電型之第1區域（22)包括：形成於 沒極區域（121)之正下方之圓盤狀之區域（22c);以及形成 於第1導電型之第1區域（15)之下之環狀之區域（22R)。 較好的是，上述圓盤狀之區域（22C)及上述環狀之區域 (22R)分別包括r部、倒r部、及直線部，上述r部之雜質 濃度設為比上述直線部之雜質濃度高，並且上述直線部之 雜質濃度設為比上述倒R部之雜質濃度高。 較好的是，上述圓盤狀之區域（22C)及上述環狀之區域 (22R)係使用開口率可設定之離子遮罩並藉由離子注入而 形成，與上述圓盤狀之區域（22C)及環狀之區域（22R)之R 部對應之部分的開口率設為比與直線部對應之部分的開口 率高’並且與直線部對應之部分的開口率設為比與倒尺部 對應之部分的開口率高。 較好的是，上述第2導電型之第1區域（22)係使用開口率 可設定之離子遮罩並藉由離子注入而形成。 較好的是，上述第1導電型之元件分離區域（1 3)係以包 圍上述第2導電型之第1區域（22)及上述第1導電型之第1區 域（15)之方式而形成為圈狀。 較好的是，上述第2導電型之第2源極區域（23)係於上述 143695.doc 201025567 第1導電型之第1區域（15)與上述元件分離區域（13)之間形 成為圈狀。 較好的是，上述第2導電型之第2源極區域（23)係於上述 第1導電型之第1區域（15)與上述元件分離區域（13)之間， 於圓周方向之一部分形成有1個或複數個。 例如，上述第2導電型之汲極區域（121)、上述第2導電 •型之第1源極區域（16)及閘極電極（20)構成 ^ LDMOS(Laterally Diffused MOS)，上述第 2 導電型之汲極 區域（121)、第2導電型之第2源極區域（23)及上述第1導電 型之元件分離區域（13)構成jFET(junction Field-Effect201025567 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, and is generally concerned with a high withstand voltage semiconductor device. [Prior Art] In a startup circuit used in a power supply IC (Integrated Circuit), a MOSFET (Metallic Oxide Semiconductor Field Effect Transistor) is generally used. For example, LDMOS (Laterally Diffused MOS). As shown in Fig. 32A, the previous starting circuit is connected to a resistor R of a few Ω Ω between the drain and the gate of the LDMOS 411 to control the bias current when the LDMOS 4 11 is driven and turned off. In the circuit configuration, when a high level voltage is applied to the start terminal T by the conduction of the main power source, a high level voltage is applied to the gate of the LDMOS 411 via the resistor R, so that the LDMOS 41 1 is turned on, and the current is supplied to Internal circuit 412. Thereafter, when the internal circuit 412 operates to set the gate voltage of the LDMOS to the low level, the LDMOS 411 is turned off, and the supply of current to the internal circuit 412 is stopped. In the starting circuit, a bias current corresponding to the power supply voltage is always flowing through the resistor R. Therefore, it is not suitable for low power consumption. Further, since the drain of the LDMOS 411 is directly bonded to the pin of the 1C package, the resistance may be broken when static electricity or the like is applied. Therefore, considering the electrical configuration shown in Fig. 328, the driving of the LDMOS 411 and the leakage current control are controlled by the 413 695.doc 201025567, thereby improving the above problem. With this circuit configuration, the bias current during the period in which the LDMOS 411 is turned off is defined as the saturation current of the JFET 413, and the current with respect to the voltage becomes a fixed value. Further, since the high resistance to the surge voltage is not used, the damage becomes strong. However, if the starting circuit is directly ICized, two high withstand voltage elements are required to occupy a wider wafer area. Further, it is known that a JFET is used to perform high voltage resistance and low on-resistance of a starting element. However, if such a composition of 1!?]£11 is used, the area will increase and two independent high-voltage components are required, and there is no change in this point. [Problem to be Solved by the Invention] The present invention has been made in view of the above-described actual circumstances, and an object thereof is to provide a semiconductor circuit having excellent characteristics as a starting circuit and suitable for integration. Further, the present invention is another object of constituting a starting circuit using a semiconductor element of a single type or a starting circuit for a semiconductor element having a small occupied area. [Means for Solving the Problems] In order to achieve the above object, a semiconductor device of the present invention is characterized in that: a layer of a first conductivity type (a layer of a second conductivity type) and a layer of a second conductivity type (2) are formed in the above-mentioned first! Conductive type layer (9) 143695.doc 201025567 The first conductivity type element isolation region (13)' is obtained from the surface region of the second conductivity type layer (12) to the layer 11 conductivity type layer (11). An element region that functions as a drain region (121) of the second conductivity type; a first region (15) of the first conductivity type is formed in the element region; and a first source region (16) of the second conductivity type Formed in the first region (15) of the first conductivity type; the first gate electrode (20) is formed in the first region (15) of the first conductivity type in the drain region ( 121) above the region between the second source region (16); and the second source region (23) formed in the second conductivity type layer (12) during reverse bias Controlling the above by the depletion layer extending from at least one of the element isolation region (3), the first conductivity type layer (11), and the ith region of the first conductivity type (ls) The position of the channel between the bungee regions (ΐ2ι). Preferably, the element isolation region of the first conductivity type includes: a ring portion (131) having a portion (133) formed therein and defining the drain region (121) and a portion (132). a second conductivity type extension region (122) connected to the drain region (121) via the opening (133) is defined; and the second conductivity type second source region (23) is formed on the second conductive region Extended area of type (122). Preferably, the extension region (122) of the second conductivity type is formed along the loop portion (131). 143695.doc 201025567 Preferably, the semiconductor device includes means for applying a specific voltage to the element isolation region (13) of the first conductivity type. Preferably, the opening portion (133) is provided in a portion of the ring portion (Mi) of the element isolation region (13). Preferably, the portion (132) defining the extension region (122) of the second conductivity type is formed in an arc shape, and the extension region of the second conductivity type is defined by the loop portion (131) and the predetermined number The conductive portion (122) φ portion (132) is formed in an arc shape. Preferably, an insulating film (35) is formed on the opening (133), and a gate electrode (36) is disposed on the gate insulating film (35), and can be set or adjusted to be applied to the gate electrode. (3 6) The gate voltage. Preferably, a concentration is formed between the layer (11) of the first conductivity type and the layer (12) of the second conductivity type in the opening (133) in a ratio of the opening (13 3). The second region (37) of the second conductivity type in which the second conductivity type layer (12) has a high impurity concentration. Preferably, the second region (37) of the second conductivity type is formed in the opening (133) and the extension region (122) of the second conductivity type. Preferably, the second source region (23) of the second conductivity type is the first region (15) of the first conductivity type and the element isolation region (13) defining the drain region (121). Between the surface regions of the above-described drain region (121). Preferably, the second source region (23) of the second conductivity type is formed to be shallower than the first region (15) of the first conductivity type and the element isolation region (13). 143695.doc 201025567 Preferably, a non-polar lead-out area (14) is formed in a central portion of the second conductivity type drain region (121), and the first conductive type first region (15) is surrounded The drain lead-out region (14) is formed in a loop shape. Preferably, the first region (22) of the second conductivity type in which the impurity concentration is adjustable is formed on the surface region of the layer (U) of the first conductivity type. Preferably, the first region (22) of the second conductivity type includes a disk-shaped region (22c) formed directly under the non-polar region (121); and a first region formed in the first conductivity type The area of the ring below the area (15) (22R). Preferably, the disk-shaped region (22C) and the annular region (22R) respectively include a r portion, an inverted r portion, and a straight portion, and an impurity concentration of the r portion is set to be larger than an impurity of the linear portion. The concentration is high, and the impurity concentration of the straight portion is set to be higher than the impurity concentration of the inverted R portion. Preferably, the disc-shaped region (22C) and the annular region (22R) are formed by ion implantation using an ion mask having an aperture ratio, and the disc-shaped region (22C) The aperture ratio of the portion corresponding to the R portion of the annular region (22R) is set to be higher than the aperture ratio of the portion corresponding to the straight portion, and the aperture ratio of the portion corresponding to the straight portion is set to correspond to the scale portion. The portion of the opening ratio is high. Preferably, the first region (22) of the second conductivity type is formed by ion implantation using an ion mask whose aperture ratio can be set. Preferably, the element isolation region (13) of the first conductivity type is formed to surround the first region (22) of the second conductivity type and the first region (15) of the first conductivity type. It is a circle. Preferably, the second source region (23) of the second conductivity type is formed as a circle between the first region (15) of the first conductivity type and the element isolation region (13) of the 143695.doc 201025567. shape. Preferably, the second source region (23) of the second conductivity type is formed between the first region (15) of the first conductivity type and the element isolation region (13), and is formed in one of the circumferential directions. There are 1 or a plurality. For example, the second conductivity type drain region (121), the second conductivity type first source region (16), and the gate electrode (20) constitute LDMOS (Laterally Diffused MOS), and the second conductive layer The drain region (121) of the type, the second source region (23) of the second conductivity type, and the element isolation region (13) of the first conductivity type constitute a jFET (junction Field-Effect)
Transistor)。 [發明之效果] 根據本發明，可使LDM0S與JFET之構成之一部分共用 化。 【實施方式】 ❿ 參照圖式說明本發明實施形態之半導體裝置及其製造方 法。 (第1實施形態） 以下，說明本發明第1實施形態之半導體裝置。 本實細形態之半導體裝置100具有内置有LDMOS(Latera办 Diffused MOS)^JFET(Junction FET(Field-Effect Transistor)(# 面型場效電晶體））的構成β 首先’參照圖1〜圖5說明該半導體裝置100之構成。圖1〜 圖3係半導體裝置1〇〇之 剖面圖’圖4係表示圖1所示之磊晶 143695.doc 201025567 層之表面區域中所呈現之雜質層之分布的平面圖。圖5係 表示電極配置之平面圖。圖1係圖4及圖5之Α_Α線處之箭頭 剖面圖’圖2係圖4及圖5之Β-Β線處之箭頭剖面圖，圖3係 圖4及圖5之C-C線處之箭頭剖面圖。 參照圖1〜圖5說明半導體裝置1〇〇之構成。 如圖1_所示’半導體裝置1〇〇包括ρ型半導體基板（第1導 電型之贗）11、磊晶層（第2導電型之層）12、Ρ型之元件分離 區域（第1導電型之元件分離區域）13、汲極引出區域14、p 型之主靆區域（第1導電型之第i區域）15、N型之源極區域 (第2導電型之第丄源極區域）16、主體引出區域17、場絕緣 膜18、間極絕緣膜19、閘極電極（第1閘極電極）20、場板 21、N型嵌入區域（第2導電型之第1區域）22、N型之源極引 出區域（第2導電型之第2源極區域）23、表面絕緣膜14〇、汲 極電極141、源極電極161、主體電極171及源極電極231。 P型丰導體基板n包括p型單晶矽基板。 蟲曰曰層12為藉由蟲晶成長而形成於P型半導體基板11上 之1^型早晶發層。 表面絕緣膜140為形成於磊晶層12之整個表面之相對較 厚之Si〇2等絕緣體之層。 元件;^離區域13係規定元件區域者，由p型之擴散區域 所構成，且具有自磊晶層12之表面到達ρ型半導體基板u 之深度。元件分離區域13係由相對高濃度之基板側擴散區 域°卩位輿相對低濃度之表面側擴散區域部位所構成。元件 分離區域13係以與主體區域15相同之步驟而製造。再者， 143695.doc -10- 201025567 較理想的是元件分離區域13係以專用步驟而形成，且將元 件分離區域13整體設為相對高濃度。 如圖1、圖2、圖4所示，元件分離區域13係以包圍n型篏 入區域（第2導電型之第1區域）22及主體區域15之方式而形 成為圈狀，詳細而言形成為環狀《元件分離區域13具備： 一部分形成有寬度為5〜100 μπι、例如30 μιη左右之開口部 ' 133的圈狀詳細而言為環狀的環狀部13 1 ;以及鄰接於環狀 參 部且自開口部I33延伸之圓弧狀延伸部I32。 由環狀部131與Ρ型半導體基板1丨所圍成之ν型之島狀區 域係作為LDMOS與JFET所共用之Ν型没極區域121而發揮 功能。 又’環狀部13 1、延伸部13 2、及Ρ型半導體基板11係規 定經由開口部133而連接於島狀區域（環狀部13 1所定義之 圓盤狀之Ν型汲極區域121)的Ν型延伸區域（第2導電型之延 伸區域）122。即，Ν型延伸區域122以沿著環狀部13 1之方 φ 式於環狀部131與延伸部132之間形成為圓弧狀。即，磊晶 層12包括Ν型汲極區域121及Ν型延伸區域122。 没極引出區域14形成於Ν型沒極區域121之中央部之表面 區域，且如圖4所示，係平面形狀為環狀之ν型高濃度層。 汲極引出區域14之中央部分配置有場絕緣膜24。 表面絕緣膜140上配置有由Α1(鋁）等導電體所構成之汲 極電極141。汲極電極141經由接觸孔連接於汲極引出區域 14。汲極電極141亦可作為連接墊而發揮功能，例如，直 接連接（焊接）有接線。 143695.doc •11- 201025567 汲極引出區域14實現LDMOS及JFET所共用之1^型汲極區 域121與汲極電極141之歐姆接觸。 主體區域〗5為p型之擴散區域，且如圖4所示，於N型沒 極區域121内形成為圈狀詳細而言形成為環狀。位於主體 區域15之内周側且與閘極電極2〇對向之表面區域係作為 LDMOS之通道區域而發揮功能。又，主體區域15之其他 區域係作為LDMOS之主體區域而發揮功能。 源極區域16為N型之區域，且如圖4所示，於主體區域15 内形成為環狀。源極區域16係作為LDMOS之源極區域而 發揮功能。 主體引出區域17為P型之高濃度區域，且於主體區域15 内之源極區域16之外側形成為圈狀詳細而言形成為環狀。 如圖1及圖5所示，於主體引出區域17之上配置有包括…等 導電體之環狀之主體電極171。主體電極171經由接觸孔而 與主體引出區域17接觸。主體引出區域17將自主體電極 1 71施加之固定之後閘極電壓施加至主體區域〗5。 % 絕緣膜 18包括 LOCOS(Local Oxidation of Silicon，石夕 局部氧化）等相對較厚之絕緣膜。場絕緣膜i 8以包圍汲極 引出區域14之方式形成於n型沒極區域121上。 閘極絕緣膜19包括Si〇2膜等絕緣膜，且形成於場絕緣膜 1 8與源極區域16之間之通道區域上。 閘極電極20包括添加有雜質之多晶矽膜或A1膜等導電 膜’且形成於閘極絕緣膜19之上及場絕緣膜18之端部之 143695.doc -12· 201025567 場板2 1包括經由絕緣膜21丨而彼此電容耦合之複數個環 狀之導電體。場板21將其正下方之N型汲極區域121之電位 之梯度維持為大致固定之梯度。 N型嵌入區域22為形成於p型半導體基板丨丨之表面區域上 且雜質濃度可調整之N型區域。該N型嵌入區域22若為要 求高耐壓之元件，則雜質濃度形成為相對較低，另一方 面，若為要求低導通電阻之元件，則雜質濃度形成為相對 較高。 源極引出區域23為配置於N型延伸區域122之表面區域之 N型之尚濃度層。如圖1及圖5所示，於表面絕緣膜14〇之上 配置有包括A1等導電體之jFET之源極電極231。源極電極 23 1經由接觸孔連接於源極引出區域23。N型延伸區域1 係作為JFET之源極區域而發揮功能。源極引出區域23係形 成源極引出電極231與N型延伸區域122之間之歐姆接觸。 上述之構成中，LDMOS之沒極區域包括n型汲極區域 121’通道區域包括主體區域15之内周側之表面區域，源 極包括源極區域16’主體包括主體區域15,汲極電極包括 沒極電極141，閘極電極包括閘極電極2〇，源極電極包括 源極電極161 ’主體電極包括主體電極17丨，閘極絕緣膜包 括閘極絕緣膜19。 另一方面，JFET之汲極區域包括n型j：及極區域121，通 道區域包括元件分離區域13之開口部133，源極區域包括N 型延伸區域122’汲極電極包括汲極電極14][，閘極電極包 括元件分離區域13，源極電極包括源極電極231。 143695.doc 201025567 於如此之構成之半導體裝置100上，例如，如圖6所示配 置有電極墊。例如，汲極電極141上直接焊接有接線。 又，閘極電極20連接於電極墊31，LDMOS之源極電極161 連接於電極墊32。進而，JFET之源極電極23 1連接於電極 墊33。各電極墊上焊接有接線。再者，該等電極墊之配置 之有無或配置位置等可任意設定。 藉由上述構成，如圖7之等價電路所示，半導體裝置100 構成具有共用之汲極區域（汲極電極141)之LDMOS 51與 JFET 52，進而形成於LDMOS 51與JFET 52之間之元件分 離區域13之開口部133構成JFET 52之閘極之一部分。 考察在該狀態下，以如圖8所示之方式進行連接，而構 成與圖32B所示之起動電路相同之由LDMOS 51與JFET 52 形成之起動電路的情形。 該構成中，元件分離區域13(JFET 52之閘極電極）及 LDMOS 51之主體電極171均接地。又，LDMOS 51之閘極 電極20與JFET 52之源極電極231相連接。又，LDMOS 51 及JFET 52之共用之汲極電極141連接於施加汲極電壓Vd之 電源。進而，LDMOS 51之源極電極161與JFET 52之源極 電極231均連接於内部電路413。 若在該狀態下向汲極電極141施加正之汲極電壓Vd，則 電流（汲極-源極間電流Ids)按照汲極電極141 —汲極引出區 域14—N型汲極區域121 —環狀部131之開口部133 —延伸區 域122 —源極引出區域23 —源極電極231之路徑而流經JFET 5 2之汲極-源極間。 143695.doc -14- 201025567 而且，若使汲極電壓Vd逐漸上升，則如圖10所示， JFET 52之没極-源極間電流Ids逐漸增加。又，藉由j：及極_ 源極間電流Ids，LDMOS 5 1之閘極電極20得到充電，電流 亦流經LDMOS 5 1之没極-源極間，且伴隨没極電壓yd之上 升而電流增加。 • 藉由將正之汲極電壓Vd施加至汲極電極141，從而正之 ‘ 電壓經由汲極引出區域14而施加至蟲晶層12。於是，由元 ^ 件分離區域13之P型之環狀部131及P型半導體基板11與1^型 之從日日層12所構成之PN接面，會因施加至蟲晶層12之正之 電壓而發生逆偏壓。因此’如圖9A〜圖9C模式性地所示， 伴隨汲極電壓Vd之上升，自pn接面起於磊晶層丨2之開口 部133 ’空乏層DL逐漸擴展。如此，若汲極電壓vd低於特 定值（飽和電壓：圖10中為電壓Vsat)，則環狀部131之開口 部133不會被空乏層DL封閉，通道被導通（控制），汲極_源 極間流動有電流Ids。 修另一方面’若沒極電壓Vd達到特定值（飽和電壓：圖1〇 中為電壓Vsat)，則如圖9D模式性地所示，環狀部131之開 口部133(JFET 52之通道區域）中磊晶層12整體被空乏層DIj 封閉，通道被阻斷（控制），成為夾斷（pinch 〇闳狀態。如 圖1〇所不，夾斷以後，JFET 52之汲極-源極間電流Ids飽 和’而成為大致固定。 因此，根據上述構成之起動電路，LDMOS 51與JFET 52 並聯連接，不僅可而耐壓化，而且藉由對ldM〇s 5丨及 FET 52所共用之汲極電極丨4丨施加特定電壓（電壓乂以{)以上 143695.doc 15 201025567 之没極電壓Vd而成為夾斷狀態，JFET 5 2之；ρ及極-源極間電 流Ids被限制為固定值，從而可抑制功耗。 又，上述構成之半導體裝置100中，形成於LDMOS 51與 JFET 52之間之元件分離區域13之開口部133構成JFET 5 2 之閘極之一部分，進而LDMOS 51與JFET 52共有N型沒極 區域121，JFET 52沿著LDMOS 51之外周而形成。因此， 以相對較小之佔有面積便可形成2個半導體元件。 又’藉由使汲極電極141形成為相對較大，而可直接焊 接於汲極電極141上，從而無需自元件之中心引出高壓配 線又，；及極電極141兼作焊墊，因此無需設置汲極電極 141用之焊墊，從而不需要用於連接之焊墊面積。 因可直接焊接於汲極電極141上，故不再另外需要保護 元件，且，以LDMOS 51之耐受量便可實現針對突波之保 護。 以上之說明中，係將形成於環狀部131之作為通道區域 之開口和3的寬度（JFET52之閘極電極之寬度）設為3〇叫 左右進行說明，但開口部133之大小亦可進行適#設定以 獲得目標飽和電Μ及飽和電流。即，可適#變更開口部 133之大小、雜質濃度、N型延伸區域122之雜質濃度、大 小等，藉此控制空乏層之楯屎。& n , 擴展而且，藉此，可將飽和電 壓及飽和電流設定為所期望之佶 q ,别至炙值，或者以任意之特性進行 控制。 又’以上之說明中，係俊pj主 1之P里丰導體基板n及元件分離 區域13(JFET 52之閘極電極、技从 毪）接地，但施加至各區域之電壓 143695.doc •16· 201025567 為任意。例如’在理論上亦可藉由使用作為施加特定電壓 之機構之直流電源對p型半導體基板U&P型之元件分離區 域13施加負電壓，從而使自元件分離區域13與磊晶層12之 PN接面延伸之空乏層〇]1進一步擴展以降低飽和電壓及飽 和電流。 圖11表示使p型半導體基板丨丨及卩型之元件分離區域13之 . 電位（對元件分離區域13之施加電壓）強制性變化之情形時 φ 的汲極電壓Vd與JFET52之汲極-源極間電流Ids的關係。如 圖所示藉由使52之閘極電塵Vg(對元件分離區域13 之施加電壓）變化，成為夾斷之電壓（飽和電壓Vsat)發生變 化’並且飽和電流Isat亦發生變化。 又，如圖12中之刮面所示，於元件分離區域〖3之開口部 133(JFET 52之通道區域）上形成絕緣膜（閘極絕緣膜）35。 而且’亦可構成為於該閘極絕緣膜35上配置閘極電極％， 且可設定或調整施加於閘極電極3 6之閘極電壓。 ❹ 若以接地電位（P型半導體基板11之電位）為基準而對閘 極電極36施加正之閘極電壓Vg，則JFET 52之通道區域（開 口部133内之N型磊晶層12)上所生成之空乏層難以延伸。 因此，隨著進一步正增大閘極電壓Vg ’飽和電壓Vsat及飽 和電流Isat均可增大。再者’閘極電極3 6可僅配置於開口 部133之上’或者’亦可呈環狀地整體配置。 又’如圖13之剖面所示，藉由將n型嵌入區域（第2導電 型之第2區域）37配置於JFET 52之通道區域（開口部133)， 可調整飽和電流Isat。即’藉由於開口部13 3内之P型半導 143695.doc 17 201025567 體基板11與磊晶層12之間，形成高濃度（以開口部i33内之 N型磊晶層12之雜質濃度為基準）tN型嵌入區域37，且調 整N型嵌入區域37之雜質濃度與n型嵌入區域37之上面之 深度’從而可調整没極-源極間之飽和電流Isat。 比起未配置N型嵌入區域37之情形，藉由配置N型嵌入 區域37，自P型半導體基板U側延伸之空乏層之位置更 低，飽和電壓Vsat更大，飽和電流Isat亦更大。再者，]^型 嵌入區域37亦能以開口部133内之N型磊晶層12為基準而設 為低雜質濃度。 又，N型嵌入區域37例如，可如圖14A所示僅形成於 JFET 52之通道區域’可如圖14B所示形成於JFET 52之通 道區域及其附近，亦可如圖14C所示形成於JFET 52之通道 區域及N型延伸區域122内。如此，n型嵌入區域37所佔之 面積越大’則飽和電壓Vsat及飽和電流isat越大。又，亦 可如圖14D所示使N型嵌入區域37延伸而與N型嵌入區域22 構成為一體。進而，亦可如圖14E所示，不形成（除去）主體 區域15之一部分，而調整飽和電壓Vsat及飽和電流Isat。 一般而言，只要其他條件相同，則N型嵌入區域37之N 型之雜質濃度越高，飽和電壓Vsat及飽和電流Isat越上 升；N型嵌入區域37越深，飽和電壓Vsat及飽和電流13以越 上升；N型嵌入區域37越寬，飽和電壓Vsat及飽和電流Isat 越上升。 再者，N型嵌入區域22、37之濃度或濃度分布，例如， 可如後述般’藉由適當設定離子注入（擴散）時所使用之離 143695.doc 201025567 子遮罩之開口率而進行調整。 又，亦可藉由變更JFET 52之源極引出區域23及源極電 極231之位置，而調節飽和電流Isat。例如，如圖15所示， 伴隨使自開口部133至源極引出區域23及源極電極231的位 置由距離JFET 52之通道區域（開口部133)較近之第1位置pi 起依序遠離至P2、P3，可縮小飽和電流Isat。尤其藉由設 • 置由環散部131與圓弧狀之延伸部132所夾持之圓弧狀之n 型延伸區域122，不會過度增大JFET 52之大小便可縮小飽 和電流Isat。 (實施形態之半導體裝置之說明） 以上說明之參考用半導體裝置之構成中，開口部133之 大小（寬度）被限定’伴隨汲極電壓Vd之上升，環狀部13 1 之開口部133中之磊晶層12内之空乏層D]L自3方向（左右之 環狀部131與下方之P型半導體基板U2PN接面）起延伸， 因此，當汲極電壓Vd相對較小時，閘極區域夾斷。因此， Φ 難以獲传較大之飽和電壓及飽和電流。相反，即便擴大開 口部133之寬度’亦無法抑制自與p型半導體基板"之州接 自起延伸之空乏層，從而飽和電壓及飽和電流之增大化有 限。 對此U下將說明獲得相對較大之飽和電壓及飽和電流 之半導體裝置200。 (第2實施形態） 上述第1實施形態之半 LDMOS 5 1之外周之方式 導體装置100中，係以沿著 於環狀部1 3 1之外側形成有 143695.doc -19- 201025567 JFET 52之N型延伸區域（源極區域）122。與此相對，本第2 實施形態之半導體裝置2〇〇中，為進一步使半導體元件之 佔有區域小型化，而將JFET 52之源極區域配置於ldm〇s 之元件區域内。除此以外之構成除以下特別說明之情形外 與第1實施形態之半導體裝置i 〇〇相同。 圖16與圖17表示第2實施形態之半導體裝置2〇〇之結構， 圖16係半導體裝置2〇〇之剖面圖，圖17係表示圖16所示之 磊晶層12之表面區域中所呈現之雜質層之分布的平面圖。 圖1 8 A〜圖18C係模式性地表示伴隨汲極電壓Vd之上升 (0<V21<V22)而空乏層如何自主體區域15及元件分離區域 13延伸之圖。圖19係表示另一磊晶層之表面區域中所呈現 之雜質層之分布的平面圖。再者，圖16相當於圖17及圖19 之A-A線處之箭頭剖面圖。 如圖所示，第2實施形態中，元件分離區域13係以包圍N 型汲極區域121之方式而形成為圈狀詳細而言形成為環 狀，且未配置有延伸部132。元件分離區域13形成為一重 之環狀。 主體區域15以包圍汲極引出區域14之方式而形成為環 狀。 JFET 52之源極引出區域23為濃度高於N型汲極區域121 之N型之區域。源極引出區域23係於主體區域15與規定N 型汲極區域121之元件分離區域13之間，在N型沒極區域 121之表面區域上形成為環狀。源極引出區域23係比鄰接 之主體區域15及元件分離區域13形成為更淺。表面絕緣膜 143695.doc -20- 201025567 140上之與源極引出區域23對向之位置處配置有源極電極 23 1，且經由接觸孔而連接於源極引出區域23。 又’ N型嵌_入區域22包括：形成於N型沒極區域121之正 下方之圓盤狀之區域22C;以及形成於主體區域15之下之 環狀之區域22R。 該構成中，例如，若將LDMOS之主體區域15之電壓、 ' 元件分離區域U之電壓、P型半導體基板11之電壓分別設 參 為接地位準（接地電位），則伴隨汲極電壓Vd之上升，如圖 18A〜圖18C模式性地所示，空乏層DL自P型之主體區域 15、P型之元件分離區域13、及p型半導體基板丨丨與^^型之 磊晶層12及環狀之區域22R之間的PN接面起延伸。而且， 若汲極電壓Vd達到固定位準V22(V22>V21>0)，則會爽 斷。 根據該構成’ JFET 52之通道區域存在於N型之磊晶層12 內，該N型之磊晶層12存在於P型之主體區域15、p型之元 φ 件分離區域i3、P型半導體基板11之區域之間。而且，伴 隨沒極電壓Vd之上升，空乏層DL自N型之磊晶層12與主體 區域15之PN接面，及N型之磊晶層12與P型半導體基板11 之PN接面之上下2方向起延伸並夾斷。該JFET 52為藉由自 上下2方向延伸之空乏層DL而爽斷之構成。因此，可使與 閘極之橫方向之長度（本實施形態中為圓形之LDMOS，因 此相當於源極引出區域23之圓周長）對應的電流（汲極-源極 間電流Ids)流動。而且，主體區域15、源極引出區域23、 及作為JFET 52之閘極電極的元件分離區域13均係到達 143695.doc -21- 201025567 LDMOS之全周而形成為環狀，因此在可確保JFET 52之大 小較小之同時，確保吓£丁52之飽和電流18&1較大。此處， 飽和電流Isat係依存於JFET 52之大小，但亦可流動至數十 mA為止。 再者，JFET 52之源極引出區域23並不限於全周形成為 環狀之構成，亦可如圖19所示，於圓周方向之一部分形成 有1個或複數個。藉此，比起如圖17所示之源極引出區域 23到達全周而形成為環狀之結構，JFET 52之閘極電極寬 度更窄，且在維持飽和電壓Vsat(夾斷電壓）之狀態下可使 飽和電流I s at更小。 又，如圖18A-圖18C所示，利用N型嵌入區域22R之有 無，可控制自與P型半導體基板11之PN接面起之空乏層的 延伸，亦可調整飽和電壓Vsat。 又，圖16及圖17所示之結構中，與半導體裝置100不 同，N型嵌入區域22包括N型汲極區域121之正下方之N型 嵌入區域22C及主體區域15之附近之環狀之N型嵌入區域 22R。該N型嵌入區域22C、22R尤其可藉由適當設定環狀 之N型嵌入區域22R之位置、大小及雜質濃度，而控制空 乏層之擴展，且可將飽和電壓Vsat及飽和電流Isat設定為 所期望之值，或者以任意之特性進行控制。 例如，將如圖20A所示之配置於主體區域15之下之N型 嵌入區域22R，如圖20B所示延伸至源極引出區域23之下 方為止，藉此可使飽和電壓Vsat上升。 例如，將如圖20C所示之相對較淺之N型嵌入區域22R， 143695.doc -22- 201025567 如圖20D所示形成為較深，藉此可使飽和電壓Vsat上升。 例如，將如圖20E所示之主體區域15，如圖2 0F所示設得 較淺，藉此可使飽和電壓Vs at上升。 又，將如圖20G所示之主體區域15與源極引出區域23之 距離，如圖20H所示設為較長，藉此可使飽和電壓Vsat上 升。 進而，如圖21A及圖21B所示，亦可將配置於主體區域 15之下之N型嵌入區域22R於圓周方向之一部分形成1個或 複數個。其中，飽和電壓Vsat係由不存在N型嵌入區域22R 之部分所規定。 進而，亦可為N型汲極區域121正下方之N型嵌入區域 22C或配置於主體區域15之下之N型嵌入區域22R之任一者 不配置之構成。 再者，N型嵌入區域22R、22C之濃度或濃度分布例如後 述般，藉由適當設定離子注入（擴散）時所使用之離子遮罩 之開口率而實施。 如此，根據半導體裝置200，由LDMOS 5 1之主體區域 15、元件分離區域13、P型半導體基板11、及藉由該等而 夾持之N型之磊晶層12構成LDMOS 51之閘極部，並且 LDMOS 51與JFET 52共有N型汲極區域121，主體區域15與 元件分離區域1 3之間設置源極引出區域23，因此以一個元 件面積便可獲得LDMOS與JFET之兩個特性。 又，因將LDMOS與JFET並聯複合化，故而為高耐壓。 又，可直接焊接於汲極電極，因此不再另外需要用於連 143695.doc -23- 201025567 接之焊墊面積，且無需自半導體裝置之中心部引出高壓之 配線。 因可直接焊接於汲極電極141，故不再另外需要保護元 件，且以LDMO S之耐受量便可進行保護。 無需較大地變更製造製程，僅利型嵌入區域22R之 濃度、長度、位置之調整便可設定JFET 52之飽和電壓 Vsat與飽和電流isat。 (第3實施形態） 上述第1及第2實施形態中，係將LDM〇s設為圓形為 了進一步大電流化，亦可設為棒狀或梳齒狀。 如此之構成之半導體裝置之平面構成示於圖22中。再 者，圖22係表示露出於蟲晶層12之表面之半導體區域，沒 極引出區域14形成為梳形。 以包圍汲極引出區域14及場絕緣膜24之方式，將場絕緣 膜18、場板21、閘極絕緣膜19、閘極電極2〇、主體區域 15、源極區域16、主體引出區域17、源極引出區域以、及 元件分離區域13分別形成為圈狀。 因此，例如，圖22之D-D線、E-E線、F-F線處之剖面係 以圖1 6所示之構成進行說明。再者，汲極引出區域丨4是否 形成為環狀、是否配置場絕緣媒24為任意。 根據如此之構成，可使電流（汲極-源極間電流Ids)之電 流路徑形成為較寬，且可控制大電流。 再者’本第3實施形態與第2實施形態相同，係將jfeT 52 之源極區域（相當於第1實施形態之N型延伸區域122)配置 143695.doc •24· 201025567 於主體區域15與元件分離區域13之間。然而，並不限定於 此亦可與第1實施形態相同，於主體區域15之外形成具 有開口部133之環狀部13卜而且，沿著[1)河〇8配置經由 °亥開口部133連接於N型汲極區域121之N型延伸區域122。 . 進而，亦可型延伸區域122上形成源極引出區域23及源 極電極231。 • 於LDM〇S2元件結構設為棒狀之情形時，有電場集中 φ 於以包圍汲極之方式彎曲之部分（R部；圖22中為朝向下凸 出彎曲之區域），而使LDM〇s之耐壓降低之虞。另一方 面，電場未集中於雖彎曲但不包圍汲極之部分（倒尺部；圖 22中朝向上凸出彎曲之區域）。因此，為了緩和r部之電 場，較為有效的是將R部之N型嵌入區域22C ' 22R之雜質 濃度設為比直線部之N型嵌入區域22C、22R之雜質濃度 高，將直線部之N型嵌入區域22C、22R之雜質濃度設為比 倒R部之N型嵌入區域22C、22R之雜質濃度高。 φ 該情形時，若僅針對區域變更離子注入或雜質擴散之濃 度，則需要相應於離子注入之位置而變更注入製程，且必 需追加步驟，從而會導致成本上升。 該情形時，藉由對離子注入時或者雜質擴散時之遮罩進 行研究而可進行適當之濃度設定。 例如，當形成如圖22所示之梳形之元件結構的半導體裝 置100或200之嵌入區域22C時，可使用圖23A概略所示之 離子遮罩41作為離子注入遮罩。 該離子遮罩41之與如圖22之元件之R部對應之部分之開 143695.doc -25- 201025567 口 〇p的開口率（每單位面積之開口面積），設為比與直線部 對應之部分（例如，區域ST)之開口 OP的開口率高（寬），並 且與直線部對應之部分之開口 op的開口率S為比與隹代部 對應之部分之開口OP的開口率高（寬）。 因此，例如，如圖23B模式性地所示，於p型半導體基板 11上配置離子遮罩41，若自離子照射源42以均—之密度將 離子束IB照射至整個面上，貝,】以適當之濃度將離子注入至 P型半導體基板U之表面區域。注入之離子於之後之熱處 理中擴散’藉此可獲得適當之濃度分布之N型嵌入區域 22，即後步驟中所形成之梳形LDM〇s之彎曲部所對應之 部分（電場容易相對集中之部分）處雜質濃度較高而直線 部所對應之部分（電場難以相對集中之部分）處雜質濃度較 低之N型嵌入區域22。因此，即便未控制離子注入之摻雜 量或能量，亦可於彎曲部形成適當之濃度分布之N型埋設 區域22。 再者，離子遮罩41並不限於離子注入，亦可用作任音之 擴散方法之雜質遮罩。 再者’無需整體以1片離子璉罩41而形成。例如，如圖 24A〜圖241所示，準備開口 〇p之圖案或開口率不同之複數 個遮罩（或注入遮罩形成用之先罩）41a〜4u，例如，亦可於 離子注入時，以彎曲部中使用開口率高之遮罩且直線部中 使用開口率低之遮罩的方式，一面切換所使用之離子遮罩 一面進行離子注入。例如，圖24A〜圖24C中，適當調整圓 形之開口 OP之直徑、數量、配置等以調整開口率。又，圖 143695.doc •26· 201025567 24E〜圖24G中，適當調整條紋狀之開口 OP之長度、寬度、 數量、配置等以調整開口率。圖24D及圖24H中，進而調 整開口 OP之形狀以調整開口率。圖241中，可給予濃度分 布以梯度。 如上述般，藉由調整N型嵌入區域22C之濃度，可改善 及變更LDMOS之耐壓、Vd-Id特性等。例如，自尚未呈現 出圖25 A所示之飽和區域且元件耐壓較低之狀態起，適當 設定N型嵌入區域22之濃度及其分布，藉此可明確呈現出 如圖25B所示之飽和區域，從而可變更為元件财壓較高之 特性。 (第4實施形態） 其次，說明於1晶片上積體化有上述之LDMOS 5 1與 JFET 52之複合元件及其他任意之半導體元件的第4實施形 態。 此處，如圖26所示，除了 LDMOS 51與JFET 52之外，亦 使如下電路共用汲極地形成於1晶片上，該電路包括用於 大電流所流經之功率LDMOS 53、及用於檢測流經功率 LDMOS 53之電流的感測器LDMOS 54。 圖2 7表不於1晶片上形成圖26所不之電路時之區域配置 與電極配置之一例。該構成係採用圖1〜3所示之構成作為 LDMOS 51及JFET 52日寺之示例。 圖27中，區域411上形成有第1實施形態中所說明之 LDMOS 51及JFET 52。自N型汲極區域121引出延伸區域 122，N型汲極區域121上配置有LDMOS 51之閘極電極20、 143695.doc -27- 201025567 源極電極161、及主體電極171。進而’延伸區域122上配 置有JFET 52之源極電極231。區域411之剖面G-G與自圖1 之剖面之汲極電極141算起的右半分為相同之構成。 又，區域412上形成有感測器LDM〇S 54，感測器 LDMOS 54上配置有閘極電極（第3閘極電極）321與源極電 極3 22。其他區域上形成有功率LDMOS 53，且配置有：於 區域411處開口且以包圍汲極電極141之方式而配置之閘極 電極（第2閘極電極）331，及於區域411及區域412具有開口 部且以包圍汲極電極141之方式而配置之琢極電極332。 功率LDMOS 53之閘極電極331與感測IfLDMOS 54之閘 極電極321形成為一體。又，LDMOS 51之閘極電極20、功 率LDMOS 53之閘極電極331及感測器LDMOS 54之閘極電 極321係異體地構成。進而，功率LDMO S 53之源極電極 332、感測器LDMOS 54之源極電極322、LDMOS 51之源極 電極161、及JFET 5 2之源極電極231分別異體地構成。 再者，功率LDMOS 53之主體引出區域與主體電極以任 意之大小而形成於任意之位置。 功率LDMOS 53之剖面H-H、及感測器LDMOS 54之剖面 I-Ι具有共同之構成，且如圖29所示，除了未設置JFET 52 之源極區域23、主體區域（第1導電型之第2區域）15與元件 分離區域13係連接之外，與上述LDMOS 51之構成相同。 再者，功率LDMOS 53用之主體區域（第1導電型之第2區 域）15與感測器LDMOS 54用之主體區域（第1導電型之第3區 域）15構成為一體。又，LDMOS 51及JFET 52用之主體區域 143695.doc -28· 201025567 15與功率LDMOS 53及感測器LDMOS 54用之主體區域15係 異體地構成。再者，功率LDMOS 53用之主體區域15與感 測器LDMOS 54用之主體區域15亦可為異體。 而且，於元件區域之中央部配置有4個元件之共用 汲極區域121，其中央配置有汲極引出區域14與汲極電極 14卜Transistor). [Effect of the Invention] According to the present invention, it is possible to share a part of the configuration of the LDMOS and the JFET. [Embodiment] A semiconductor device and a method of manufacturing the same according to embodiments of the present invention will be described with reference to the drawings. (First embodiment) Hereinafter, a semiconductor device according to a first embodiment of the present invention will be described. The semiconductor device 100 of the present embodiment has a configuration in which an LDMOS (Dafused MOS) device (Junction FET (Field-Effect Transistor)) is built in. First, 'refer to FIG. 1 to FIG. 5 The configuration of the semiconductor device 100 will be described. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 to Fig. 3 are cross-sectional views of a semiconductor device 1'. Fig. 4 is a plan view showing the distribution of impurity layers present in the surface region of the epitaxial layer 143695.doc 201025567 shown in Fig. 1. Fig. 5 is a plan view showing an electrode configuration. 1 is an arrow cross-sectional view of the Α-Α line at FIGS. 4 and 5'. FIG. 2 is an arrow cross-sectional view of the Β-Β line at FIGS. 4 and 5, and FIG. 3 is an arrow at the CC line of FIG. 4 and FIG. Sectional view. The configuration of the semiconductor device 1A will be described with reference to Figs. 1 to 5 . As shown in FIG. 1_, the semiconductor device 1 includes a p-type semiconductor substrate (first conductivity type) 11 , an epitaxial layer (layer of a second conductivity type) 12, and a germanium-type element isolation region (first conductive) Type element isolation region) 13, drain lead region 14, p-type main germanium region (first conductivity type i-th region) 15, N-type source region (second conductivity type third source region) 16. The main body lead-out region 17, the field insulating film 18, the inter-electrode insulating film 19, the gate electrode (first gate electrode) 20, the field plate 21, and the N-type embedded region (the first region of the second conductivity type) 22, The N-type source lead-out region (the second conductivity type second source region) 23, the surface insulating film 14A, the drain electrode 141, the source electrode 161, the body electrode 171, and the source electrode 231. The P-type conductor substrate n includes a p-type single crystal germanium substrate. The insect layer 12 is a type of early crystal growth layer formed on the P-type semiconductor substrate 11 by the growth of insect crystals. The surface insulating film 140 is a layer of a relatively thick insulator such as Si〇2 formed on the entire surface of the epitaxial layer 12. The element 13 is a region defining a device region, and is composed of a p-type diffusion region and has a depth from the surface of the epitaxial layer 12 to the p-type semiconductor substrate u. The element isolation region 13 is composed of a relatively high concentration substrate-side diffusion region, a relatively low-concentration surface-side diffusion region portion. The element separation region 13 is manufactured in the same steps as the body region 15. Further, 143695.doc -10- 201025567 It is preferable that the element isolation region 13 is formed in a dedicated step, and the entire element isolation region 13 is set to a relatively high concentration. As shown in FIG. 1 , FIG. 2 , and FIG. 4 , the element isolation region 13 is formed in a ring shape so as to surround the n-type intrusion region (the first region of the second conductivity type) 22 and the body region 15 . The element-separating region 13 is provided with a ring-shaped annular portion 13 1 having a ring shape in which a portion of the opening portion 133 having a width of 5 to 100 μm, for example, about 30 μm is formed in detail; and a ring-shaped portion 13 1 adjacent to the ring An arc-shaped extending portion I32 extending from the opening portion I33. The island-shaped region of the ν-type surrounded by the annular portion 131 and the Ρ-type semiconductor substrate 1 发挥 functions as the 没-type non-polar region 121 shared by the LDMOS and the JFET. Further, the annular portion 13 1 , the extending portion 13 2 , and the 半导体-type semiconductor substrate 11 are connected to the island-shaped region via the opening 133 (the disk-shaped 汲-type drain region 121 defined by the annular portion 13 1 ) The 延伸-type extension region (the extension region of the second conductivity type) 122. That is, the meandering extension region 122 is formed in an arc shape between the annular portion 131 and the extending portion 132 along the square φ of the annular portion 13 1 . That is, the epitaxial layer 12 includes a Ν-type drain region 121 and a Ν-type extension region 122. The electrodeless lead-out region 14 is formed in a surface region of the central portion of the meandering-type non-polar region 121, and as shown in Fig. 4, is a v-shaped high-concentration layer having a circular planar shape. A field insulating film 24 is disposed at a central portion of the drain lead-out region 14. A surface electrode 141 made of a conductor such as Α1 (aluminum) is disposed on the surface insulating film 140. The drain electrode 141 is connected to the drain lead-out region 14 via a contact hole. The drain electrode 141 can also function as a connection pad, for example, a connection (weld) is directly connected. 143695.doc •11- 201025567 The drain lead-out area 14 realizes ohmic contact between the 1^-type drain region 121 shared by the LDMOS and the JFET and the drain electrode 141. The main body region 〖5 is a p-type diffusion region, and as shown in Fig. 4, it is formed in a ring shape in the N-type non-polar region 121 and is formed in a ring shape in detail. The surface region located on the inner peripheral side of the main body region 15 and facing the gate electrode 2A functions as a channel region of the LDMOS. Further, the other regions of the main body region 15 function as the main region of the LDMOS. The source region 16 is an N-type region, and as shown in FIG. 4, is formed in a ring shape in the body region 15. The source region 16 functions as a source region of the LDMOS. The main body lead-out area 17 is a P-type high concentration region, and is formed in a ring shape on the outer side of the source region 16 in the main body region 15 in detail in a ring shape. As shown in Figs. 1 and 5, a ring-shaped body electrode 171 including a conductor such as ... is disposed on the main body lead-out area 17. The body electrode 171 is in contact with the body lead-out region 17 via the contact hole. The body lead-out area 17 applies a gate voltage to the body area 〖5 after the fixing from the body electrode 171 is applied. The % insulating film 18 includes a relatively thick insulating film such as LOCOS (Local Oxidation of Silicon). The field insulating film i 8 is formed on the n-type non-polar region 121 so as to surround the drain lead-out region 14. The gate insulating film 19 includes an insulating film such as a Si 〇 2 film, and is formed on a channel region between the field insulating film 18 and the source region 16. The gate electrode 20 includes a polysilicon film or a conductive film such as an A1 film to which an impurity is added, and is formed on the gate insulating film 19 and the end portion of the field insulating film 18. 143695.doc -12· 201025567 Field plate 2 1 includes via The insulating film 21 is a plurality of annular conductors that are capacitively coupled to each other. The field plate 21 maintains the gradient of the potential of the N-type drain region 121 directly below it to a substantially constant gradient. The N-type embedded region 22 is an N-type region formed on the surface region of the p-type semiconductor substrate and having an adjustable impurity concentration. In the case where the N-type embedded region 22 is a device requiring a high withstand voltage, the impurity concentration is relatively low, and on the other hand, if the device requires a low on-resistance, the impurity concentration is relatively high. The source lead-out region 23 is an N-type concentration layer disposed in the surface region of the N-type extension region 122. As shown in Figs. 1 and 5, a source electrode 231 of a jFET including a conductor such as A1 is disposed on the surface insulating film 14A. The source electrode 23 1 is connected to the source lead-out region 23 via a contact hole. The N-type extension region 1 functions as a source region of the JFET. The source lead-out region 23 forms an ohmic contact between the source lead-out electrode 231 and the N-type extension region 122. In the above configuration, the gate region of the LDMOS includes the n-type drain region 121', the channel region includes the surface region of the inner peripheral side of the body region 15, the source includes the source region 16', the body includes the body region 15, and the drain electrode includes The electrode electrode 141, the gate electrode includes a gate electrode 2A, the source electrode includes a source electrode 161', the body electrode includes a body electrode 17A, and the gate insulating film includes a gate insulating film 19. On the other hand, the drain region of the JFET includes an n-type j: and a polar region 121, the channel region includes an opening portion 133 of the element isolation region 13, and the source region includes an N-type extension region 122' the drain electrode includes a drain electrode 14] [The gate electrode includes the element isolation region 13 and the source electrode includes the source electrode 231. 143695.doc 201025567 On the semiconductor device 100 thus constructed, for example, an electrode pad is disposed as shown in FIG. For example, the gate electrode 141 is directly soldered with a wiring. Further, the gate electrode 20 is connected to the electrode pad 31, and the source electrode 161 of the LDMOS is connected to the electrode pad 32. Further, the source electrode 23 1 of the JFET is connected to the electrode pad 33. Wiring is soldered to each electrode pad. Further, the presence or absence of the arrangement of the electrode pads, the arrangement position, and the like can be arbitrarily set. With the above configuration, as shown in the equivalent circuit of FIG. 7, the semiconductor device 100 constitutes the LDMOS 51 and the JFET 52 having the common drain region (the drain electrode 141), and further forms the element between the LDMOS 51 and the JFET 52. The opening portion 133 of the separation region 13 constitutes a part of the gate of the JFET 52. In this state, the case where the start-up circuit formed by the LDMOS 51 and the JFET 52 is formed in the same manner as the start-up circuit shown in Fig. 32B is constructed in the manner shown in Fig. 8. In this configuration, the element isolation region 13 (the gate electrode of the JFET 52) and the body electrode 171 of the LDMOS 51 are both grounded. Further, the gate electrode 20 of the LDMOS 51 is connected to the source electrode 231 of the JFET 52. Further, the common drain electrode 141 of the LDMOS 51 and the JFET 52 is connected to a power source to which the gate voltage Vd is applied. Further, the source electrode 161 of the LDMOS 51 and the source electrode 231 of the JFET 52 are both connected to the internal circuit 413. When a positive drain voltage Vd is applied to the drain electrode 141 in this state, the current (drain-source current Ids) is ring-shaped according to the drain electrode 141 - the drain lead-out region 14 - the N-type drain region 121 - The opening portion 133 of the portion 131 - the extension region 122 - the source extraction region 23 - the path of the source electrode 231 flows between the drain and the source of the JFET 52. 143695.doc -14- 201025567 Moreover, if the drain voltage Vd is gradually increased, as shown in FIG. 10, the gate-source current Ids of the JFET 52 gradually increases. Moreover, the gate electrode 20 of the LDMOS 5 1 is charged by the j: and the pole-source current Ids, and the current also flows between the gate and the source of the LDMOS 5 1 with the rise of the gate voltage yd. The current increases. • By applying the positive drain voltage Vd to the drain electrode 141, the positive voltage is applied to the crystal layer 12 via the drain lead-out region 14. Then, the P-shaped annular portion 131 and the P-type semiconductor substrate 11 of the element isolation region 13 and the PN junction formed by the solar layer 12 are formed by the crystallization layer 12 Reverse bias occurs with voltage. Therefore, as shown schematically in Fig. 9A to Fig. 9C, the opening portion 133' of the epitaxial layer 丨2 from the pn junction gradually expands with the increase of the gate voltage Vd. As described above, if the drain voltage vd is lower than a specific value (saturation voltage: voltage Vsat in FIG. 10), the opening portion 133 of the annular portion 131 is not closed by the depletion layer DL, and the channel is turned on (controlled), the drain _ There is a current Ids flowing between the sources. On the other hand, if the electrodeless voltage Vd reaches a specific value (saturation voltage: voltage Vsat in FIG. 1A), as shown schematically in FIG. 9D, the opening portion 133 of the annular portion 131 (the channel region of the JFET 52) The middle epitaxial layer 12 is completely enclosed by the depletion layer DIj, and the channel is blocked (controlled) to become pinch-off (pinch 〇闳 state. As shown in Figure 1 ,, after pinch-off, the JFET 52 drain-source The current Ids is saturated and becomes substantially constant. Therefore, according to the start-up circuit of the above configuration, the LDMOS 51 is connected in parallel with the JFET 52, and is not only resistant to voltage but also has a drain which is shared by the ldM〇s 5丨 and the FET 52. The electrode 丨4丨 is applied to a pinch-off state by applying a specific voltage (voltage 乂 to {) to 143695.doc 15 201025567, the pinch-off state, JFET 5 2; ρ and the pole-source current Ids are limited to a fixed value, Further, in the semiconductor device 100 having the above configuration, the opening portion 133 of the element isolation region 13 formed between the LDMOS 51 and the JFET 52 constitutes one of the gates of the JFET 5 2, and further the LDMOS 51 and the JFET 52. There is a total of N-type non-polar region 121, JFET 52 along LDMOS 51 The outer circumference is formed. Therefore, two semiconductor elements can be formed with a relatively small occupied area. Further, by forming the drain electrode 141 to be relatively large, it can be directly soldered to the drain electrode 141, thereby eliminating the need for self- The center of the component leads to the high-voltage wiring, and the electrode 141 also serves as a pad. Therefore, it is not necessary to provide a pad for the gate electrode 141, so that the pad area for connection is not required. Since it can be directly soldered to the gate electrode 141 Therefore, the protection element is no longer needed separately, and the protection against the surge can be achieved with the tolerance of the LDMOS 51. In the above description, the opening of the annular portion 131 as the channel region and the width of 3 are formed. (The width of the gate electrode of JFET 52) is described as about 3 〇, but the size of the opening 133 can also be set to obtain the target saturation voltage and saturation current. That is, the opening portion 133 can be changed. The size, the impurity concentration, the impurity concentration and size of the N-type extension region 122, etc., thereby controlling the enthalpy of the depletion layer. & n, expanding, and thereby, the saturation voltage and the saturation current can be set to the desired period.佶q, not to the value of 炙, or to control with any characteristics. In the above description, the Department of Pj main 1 P Penetron conductor substrate n and component separation area 13 (JFET 52 gate electrode, technology Grounding from 毪), but the voltage applied to each area is 143695.doc •16· 201025567 is arbitrary. For example, 'Phase-type P-type semiconductor substrate U&P type can also be theoretically used by using a DC power supply as a mechanism for applying a specific voltage. The element isolation region 13 applies a negative voltage, thereby further expanding the depletion layer 〇]1 extending from the element isolation region 13 and the PN junction of the epitaxial layer 12 to lower the saturation voltage and the saturation current. Fig. 11 shows the drain-source of φ and the drain-source of φ when the potential (the applied voltage to the element isolation region 13) is forcibly changed in the case of the p-type semiconductor substrate 卩 and the 分离-type element isolation region 13. The relationship between the inter-electrode current Ids. As shown in the figure, by changing the gate electric dust Vg of 52 (the applied voltage to the element isolation region 13), the pinch-off voltage (saturation voltage Vsat) changes and the saturation current Isat also changes. Further, as shown by the shaving surface in Fig. 12, an insulating film (gate insulating film) 35 is formed on the opening portion 133 (channel region of the JFET 52) of the element isolation region [3]. Further, the gate electrode % may be disposed on the gate insulating film 35, and the gate voltage applied to the gate electrode 36 may be set or adjusted. ❹ If a positive gate voltage Vg is applied to the gate electrode 36 with reference to the ground potential (potential of the P-type semiconductor substrate 11), the channel region of the JFET 52 (the N-type epitaxial layer 12 in the opening 133) is The resulting depletion layer is difficult to extend. Therefore, the saturation voltage Vsat and the saturation current Isat can be increased as the gate voltage Vg' is further increased. Further, the gate electrode 36 may be disposed only on the opening portion 133 or may be disposed integrally in a ring shape. Further, as shown in the cross section of Fig. 13, the saturation current Isat can be adjusted by disposing the n-type embedded region (the second region of the second conductivity type) 37 in the channel region (opening portion 133) of the JFET 52. That is, a high concentration is formed between the bulk substrate 11 and the epitaxial layer 12 by the P-type semiconductor 143695.doc 17 201025567 in the opening portion 13 3 (the impurity concentration of the N-type epitaxial layer 12 in the opening portion i33 is The reference n) is embedded in the region 37, and the impurity concentration of the N-type embedded region 37 and the depth of the upper surface of the n-type embedded region 37 are adjusted to adjust the saturation current Isat between the gate and the source. In the case where the N-type embedded region 37 is not disposed, by arranging the N-type embedded region 37, the position of the depletion layer extending from the P-type semiconductor substrate U side is lower, the saturation voltage Vsat is larger, and the saturation current Isat is also larger. Further, the ?-type embedded region 37 can also have a low impurity concentration based on the N-type epitaxial layer 12 in the opening portion 133. Further, the N-type embedded region 37 may be formed, for example, only in the channel region of the JFET 52 as shown in FIG. 14B and may be formed in the vicinity of the channel region of the JFET 52 as shown in FIG. 14B, or may be formed as shown in FIG. 14C. The channel region of the JFET 52 and the N-type extension region 122. Thus, the larger the area occupied by the n-type embedded region 37, the larger the saturation voltage Vsat and the saturation current isat. Further, as shown in Fig. 14D, the N-type embedded region 37 may be extended to be integrated with the N-type embedded region 22. Further, as shown in Fig. 14E, the saturation voltage Vsat and the saturation current Isat may be adjusted without forming (removing) a part of the body region 15. In general, as long as other conditions are the same, the higher the impurity concentration of the N-type of the N-type embedded region 37, the higher the saturation voltage Vsat and the saturation current Isat; the deeper the N-type embedded region 37, the saturation voltage Vsat and the saturation current 13 The higher the N-type embedded region 37 is, the higher the saturation voltage Vsat and the saturation current Isat rise. Further, the concentration or concentration distribution of the N-type embedded regions 22, 37 can be adjusted, for example, as described later by appropriately setting the aperture ratio of the 143695.doc 201025567 sub-mask used for ion implantation (diffusion). . Further, the saturation current Isat can be adjusted by changing the positions of the source lead-out region 23 and the source electrode 231 of the JFET 52. For example, as shown in FIG. 15, the position from the opening 133 to the source lead-out area 23 and the source electrode 231 is sequentially moved away from the first position pi which is closer to the channel region (opening portion 133) of the JFET 52. To P2 and P3, the saturation current Isat can be reduced. In particular, by providing the arc-shaped n-type extension region 122 sandwiched by the annular portion 131 and the arc-shaped extending portion 132, the saturation current Isat can be reduced without excessively increasing the size of the JFET 52. (Description of the semiconductor device according to the embodiment) In the configuration of the reference semiconductor device described above, the size (width) of the opening 133 is defined as 'increased with the threshold voltage Vd, and the opening portion 133 of the annular portion 13 1 The depletion layer D]L in the epitaxial layer 12 extends from the three directions (the left and right annular portions 131 and the lower P-type semiconductor substrate U2PN junction), and therefore, when the gate voltage Vd is relatively small, the gate region Pinched. Therefore, it is difficult for Φ to transmit a large saturation voltage and saturation current. On the other hand, even if the width □ of the opening portion 133 is enlarged, the depletion layer extending from the state of the p-type semiconductor substrate cannot be suppressed, and the increase in the saturation voltage and the saturation current is limited. A semiconductor device 200 that obtains a relatively large saturation voltage and saturation current will be described below. (Second Embodiment) In the conductor device 100 of the outer periphery of the half LDMOS 5 1 of the first embodiment, 143695.doc -19-201025567 JFET 52 is formed along the outer side of the annular portion 133. N-type extension region (source region) 122. On the other hand, in the semiconductor device 2 of the second embodiment, in order to further reduce the area occupied by the semiconductor element, the source region of the JFET 52 is placed in the element region of ldm〇s. The other configuration is the same as that of the semiconductor device i 第 of the first embodiment except for the case where it is specifically described below. 16 and FIG. 17 show the structure of the semiconductor device 2 of the second embodiment, FIG. 16 is a cross-sectional view of the semiconductor device 2, and FIG. 17 is a view showing the surface region of the epitaxial layer 12 shown in FIG. A plan view of the distribution of the impurity layers. Figs. 18A to 18C schematically show how the depletion layer extends from the main body region 15 and the element isolation region 13 accompanying the rise of the gate voltage Vd (0<V21<V22). Figure 19 is a plan view showing the distribution of the impurity layers present in the surface region of another epitaxial layer. Further, Fig. 16 corresponds to an arrow sectional view taken along line A-A of Figs. 17 and 19. As shown in the figure, in the second embodiment, the element isolation region 13 is formed in a ring shape so as to surround the N-type drain region 121, and is formed in a ring shape in detail, and the extension portion 132 is not disposed. The element separation region 13 is formed in a heavy ring shape. The body region 15 is formed in a ring shape so as to surround the drain lead-out region 14. The source lead-out area 23 of the JFET 52 is an N-type region having a higher concentration than the N-type drain region 121. The source lead-out region 23 is formed between the body region 15 and the element isolation region 13 defining the N-type drain region 121, and is formed in a ring shape on the surface region of the N-type gate region 121. The source lead-out area 23 is formed shallower than the adjacent body area 15 and the element isolation area 13. The surface insulating film 143695.doc -20- 201025567 140 is provided with a source electrode 23 1 at a position opposite to the source lead-out region 23, and is connected to the source lead-out region 23 via a contact hole. Further, the N-type embedded region 22 includes a disk-shaped region 22C formed directly under the N-type non-polar region 121, and an annular region 22R formed under the body region 15. In this configuration, for example, when the voltage of the main body region 15 of the LDMOS, the voltage of the element isolation region U, and the voltage of the P-type semiconductor substrate 11 are respectively set to the ground level (ground potential), the gate voltage Vd is applied. As shown in FIG. 18A to FIG. 18C, the depletion layer DL is derived from the P-type body region 15, the P-type element isolation region 13, and the p-type semiconductor substrate and the epitaxial layer 12 of the type and The PN junction between the annular regions 22R extends. Further, if the drain voltage Vd reaches a fixed level V22 (V22 > V21 > 0), it will be cooled. According to the channel region of the JFET 52, the N-type epitaxial layer 12 is present in the P-type body region 15, the p-type element φ-part isolation region i3, and the P-type semiconductor. Between the regions of the substrate 11. Further, with the rise of the gate voltage Vd, the depletion layer DL is from the PN junction of the N-type epitaxial layer 12 and the body region 15, and the PN junction of the N-type epitaxial layer 12 and the P-type semiconductor substrate 11 Extend and pinch off in 2 directions. The JFET 52 is configured to be cooled by a depletion layer DL extending from the upper and lower directions. Therefore, it is possible to flow a current (dip-source-to-source current Ids) corresponding to the length of the gate in the lateral direction (the circular LDMOS in the present embodiment, which corresponds to the circumferential length of the source lead-out region 23). Further, the body region 15, the source lead-out region 23, and the element isolation region 13 which is the gate electrode of the JFET 52 are all formed in a ring shape up to the entire circumference of the 143695.doc -21 - 201025567 LDMOS, thereby ensuring the JFET. At the same time as the size of 52 is small, it is ensured that the saturation current of 18 and 1 is larger. Here, the saturation current Isat depends on the size of the JFET 52, but may flow to several tens of mA. Further, the source lead-out area 23 of the JFET 52 is not limited to being formed in a ring shape over the entire circumference, and as shown in Fig. 19, one or a plurality of ones may be formed in one of the circumferential directions. Thereby, the gate electrode region 23 is formed in a ring shape as compared with the case where the source lead-out region 23 as shown in FIG. 17 reaches the entire circumference, and the gate electrode width of the JFET 52 is narrower and maintains the saturation voltage Vsat (pinch-off voltage). The saturation current I s at can be made smaller. Further, as shown in Figs. 18A to 18C, by the presence or absence of the N-type embedded region 22R, the extension of the depletion layer from the PN junction of the P-type semiconductor substrate 11 can be controlled, and the saturation voltage Vsat can be adjusted. Further, in the configuration shown in FIGS. 16 and 17, unlike the semiconductor device 100, the N-type embedded region 22 includes the N-type embedded region 22C directly under the N-type drain region 121 and the ring-shaped portion in the vicinity of the body region 15. N-type embedded region 22R. In particular, the N-type embedded regions 22C and 22R can control the expansion of the depletion layer by appropriately setting the position, size, and impurity concentration of the annular N-type embedded region 22R, and can set the saturation voltage Vsat and the saturation current Isat to Expected value, or controlled by any characteristic. For example, the N-type embedded region 22R disposed under the body region 15 as shown in Fig. 20A extends as shown below the source lead-out region 23 as shown in Fig. 20B, whereby the saturation voltage Vsat can be raised. For example, the relatively shallow N-type embedded region 22R, 143695.doc -22-201025567 as shown in FIG. 20C is formed deep as shown in FIG. 20D, whereby the saturation voltage Vsat can be raised. For example, the body region 15 as shown in Fig. 20E is set shallow as shown in Fig. 20F, whereby the saturation voltage Vsat can be raised. Further, the distance between the body region 15 and the source lead-out region 23 as shown in Fig. 20G is set to be long as shown in Fig. 20H, whereby the saturation voltage Vsat can be raised. Further, as shown in Figs. 21A and 21B, one or a plurality of N-type embedded regions 22R disposed under the main body region 15 may be formed in one of the circumferential directions. Among them, the saturation voltage Vsat is defined by a portion where the N-type embedded region 22R is not present. Further, it may be configured such that either the N-type embedded region 22C directly under the N-type drain region 121 or the N-type embedded region 22R disposed under the body region 15 is disposed. Further, the concentration or concentration distribution of the N-type embedded regions 22R and 22C is carried out by appropriately setting the aperture ratio of the ion mask used for ion implantation (diffusion) as will be described later. As described above, according to the semiconductor device 200, the main body region 15, the element isolation region 13, the P-type semiconductor substrate 11, and the N-type epitaxial layer 12 sandwiched by the LDMOS 51 constitute the gate portion of the LDMOS 51. And the LDMOS 51 and the JFET 52 share the N-type drain region 121, and the source lead-out region 23 is provided between the body region 15 and the element isolation region 13, so that two characteristics of the LDMOS and the JFET can be obtained with one element area. Further, since the LDMOS and the JFET are combined in parallel, the voltage is high. Moreover, it can be directly soldered to the drain electrode, so that it is no longer necessary to additionally connect the pad area to 143695.doc -23- 201025567, and it is not necessary to draw high voltage wiring from the center of the semiconductor device. Since it can be directly soldered to the drain electrode 141, the protection element is no longer required and can be protected with the tolerance of the LDMO S. The saturation voltage Vsat and the saturation current isat of the JFET 52 can be set only by adjusting the concentration, length, and position of the profit-type embedded region 22R without greatly changing the manufacturing process. (Third Embodiment) In the first and second embodiments, the LDM 〇s is rounded to have a large current, and may be a rod shape or a comb shape. The planar configuration of the semiconductor device thus constructed is shown in FIG. Further, Fig. 22 shows a semiconductor region exposed on the surface of the crystal layer 12, and the non-polar lead-out region 14 is formed in a comb shape. The field insulating film 18, the field plate 21, the gate insulating film 19, the gate electrode 2, the body region 15, the source region 16, and the body lead-out region 17 are surrounded by the drain region 14 and the field insulating film 24. The source lead-out area and the element isolation region 13 are each formed in a ring shape. Therefore, for example, the cross-sections at the D-D line, the E-E line, and the F-F line in Fig. 22 will be described with reference to the configuration shown in Fig. 16. Further, whether or not the buckling lead-out area 丨4 is formed in a ring shape or whether or not the field insulating medium 24 is disposed is arbitrary. According to this configuration, the current path of the current (drain-source current Ids) can be made wider, and a large current can be controlled. In the third embodiment, the source region of the jfeT 52 (corresponding to the N-type extension region 122 of the first embodiment) is disposed 143695.doc •24·201025567 in the body region 15 as in the second embodiment. Between the component separation regions 13. However, the present invention is not limited thereto, and the annular portion 13 having the opening 133 may be formed outside the main body region 15 and may be disposed along the [1] bank 8 via the opening portion 133. The N-type extension region 122 is connected to the N-type drain region 121. Further, the source lead-out region 23 and the source electrode 231 may be formed on the extension region 122. • When the LDM 〇 S2 element structure is rod-shaped, there is an electric field concentration φ in a portion that is bent so as to surround the dipole (R portion; in Fig. 22, a region that is convex toward the lower side), and the LDM 〇 The pressure resistance of s is reduced. On the other hand, the electric field is not concentrated on the portion that is curved but does not surround the drain (the ruled portion; the region in Fig. 22 that is convex toward the upper side). Therefore, in order to alleviate the electric field of the r portion, it is effective to set the impurity concentration of the N-type embedded region 22C ' 22R of the R portion to be higher than the impurity concentration of the N-type embedded regions 22C and 22R of the straight portion, and to set the N of the straight portion. The impurity concentrations of the embedded regions 22C and 22R are set to be higher than the impurity concentrations of the N-type embedded regions 22C and 22R of the inverted R portion. φ In this case, if the concentration of ion implantation or impurity diffusion is changed only for the region, the injection process needs to be changed depending on the position of the ion implantation, and an additional step is necessary, which causes an increase in cost. In this case, an appropriate concentration setting can be performed by investigating the mask at the time of ion implantation or when the impurities are diffused. For example, when the embedded region 22C of the semiconductor device 100 or 200 having the comb-shaped element structure as shown in Fig. 22 is formed, the ion mask 41 schematically shown in Fig. 23A can be used as the ion implantation mask. The opening ratio (opening area per unit area) of the opening 143695.doc -25- 201025567 of the ion mask 41 corresponding to the R portion of the element of FIG. 22 is set to correspond to the straight portion. The aperture ratio of the opening OP of the portion (for example, the region ST) is high (width), and the aperture ratio S of the opening op corresponding to the portion corresponding to the straight portion is higher than the aperture ratio of the opening OP corresponding to the portion corresponding to the depression portion (width) ). Therefore, for example, as schematically shown in FIG. 23B, the ion mask 41 is disposed on the p-type semiconductor substrate 11, and if the ion beam IB is irradiated to the entire surface from the ion irradiation source 42 at a uniform density, Ions are implanted into the surface region of the P-type semiconductor substrate U at an appropriate concentration. The implanted ions are diffused in the subsequent heat treatment 'by thereby obtaining an appropriate concentration distribution of the N-type embedded region 22, that is, a portion corresponding to the curved portion of the comb-shaped LDM 〇s formed in the subsequent step (the electric field is easily concentrated) The N-type embedded region 22 having a low impurity concentration at a portion where the impurity concentration is high and the portion corresponding to the straight portion (the portion where the electric field is difficult to be concentrated) is low. Therefore, even if the doping amount or energy of the ion implantation is not controlled, the N-type buried region 22 of an appropriate concentration distribution can be formed in the bent portion. Further, the ion mask 41 is not limited to ion implantation, and can also be used as an impurity mask for the diffusion method of the tone. Furthermore, it is not necessary to form the entire ion mask 41 as a whole. For example, as shown in FIG. 24A to FIG. 241, a plurality of masks (or hoods for forming a mask) 41a to 4u having different patterns or openings having different aperture ratios are prepared, for example, during ion implantation. In the curved portion, a mask having a high aperture ratio is used, and a mask having a low aperture ratio is used in the straight portion, and ion implantation is performed while switching the ion mask to be used. For example, in Figs. 24A to 24C, the diameter, the number, the arrangement, and the like of the circular opening OP are appropriately adjusted to adjust the aperture ratio. Further, in Fig. 143695.doc • 26· 201025567 24E to Fig. 24G, the length, the width, the number, the arrangement, and the like of the stripe-shaped opening OP are appropriately adjusted to adjust the aperture ratio. In Figs. 24D and 24H, the shape of the opening OP is further adjusted to adjust the aperture ratio. In Figure 241, the concentration distribution can be given as a gradient. As described above, by adjusting the concentration of the N-type embedded region 22C, the withstand voltage and Vd-Id characteristics of the LDMOS can be improved and changed. For example, since the saturation region shown in Fig. 25A is not present and the component withstand voltage is low, the concentration of the N-type embedded region 22 and its distribution are appropriately set, whereby the saturation as shown in Fig. 25B can be clearly exhibited. The area, thus changing the characteristics of higher component financial pressure. (Fourth Embodiment) Next, a fourth embodiment in which a composite element of the above-described LDMOS 5 1 and JFET 52 and any other semiconductor element are integrated on one wafer will be described. Here, as shown in FIG. 26, in addition to the LDMOS 51 and the JFET 52, the following circuit is also commonly formed on the first wafer, the circuit including the power LDMOS 53 for a large current flowing, and for detecting A sensor LDMOS 54 that flows through the current of the power LDMOS 53. Fig. 2 shows an example of an area arrangement and an electrode arrangement when a circuit of Fig. 26 is not formed on a wafer. This configuration uses the configuration shown in Figs. 1 to 3 as an example of the LDMOS 51 and the JFET 52. In Fig. 27, the LDMOS 51 and the JFET 52 described in the first embodiment are formed in the region 411. The extension region 122 is drawn from the N-type drain region 121, and the gate electrode 20, the 143695.doc -27-201025567 source electrode 161, and the body electrode 171 of the LDMOS 51 are disposed on the N-type drain region 121. Further, the source electrode 231 of the JFET 52 is disposed on the extension region 122. The section G-G of the region 411 has the same configuration as the right half of the gate electrode 141 of the section of Fig. 1. Further, a sensor LDM 〇 S is formed in the region 412. The sensor LDMOS 54 is provided with a gate electrode (third gate electrode) 321 and a source electrode 3 22 . The power LDMOS 53 is formed in another region, and is provided with a gate electrode (second gate electrode) 331 which is opened at the region 411 and is disposed to surround the gate electrode 141, and has a region 411 and a region 412 The drain electrode 332 is disposed to surround the drain electrode 141. The gate electrode 331 of the power LDMOS 53 is formed integrally with the gate electrode 321 of the sense IfLDMOS 54. Further, the gate electrode 20 of the LDMOS 51, the gate electrode 331 of the power LDMOS 53 and the gate electrode 321 of the sensor LDMOS 54 are formed separately. Further, the source electrode 332 of the power LDMO S 53 , the source electrode 322 of the sensor LDMOS 54 , the source electrode 161 of the LDMOS 51 , and the source electrode 231 of the JFET 5 2 are formed separately. Further, the main body lead-out area of the power LDMOS 53 and the main body electrode are formed at arbitrary positions in an arbitrary size. The profile HH of the power LDMOS 53 and the profile I-Ι of the sensor LDMOS 54 have a common configuration, and as shown in FIG. 29, the source region 23 and the body region of the JFET 52 are not provided (the first conductivity type) The 2 region) 15 is the same as the above-described LDMOS 51 except that it is connected to the element isolation region 13. Further, the main body region (the second region of the first conductivity type) 15 for the power LDMOS 53 and the body region (the third region of the first conductivity type) 15 for the sensor LDMOS 54 are integrally formed. Further, the body region 143695.doc -28·201025567 15 for the LDMOS 51 and the JFET 52 is configured separately from the body region 15 for the power LDMOS 53 and the sensor LDMOS 54. Further, the body region 15 for the power LDMOS 53 and the body region 15 for the sensor LDMOS 54 may be foreign bodies. Further, a common drain region 121 of four elements is disposed in the central portion of the element region, and a drain lead-out region 14 and a drain electrode 14 are disposed in the center thereof.
圖28表示於1晶片上形成圖26所示之電路時之區域配置 與電極配置之另一例。該構成為採用圖i 6及圖丨7所示之構 成作為LDMOS 51及JFET 52之情形時的構成例。圖28中， 區域411上形成有LDMOS 51與JFET 52，且形成有LDMOS 51之閘極電極20、源極電極161及主體電極171。而且，主 體電極171與元件分離區域13之間配置有jFET 52之源極電 極231。區域411之剖面G-G與自圖16之剖面之汲極電極141 鼻起的右半部分為相同之構成。 又’鄰接於區域411之區域412上形成有感測器LDMOS 54，且配置有閘極電極321與源極電極322。其他區域上形 成有功率LDMOS 53 ’且配置有：於區域413處開口且以包 圍汲極電極141之方式配置之閘極電極331，及於區域412 及區域413具有開口部且以包圍汲極電極141之方式配置成 C字狀的源極電極332。 又’功率LDMOS 53之主體引出區域與主體電極以任意 大小形成於任意位置。 功率LDMOS 53之剖面H-H、及感測器LDMOS 54之剖面 I-Ι之構成如圖29所示，除了未設置JFET 52之源極區域23、 143695.doc -29- 201025567 及主體區域（第1導電型之第2區域）15與元件分離區域13係 連接之外，與上述LDMOS 51之構成相同。 再者，功率LDMOS 53之閘極電極331與感測器LDMOS 54之閘極電極321形成為一體。又，LDMOS 51之閘極電極 20與功率LDMOS 53之閘極電極331及感測器LDMOS 54之 閘極電極321係異體地構成。進而，功率LDMOS 53之源極 電極332與感測器LDMOS 54之源極電極322係異體地椽成。 晶片之周緣部配置有功率LDMOS閘極電極連接塾*、功 率LDMOS源極電極墊、感測器LDMOS源極電極墊、 參 LDMOS源極電極墊、及LDMOS閘極墊電極等，且氽別經 由未圖示之配線及觸點而連接於對應之電極。 再者，功率LDMOS 53之主體引出區域與主體電極以任 意大小形成於任意位置。 功率LDMOS 53之剖面H-H、及感測器LDMOS 54之剖面 I-Ι具有共同之構成，且如圖29所示，除了未設置JFET 52 之源極區域23、及主體區域（第1導電型之第2區域）15與元件 分離區域13係連接之外，與上述LDMOS 51之構成相同。 . 再者，功率LDMOS 53用之主體區域（第1導電型之第2區 域）15與感測器LDMOS 54用之主體區域（第1導電型之第3 . 區域）15係構成為一體。 又，LDMOS 51及JFET 52用之主體區域15與功率 LDMOS 53及感測器LDMOS 54用之主體區域15係異體地構 成。再者，功率LDMOS 53用之主體區域15與感測器 LDMOS 54用之主體區域15亦可為異體。 143695.doc •30- 201025567 而且，於元件區域之中央部配置有4個元件之共用之N型 汲極區域121，N型汲極區域121之中央部配置有汲極引出 區域14與汲極電極14ι。 藉由如此之構成之半導體裝置，例如，i}藉由lDM〇s 51與JFET 52構成起動電路，於起動時開始對内部電路 進行電力之供給從而起動内部電路412，丨丨）起動之内部電 路412起動作為周邊電路之功率LDMOS 53而將大電流供給 φ 至對象電路，進而，根據作為周邊電路之感測器LDMOS 54之輸出而可進行監控電流值之動作，從而不再另外需要 原本所需之分立裝置。 又，藉由調整配置之電極墊，可設定任意之元件之使 用、不使用。例如，於不需要感測器LDM〇s 54之情形 夺亦可不配置感測器用之電極墊。又，於不需要高耐壓 開關之情形時，亦可不配置功率LDM〇s幻用之電極墊。 再者’亦可不組裝元件本身。 • 以上之例中，係將4個半導體元件組裝於基板π上，而 組裝何種半導體元件為任意，可僅組裝4個半導體元件中 之2個或3個’或者亦可組裝其他種類之元件等。 例如，可將JFET複合化於功率LDMOS 53上，而對共計 5個元件進行1晶片化（積體化）。該情形時，例如，如圖3〇 所示，將功率LDMOS 53設為圖1〜圖3所示之構成，且可於 任意之位置，例如於區域414上’在功率1^]^〇8幻之環狀 之凡件分離區域13形成開口部，並引出延伸部132，於該 延伸部132形成源極引出區域，且配置源極電極232。進而， 143695.doc -31· 201025567 配置JFET用之電極墊。 又，例如，如圖3 1所示，將功率LDMOS 53設為如圖16 及圖17所示之構犮，並於任意之位置，例如於區域415 上，在功率LDMOS 53之主體區域（第1導電型之第2區 域）1 5與元件分離區域13之間形成源極引出區域，並配置 源極電極232。又，配置JFET用之電極墊。 . 若設為如此之構成，例如，可將功率LDMOS與JFET之 複合體、LDMOS與· JFET之複合體、感測器LDMOS等以共 用汲極的方式組裝於1個晶片上，從而不需要分立裝置。 β 又，為了進一步增高功率LDMOS 53之耐壓且可進行大 電流驅動，而可與圖22所例示之LDMOS相同，將汲極設 為梳齒狀，且將功率LDMOS 53之閘極及源極沿著梳齒狀 之沒極區域而配置。 本發明並不限於上述實施形態，可進行各種修正及應 用。元件結構為一例，可進行適當變更。 本申請案係基於且主張2008年9月30曰申請的曰本專利 申請案第2008-25 5733號、及2009年9月25日申請的日本專 利申請案第2009-221684號之優先權，且包含該申請案之 發明之詳細說明（記明書）、申請專利範圍、圖式及發明之 概要。日本專利申請案第2008-255 733號及2009-22 1684號 所揭示之内容以引用的方式全部併入本文。 【圖式簡單說明】 圖1係本發明第1f施形態之半導體裝置之剖面圖，相當 於圖4及圖5之A-A線剖面圖； 143695.doc -32- 201025567 2係本發明第i實施形態之半導體裝置之刻面圖，相當 於圖4及圖5之B-B線剖面圖； 圖3係本發明第1實施形態之半導體裝置之剖面圖’相當 於圖4及圖5之C-C線剖面圖； 圖4係表不本發明第1實施形態之半導體裝置之蟲晶層表 面之雜質層的配置構成之平面圖； 圖5係表不本發明第1實施形態之半導體裝置之電極的配 置構成之平面圖； ❹ 圖6係表不本發明第1實施形態之半導體裝置之電極及焊 塾的配置構成之平面圖； 圖7係本發明第1實施形態之半導體裝置之等價電路之電 路圖； 圖8係將本發明第丨實施形態之半導體裝置用作起動電路 之情形時之電路圖； 圖9A係模式性地表示本發明第1實施形態之半導體裝置 Φ 中伴隨及極電壓Vd之上升（Vd=0)，空乏層於分離區域之 開口部處如何延伸之圖； 圖9 B係模式性地表示本發明第i實施形態之半導體裝置 中，伴隨汲極電壓Vd之上升（vd=vi)，空乏層於分離區域 之開口部處如何延伸之圖； 圖9C係模式性地表示本發明第1實施形態之半導體裝置 中，伴隨汲極電壓Vd之上升（Vd=V2)，空乏層於分離區域 之開口部處如何延伸之圖； 圖9D係模式性地表示本發明第1實施形態之半導體裝置 143695.doc -33· 201025567 中’伴隨沒極電壓Vd之上升（Vd=V3)，空乏層於分離區域 之開口部處如何延伸之圖j 圖10係表示本發明第1實施形態之半導體裝置中，汲極 電壓Vd與JFET之汲極-源極間電流Ids之關係之圖； 圖11係耒示本發明第1實施形態之半導體裝置中，使 JFET之閘極電壓vg變化之情形時的汲極電壓vd與JFETi 汲極-源極間電流Ids之關係的圖； 圖12係本發明第1實施形態之半導體裝置中，元件分離 區域之開口部上配置有閘極絕緣膜及閘極電極之構成的說 明圖； 圖13係本發明第1實施形態之半導體裝置中，元件分離 區域之開口部上配置有N型嵌入區域之構成的說明圖； 圖14A|表示本發明第！實施形態之半導體裝置中，圖13 所示之N型嵌入區域之平面性配置例的圖； 圖1 4B係表示本發明第！實施形態之半導體裝置中，圖13 所示之N型嵌入區域之平面性配置例的圖； 圖14C係表示本發明第！實施形態之半導體裝置中，圖13 所示之N型嵌入區域之平面性配置例的圖； 圖14D眘、表示本發明第1實施形態之半導體裝置中，圖13 所示之N型嵌入區域之平面性配置例的圖； 圖14E係表示本發明第！實施形態之半導體裝置中，主體 區域之平®性配置例的圖； 圖15係本發明第i實施形態之半導體裝置中，使jfet之 源極電極之配置變化之例的說明圖； 143695.doc • 34· 201025567 圖16係本發明第2實施形態之半導體裝置之剖面圖，相 當於圖17之A-A線剖面圖； 圖17係表示本發明第2實施形態之半導體裝置之蟲晶層 之表面上之雜質層的配置構成之平面圖； 圖18A係模式性地表示本發明第2實施形態之半導體裝置 • 中，伴隨汲極電壓Vd之上升（Vd=0)，空乏層如何自主體區 ' 域及分離區域起延伸的圖； 參 圖18B係模式性地表示本發明第2實施形態之半導體裝置 中，伴隨汲極電壓Vd之上升（Vd=V21)，空乏層如何自主 體區域及分離區域起延伸的圖； 圖18C係模式性地表示本發明第2實施形態之半導體裝置 中，伴隨汲極電壓Vd之上升（Vd=V22)，空乏層如何自主 體區域及分離區域起延伸的圖； 圖19係表示本發明第2實施形態之半導體裝置之變形例 的屋晶層之表面上之雜質層之配置構成的平面圖； • 圖2〇A係用於說明N型嵌入區域之構成之變化對飽和電 壓及飽和電流所造成的影響之圖； 圖20B係用於說明N型嵌入區域之構成之變化對飽和電 壓及飽和電流所造成的影響之圖； 圖20C係用於說明N型嵌入區域之構成之變化對飽和電 壓及飽和電流所造成的影響之圖； 圖20D係用於說明N型嵌入區域之構成之變化對飽和電 壓及飽和電流所造成的影響之圖； 圖20E係用於說明主體區域之構成對飽和電壓及飽和電 143695.doc •35- 201025567 流所造成的影響之圖； 圖20F係用於說明主體區域之構成對飽和電壓及飽和電 流所造成的影響之圖； 圖20G係用於說明主體區域與源極引出區域之距離對飽 和電壓及飽和電流所造成的影響之圖； 圖20H係用於說明主體區域與源極引出區域之距離對飽 和電壓及飽和電流所造成的影響之圖； 圖21A係表示N型嵌入區域之構成之變形例的圖； 圖21B係表示N型嵌入區域之構成之另一變形例的圖； 圖22係表示第3實施形態之半導體裝置之磊晶層之表面 區域之雜質層的配置構成之平面圖； 圖23A係表示用於形成第3實施形態之半導體裝置之N型 嵌入區域的離子遮罩之構成之圖； 圖23B係使用用於形成第3實施形態之半導體裝置之N型 嵌入區域的離子遮罩t雜質擴散之製程之說明圖； 圖24A係表示開口率不同之離子遮罩之一例的圖； 圖24B係表示開口率不同之離子遮罩之一例的圖； 圖24C係表示開口率不同之離子遮罩之一例的圖； 圖24D係表示開口率不同之離子遮罩之一例的圖； 圖24E係表示開口率不同之離子遮罩之一例的圖； 圖24F係表示開口率不同之離子遮罩之一例的圖； 圖24G係表示開口率不同之離子遮罩之一例的圖； 圖24H係表示開口率不同之離子遮罩之一例的圖； 圖241係表示開口率不同之離子遮罩之一例的圖； 143695.doc -36- 201025567 圖25 A係表示藉由調整N型嵌入區域之雜質濃度而汲極 電壓-源極、汲極電流特性發生變化之圖； 圖25B係表示藉由調整N型嵌入區域之雜質濃度而汲極 電壓-源極、汲極電流特性發生變化之圖； 圖26係表示第4實施形態之半導體裝置之等價電路之電 ‘ 路圖； 圖27係表示第4實施形態之半導體裝置之電極配置之第1 例之平面圖； 圖28係表示第4實施形態之半導體裝置之電極配置之第2 例之平面圖； 圖29係第4實施形態之半導體裝置之剖面圖，相當於圖 27、28之H-H線及I-Ι線剖面圖； 圖3 0係表示將JFET複合化於第4實施形態之半導體裝置 之功率LDMOS之第1例的平面圖； 圖31係表示將JFET複合化於第4實施形態之半導體裝置 φ 之功率LDMOS之第2例的平面圖； 圖32A係表示先前之起動電路之構成之電路圖；及 圖32B係使用JFET與LDMOS之起動電路之電路圖。 【主要元件符號說明】 11 P型半導體基板（第1導電型之 層） 12 磊晶層（第2導電型之層） 13 P型之元件分離區域（第1導電 型之元件分離區域） 143695.doc -37- 201025567Fig. 28 shows another example of the arrangement of the regions and the arrangement of the electrodes when the circuit shown in Fig. 26 is formed on one wafer. This configuration is a configuration example in the case where the configuration shown in Figs. 6 and 7 is used as the LDMOS 51 and the JFET 52. In FIG. 28, an LDMOS 51 and a JFET 52 are formed in a region 411, and a gate electrode 20, a source electrode 161, and a body electrode 171 of the LDMOS 51 are formed. Further, a source electrode 231 of the jFET 52 is disposed between the main electrode 171 and the element isolation region 13. The cross section G-G of the region 411 has the same configuration as the right half of the nose electrode 141 from the cross section of Fig. 16. Further, a sensor LDMOS 54 is formed on a region 412 adjacent to the region 411, and a gate electrode 321 and a source electrode 322 are disposed. The power LDMOS 53' is formed in another region, and is provided with a gate electrode 331 which is opened at the region 413 and is disposed to surround the gate electrode 141, and has an opening portion in the region 412 and the region 413 to surround the gate electrode In the manner of 141, the source electrode 332 is formed in a C shape. Further, the main body lead-out area of the power LDMOS 53 and the main body electrode are formed at arbitrary positions in an arbitrary size. The cross-section HH of the power LDMOS 53 and the profile I-Ι of the LDMOS 54 of the sensor are as shown in FIG. 29 except that the source region 23, 143695.doc -29-201025567 and the main body region of the JFET 52 are not provided (1st) The second region 15 of the conductivity type is connected to the element isolation region 13 and has the same configuration as that of the LDMOS 51 described above. Furthermore, the gate electrode 331 of the power LDMOS 53 is formed integrally with the gate electrode 321 of the sensor LDMOS 54. Further, the gate electrode 20 of the LDMOS 51 is formed separately from the gate electrode 331 of the power LDMOS 53 and the gate electrode 321 of the sensor LDMOS 54. Further, the source electrode 332 of the power LDMOS 53 and the source electrode 322 of the sensor LDMOS 54 are formed separately. The peripheral portion of the wafer is provided with a power LDMOS gate electrode connection 塾*, a power LDMOS source electrode pad, a sensor LDMOS source electrode pad, a reference LDMOS source electrode pad, and an LDMOS gate pad electrode, etc. Wiring and contacts (not shown) are connected to the corresponding electrodes. Further, the main body lead-out area of the power LDMOS 53 and the main body electrode are formed at an arbitrary position in an arbitrary size. The profile HH of the power LDMOS 53 and the profile I-Ι of the sensor LDMOS 54 have a common configuration, and as shown in FIG. 29, except for the source region 23 where the JFET 52 is not provided, and the body region (the first conductivity type) The second region) 15 is the same as the above-described LDMOS 51 except that it is connected to the element isolation region 13. Further, the main body region (the second region of the first conductivity type) 15 for the power LDMOS 53 and the main body region (the third region of the first conductivity type) 15 for the sensor LDMOS 54 are integrally formed. Further, the body region 15 for the LDMOS 51 and the JFET 52 is formed separately from the body region 15 for the power LDMOS 53 and the sensor LDMOS 54. Furthermore, the body region 15 for the power LDMOS 53 and the body region 15 for the sensor LDMOS 54 may be foreign bodies. 143695.doc • 30- 201025567 Further, a common N-type drain region 121 of four elements is disposed in a central portion of the element region, and a drain lead-out region 14 and a drain electrode are disposed at a central portion of the N-type drain region 121. 14ι. With the semiconductor device thus constructed, for example, the start-up circuit is constituted by the lDM〇s 51 and the JFET 52, and the supply of electric power to the internal circuit is started at the time of starting to start the internal circuit 412, and the internal circuit is activated. 412 starts the power LDMOS 53 as the peripheral circuit and supplies a large current to φ to the target circuit, and further, according to the output of the sensor LDMOS 54 as the peripheral circuit, the operation of monitoring the current value can be performed, so that the original required is no longer required. Separate device. Further, by adjusting the electrode pads of the arrangement, it is possible to set the use of any of the components without using them. For example, the electrode pad for the sensor may not be disposed in the case where the sensor LDM 〇 s 54 is not required. Further, when a high withstand voltage switch is not required, the electrode pad of the power LDM 〇 s illusion may not be disposed. Furthermore, the components themselves may not be assembled. • In the above example, four semiconductor components are mounted on the substrate π, and any semiconductor components are assembled. Only two or three of the four semiconductor components can be assembled' or other types of components can be assembled. Wait. For example, the JFET can be composited on the power LDMOS 53, and a total of five elements can be wafer-formed (integrated). In this case, for example, as shown in FIG. 3A, the power LDMOS 53 is configured as shown in FIGS. 1 to 3, and can be at any position, for example, on the area 414, 'at power 1^^^8 The phantom ring-shaped portion separating region 13 forms an opening portion, and leads the extending portion 132. The extending portion 132 forms a source lead-out region, and the source electrode 232 is disposed. Further, 143695.doc -31· 201025567 configures an electrode pad for a JFET. Further, for example, as shown in FIG. 31, the power LDMOS 53 is configured as shown in FIGS. 16 and 17, and is located at any position, for example, on the region 415, in the main region of the power LDMOS 53 (the A source lead-out region is formed between the first region of the first conductivity type 1 and the element isolation region 13 and the source electrode 232 is disposed. Further, an electrode pad for a JFET is disposed. With such a configuration, for example, a composite of a power LDMOS and a JFET, a composite of an LDMOS and a JFET, a sensor LDMOS, and the like can be assembled on one wafer so as to share a drain, thereby eliminating the need for separation. Device. Further, in order to further increase the withstand voltage of the power LDMOS 53 and perform high-current driving, the drain electrode can be set to be comb-like and the gate and source of the power LDMOS 53 can be the same as the LDMOS illustrated in FIG. It is arranged along the comb-toothed region. The present invention is not limited to the above embodiment, and various modifications and applications are possible. The element structure is an example and can be changed as appropriate. The present application is based on and claims the priority of Japanese Patent Application No. 2008-25517, filed on Sep. 30, 2008, and Japanese Patent Application No. 2009-221684, filed on Sep. 25, 2009. A detailed description (description) of the invention including the application, an outline of the patent application, a schematic and an outline of the invention. The contents disclosed in Japanese Patent Application No. 2008-255733 and No. 2009-22 1684 are hereby incorporated by reference in entirety. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention, which corresponds to a cross-sectional view taken along line AA of FIG. 4 and FIG. 5; 143695.doc -32-201025567 2 is an i-th embodiment of the present invention 3 is a cross-sectional view taken along line BB of FIG. 4 and FIG. 5; FIG. 3 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention, which corresponds to a cross-sectional view taken along line CC of FIG. 4 and FIG. 5; 4 is a plan view showing an arrangement of impurity layers on the surface of the crystal layer of the semiconductor device according to the first embodiment of the present invention; and FIG. 5 is a plan view showing an arrangement of electrodes of the semiconductor device according to the first embodiment of the present invention; FIG. 6 is a plan view showing an arrangement of electrodes and pads of the semiconductor device according to the first embodiment of the present invention; FIG. 7 is a circuit diagram of an equivalent circuit of the semiconductor device according to the first embodiment of the present invention; FIG. 9A is a circuit diagram showing a case where the semiconductor device according to the first embodiment of the present invention is used as a starter circuit. FIG. 9A is a schematic diagram showing the rise of the pole voltage Vd (Vd=0) in the semiconductor device Φ according to the first embodiment of the present invention. FIG. 9B schematically shows a rise in the drain voltage Vd (vd=vi) in the semiconductor device according to the first embodiment of the present invention, and the depletion layer is in the separation region. FIG. 9C is a view schematically showing how the depletion layer is at the opening of the separation region in the semiconductor device according to the first embodiment of the present invention, with the increase in the gate voltage Vd (Vd=V2). FIG. 9D is a schematic diagram showing the rise of the immersion voltage Vd (Vd=V3) in the semiconductor device 143695.doc-33·201025567 according to the first embodiment of the present invention, and the opening of the vacant layer in the separation region. FIG. 10 is a view showing the relationship between the drain voltage Vd and the drain-source current Ids of the JFET in the semiconductor device according to the first embodiment of the present invention; FIG. 11 is a view showing the first aspect of the present invention. In the semiconductor device of the embodiment, the relationship between the gate voltage vd when the gate voltage vg of the JFET is changed and the JFETi drain-source current Ids is shown in FIG. 12; FIG. 12 is a semiconductor device according to the first embodiment of the present invention. Medium component separation FIG. 13 is a view showing a configuration in which an N-type embedded region is disposed in an opening portion of the element isolation region in the semiconductor device according to the first embodiment of the present invention. Figure 14A| shows the invention! In the semiconductor device of the embodiment, a plan view of the N-type embedded region shown in Fig. 13 is shown; Fig. 1B shows the invention! In the semiconductor device of the embodiment, FIG. 13 is a view showing a planar arrangement example of the N-type embedded region; and FIG. 14C is a view showing the present invention! In the semiconductor device of the embodiment, a planar arrangement example of the N-type embedded region shown in FIG. 13 is shown. FIG. 14D shows the N-type embedded region shown in FIG. 13 in the semiconductor device according to the first embodiment of the present invention. A diagram of a planar arrangement example; Fig. 14E shows the invention of the present invention! FIG. 15 is an explanatory diagram showing an example in which the arrangement of the source electrodes of jfet is changed in the semiconductor device according to the first embodiment of the present invention; FIG. 15 is an explanatory diagram of an example in which the arrangement of the source electrodes of the jfet is changed in the semiconductor device according to the first embodiment of the present invention; FIG. 16 is a cross-sectional view of the semiconductor device according to the second embodiment of the present invention, and corresponds to a cross-sectional view taken along line AA of FIG. 17. FIG. 17 is a view showing the surface of the crystal layer of the semiconductor device according to the second embodiment of the present invention. FIG. 18A is a plan view showing a semiconductor device according to a second embodiment of the present invention. With the increase of the gate voltage Vd (Vd=0), how does the depletion layer form from the body region and FIG. 18B schematically shows how the depletion layer extends from the main body region and the separation region in accordance with the rise of the gate voltage Vd (Vd=V21) in the semiconductor device according to the second embodiment of the present invention. FIG. 18C is a view schematically showing how the depletion layer starts from the main body region and the separation region in the semiconductor device according to the second embodiment of the present invention, with the increase in the gate voltage Vd (Vd=V22). FIG. 19 is a plan view showing an arrangement of impurity layers on the surface of a roof layer of a modification of the semiconductor device according to the second embodiment of the present invention; FIG. 2A is for explaining an N-type embedded region. Fig. 20B is a diagram for explaining the influence of the change of the configuration of the N-type embedded region on the saturation voltage and the saturation current; Fig. 20C is a diagram for explaining N Figure 20D is a diagram illustrating the effect of changes in the configuration of the N-type embedded region on saturation voltage and saturation current; Figure 20E is a diagram illustrating the effect of changes in the composition of the embedded region on saturation voltage and saturation current; It is used to illustrate the effect of the composition of the body region on the saturation voltage and the saturation current 143695.doc •35- 201025567 flow; Figure 20F is a diagram illustrating the effect of the composition of the body region on the saturation voltage and saturation current. Fig. 20G is a diagram for explaining the influence of the distance between the main body region and the source lead-out region on the saturation voltage and the saturation current; Fig. 20H is for explaining the main body region FIG. 21A is a view showing a modification of the configuration of the N-type embedded region; FIG. 21B is a view showing another modification of the configuration of the N-type embedded region; FIG. 21A is a view showing a modification of the configuration of the N-type embedded region; Fig. 22 is a plan view showing an arrangement of impurity layers in a surface region of an epitaxial layer of a semiconductor device according to a third embodiment; and Fig. 23A is a view showing an N-type embedded region for forming a semiconductor device according to a third embodiment. FIG. 23B is an explanatory view showing a process for forming an ion mask t impurity diffusion for forming an N-type embedded region of the semiconductor device of the third embodiment; FIG. 24A is a view showing an ion mask having a different aperture ratio. Fig. 24B is a view showing an example of an ion mask having different aperture ratios; Fig. 24C is a view showing an example of an ion mask having different aperture ratios; and Fig. 24D is a diagram showing an ion mask having different aperture ratios. Fig. 24E is a view showing an example of an ion mask having different aperture ratios; Fig. 24F is a view showing an example of an ion mask having different aperture ratios; and Fig. 24G is a diagram showing different aperture ratios. Fig. 24H is a view showing an example of an ion mask having different aperture ratios; Fig. 241 is a view showing an example of an ion mask having different aperture ratios; 143695.doc -36- 201025567 Fig. 25 A The diagram shows the change of the drain voltage-source and drain current characteristics by adjusting the impurity concentration of the N-type embedded region; FIG. 25B shows the drain voltage-source by adjusting the impurity concentration of the N-type embedded region. FIG. 26 is a view showing an electric circuit of an equivalent circuit of the semiconductor device of the fourth embodiment; FIG. 27 is a view showing a first example of the electrode arrangement of the semiconductor device of the fourth embodiment. Fig. 28 is a plan view showing a second example of the electrode arrangement of the semiconductor device of the fourth embodiment; Fig. 29 is a cross-sectional view showing the semiconductor device of the fourth embodiment, corresponding to the HH line and I-Ι of Figs. 27 and 28. FIG. 3 is a plan view showing a first example of a power LDMOS in which a JFET is combined with a semiconductor device according to a fourth embodiment; FIG. 31 is a view showing a combination of a JFET and a semiconductor device of the fourth embodiment. LD A plan view of a second example of MOS; Fig. 32A is a circuit diagram showing a configuration of a prior art starter circuit; and Fig. 32B is a circuit diagram of a starter circuit using JFETs and LDMOSs. [Description of main component symbols] 11 P-type semiconductor substrate (layer of the first conductivity type) 12 Epitaxial layer (layer of the second conductivity type) 13 P-type element isolation region (element separation region of the first conductivity type) 143695. Doc -37- 201025567
14 汲極引出區域 15 P型之主體區域（第1導電型之 第1區域） 16 N痤之源極區域（第2導電型之 第1源極區域） 17’ 主體引出區域 18、24 場絕緣膜 19 閘極絕緣膜 20 閘極電極（第1閘極電極） 21 場板 22 N型嵌入區域（第2導電型之第 1區域） 22C 圓盤狀之區域 22R 環狀之區域 23 N魂之源極引出區域（第2導電 型之第2源極區域） 31 、 32 、 33 電極墊 35 、 211 絕緣膜 36 開極電極 37 第2導電型之第2區域 41 離子遮罩 41a〜41i 遮罩 42 離子照射源 51 、 411 LDMOS 143695.doc -38- 201025567 52 ' 413 JFET 53 功率LDMOS 54 感測器LDMOS 100 、 200 半導體裝置 121 苐2導電型之沒極區域 122 第2導電型之延伸區域 131 圈狀部 132 部分 133 開口部 140 表面絕緣膜 141 >及極電極 161、231、322、332 源極電極 171 主體電極 321 第3閘極電極 331 第2閘極電極 ^ 411 、 412 、 413 、 414 、 415 區域 412 内部電路 DL 空乏層 IB 離子束 Ids 電流 OP 開口 PI、P2、P3 位置 R 電阻 ST 區域 143695.doc 39- 201025567 τ 起動端子 V21 、 V22 固定位準 Vd、VI、V2、V3 汲極電壓 Vg 閘極電壓 Vsat 電壓 143695.doc 40-14 Deuterium lead-out area 15 P-type main body area (first area of the first conductivity type) 16 N痤 source area (first source type of the second conductivity type) 17' Main body lead-out area 18, 24 Field insulation Membrane 19 Gate insulating film 20 Gate electrode (first gate electrode) 21 Field plate 22 N-type embedded region (first region of the second conductivity type) 22C Disc-shaped region 22R Ring region 23 N soul Source lead-out area (second source type of second conductivity type) 31, 32, 33 electrode pad 35, 211 insulating film 36 open electrode 37 second region of the second conductivity type 41 ion mask 41a to 41i mask 42 ion irradiation source 51, 411 LDMOS 143695.doc -38- 201025567 52 ' 413 JFET 53 power LDMOS 54 sensor LDMOS 100, 200 semiconductor device 121 苐2 conductivity type non-polar region 122 second conductivity type extension region 131 Ring portion 132 portion 133 opening portion 140 surface insulating film 141 > and electrode electrodes 161, 231, 322, 332 source electrode 171 body electrode 321 third gate electrode 331 second gate electrode ^ 411, 412, 413, 414, 415 Area 412 Internal Circuit DL Deficient Layer IB Ion Beam Ids Current OP Opening PI, P2, P3 Position R Resistance ST Area 143695.doc 39- 201025567 τ Start Terminals V21, V22 Fixed Levels Vd, VI, V2, V3 Buckling Voltage Vg Gate voltage Vsat voltage 143695.doc 40-