201024756 '九、發明說明： ^【發明所屬之技術領域】 本發明係關於一種測試裝置，尤其係一種測試訊號完 整性之測試裝置。 【先前技術】 存儲橋接艙（Storage Bridge Bay，SBB)工作組是 EMC、Dell、Intel及LSI Logic聯手組建之致力於入門級 外置存儲標準化之非營利協作組織。該組織透過標準化存 ❹儲控制卡之插槽介面，使之適用於多廠商多類型之記憶體 產品，以節省供應商們在硬體架構設計上之重複投入。 SBB組織定義之存儲控制卡插槽介面就是SBBMI(SBB Midplane Interconnect)介面 〇 SBBMI介面是基於SBB架構之記憶體用來連接存儲 控制卡及存儲單元（如硬碟）之介面，存儲控制卡透過 SBBMI介面來實現及存儲單元之資料交換。為了確保記 憶體產品之品質，需對SBBMI介面中傳輸之SAS、SATA ❹及FC等高頻數位訊號進行訊號完整性測試，以驗證其是 否符合SBB規範。201024756 'Nine, invention description: ^ [Technical field to which the invention pertains] The present invention relates to a test apparatus, and more particularly to a test apparatus for testing signal integrity. [Prior Art] The Storage Bridge Bay (SBB) Working Group is a non-profit collaborative organization dedicated to entry-level external storage standardization by EMC, Dell, Intel, and LSI Logic. The organization's slot interface for standardized storage control cards is suitable for multi-vendor and multi-type memory products to save suppliers' repetitive investment in hardware architecture design. The storage control card slot interface defined by SBB is the SBBMI (SBB Midplane Interconnect) interface. The SBBMI interface is based on the SBB architecture memory used to connect the storage control card and storage unit (such as hard disk) interface. The storage control card is transmitted through SBBMI. Interface to achieve data exchange with storage units. In order to ensure the quality of the memory products, signal integrity tests are performed on high-frequency digital signals such as SAS, SATA, and FC transmitted in the SBBMI interface to verify compliance with SBB specifications.
然而，SBB規範定義了 SBBMI介面中訊號之測試 點，並將測試點分為ITx、ITy及IRy三類，且定義了三 類測試點中各種訊號（如SAS、PCIe及FC等）之測量規 範，但卻並未給出如何進行訊號採集之步驟及方法，業界 亦沒有針對SBBMI介面進行測試之裝置，這樣就造成以 下弊端：如果因沒有捕獲訊號之治具而放棄對SBBMI介 面中訊號完整性之測試，就無法知道訊號在到達SBBMI 5 201024756 \ ^面時^情況，從而使記憶體產品存在著a質隱患；如果 採用將探棒直接接觸SBBMI介面引腳之方式來捕獲訊 號，則會因背板上較長走線引起之訊號反射，而使得測試 結果不準確。 【發明内容】 鑒於以上内容，有必要提供一種對SBBMI介面中訊 號之完整性進行測試之測試裝置。 一種測試裝置，包括一連接一待測設備之連接器及一 ©包括至少一測試單元之測試電路，該測試單元包括一第一 輸入端、一第二輸入端、一第一電容、一第二電容、一第 一電阻、一第二電阻、一第一輸出端及一第二輸出端，該 第一輸入端透過該第一電容及第一電阻接地，該第二輸入 端透過該第二電容及第二電阻接地，該第一輸出端連接在 該第一電容與第一電阻之間之節點上，該第二輸出端連接 在該第二電容與第二電阻之間之節點上，該第一及第二輸 入端可透過該連接器與該待測設備對應之連接器相連，用 ❿於接收該待測設備輸出之待測訊號，該第一及第二輸出端 用於輸出該待測訊號。 上述測試裝置透過該連接器與該待測設備對應之連接 器相連以接收該待測訊號，並利用該測試單元來隔離直流 訊號及降低傳輸線上之訊號反射，再透過該第一及第二輸 出端將該待測訊號輸出給一電子測試儀器，以對該待測訊 號進行測量，提高了測試之準確度及可靠性。 【實施方式】 6 201024756 - 請一併參閱圖1至圖3,本發明測試裝置用於測試一 記憶體之背板200之SBBMI介面中各個測試點輸出訊號 之完整性，其較佳實施方式包括三個分別用於測試 SBBMI介面中ITx、ITy及IRy類測試點輸出訊號之測試 治具。該三測試治具分別與該ITx、ITy及IRy類測試點 之連接器類型及測試點引腳位置相匹配。其中，該ITx及 ITy類測試點之連接器210及220均為公頭連接器，該 IRy類測試點之連接器230為母頭連接器。在本實施方式 ❹中，僅以第一測試治具100為例來進行說明。 該第一測試治具100用於測試該SBBMI介面中ITx 類測試點輸出之待測訊號，其包括一母頭連接器110、一 測試電路120及六個接頭J。該母頭連接器110與該公頭 連接器210相連。該測試電路120包括六個測試單元 123，該六測試單元123分別用於捕獲該ITx類測試點輸 出之六個待測訊號，並透過該六接頭J將捕獲到之六個待 ©測訊號傳輸給一電子測試儀器（如示波器300)，以透過 該示波器300對該待測訊號之進行測量。在其他實施方式 中，該測試單元123及接頭J之具體數目可根據實際情況 而進行相應調整。 在該測試電路120中，每一測試單元123均包括兩輸 入端Al、A2，兩電容Cl、C2，兩電阻Rl、R2及兩輸出 端Bl、B2。該輸入端A1透過該電容C1及電阻R1接 地，該輸入端A2透過該電容C2及電阻R2接地，該輸出 端B1與該電容C1及電阻R1之間之節點相連，該輸出端 7 201024756 ' B2與該電容C2及電阻R2之間之節點相連。該六測試單 元123之輸入端Al、A2分別與該母頭連接器110之六對 引腳 Gl、HI，H2、12，G3、H3，H4、14，G5、H5 及 H6、16相連，用以接收該公頭連接器210輸出之六個待 測訊號。該六測試單元123之輸出端Bl、B2分別與該六 接頭J相連。該示波器300可透過該接頭J之兩針腳對該 輸出端Bl、B2輸出之訊號進行測量。 在本實施方式中，該兩電容C1、C2均為耦合電容， ®用於隔離直流訊號，該兩電阻Rl、R2均為終結電阻，用 於阻抗匹配以降低傳輸線上之訊號反射。該第一測試治具 100及該背板200均為印刷電路板。在其他實施方式中， 該第一及第二輸出端Bl、B2可為測試治具上之兩焊盤， 此時，將該示波器300之兩探針直接與焊盤接觸，便可對 訊號進行測試，故可省去該接頭J。 當運用該第一測試治具100對該SBBMI介面中ITx _類測試點之訊號進行測試時，先對該記憶體之存儲控制卡 進行設置以生成測試所需之測試代碼（具體設置過程及生 成測試代碼之類型，在SBB規範中均有詳細說明），再將 該測試治具100之母頭連接器110與該背板200之公頭連 接器210相連，然後將該示波器300之兩探針接觸到與一 待測訊號（如SAS訊號）相對應之測試單元相連之接頭J之 兩針腳上，此時該示波器300上顯示出該測試單元輸出訊 號之波形，根據該波形即可判斷該待測訊號是否符合 SBB規範，進而確定該待測訊號之完整性。 8 201024756 - 第二及第三測試治具分別用於測試該SBBMI介面中 ITy、IRy類測試點輸出之待測訊號，其結構與該第一測 試治具100類似，區別僅在於連接器之類型、測試單元及 接頭之數目不同。該第二及第三測試治具之測試原理及測 試過程亦與該第一測試治具100之測試原理及測試過程相 同，這裡不再一一贅述。 上述測試裝置透過該第一測試治具100之母頭連接器 110、第二測試治具之母頭連接器及第三測試治具之公頭 ®連接器分別與該背板200之公頭連接器210、220及母頭 連接器230相連，用以接收該SBBMI介面中各個測試點 輸出之待測訊號，並利用該測試單元中之耦合電容及終結 電阻來隔離直流訊號及降低傳輸線上之訊號反射，再透過 該示波器來對接收到之待測訊號進行測量，提高了測試之 準確性及可靠性，確保了所測試記憶體產品之品質，且該 測試裝置結構簡單，成本較低，實用性強。 φ 綜上所述，本發明符合發明專利要件，爰依法提出專 利申請。惟，以上所述者僅為本發明之較佳實施例，舉凡 熟悉本案技藝之人士，在爰依本發明精神所作之等效修飾 或變化，皆應涵蓋於以下之申請專利範圍内。 9 201024756 '【圖式簡單說明】 圖1係本發明測試裝置第一測試治具之較佳實施方 式之示意圖。 圖2係本發明測試裝置第一測試治具之較佳實施方 式之電路圖。 圖3係本發明測試裝置第一測試治具之較佳實施方 式借助電子測試儀器測試SBBMI介面中輸出訊號完整性 之示意圖。 ❿【主要元件符號說明】However, the SBB specification defines test points for signals in the SBBMI interface, and divides the test points into three categories: ITx, ITy, and IRy, and defines measurement specifications for various signals (such as SAS, PCIe, and FC) in the three types of test points. However, it does not give the steps and methods of how to collect the signal. The industry does not have a device for testing the SBBMI interface. This has the following drawbacks: if the signal integrity of the SBBMI interface is abandoned because there is no fixture to capture the signal. In the test, it is impossible to know the situation when the signal arrives at SBBMI 5 201024756. Therefore, there is a hidden danger in the memory product; if the probe is directly contacted with the SBBMI interface pin to capture the signal, it will be The signal reflection caused by the long trace on the backplane makes the test result inaccurate. SUMMARY OF THE INVENTION In view of the above, it is necessary to provide a test apparatus for testing the integrity of signals in the SBBMI interface. A test device includes a connector connected to a device under test and a test circuit including at least one test unit, the test unit including a first input terminal, a second input terminal, a first capacitor, and a second a capacitor, a first resistor, a second resistor, a first output, and a second output, the first input is grounded through the first capacitor and the first resistor, and the second input is transmitted through the second capacitor And the second resistor is grounded, the first output end is connected to the node between the first capacitor and the first resistor, and the second output end is connected to the node between the second capacitor and the second resistor, the first The first input terminal and the second input end are connected to the connector corresponding to the device to be tested, and are used for receiving the signal to be tested outputted by the device under test, and the first and second output terminals are configured to output the to-be-tested Signal. The test device is connected to the connector corresponding to the device to be tested through the connector to receive the signal to be tested, and the test unit is used to isolate the DC signal and reduce the signal reflection on the transmission line, and then pass the first and second outputs. The terminal outputs the signal to be tested to an electronic test instrument to measure the signal to be tested, thereby improving the accuracy and reliability of the test. [Embodiment] 6 201024756 - Please refer to FIG. 1 to FIG. 3 together, the test device of the present invention is used for testing the integrity of the output signals of each test point in the SBBMI interface of the backplane 200 of a memory, and preferred embodiments thereof include Three test fixtures for testing the output signals of ITx, ITy and IRy test points in the SBBMI interface. The three test fixtures match the connector type and test point pin locations of the ITx, ITy, and IRy test points, respectively. The connectors 210 and 220 of the ITx and ITy test points are male connectors, and the connector 230 of the IRy test point is a female connector. In the present embodiment, only the first test fixture 100 will be described as an example. The first test fixture 100 is used to test the signal to be tested outputted by the ITx class test point in the SBBMI interface, and includes a female connector 110, a test circuit 120 and six connectors J. The female connector 110 is coupled to the male connector 210. The test circuit 120 includes six test units 123 for capturing the six signals to be tested outputted by the ITx type test points, and transmitting the six signals to be detected through the six connectors J. An electronic test instrument (such as oscilloscope 300) is provided to measure the signal to be tested through the oscilloscope 300. In other embodiments, the specific number of the test unit 123 and the joint J can be adjusted accordingly according to actual conditions. In the test circuit 120, each test unit 123 includes two input terminals A1 and A2, two capacitors C1 and C2, two resistors R1 and R2, and two output terminals B1 and B2. The input terminal A1 is grounded through the capacitor C1 and the resistor R1. The input terminal A2 is grounded through the capacitor C2 and the resistor R2. The output terminal B1 is connected to the node between the capacitor C1 and the resistor R1. The output terminal 7 201024756 'B2 Connected to the node between the capacitor C2 and the resistor R2. The input terminals A1 and A2 of the six test units 123 are respectively connected to the six pairs of pins G1, HI, H2, 12, G3, H3, H4, 14, G5, H5 and H6, 16 of the female connector 110. The six signals to be tested output by the male connector 210 are received. The output terminals B1, B2 of the six test units 123 are respectively connected to the six connectors J. The oscilloscope 300 can measure the signals output from the output terminals B1 and B2 through the two pins of the connector J. In this embodiment, the two capacitors C1 and C2 are coupling capacitors, and the two resistors R1 and R2 are terminating resistors for impedance matching to reduce signal reflection on the transmission line. The first test fixture 100 and the backplane 200 are both printed circuit boards. In other embodiments, the first and second output terminals B1 and B2 can be two pads on the test fixture. At this time, the two probes of the oscilloscope 300 are directly in contact with the pads, and the signals can be performed on the signals. Test, so the joint J can be omitted. When the first test fixture 100 is used to test the signal of the ITx_type test point in the SBBMI interface, the storage control card of the memory is first set to generate the test code required for the test (specific setting process and generation). The type of test code is detailed in the SBB specification. The female connector 110 of the test fixture 100 is connected to the male connector 210 of the backplane 200, and then the two probes of the oscilloscope 300 are connected. Contacting the two pins of the connector J connected to the test unit corresponding to a signal to be tested (such as the SAS signal), the waveform of the output signal of the test unit is displayed on the oscilloscope 300, and the waveform can be determined according to the waveform. Whether the test signal complies with the SBB specification and determines the integrity of the signal to be tested. 8 201024756 - The second and third test fixtures are respectively used to test the signal to be tested outputted by the ITy and IRy test points in the SBBMI interface, and the structure thereof is similar to that of the first test fixture 100, except that the type of the connector is only The number of test units and connectors is different. The test principle and test procedure of the second and third test fixtures are also the same as the test principle and test procedure of the first test fixture 100, and will not be further described herein. The test device is connected to the male connector of the backplane 200 through the female connector 110 of the first test fixture 100, the female connector of the second test fixture, and the male connector of the third test fixture. The controllers 210 and 220 are connected to the female connector 230 for receiving the signals to be tested outputted by the test points in the SBBMI interface, and using the coupling capacitors and the terminating resistors in the test unit to isolate the DC signals and reduce the signals on the transmission line. Reflecting, and then measuring the received signal to be tested through the oscilloscope, improving the accuracy and reliability of the test, ensuring the quality of the tested memory product, and the test device has a simple structure, low cost, and practicality. Strong. φ In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. However, the above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be included in the following claims. 9 201024756 '[Simple description of the drawings] Fig. 1 is a schematic view showing a preferred embodiment of the first test fixture of the test apparatus of the present invention. Figure 2 is a circuit diagram showing a preferred embodiment of the first test fixture of the test apparatus of the present invention. Figure 3 is a schematic illustration of the preferred embodiment of the first test fixture of the test apparatus of the present invention for testing the integrity of the output signal in the SBBMI interface by means of an electronic test instrument. ❿[Main component symbol description]
第一測試治具 100 母頭連接器 110、230 測試電路 120 測試單元 123 背板 200 公頭連接器 210 ' 220 示波器 300 輸入端 Al、A2 輸出端 Bl、B2 電容 Cl、C2 電阻. Rl、R2 接頭 JThe first test fixture 100 female connector 110, 230 test circuit 120 test unit 123 backplane 200 male connector 210 ' 220 oscilloscope 300 input terminal A1, A2 output terminal Bl, B2 capacitor Cl, C2 resistance. Rl, R2 Connector J