201023701 >、、發明說明： '【發明所屬之技術領域】 • 本發明是有關於一種線路板（wiring board)及其製 程，且特別是有關於一種具有活化絕緣層（activable insulation layer)的線路板及其製程。 【先前技術】 線路板是手機、電腦與數位相機等電子裝置（electr〇nic device)，以及電視、洗衣機與冰箱等家電用品所需要的元 ❹ 件。詳言之，線路板能承載及組裝晶片（chip)、被動元件 (passive component)與主動元件(active component)等 多種電子元件（electronic component)，並讓這些電子元件 彼此電性連接。如此，電訊號可以在這些電子元件之間傳遞， 而讓上述電子裝置及家電用品運作。 【發明内容】 本發明提供一種線路板的製程，用來製造線路板。 ❹ 本發明提供一種線路板，其能與多個電子元件組裝。 本發明提出一種線路板的製程，其包括形成至少一初 始絕緣層於一基板上。接著，進行一活化程序’以使初始 絕緣層變成一活化絕緣層。活化絕緣層具有一表面以及一 位於表面的活化區，並包括多顆觸媒顆粒，其中一些觸媒 顆粒活化並裸露於活化區内。接著，在活化區内形成一導 電圖案層，其中導電圖案層凸出於表面。 在本發明一實施例中，這些觸媒顆粒為多個奈米顆粒。 201023701 在本發明一實施例中，這些觸媒顆粒的材質包括至少 • 一種過渡金屬配位化合物。 • 纟本發明—實施例巾’上述過渡金屬化合物為過 渡金屬氧化物、過渡€ 避，又金屬氮化物、過渡金屬錯合物或 金屬螯合物。 ^ 纟本發明-實施例中，這些㈣顆粒的材質選自於過 •渡金屬氧化物、過渡金屬氮化物、過渡金屬錯合物以及過 渡金屬螯合物所組成的群組。 ❹ 在本發明實施例巾，上述過渡金屬配位化合物 質選自於由辞、銅、銀、金、鎳、鈀、鉑、鈷、铑、銥、 姻鐵猛絡、钥、鶴、飢、组以及欽所組成的群組。 在本發明-實施例中，上述活化絕緣層更包括一高分 子ΐ化合物，而這些觸媒顆粒分佈於高分子量化合物中。 在本發明-實施例中，上述高分子量化合物為一高分 子聚合物。 在本發明一實施例中，上述高分子聚合物的材質是選 自於由環氧樹脂、改質的環氧樹脂、聚脂、丙烯酸酯、氟 素聚合物、聚亞苯基氧化物、聚醯亞胺、酚醛樹脂、聚颯、 梦素聚合物、雙順丁稀二酸^三氮雜苯樹脂（Bismaleimide Triazine resin，BT resin，即所謂BT樹脂）、氰酸聚酯、聚 乙烯、聚碳酸酯樹脂、丙烯_丁二烯·苯乙烯共聚合物、聚 對苯二甲酸乙二酯樹脂、聚詞_笨二曱酸丁二酯樹脂、液晶 咼分子、聚醯胺6、尼龍、共聚聚曱搭、聚苯硫醚以及環 201023701 狀烯烴共聚高分子所組成的群組。 在本發明一實施例中，上述進行活化程序的方法包括 對初始絕緣層進行雷射燒蝕、電漿蝕刻或機械加工法。 在本發明一實施例中，上述雷射燒蝕所採用的雷射光 源為紅外線雷射、紫外線雷射、準分子雷射或遠紅外線雷 射。 在本發明一實施例中，上述機械加工法包括水刀切 割、喷砂或外型切割。 ❹ 在本發明一實施例中，上述形成導電圖案層的方法包 括無電電鍍法或化學氣相沉積。 在本發明一實施例中，上述形成導電圖案層的方法包 括電鑛法。 在本發明一實施例中 媒顆粒。 在本發明一實施例中 路基板包括一第一線路層 上述初始絕緣層也包括這些觸 上述基板為一線路基板，且線 一相對於第一線路層的第二線 路層、一位於第一線路層與第二線路層之間的介電層以及 一電性連接於第一線路層與第二線路層之間的内部線路結 構。 在本發明一實施例中，更包括形成至少一樹脂層於基 板上。接著，形成初始絕緣層於樹脂層上。 在本發明一實施例中，上述形成樹脂層的方法包括壓 合樹脂層於基板上。 6 201023701 在本發明一實施例中，上述樹脂層為選自由膠片 • (prepreg)以及空白核心層（blank core)所組成之群組。 . 在本發明一實施例中，在形成初始絕緣層之後，更包 括形成至少一導電連接結構（conductive connection structure)，其中導電連接結構連接於基板與導電圖案層之 間。 在本發明一實施例中，上述導電連接結構為一導電盲 孑L結構（conductive via structure)。 ❿ 在本發明一實施例中，上述形成導電連接結構的方法 包括進行一鑽孔程序。 在本發明一實施例中，上述鑽孔程序為雷射鑽孔或機 械鑽孔。 在本發明一實施例中，更包括在形成導電圖案層以 前，形成至少一阻障圖案層於基板之上，其中阻障圖案層 具有一暴露活化區的鏤空圖案。接著，形成導電圖案層於 φ 鏤空圖案所暴露的活化區内。接著，移除阻障圖案層。 在本發明一實施例中，上述阻障圖案層為圖案化光阻 層。 在本發明一實施例中，上述形成導電圖案層的方法包 括在形成阻障圖案層以前，形成至少一金屬層，其中金屬 層全面性地覆蓋表面。接著，形成阻障圖案層於金屬層上。 接著，對金屬層進行電鐘。 在本發明一實施例中，在對金屬層進行電鐘以及在移 7 201023701 除阻障圖案層之後，更包括移除部分金屬層。 • 在本發明一實施例中，上述移除部分金屬層的方法包 . 括對金屬層進行餘刻。 本發明另提出一種線路板，其包括一基板、一第一活 化絕緣層、一第二活化絕緣層、一第一導電圖案層以及一 第二導電圖案層。基板具有一上表面與一相對上表面的下 表面。第一活化絕緣層配置於上表面，並具有一第一表面 以及一位於第一表面的第一活化區。第二活化絕緣層配置 ❿ 於下表面，並具有一第二表面以及一位於第二表面的第二 活化區。第一活化絕緣層與第二活化絕緣層皆包括多顆觸 媒顆粒。第一導電圖案層配置於第一表面，並連接一些位 於第一活化區内的觸媒顆粒，其中第一導電圖案層凸出於 第一表面。第二導電圖案層配置於第二表面，並連接一些 位於第二活化區内的觸媒顆粒，其中第二導電圖案層凸出 於第二表面。 Q 在本發明一實施例中，上述第一活化區相對於第一表 面的深度不大於10微米。 在本發明一實施例中，上述第二活化區相對於第二表 面的深度不大於10微米。 在本發明一實施例中，上述基板為線路基板，而線路 板更包括至少一第一導電連接結構。第一導電連接結構配 置於第一活化絕緣層中，並連接於第一導電圖案層與線路 基板的第一線路層之間。 8 201023701 在本發明一實施例中，上述線路板更包括至少一第二 - 導電連接結構。第二導電連接結構配置於第二活化絕緣層 . 中，並連接於第二導電圖案層與線路基板的第二線路層之 間。 综上所述，利用上述活化絕緣層，本發明得以形成導 電圖案層，進而製造可供多個電子元件組裝的線路板。 【實施方式】 圖1是本發明之線路板的製程的流程圖。請參閱圖1’ ❹ 本發明的線路板的製程能製造單面線路板（single-side circuit board )、雙面線路板（double-side circuit board )以及多層線路 板（multi-layer circuit board )。在此線路板的製程中，首先， 形成至少一初始絕緣層於一基板上（S100)，其中此初始絕 緣層可為一種乾膜或渔膜，因此初始絕緣層可透過壓合或 塗佈的方式而形成於基板上。此外，基板可以是線路基板。 初始絕緣層包括多顆觸媒顆粒，其中這些觸媒顆粒可 ❿ 以是多個奈米顆粒’而且也可以是具有金屬成分的金屬顆 粒（metallic particle)。這些金屬顆粒有多種不同種類，且 可以被活化。特別的是，在這些金屬顆粒未被活化之前， 這些金屬顆粒的物理及化學特性並不一定與金屬塊材 (metal bulk)相同’例如有些種類的金屬顆粒在未活化之 前是具有絕緣性。 承上述，這些金屬顆粒的成分含有金屬原子或金屬離 子，而這些觸媒顆粒的材質包括一種過渡金屬配位化合 9 201023701 物。此過渡金屬配位化合物例如是過渡金屬氧化物、過渡 * 金屬氮化物、過渡金屬錯合物或過渡金屬螯合物，其中過 . 渡金屬配位化合物的材質例如是選自於鋅、銅、銀、金、鎳、 把、銘、钻、錯、銥、銦、鐵、猛、絡、錮、鶴、鈒、组、 鈦或這些金屬的任意組合。 另外，這些觸媒顆粒的材質可以包括多種過渡金屬配 位化合物。詳細而言，這些觸媒顆粒的材質可以是選自於 過渡金屬氧化物、過渡金屬氮化物、過渡金屬錯合物、過 ❿ 渡金屬螯合物或這些化合物的任意組合。舉例來說，這些 觸媒顆粒可包括過渡金屬氧化物、過渡金屬氮化物或過渡 金屬錯合物’或者是這些觸媒顆粒也可包括過渡金屬氧化 物與過渡金屬錯合物等多種過渡金屬配位化合物，其中這 些觸媒顆粒例如是氧化銅、氮化鈦、鈷鉬雙金屬氮化物 (Co2Mo3Nx)顆粒或把金屬顆粒。 初始絕緣層更包括一高分子量化合物，而這些觸媒顆 φ 粒分佈於高分子量化合物中。詳細而言，此高分子量化合 物可以是一種高分子聚合物，其材質例如是選自於環氧樹 脂、改質的環氧樹脂、聚脂（polyester)、丙烯酸酯、氟素 聚合物（fluoro-polymer)、聚亞苯基氧化物（polyphenylene oxide )、聚醯亞胺（polyimide )、紛醒樹脂（phenolicresin )、 聚礙（polysulfone)、梦素聚合物（silicone polymer)、雙順 丁烯二酸-三氮雜苯樹脂（bismaleimide triazine modified epoxy ’即所謂的BT樹脂）、氰酸聚醋（cyanate ester)、聚 201023701 乙烯（polyethylene)、聚碳酸酯樹脂（polycarbonate，PC)、201023701 >, invention description: '[Technical field to which the invention pertains] The present invention relates to a wiring board and a process thereof, and more particularly to a circuit having an activable insulation layer Board and its process. [Prior Art] The circuit board is an electronic device such as a mobile phone, a computer, a digital camera, and the like, and a home appliance required for a home appliance such as a television, a washing machine, and a refrigerator. In detail, the circuit board can carry and assemble various electronic components such as a chip, a passive component, and an active component, and electrically connect the electronic components to each other. In this way, the electrical signal can be transmitted between the electronic components, and the electronic device and the household electrical appliance are operated. SUMMARY OF THE INVENTION The present invention provides a circuit board process for manufacturing a circuit board. ❹ The present invention provides a wiring board that can be assembled with a plurality of electronic components. The present invention provides a process for a wiring board comprising forming at least one initial insulating layer on a substrate. Next, an activation process is performed to make the initial insulating layer an activated insulating layer. The activated insulating layer has a surface and an active region on the surface and includes a plurality of catalyst particles, some of which are activated and exposed in the active region. Next, a conductive pattern layer is formed in the active region, wherein the conductive pattern layer protrudes from the surface. In an embodiment of the invention, the catalyst particles are a plurality of nanoparticles. 201023701 In an embodiment of the invention, the material of the catalyst particles comprises at least one transition metal coordination compound. • The present invention—the embodiment of the transition metal compound is a transition metal oxide, a transition metal, a metal nitride, a transition metal complex or a metal chelate. In the present invention - the examples, the material of the (iv) particles is selected from the group consisting of a transition metal oxide, a transition metal nitride, a transition metal complex, and a transition metal chelate. In the embodiment of the present invention, the transition metal complex compound is selected from the group consisting of: rhodium, copper, silver, gold, nickel, palladium, platinum, cobalt, rhodium, ruthenium, ruthenium, stagnation, crane, hunger, Group and group of Chin. In the present invention - the embodiment, the activating insulating layer further comprises a high molecular weight cerium compound, and the catalyst particles are distributed in the high molecular weight compound. In the present invention - the embodiment, the above high molecular weight compound is a high molecular polymer. In an embodiment of the invention, the material of the polymer is selected from the group consisting of epoxy resins, modified epoxy resins, polyesters, acrylates, fluoropolymers, polyphenylene oxides, and poly Bismumine, phenolic resin, polyfluorene, dreamer polymer, Bismaleimide Triazine resin (BT resin, so-called BT resin), cyanate polyester, polyethylene, poly Carbonate resin, propylene-butadiene-styrene copolymer, polyethylene terephthalate resin, poly-succinic acid butyl diester resin, liquid crystal ruthenium molecule, polyamine 6, nylon, copolymerization A group consisting of polybenzazole, polyphenylene sulfide, and ring 201023701 olefin copolymer copolymer. In one embodiment of the invention, the method of performing the activation process includes performing a laser ablation, plasma etching, or machining on the initial insulating layer. In an embodiment of the invention, the laser source used in the laser ablation is an infrared laser, an ultraviolet laser, an excimer laser or a far infrared laser. In an embodiment of the invention, the mechanical machining method comprises water jet cutting, sand blasting or profile cutting. In one embodiment of the invention, the method of forming the conductive pattern layer includes electroless plating or chemical vapor deposition. In an embodiment of the invention, the method of forming the conductive pattern layer includes an electric ore method. In one embodiment of the invention, the media particles. In an embodiment of the invention, the circuit substrate includes a first circuit layer, the initial insulating layer also includes the touch substrate being a circuit substrate, and the second circuit layer of the line relative to the first circuit layer and the first circuit layer And a dielectric layer between the second circuit layer and an internal wiring structure electrically connected between the first circuit layer and the second circuit layer. In an embodiment of the invention, the method further comprises forming at least one resin layer on the substrate. Next, an initial insulating layer is formed on the resin layer. In an embodiment of the invention, the method of forming a resin layer includes pressing a resin layer on a substrate. 6 201023701 In an embodiment of the invention, the resin layer is selected from the group consisting of a film prepreg and a blank core. In an embodiment of the invention, after forming the initial insulating layer, further comprising forming at least one conductive connection structure, wherein the conductive connection structure is connected between the substrate and the conductive pattern layer. In an embodiment of the invention, the conductive connection structure is a conductive via structure. In one embodiment of the invention, the method of forming the electrically conductive connection structure includes performing a drilling procedure. In an embodiment of the invention, the drilling procedure is a laser drilling or a mechanical drilling. In an embodiment of the invention, the method further comprises forming at least one barrier pattern layer on the substrate before forming the conductive pattern layer, wherein the barrier pattern layer has a hollow pattern exposing the active region. Next, a conductive pattern layer is formed in the active region exposed by the φ hollow pattern. Next, the barrier pattern layer is removed. In an embodiment of the invention, the barrier pattern layer is a patterned photoresist layer. In an embodiment of the invention, the method of forming a conductive pattern layer includes forming at least one metal layer before forming the barrier pattern layer, wherein the metal layer comprehensively covers the surface. Next, a barrier pattern layer is formed on the metal layer. Next, an electric clock is applied to the metal layer. In an embodiment of the invention, after the electric clock is applied to the metal layer and after the barrier pattern layer is removed, the partial metal layer is removed. • In an embodiment of the invention, the method of removing a portion of the metal layer includes engraving the metal layer. The invention further provides a circuit board comprising a substrate, a first active insulating layer, a second active insulating layer, a first conductive pattern layer and a second conductive pattern layer. The substrate has a lower surface and an upper surface opposite the upper surface. The first activating insulating layer is disposed on the upper surface and has a first surface and a first active region on the first surface. The second activating insulating layer is disposed on the lower surface and has a second surface and a second active region on the second surface. Both the first activating insulating layer and the second activating insulating layer comprise a plurality of catalyst particles. The first conductive pattern layer is disposed on the first surface and connects some of the catalyst particles in the first active region, wherein the first conductive pattern layer protrudes from the first surface. The second conductive pattern layer is disposed on the second surface and connects some of the catalyst particles located in the second active region, wherein the second conductive pattern layer protrudes from the second surface. In an embodiment of the invention, the depth of the first activation zone relative to the first surface is no greater than 10 microns. In an embodiment of the invention, the second activation zone has a depth of no greater than 10 microns relative to the second surface. In an embodiment of the invention, the substrate is a circuit substrate, and the circuit board further includes at least one first conductive connection structure. The first conductive connection structure is disposed in the first active insulating layer and is connected between the first conductive pattern layer and the first circuit layer of the wiring substrate. 8 201023701 In an embodiment of the invention, the circuit board further includes at least one second-conductive connection structure. The second conductive connection structure is disposed in the second active insulating layer, and is connected between the second conductive pattern layer and the second circuit layer of the circuit substrate. As described above, with the above-described activating insulating layer, the present invention can form a conductive pattern layer, thereby fabricating a wiring board which can be assembled by a plurality of electronic components. Embodiments Fig. 1 is a flow chart showing the process of a circuit board of the present invention. Referring to Fig. 1', the process of the circuit board of the present invention can manufacture a single-side circuit board, a double-side circuit board, and a multi-layer circuit board. In the process of the circuit board, first, at least one initial insulating layer is formed on a substrate (S100), wherein the initial insulating layer may be a dry film or a film, so that the initial insulating layer is permeable or coated. The method is formed on the substrate. Further, the substrate may be a wiring substrate. The initial insulating layer includes a plurality of catalyst particles, wherein the catalyst particles may be a plurality of nanoparticles ' and may also be metallic particles having a metal component. These metal particles come in many different types and can be activated. In particular, the physical and chemical properties of these metal particles are not necessarily the same as those of the metal bulk before these metal particles are activated. For example, some types of metal particles are insulative before being activated. In view of the above, the components of these metal particles contain metal atoms or metal ions, and the materials of these catalyst particles include a transition metal coordination compound 9 201023701. The transition metal complex compound is, for example, a transition metal oxide, a transition metal nitride, a transition metal complex or a transition metal chelate, wherein the material of the metal complex compound is selected, for example, from zinc or copper. Silver, gold, nickel, handle, inscription, drill, wrong, antimony, indium, iron, fission, enthalpy, hydrazine, crane, bismuth, group, titanium or any combination of these metals. Additionally, the materials of these catalyst particles can include a variety of transition metal coordination compounds. In detail, the material of these catalyst particles may be selected from transition metal oxides, transition metal nitrides, transition metal complexes, over-metal chelates or any combination of these compounds. For example, these catalyst particles may include transition metal oxides, transition metal nitrides or transition metal complexes' or these catalyst particles may also include various transition metal complexes such as transition metal oxides and transition metal complexes. The compound, wherein the catalyst particles are, for example, copper oxide, titanium nitride, cobalt molybdenum bimetallic nitride (Co2Mo3Nx) particles or metal particles. The initial insulating layer further comprises a high molecular weight compound, and the catalyst particles φ are distributed in the high molecular weight compound. In detail, the high molecular weight compound may be a high molecular polymer, and the material thereof is, for example, selected from the group consisting of an epoxy resin, a modified epoxy resin, a polyester, an acrylate, and a fluoropolymer (fluoro- Polymer), polyphenylene oxide, polyimide, phenolic resin, polysulfone, silicone polymer, bis-maleic acid -Bismaleimide triazine modified epoxy (so-called BT resin), cyanate ester, poly 201023701 ethylene, polycarbonate resin (PC),
- 丙婦-丁 二稀-苯乙稀共聚合物 . (acrylonitrile-butadiene-styrene copolymer ， ABS copolymer )、聚對苯二甲酸乙二酯樹脂（polyethylene terephthalate，PET )、聚對苯二甲酸丁二酯樹脂 (polybutylene terephthalate，PBT )、液晶高分子（liquid crystal polymers，LCP)、聚醢胺 6 (polyamide 6，PA 6)、 尼龍（Nylon )、共聚聚甲酸·（ polyoxymethylene，POM )、 ❿聚苯硫醚（polyphenylene sulfide，PPS)、環狀烯烴共聚高 分子（cyclic olefin copolymer，COC)或這些高分子材料 的任意组合。 初始絕緣層可以接觸基板，而直接形成於基板上。然- Acrylonitrile-butadiene-styrene copolymer (ABS copolymer), polyethylene terephthalate (PET), polybutylene terephthalate Polybutylene terephthalate (PBT), liquid crystal polymer (LCP), polyamide 6, PA 6 , nylon (Nylon), polyoxymethylene (POM), polyphenylene Polyphenylene sulfide (PPS), cyclic olefin copolymer (COC) or any combination of these polymeric materials. The initial insulating layer may be in contact with the substrate and formed directly on the substrate. Of course
而，初始絕緣層也可以未接觸基板，而間接形成於基板上。 舉例而言，在形成初始絕緣層之前，可以先形成至少一層 樹脂層於基板上，其巾形賴脂層时法可以是壓合樹脂 層於基板上，且樹脂層可以是膠片或空白核心層。之後，曰 形成初始絕緣層於此樹脂層上。 在形成初始絕緣層之後，進行一活化程序（讓），以 使初始絕緣層㈣-活化絕緣層，而活化絕緣層包括 两分子量化合物與分佈於此高分子量化合物中的這此 顆粒。因此，初始轉層麟㈣緣層二麵結構相似，、 而二者顯著的差異在於：活化絶、缘層具有—表面以及一位 於此表面的活化區，其中-麵媒活化並裸露於活化 11 201023701 區内。 上述進行活化程序的方法有很多種。舉例而言，進行 活化程序的方法可以是對初始絕緣層進行雷射燒蝕或電漿 蝕刻。上述雷射燒#所使用的雷射，其所發出的雷射光束 (laser beam)的波長可以是在可見光、紅外光或紫外光的 範圍内。因此，雷射燒蝕所採用的雷射光源可以是紅外線 雷射、紫外線雷射、石權石雷射（Yttdum Ahjminum ❹However, the initial insulating layer may also be formed on the substrate indirectly without contacting the substrate. For example, before forming the initial insulating layer, at least one resin layer may be formed on the substrate, and the towel-shaped layer may be a pressure-sensitive resin layer on the substrate, and the resin layer may be a film or a blank core layer. . Thereafter, 曰 forms an initial insulating layer on this resin layer. After the initial insulating layer is formed, an activation process is performed to cause the initial insulating layer (4) to activate the insulating layer, and the activating insulating layer includes the two molecular weight compounds and the particles distributed in the high molecular weight compound. Therefore, the initial transition layer (four) edge layer has a similar structure on both sides, and the significant difference between the two is that the activation barrier layer has a surface and an activation region on the surface, wherein the surface medium is activated and exposed to activation 11 201023701 Area. There are many methods for performing the activation procedure described above. For example, the method of performing the activation process may be laser ablation or plasma etching of the initial insulating layer. The laser used in the above-mentioned laser burning # can emit a laser beam having a wavelength in the range of visible light, infrared light or ultraviolet light. Therefore, the laser source used for laser ablation can be infrared laser, ultraviolet laser, and stone weight laser (Yttdum Ahjminum ❹
G麵t，YAGlaser)、二氧化碳雷射、準分子雷射（㈤順 laser)或遠紅外線雷射。 另外，進行活化程序的方法也可以是對初始絕緣層進 打機械加工法。詳言之，此機械加工法可以々、’、 喷砂或外型_，其中這裡所料外型切^水刀切割、 割（V-cut)或銑割（訓ting)。透過上述機°以是V型切 區也可以形成。 碼加工法，活化 接著，在活化區内形成1電圖案層 電圖案層凸出於活化絕緣層的表面， υ4)’其中導 少-接墊以及多條走線。形成導電圖案:電圖案層包括至 用無需施加外部電流的化學方法，其例如7方法可以是採 化學氣相沉積。 ’ $無電電鍍法或 當導電圖案層是採用上述化學方法來， 的觸媒顆粒能直接與形成導電圖案層的反形成時，活化種 詳細而言，切活祕緣層進行雷射 2產生反應。 程中，雷射光束與電漿皆能打斷在活化或電槳蝕刻的进 &内的這些觸媒彩 12 201023701 粒的化學鍵（Chemical bond)，讓這些觸媒顆粒活化。 - 其次，導電圖案層可透過至少一層阻障圖案層來形 - 成，其中阻障圖案層具有一鏤空圖案。詳細而言，在形成 導電圖案層以前，可以形成阻障圖案層於基板之上，而阻 障圖案層可以是圖案化光阻層，其例如是顯影後的溼式光 阻或乾膜。接著，形成導電圖案層於鏤空圖案中。之後， 移除阻障圖案層。 在本發明其中一實施例中，導電圖案層更可以是透過 ❹ 上述阻障圖案層與至少一層金屬層來形成。詳細而言，首 先，讓活化區完全涵蓋其所位於的活化絕緣層的表面。接 著，形成一金屬層於活化絕緣層的活化區内。由於活化區 完全涵蓋其所位於的活化絕緣層的表面，因此金屬層能全 面性地覆蓋活化絕緣層的表面。 接著，形成阻障圖案層於金屬層上，其中阻障圖案層 的鏤空圖案局部暴露金屬層。之後，對金屬層進行電鍍， ⑩ 以在鏤空圖案内形成導電圖案層。由此可知，導電圖案層 也可以是用施加外部電流的電鍍法來形成。之後，移除部 分金屬層，以暴露出部分活化絕緣層，其中移除部分金屬 層的方法可以是對金屬層進行姓刻。如此，導電圖案層得 以形成。 值得一提的是，在本發明其中一實施例中，上述線路 板的製程更可以包括形成至少一導電連接結構。詳細而 言，導電連接結構連接於基板與導電圖案層之間，而透過 13 201023701 導電連接結構，基板與導電圖案層二者得以電性導通。 - 形成導電連接結構的方法有很多種。在其中一種形成 . 導電連接結構的方法中，首先，進行一鑽孔程序，以形成 至少一盲孔，其中此鑽孔程序可以是雷射鑽孔或機械鑽 孔。之後，進行無電電鍍法或電鍍法，以形成導電連接結 構於盲孔中。因此，導電連接結構可以是一種位於盲孔内 的導電盲孔結構，其例如是空心導電柱或是實心導電柱。 為了能具體說明本發明的特徵，以下舉出一些實施 ❿ 例，並配合圖式，以進行說明。 「第一實施例」 圖2A至圖2G是本發明第一實施例之線路板的製程的 示意圖。請先參閱圖2G，在此先介紹本實施例的線路板 200在結構方面的特徵。線路板200包括一基板210、多層 活化絕緣層以及多層導電圖案層。這些活化絕緣層包括一 ⑩ 第一活化絕緣層220a與一第二活化絕緣層220b，而這些 導電圖案層包括一第一導電圖案層230a與一第二導電圖 案層230b。 基板210具有一上表面210a與一下表面210b，而上 表面210a相對於下表面210b，其中第一活化絕緣層220a 配置於上表面210a，而第二活化絕緣層220b配置於下表 面210b。基板210可以是一種線路基板，其包括一第一線 路層212a、一第二線路層212b、一介電層214以及一電性 201023701 連接於第一線路層212a與第二線路層212b之間的内部線 - 路結構（未繪示）。第一線路層212a相對於第二線路層 . 212b，而介電層214位於第一線路層212a與第二線路層 212b之間。 内部線路結構可包括至少一導電連接結構與至少一層 内部線路層，其中内部線路層電性連接此導電連接結構， 而導電連接結構例如是導電盲孔結構、導電通孔結構 (conductive through hole structure )或導電埋孔結構 ® ( conductive buried hole structure)。 由於上述導電連接結構與内部線路層皆為本發明所屬 技術領域中具有通常知識者所知曉的習知線路板的結構， 因此，縱使圖式未繪示出内部線路結構，本發明所屬技術 領域中具有通常知識者仍可以容易並清楚地得知内部線路 結構的具體特徵。 第一活化絕緣層220a具有一第一表面222a以及一位 參 於第一表面222a的第一活化區224a，而第二活化絕緣層 220b具有一第二表面222b以及一位於第二表面222b的第 二活化區224b，其中第一活化絕緣層220a與第二活化絕 緣層220b皆包括多顆觸媒顆粒226。 這些觸媒顆粒226可以是多個奈米顆粒，而且這些觸 媒顆粒226的材質可包括至少一種過渡金屬配位化合物， 其材質選自於由鋅、銅、銀、金、鎳、把、鈾、銘、姥、 錶、銦、鐵、猛、絡、錮、鑄、飢、组以及欽，或這些金 15 201023701 因此，觸媒顆粒226可以是具有金屬成 此外上述過渡金屬配位化合物可以是過渡金屬氧化 物、過渡金屬氮化物、過渡金屬錯合物或過渡金屬螯合物， 而這些觸媒顆粒226的材質例如是選自於過渡金屬氧化 物、過渡金屬氮化物、過渡金屬錯合物、過渡金屬螯合物 或這些化合物的任意組合。G-plane t, YAGlaser), carbon dioxide laser, excimer laser ((5) cis laser) or far-infrared laser. Alternatively, the method of performing the activation process may be a machining method for the initial insulating layer. In particular, this machining method can be used for 々, ', sand blasting or appearance _, where the shape is cut, water knife cutting, cutting (V-cut) or milling (training ting). It is also possible to form a V-cut through the above machine. Code processing, activation Next, an electrical pattern layer is formed in the active region. The electrical pattern layer protrudes from the surface of the active insulating layer, υ4)' where the pad is formed and a plurality of traces are formed. The conductive pattern is formed: the electrical pattern layer includes a chemical method to which no external current is applied, and for example, the method 7 may be chemical vapor deposition. '$Electroless plating method or when the conductive pattern layer is formed by the above chemical method, the catalyst particles can directly form a reverse formation with the conductive pattern layer, and the activation species in detail, incision of the secret layer to perform the laser 2 reaction . During the process, both the laser beam and the plasma can interrupt the catalytic bonds of the particles in the activation or paddle etching to activate these catalyst particles. - Second, the conductive pattern layer is formed by at least one barrier pattern layer, wherein the barrier pattern layer has a hollow pattern. In detail, a barrier pattern layer may be formed over the substrate before forming the conductive pattern layer, and the barrier pattern layer may be a patterned photoresist layer, such as a developed wet photoresist or dry film. Next, a conductive pattern layer is formed in the hollow pattern. After that, the barrier pattern layer is removed. In one embodiment of the invention, the conductive pattern layer may be formed by transmitting the barrier pattern layer and the at least one metal layer. In detail, first, the activation zone is completely covered by the surface of the activated insulating layer on which it is located. Next, a metal layer is formed in the active region of the activated insulating layer. Since the active region completely covers the surface of the activating insulating layer on which it is located, the metal layer can cover the surface of the activating insulating layer in a full-face manner. Next, a barrier pattern layer is formed on the metal layer, wherein the hollow pattern of the barrier pattern layer partially exposes the metal layer. Thereafter, the metal layer is plated 10 to form a conductive pattern layer in the hollow pattern. From this, it is understood that the conductive pattern layer can also be formed by an electroplating method in which an external current is applied. Thereafter, a portion of the metal layer is removed to expose a portion of the activated insulating layer, wherein the method of removing a portion of the metal layer may be by engraving the metal layer. Thus, a conductive pattern layer is formed. It is to be noted that, in an embodiment of the invention, the process of the circuit board may further comprise forming at least one conductive connection structure. In detail, the conductive connection structure is connected between the substrate and the conductive pattern layer, and through the conductive connection structure of 13 201023701, the substrate and the conductive pattern layer are electrically connected. - There are many ways to form a conductive connection structure. In one method of forming a conductive connection structure, first, a drilling procedure is performed to form at least one blind hole, wherein the drilling procedure may be a laser drilling or a mechanical drilling. Thereafter, electroless plating or electroplating is performed to form a conductive connection structure in the blind via. Therefore, the conductive connection structure may be a conductive blind hole structure located in the blind hole, which is, for example, a hollow conductive column or a solid conductive column. In order to be able to specifically describe the features of the present invention, some embodiments will be described below, and the drawings will be described in conjunction with the drawings. "First Embodiment" Figs. 2A to 2G are schematic views showing the process of a wiring board according to a first embodiment of the present invention. Referring first to Fig. 2G, the structural features of the circuit board 200 of the present embodiment will be described first. The circuit board 200 includes a substrate 210, a plurality of layers of activating insulating layers, and a plurality of layers of conductive patterns. The activating insulating layer includes a first active insulating layer 220a and a second activating insulating layer 220b, and the conductive pattern layer includes a first conductive pattern layer 230a and a second conductive pattern layer 230b. The substrate 210 has an upper surface 210a and a lower surface 210b, and the upper surface 210a is opposite to the lower surface 210b, wherein the first activating insulating layer 220a is disposed on the upper surface 210a, and the second activating insulating layer 220b is disposed on the lower surface 210b. The substrate 210 may be a circuit substrate including a first circuit layer 212a, a second circuit layer 212b, a dielectric layer 214, and an electrical 201023701 connected between the first circuit layer 212a and the second circuit layer 212b. Internal line - road structure (not shown). The first wiring layer 212a is opposite to the second wiring layer 212b, and the dielectric layer 214 is located between the first wiring layer 212a and the second wiring layer 212b. The internal wiring structure may include at least one conductive connection structure and at least one internal circuit layer, wherein the internal circuit layer is electrically connected to the conductive connection structure, and the conductive connection structure is, for example, a conductive blind hole structure, and a conductive through hole structure. Or conductive buried hole structure®. Since the above-mentioned conductive connection structure and internal circuit layer are the structures of the conventional circuit boards known to those skilled in the art, even if the internal circuit structure is not illustrated, the present invention belongs to the technical field. Those with ordinary knowledge can still easily and clearly know the specific characteristics of the internal circuit structure. The first activating insulating layer 220a has a first surface 222a and a first active region 224a participating in the first surface 222a, and the second activating insulating layer 220b has a second surface 222b and a second surface 222b. The second active region 224b, wherein the first activating insulating layer 220a and the second activating insulating layer 220b each include a plurality of catalyst particles 226. The catalyst particles 226 may be a plurality of nano particles, and the material of the catalyst particles 226 may include at least one transition metal coordination compound selected from the group consisting of zinc, copper, silver, gold, nickel, palladium, and uranium. , Ming, 姥, Table, Indium, Iron, Meng, Luo, 锢, Cast, Hungry, Group, and Qin, or these gold 15 201023701 Therefore, the catalyst particles 226 may have a metal addition and the above transition metal coordination compound may be a transition metal oxide, a transition metal nitride, a transition metal complex or a transition metal chelate, and the material of the catalyst particles 226 is selected, for example, from a transition metal oxide, a transition metal nitride, a transition metal complex. , a transition metal chelate or any combination of these compounds.
第一活化絕緣層220a與第二活化絕緣層2篇二者更 包括-高分子量化合物228，而這些觸媒顆粒226分佈於 尚分子量化合物228中。高分子量化合物228可以是高分 子聚合物’騎質是選自於環氧樹脂、改f的環氧樹脂、 聚月曰、丙烯❹旨、氟素聚合物、&亞苯基氧化物、聚酿亞 胺、祕樹脂、聚硬、石夕素聚合物、雙順丁稀二酸-三氣雜 苯樹月旨（即BT樹脂）、氰酸聚醋、聚乙婦、聚碳酸醋樹脂、The first activating insulating layer 220a and the second activating insulating layer 2 both include a high molecular weight compound 228, and these catalyst particles 226 are distributed in the molecular weight compound 228. The high molecular weight compound 228 may be a high molecular polymer. The riding quality is selected from the group consisting of epoxy resins, epoxy resins, polystyrene, propylene polymers, fluoropolymers, & phenylene oxides, poly Brewed imine, secret resin, polyhard, sinusoidal polymer, bis-succinic diacid-tris-benzene benzene tree (ie BT resin), cyanic acid vinegar, poly-wife, polycarbonate resin,
屬所組成的群紙。 分的奈米顆粒。 丙广丁二烯·苯乙烯共聚合物、聚對苯二甲酸乙二醋樹 知、聚對苯二甲酸丁二醋樹脂、液晶高分子、聚酿胺6、 尼龍、共料甲搭、聚苯細、環輯烴絲高或這些高 分子材料的任意組合。 第一導電圖案層230a配置於第一表面222a，並連接一 些位於第—活化區224a内的觸媒顆粒226,其中第一導電 圖案層230a凸出於第-表面咖。第二導電圖案層膽 配置於第二表面222b，並連接—些位於第二活化區22扑 内的觸媒顆粒226,其中第二導電圖案層23()b凸出於第二 16 201023701 表面222b。第一導電圖案層230a與第二導電圖案層230b • 二者皆包括多個用以連接電子元件的接墊與多條傳遞電流 - 的走線。 另外，線路板200更可以包括多個導電連接結構，其 包括至少一第一導電連接結構240a與至少一第二導電連 接結構240b。第一導電連接結構240a配置於第一活化絕 .緣層220a中，並連接於第一導電圖案層230a與基板210 的第一線路層212a之間。第二導電連接結構240b配置於 ❹ 第二活化絕緣層220b中，並連接於第二導電圖案層230b 與基板210的第二線路層212b之間。 在本實施例中，第一導電連接結構240a與第二導電連 接結構240b皆可以是一種導電盲孔結構，而此導電盲孔結 構例如是一種空心導電柱，如圖2G所示。透過第一導電 連接結構240a與第二導電連接結構240b，第一導電圖案 層230a與第二導電圖案層230b二者可以與基板210電性 _ 導通。 值得一提的是，在其他未繪示的實施例中，線路板200 所包括的導電連接結構的數量可以僅為一個。也就是說， 線路板200所包括的第一導電連接結構240a與第二導電連 接結構240b二者的總數量可以僅為一個。因此，圖2G所 示的第一導電連接結構240a與第二導電連接結構240b二 者的總數量僅為舉例說明，並非限定本發明。 以上介紹本實施例的線路板200在結構方面的特徵。 17 201023701 接下來將配合圖2A至圖2G來介紹線路板200的製程。 - 請先參閱圖2A，在線路板200的製程中，首先，形成 . 至少一初始絕緣層，即形成一第一初始絕緣層220a’於基板 210的上表面210a，以及形成一第二初始絕緣層220b’於基 板210的下表面210b。第一初始絕緣層220a’與第二初始 絕緣層220b’二者可以透過壓合或塗佈的方式而形成於基 板210上。此外，第一初始絕緣層220a’與第二初始絕緣層 220b’二者也包括高分子量化合物228以及分佈於高分子量 ⑩ 化合物228中的這些觸媒顆粒226。 請參閱圖2B，接著，進行一鑽孔程序，以形成至少一 第一盲孔B1與至少一第二盲孔B2，其中第一盲孔B1與 第二盲孔B2可以是用雷射鑽孔或機械鑽孔來形成。第一盲 孔B1位於第一初始絕緣層220a’中，而第二盲孔B2位於 第二初始絕緣層220b’中。第一盲孔B1局部暴露第一線路 層212a，而第二盲孔B2局部暴露第二線路層212b。 φ 請參閱圖2C，接著，形成至少一層阻障圖案層於基板 210之上。詳細而言，形成阻障圖案層的流程包括形成一 第一阻障圖案層250a於第一初始絕緣層220a’上，形成一 第二阻障圖案層250b於第二初始絕緣層220b’上，其中第 一阻障圖案層250a與第二阻障圖案層250b皆可為圖案化 光阻層，其例如是顯影後的溼式光阻或乾膜。 承上述，第一阻障圖案層250a具有一第一鏤空圖案 252a，且第一鏤空圖案252a局部暴露第一初始絕緣層 18 201023701 220a’。第二阻障圖案層250b具有一第二鏤空圖案252b， • 且第二鏤空圖案252b局部暴露第二初始絕緣層220b’。此 - 外，第一鏤空圖案252a更暴露出整個第一盲孔B1以及第 一盲孔B1所暴露的第一線路層212a，而第二鏤空圖案252b 更暴露出整個第二盲孔B2以及第二盲孔B2所暴露的第二 線路層212b。 請參閱圖2C與圖2D，接著，進行活化程序，讓第一 初始絕緣層220a’變成第一活化絕緣層220a，第二初始絕 ❹ 緣層220b’變成第二活化絕緣層220b。進行活化程序的方 法可以是對第一初始絕緣層220a’與第二初始絕緣層220b’ 進行雷射燒触、電漿钱刻或機械加工法，其中此機械加工 法包括水刀切割、喷砂或外型切割（例如是V型切割或銑 割），而上述雷射燒蝕所採用的雷射光源可以是紅外線雷 射、紫外線雷射、石榴石雷射（YAG laser)、二氧化碳雷 射、準分子雷射或遠紅外線雷射。 ❿ 當對第一初始絕緣層220a’與第二初始絕緣層220b’進 行雷射燒蝕或電漿蝕刻時，可以將第一阻障圖案層250a與 第二阻障圖案層250b作為遮罩，並使用雷射光束或電漿來 對第一初始絕緣層220a’與第二初始絕緣層220b’作全面性 的燒蝕或蝕刻，讓第一活化區224a形成於第一鏤空圖案 252a，第二活化區224b形成於第二鏤空圖案252b中。 請參閱圖2E，其為圖2D中第一活化區224a的放大 圖。在進行上述雷射燒蝕或電漿蝕刻之後，部分第一初始 19 201023701 絕緣層220a’會被移除而形成第一活化區224。也就是說， •第一活化區224a是一種凹陷，而第一活化區224a相對於 -第一表面222a的深度D可以是不大於1〇微米，即深度D 等於或小於1〇微米。同理，第二活化區224b亦可以是一 種凹陷，且第二活化區224b相蚜於第二表面222b的深度 也可以是不大於10微米。 ' 請再次參閱圖2C與圖2D，由於本實施例是在第一阻 障圖案層250a與第二阻障圖案層25〇b作為遮罩的條件 ❹下，使用雷射光束或電漿來對第一初始絕緣層220a，與第二 初始絕緣層220b’作全面性的燒餘或姓刻，因此部分第一阻 障圖案層250a與部分第二阻障圖案層25〇b會被燒蝕或蝕 刻，而形成厚度較薄的第一阻障圖案層25〇a，與第二阻障圖 案層250b’，如圖2D所示。 另外，由於第一鏤空圖案252a會暴露出整個第一盲孔 B1，而第二鏤空圖案252b會暴露出整個第二盲孔B2 (如 ❹圖2C所示），因此在進行活化程序之後，有些觸媒顆粒226 會活化並裸露於第一盲孔B1與第二盲孔B2内，如圖2D 所示。換句話說，本實施例的活化程序不僅會讓一些觸媒 顆粒226活化並裸露於第一活化區224a與第二活化區224b 内’同時也讓另一些觸媒顆粒226活化並裸露於第一盲孔 B1與第二盲孔B2内。 請參閱圖2F，接著，在第一活化區224a内形成第一 導電圖案層230a，以及在第二活化區224b内形成第二導 20 201023701 電圖案層230b，其中第一導電圖案層230a是形成於第— • 鏤空圖案252a中，而第二導電圖案層230b是形成於第二 - 鏤空圖案252b中。形成第一導電圖案層23〇a與第二導電 圖案層230b的方法可以是採用無需施加外部電流的化學 方法，其例如是無電電鍍法或化學氣相沉積。 詳細而言，當進行上述無電電鍍法或化學氣相沉積等 化學方法時，位於第一活化區224a與第二活化區224b的 這些活化後的觸媒顆粒226能直接與形成第一導電圖案層 ❿ 230a及第二導電圖案層230b的反應物產生反應，以進一 步地形成第一導電圖案層230a與第二導電圖案層230b。 舉例來說，當第一導電圖案層230a與第二導電圖案層 230b是由無電電鑛法來形成時，第一活化絕緣層220a與 第二活化絕緣層220b可以直接沉浸於電錢液，而不需要額 外形成種子層（seed layer) ’即可在第一活化區224a與第 二活化區224b内形成第一導電圖案層230a與第二導電圖 φ 案層230b。 由於有些觸媒顆粒226活化並裸露於第一盲與第 二盲孔B2内，因此當形成第一導電圖案層23如與第二導 電圖案層230b時，同時第一導電連接結構24〇a與第二導 電連接結構240b亦會分別形成於第一盲孔B1與第二盲孔 B2中。也就是說，第一導電圖案層230a與第一導電連接 結構240a二者可以同時形成，而第二導電圖案層23〇b與 第二導電連接結構240b二者可以同時形成。 21 201023701 請參閱圖2F與圖2G，在第一導電圖案層23〇a、第一 導電圖案層230b、第一導電連接結構240a以及第二導電 連接結構240b形成之後，移除阻障圖案層，即移除第一 P且 障圖案層250a，與第二阻障圖案層250b，，讓第，活化絕’緣 層220a的第一表面222a以及第二活化絕緣層22〇b的第一 表面222b得以裸露出來。至此，線路板200基本上已製造 完成。A group of papers composed of genus. Divided nano particles. Aluminium butadiene styrene copolymer, polyethylene terephthalate, polybutylene terephthalate resin, liquid crystal polymer, polyamine 6, nylon, compositive, poly Benzene fine, cyclic hydrocarbon filaments or any combination of these polymeric materials. The first conductive pattern layer 230a is disposed on the first surface 222a and is connected to the catalyst particles 226 located in the first active region 224a, wherein the first conductive pattern layer 230a protrudes from the first surface. The second conductive pattern layer is disposed on the second surface 222b and is connected to the catalyst particles 226 located in the second active region 22, wherein the second conductive pattern layer 23()b protrudes from the second 16 201023701 surface 222b . The first conductive pattern layer 230a and the second conductive pattern layer 230b • both include a plurality of pads for connecting the electronic components and a plurality of traces for transmitting current. In addition, the circuit board 200 further includes a plurality of conductive connection structures including at least one first conductive connection structure 240a and at least one second conductive connection structure 240b. The first conductive connection structure 240a is disposed in the first active insulating layer 220a and is connected between the first conductive pattern layer 230a and the first wiring layer 212a of the substrate 210. The second conductive connection structure 240b is disposed in the second active insulating layer 220b and is connected between the second conductive pattern layer 230b and the second wiring layer 212b of the substrate 210. In this embodiment, the first conductive connection structure 240a and the second conductive connection structure 240b may each be a conductive blind hole structure, and the conductive blind hole structure is, for example, a hollow conductive column, as shown in FIG. 2G. The first conductive pattern layer 230a and the second conductive pattern layer 230b may be electrically connected to the substrate 210 through the first conductive connection structure 240a and the second conductive connection structure 240b. It should be noted that in other embodiments not shown, the number of conductive connection structures included in the circuit board 200 may be only one. That is, the total number of both the first conductive connection structure 240a and the second conductive connection structure 240b included in the circuit board 200 may be only one. Therefore, the total number of the first conductive connection structure 240a and the second conductive connection structure 240b shown in Fig. 2G is merely illustrative and not limiting. The structural features of the circuit board 200 of the present embodiment are described above. 17 201023701 Next, the process of the circuit board 200 will be described with reference to FIGS. 2A to 2G. Referring to FIG. 2A, in the process of the circuit board 200, first, at least one initial insulating layer is formed, that is, a first initial insulating layer 220a' is formed on the upper surface 210a of the substrate 210, and a second initial insulation is formed. Layer 220b' is on lower surface 210b of substrate 210. Both the first initial insulating layer 220a' and the second initial insulating layer 220b' may be formed on the substrate 210 by press bonding or coating. Further, both the first initial insulating layer 220a' and the second initial insulating layer 220b' also include a high molecular weight compound 228 and these catalyst particles 226 distributed in the high molecular weight 10 compound 228. Referring to FIG. 2B, a drilling process is performed to form at least one first blind hole B1 and at least one second blind hole B2, wherein the first blind hole B1 and the second blind hole B2 may be drilled by laser Or mechanical drilling to form. The first blind via B1 is located in the first initial insulating layer 220a', and the second blind via B2 is located in the second initial insulating layer 220b'. The first blind via B1 partially exposes the first wiring layer 212a, and the second blind via B2 partially exposes the second wiring layer 212b. φ Referring to FIG. 2C, then at least one barrier pattern layer is formed over the substrate 210. In detail, the process of forming the barrier pattern layer includes forming a first barrier pattern layer 250a on the first initial insulating layer 220a' to form a second barrier pattern layer 250b on the second initial insulating layer 220b'. The first barrier pattern layer 250a and the second barrier pattern layer 250b may each be a patterned photoresist layer, which is, for example, a developed wet photoresist or dry film. As described above, the first barrier pattern layer 250a has a first hollow pattern 252a, and the first hollow pattern 252a partially exposes the first initial insulating layer 18 201023701 220a'. The second barrier pattern layer 250b has a second open pattern 252b, and the second open pattern 252b partially exposes the second initial insulating layer 220b'. In addition, the first hollow pattern 252a exposes the entire first blind via B1 and the first trace layer 212a exposed by the first blind via B1, and the second openwork pattern 252b exposes the entire second blind via B2 and the first The second circuit layer 212b exposed by the two blind vias B2. Referring to Fig. 2C and Fig. 2D, next, an activation process is performed to change the first initial insulating layer 220a' to the first activating insulating layer 220a, and the second initial insulating layer 220b' to the second activating insulating layer 220b. The method of performing the activation process may be a laser burn, a plasma or a machining method for the first initial insulating layer 220a ′ and the second initial insulating layer 220 b ′, wherein the mechanical processing method includes water jet cutting and sand blasting. Or external cutting (for example, V-cut or milling), and the laser source used in the above laser ablation may be infrared laser, ultraviolet laser, yog laser (YAG laser), carbon dioxide laser, Excimer laser or far infrared laser. When the first initial insulating layer 220a' and the second initial insulating layer 220b' are subjected to laser ablation or plasma etching, the first barrier pattern layer 250a and the second barrier pattern layer 250b may be used as a mask. And using the laser beam or the plasma to comprehensively ablate or etch the first initial insulating layer 220a' and the second initial insulating layer 220b', so that the first active region 224a is formed in the first hollow pattern 252a, and the second The activation region 224b is formed in the second hollow pattern 252b. Please refer to Fig. 2E which is an enlarged view of the first active region 224a of Fig. 2D. After the above-described laser ablation or plasma etching, a portion of the first initial 19 201023701 insulating layer 220a' is removed to form a first active region 224. That is, the first active region 224a is a recess, and the depth D of the first active region 224a with respect to the first surface 222a may be no more than 1 〇 micrometer, that is, the depth D is equal to or smaller than 1 〇 micrometer. Similarly, the second active region 224b may also be a recess, and the depth of the second active region 224b relative to the second surface 222b may also be no more than 10 micrometers. Referring again to FIG. 2C and FIG. 2D, since the present embodiment is under the condition that the first barrier pattern layer 250a and the second barrier pattern layer 25〇b are used as a mask, a laser beam or a plasma is used. The first initial insulating layer 220a is completely burned or surnamed with the second initial insulating layer 220b', so that part of the first barrier pattern layer 250a and part of the second barrier pattern layer 25〇b are ablated or Etching forms a thin first barrier pattern layer 25A and a second barrier pattern layer 250b' as shown in FIG. 2D. In addition, since the first hollow pattern 252a exposes the entire first blind hole B1, and the second hollow pattern 252b exposes the entire second blind hole B2 (as shown in FIG. 2C), after the activation process, some The catalyst particles 226 are activated and exposed in the first blind via B1 and the second blind via B2, as shown in Figure 2D. In other words, the activation procedure of this embodiment not only activates and exposes some of the catalyst particles 226 to the first active region 224a and the second active region 224b, but also activates and exposes the other catalyst particles 226 to the first The blind hole B1 and the second blind hole B2. Referring to FIG. 2F, a first conductive pattern layer 230a is formed in the first active region 224a, and a second conductive layer 20201023701 is formed in the second active region 224b. The first conductive pattern layer 230a is formed. In the first - hollow pattern 252a, the second conductive pattern layer 230b is formed in the second - hollow pattern 252b. The method of forming the first conductive pattern layer 23a and the second conductive pattern layer 230b may be a chemical method which does not require application of an external current, such as electroless plating or chemical vapor deposition. In detail, when the above-described chemical methods such as electroless plating or chemical vapor deposition are performed, the activated catalyst particles 226 located in the first active region 224a and the second active region 224b can directly form the first conductive pattern layer. The reactants of the crucible 230a and the second conductive pattern layer 230b are reacted to further form the first conductive pattern layer 230a and the second conductive pattern layer 230b. For example, when the first conductive pattern layer 230a and the second conductive pattern layer 230b are formed by electroless ore method, the first activating insulating layer 220a and the second activating insulating layer 220b may be directly immersed in the liquid money liquid, and The first conductive pattern layer 230a and the second conductive pattern φ layer 230b may be formed in the first active region 224a and the second active region 224b without additionally forming a seed layer. Since some of the catalyst particles 226 are activated and exposed in the first blind and second blind vias B2, when the first conductive pattern layer 23 is formed, such as the second conductive pattern layer 230b, the first conductive connection structure 24A and The second conductive connection structure 240b is also formed in the first blind hole B1 and the second blind hole B2, respectively. That is, both the first conductive pattern layer 230a and the first conductive connection structure 240a may be simultaneously formed, and both the second conductive pattern layer 23b and the second conductive connection 240b may be simultaneously formed. 21 201023701 Referring to FIG. 2F and FIG. 2G, after the first conductive pattern layer 23A, the first conductive pattern layer 230b, the first conductive connection structure 240a, and the second conductive connection structure 240b are formed, the barrier pattern layer is removed, That is, the first P and barrier pattern layer 250a, and the second barrier pattern layer 250b are removed, and the first surface 222a of the first insulating layer 220a and the first surface 222b of the second activating insulating layer 22b are removed. Can be exposed. At this point, the circuit board 200 has been substantially completed.
另外，在其他未繪示的實施例中，更可以形成防焊層 (solder mask )，其中一層防焊層形成於第一表面222a ’而 另一層防焊層形成於第二表面222b。這些防焊層會暴露第 一導電圖案層230a與第二導電圖案層230b二者的多個接 墊。其次，這些防焊層更可以填滿這些第一盲孔B1與第二 盲孔B2。此外，這些防焊層的類型可以是防焊層定義 (Solder Mask Define，SMD )或非防焊層定義（N〇n_s〇lder Mask Define，SMD )。 值得一提的是 固所不的線路板200為一種四 線路板’而圖2A至圖2G揭露此以雙面基板的四 的增層法製程。然、而，本實施例的製程亦可以製 路板與多躲路板。也就是說，在其他树軸實施例中 路板遍也可以是-種單面線路板或多層線路板 2A至圖2G所财的線路板_及其製程僅為舉例=明 並非限定本發明。 明 22 201023701 「第二實施例」 . 圖3A是本發明第二實施例之線路板的示意圖。請參 閱圖3A，在此先介紹本實施例的線路板300在結構方面的 特徵。就結構而言’本實施例的線路板與第一實施例 的線路板2 00相似’而·一者之間的顯者差異在於.線路板 300更包括至少一層樹脂層，而此樹脂層配置於基板與活 . 化絕緣層之間。 具體而言，線路板300包括基板210、一第一活化絕 ❹ 緣層320a、一第二活化絕緣層320b、多層樹脂層31〇a與 310b、第一導電圖案層230a、第二導電圖案層230b、至少 一第一導電連接結構240a以及至少一第二導電連接結構 240b。 承上述，第一活化絕緣層320a與第二活化絕緣層320b 二者的材質與第一實施例的第一活化絕緣層220a與第二 活化絕緣層220b相同，即二者皆包括高分子量化合物228 _ 與分佈於高分子量化合物228中的多個觸媒顆粒226。 樹脂層31〇a配置於第一活化絕緣層320a與基板210 之間’而樹脂層31〇b則配置於第二活化絕緣層320b與基 板210之間。在本實施例中，這些樹脂層31〇a、31〇b可以 是多片膠片或多層空白核心層，而這些樹脂層310a、310b 可以強化線路板300的結構。 圖3B是圖3A中的線路板在形成樹脂層時的示意圖， 請參閱圖3B，本實施例的線路板的製程大體與第一實施例 23 201023701 相同’而差異之處在於形成樹脂層310a、310b。詳細而言， • 在線路板300的製程甲，首先，形成樹脂層310a於基板 210的上表面210a上，形成樹脂層310b於基板210的下 表面210b上，其中形成樹脂層310a、310b的方法可以是 壓合樹脂層310a、310b於基板210上。 接著，形成第一初始絕緣層320a’於樹脂層310a上， 形成第二初始絕緣層320b’於樹脂層310b上，其中第一初 始絕緣層320a’與第二初始絕緣層320b’二者的形成方法與 ❿ 第一實施例中的第一初始絕緣層220a’與第二初始絕緣層 220b’相同，故不再重複介紹。 值得一提的是，第一初始絕緣層320a’與樹脂層310a 可以同時形成於基板210的上表面210a，而第二初始絕緣 層320b’與樹脂層310b可以同時形成於基板21〇的下表面 210b。舉例而言，第一初始絕緣層320a’與樹脂層31〇a可 同時壓合於基板210的上表面210a，而第二初始絕緣層 ❹ 320b’與樹脂層310b也可同時壓合於基板21〇的下表面 210b。 接下來，如同第一實施中圖2B至圖2G所示的流程， 進行鑽孔程序與活化程序，以及形成第一導電圖案層 230a、第二導電圖案層230b、第一導電連接結構24〇a與第 二導電連接結構240b。上述鑽孔程序、活化程序以及第一 導電圖案層230a、第二導電圖案層230b、第一導電連接結 構240a與第二導電連接結構240b的形成方法皆與第一實 24 201023701 施例相同，故不再重複介紹。 「第三實施例」 -立圖4A至圖4E疋本發明第三實施例之線路板的製程的 不忍圖’其中第三實施例的製程與第一實施例相似，因此 以下將偏重介紹本實施例與第一實施例的差異。 軌參_ 4A，錢行活及形成—第一盲孔 .B3與-第二盲孔B4於第—初始絕緣層與第二初始絕緣層 ©巾之後，第-盲孔B3與第二盲孔B4分別局部暴露基板21〇 的第一線路層212a與第二線路層21沘，而一些觸媒顆粒 226活化並裸露於第-盲孔33内與第二盲孔B4内。 第一活化絕緣層420a與第二活化絕緣層42〇b皆包括 高分子量化合物228以及多顆分佈於高分子量化合物228 的觸媒顆粒226，其中第一活化絕緣層42〇a具有一第一表 面422a以及一位於第一表面422a的第一活化區424a，而 ❹ 第二活化絕緣層420b具有一第二表面422b以及一位於第 二表面422b的第二活化區424b。一些觸媒顆粒226活化 並裸露於第一活化區424a與第二活化區424b内。 第一活化區424a涵蓋整個第一表面422a，而第二活化 區424b涵蓋整個第二表面422b。因此，裸露的觸媒顆粒 226分佈於整個第一表面422a與第二表面422b，如圖4A 所示。形成第一活化區424a與第二活化區424b的方法有 多種。舉例來說’當活化程序採用雷射燒蝕或電漿蝕刻時， 25 201023701 使用雷射光束或電漿來燒蝕或蝕刻整個第一表面422a與 • 整個第二表面422b，以形成第一活化區424a與第二活化 區 424b。 請參閱圖4B，接著，形成一第一金屬層460a於第一 表面422a ’以及一第二金屬層460b於第二表面422b，其 中形成第一金屬層460a與第二金屬層460b的方法可以是 採用無需施加外部電流的化學方法，其例如是無電電鑛法 或化學氣相沉積。另外，由於第一活化區424a與第二活化 ® 區424b涵蓋整個第一表面422a與整個第二表面422b，因 此第一金屬層460a全面性地覆蓋第一表面422a，而第二金 屬層460b全面性地覆蓋第二表面422b。 其次’由於一些觸媒顆粒226活化並裸露於第一盲孔 B3内與第二盲孔B4内，因此第一金屬層460a更形成於第 一盲孔B3内’而第二金屬層460b更形成於第二盲孔B4 内。第一金屬層460a全面性地覆蓋第一盲孔B3，而第二 〇 金屬層460b全面性地覆蓋第二盲孔B4，其中第一金屬層 460a未填滿第一盲孔B3，而第二金屬層460b也未填滿第 二盲孔B4。 請參閱圖4C，接著，形成一第一阻障圖案層450a於 第一金屬層460a上，以及形成一第二阻障圖案層450b於 第二金屬層460b上。第一阻障圖案層450a具有一局部暴 露第一金屬層460a的第一鎮空圖案452a’而第二阻障圖案 層450b具有一局部暴露第二金屬層460b的第二鐘空圖宰 26 201023701 452b。第一阻障圖案層450a與第二阻障圖案層450b二者 * 的材質與形成方法皆與第一實施例相同，故不再重複介紹。 - 請參閱圖4D，在第一阻障圖案層450a與第二阻障圖 案層450b形成之後，對第一金屬層460a與第二金屬層460b 進行電鍍，以形成一第一導電圖案層430a於第一鏤空圖案 452a所局部暴露的第一金屬層460a，形成一第二導電圖案 層430b於第二鏤空圖案452b所局部暴露的第二金屬層 460b中。因此，第一導電圖案層430a與一第二導電圖案 ® 層430b二者是用施加外部電流的電鍍法來形成。 當形成第一導電圖案層430a與第二導電圖案層430b 時，透過電鍍法，同時形成一第一導電連接結構440a於第 一盲孔B3中，形成一第二導電連接結構440b於第四盲孔 B4，其中第一導電連接結構440a連接於第一導電圖案層 430a與基板210的第一線路層212a之間，而第二導電連接 結構440b連接於第二導電圖案層430b與基板210的第二 _ 線路層212b之間。 在本實施例中，第一導電連接結構440a與第二導電連 接結構440b皆可以是一種導電盲孔結構，而此導電盲孔結 構例如是一種實心導電柱，如圖4D所示。透過第一導電 連接結構440a與第二導電連接結構440b，第一導電圖案 層430a與第二導電圖案層430b二者皆可以與基板210電 性導通。 請參閱圖4D與圖4E，接著，移除第一阻障圖案層450a 27 201023701 與第二阻障圖案層450b，讓第一金屬層460a與第二金屬 ， 層460b皆得以裸露出來。之後，移除部分第一金屬層460a • 與部分第二金屬層460b，以裸露出第一表面422a與第二 表面422b ’並且避免第一導電圖案層430a與第二導電圖 案層430b發生短路。此外，移除部分第一金屬層460a與 部分第二金屬層460b的方法可以是對第一金屬層460a與 第二金屬層460b進行蝕刻。 在移除部分第一金屬層460a與部分第二金屬層460b ® 之後，基本上，一種包括基板210、第一活化絕緣層420a、 第二活化絕緣層420b、第一導電圖案層430a、第二導電圖 案層430b、第一導電連接結構440a以及第二導電連接結 構440b的線路板400已完成。 值得一提的是，第二實施例中的樹脂層31〇a、310b皆 可以應用於第三實施例中。詳細而言，在其他未繪示的實 施例中，在形成第一初始絕緣層與第二初始絕緣層之前’ ❿ 可先形成一層樹脂層於基板210的上表面210a ’形成另一 層樹脂層於基板210的下表面210b。之後，形成第一初始 絕緣層與第二初始絕緣層於這些樹脂層上。上述樹脂層的 材質與形成方法皆與第二實施例相同，故不再重覆介紹。 「第四實施例」 圖5A至圖5H是本發明第四實施例之線路板的製程的 示意圖，其中第四實施例的線路板的製程與第三實施例相 28 201023701 似’而二者顯著的差異在於：形成盲孔的時機不同。以下 將偏重介紹本實施例與第三實施例的差異。 請參閱圖5A，在進行活化程序之後，第一活化絕緣層 520a與第二活化絕緣層52〇b皆形成。第一活化絕緣層520a 與第二活化絕緣層520b皆包括高分子量化合物228以及多 顆分佈於高分子量化合物228的觸媒顆粒226,其中第一 •活化絕緣層520a具有一第一表面522a以及一位於第一表 赢 面522a的第一活化區524a，而第二活化絕緣層520b具有 響 一第二表面522b以犮一位於第二表面522b的第二活化區 524b。一些觸媒顆粒226活化並裸露於第一活化區524a與 第二活化區524b。 承上述’第一活化區524a涵蓋整個第一表面522a，而 第二活化區524b涵蓋整個第二表面522b。也就是說，裸 露的觸媒顆粒226分佈於整個第一表面522a與第二表面 522b，如圖5A所示，而形成第一活化區524a與第二活化 . 區524b的方法與第三實施例相同，故不再重覆介紹。 請參閲圖5B，接著，形成一第一金屬層560a於第一 表面522a，以及一第二金屬層560b於第二表面522b，其 中第一金屬層560a全面性地覆蓋第一表面522a，而第二金 屬層560b全面性地覆蓋第二表面522b。此外，形成第一 金屬層560a與第二金屬層560b的方法與第三實施例相同。 請參閱圖5C，接著，形成一第一盲孔B5於第一活化 絕緣層520a與第一金屬層560a中，形成一第二盲孔B6於 29 201023701 第二活化絕緣層520b與第二金屬層560b中，其中第一盲 • 孔B5與第二盲孔B6二者的形成方法與第三實施例相同。 . 第一盲孔B5局部暴露基板210的第一線路層212a，而第 二盲孔B6局部暴露基板210的第二線路層212b。 請參閱圖5C與圖5D，接著，減少第一金屬層560a 與第二金屬層560b二者厚度，以形成第一金屬層560a’與 第二金屬層560b’，其中減少第一金屬層560a與第二金屬 層560b二者厚度的方法可以是對第一金屬層560a與第二 ⑩ 金屬層560b進行餘刻。 必須說明的是，上述減少第一金屬層560a與第二金屬 層560b二者厚度的流程為本實施例中的選擇性流程，並非 是必要流程。因此，在其他實施例中，第一金屬層560a與 第二金屬層560b二者厚度可以不必減少。 請參閱圖5E，接著，形成一第一電鍍層570a與一第 二電鍍層570b。第一電鍍層570a覆蓋第一盲孔B5的表 ⑩ 面，而第二電鍍層570b覆蓋第二盲孔B6的表面，其中第 一電鍍層570a連接第一金屬層560a’，而第二電鍍層570b 連接第二金屬層560b’。 承上述，第一電鍍層570a與第二電鍍層570b可以採 用無電電鍍法來形成，因此在形成第一電鍍層570a與第二 電鍍層570b的過程中，第一金屬層560a’與第二金屬層 560b’的厚度會變厚，如圖5E所示。 請參閱圖5F，在形成第一電鍍層570a與第二電鍍層 30 201023701 570b之後，形成-第-阻障圖案層55〇a於第一金屬層 560a’上’形成一第二阻障圖案層观於第二金屬層鳩， 上，其中第-阻障圖案層55〇a與第二阻障圖案層55〇b二 者的材質與形成方法皆與第三實施例相同。In addition, in other embodiments not shown, a solder mask may be formed in which a solder resist layer is formed on the first surface 222a' and another solder resist layer is formed on the second surface 222b. These solder resist layers expose a plurality of pads of both the first conductive pattern layer 230a and the second conductive pattern layer 230b. Secondly, these solder mask layers can fill the first blind via B1 and the second blind via B2. In addition, the types of these solder masks may be Solder Mask Define (SMD) or N〇n_s〇lder Mask Define (SMD). It is worth mentioning that the fixed circuit board 200 is a four-circuit board' and Figures 2A to 2G disclose the four-layer build-up process of the double-sided board. However, the process of this embodiment can also be used for making road boards and multiple boards. That is to say, in other tree-axis embodiments, the circuit board can also be a single-sided circuit board or a multi-layer circuit board 2A to 2G. The circuit board and its process are merely examples. Ming 22 201023701 "Second Embodiment" Fig. 3A is a schematic view of a wiring board according to a second embodiment of the present invention. Referring to Fig. 3A, the structural features of the wiring board 300 of the present embodiment will be described first. In terms of structure, the circuit board of the present embodiment is similar to the circuit board 200 of the first embodiment, and the significant difference between the one is that the circuit board 300 further includes at least one resin layer, and the resin layer configuration Between the substrate and the active insulating layer. Specifically, the circuit board 300 includes a substrate 210, a first active insulating edge layer 320a, a second activating insulating layer 320b, a plurality of resin layers 31A and 310b, a first conductive pattern layer 230a, and a second conductive pattern layer. 230b, at least one first conductive connection structure 240a and at least one second conductive connection structure 240b. As described above, the materials of both the first activating insulating layer 320a and the second activating insulating layer 320b are the same as those of the first activating insulating layer 220a and the second activating insulating layer 220b of the first embodiment, that is, both include the high molecular weight compound 228. And a plurality of catalyst particles 226 distributed in the high molecular weight compound 228. The resin layer 31〇a is disposed between the first activating insulating layer 320a and the substrate 210, and the resin layer 31〇b is disposed between the second activating insulating layer 320b and the substrate 210. In the present embodiment, these resin layers 31a, 31b may be a plurality of films or a plurality of blank core layers, and these resin layers 310a, 310b may reinforce the structure of the wiring board 300. 3B is a schematic view of the circuit board of FIG. 3A when a resin layer is formed. Referring to FIG. 3B, the process of the circuit board of the present embodiment is substantially the same as that of the first embodiment 23 201023701. The difference is that the resin layer 310a is formed. 310b. In detail, in the process A of the wiring board 300, first, the resin layer 310a is formed on the upper surface 210a of the substrate 210, and the resin layer 310b is formed on the lower surface 210b of the substrate 210, wherein the resin layers 310a, 310b are formed. It may be that the resin layers 310a, 310b are laminated on the substrate 210. Next, a first initial insulating layer 320a' is formed on the resin layer 310a to form a second initial insulating layer 320b' on the resin layer 310b, wherein the first initial insulating layer 320a' and the second initial insulating layer 320b' are formed. The method and the first initial insulating layer 220a' in the first embodiment are the same as the second initial insulating layer 220b', and therefore will not be repeatedly described. It is to be noted that the first initial insulating layer 320a' and the resin layer 310a may be simultaneously formed on the upper surface 210a of the substrate 210, and the second initial insulating layer 320b' and the resin layer 310b may be simultaneously formed on the lower surface of the substrate 21〇. 210b. For example, the first initial insulating layer 320a' and the resin layer 31A may be simultaneously pressed against the upper surface 210a of the substrate 210, and the second initial insulating layer 320b' and the resin layer 310b may be simultaneously pressed onto the substrate 21. The lower surface 210b of the crucible. Next, as in the flow shown in FIG. 2B to FIG. 2G in the first embodiment, the drilling process and the activation process are performed, and the first conductive pattern layer 230a, the second conductive pattern layer 230b, and the first conductive connection structure 24A are formed. And a second conductive connection structure 240b. The drilling process, the activation process, and the first conductive pattern layer 230a, the second conductive pattern layer 230b, the first conductive connection structure 240a, and the second conductive connection structure 240b are all formed in the same manner as the first embodiment 24 201023701. The description will not be repeated. "Third Embodiment" - FIG. 4A to FIG. 4E are diagrams of the process of the circuit board according to the third embodiment of the present invention. The process of the third embodiment is similar to that of the first embodiment, and therefore the present embodiment will be emphasized below. The difference between the example and the first embodiment. Track _ 4A, money running and forming - first blind hole. B3 and - second blind hole B4 after the first initial insulating layer and the second initial insulating layer, the first blind hole B3 and the second blind hole B4 partially exposes the first circuit layer 212a and the second circuit layer 21 of the substrate 21, respectively, and some of the catalyst particles 226 are activated and exposed in the first blind hole 33 and the second blind hole B4. The first activating insulating layer 420a and the second activating insulating layer 42B include a high molecular weight compound 228 and a plurality of catalyst particles 226 distributed over the high molecular weight compound 228, wherein the first activating insulating layer 42A has a first surface 422a and a first active region 424a on the first surface 422a, and the second active insulating layer 420b has a second surface 422b and a second active region 424b on the second surface 422b. Some of the catalyst particles 226 are activated and exposed within the first activation zone 424a and the second activation zone 424b. The first activation zone 424a covers the entire first surface 422a and the second activation zone 424b covers the entire second surface 422b. Therefore, the bare catalyst particles 226 are distributed throughout the first surface 422a and the second surface 422b as shown in Fig. 4A. There are various methods of forming the first active region 424a and the second active region 424b. For example, 'When the activation procedure employs laser ablation or plasma etching, 25 201023701 uses a laser beam or plasma to ablate or etch the entire first surface 422a and the entire second surface 422b to form a first activation. Region 424a and second activation region 424b. Referring to FIG. 4B, a first metal layer 460a is formed on the first surface 422a' and a second metal layer 460b is formed on the second surface 422b. The method of forming the first metal layer 460a and the second metal layer 460b may be A chemical method that does not require application of an external current is used, for example, electroless ore or chemical vapor deposition. In addition, since the first active region 424a and the second active region 424b cover the entire first surface 422a and the entire second surface 422b, the first metal layer 460a comprehensively covers the first surface 422a, and the second metal layer 460b is comprehensive. The second surface 422b is covered sexually. Secondly, since some of the catalyst particles 226 are activated and exposed in the first blind via B3 and the second blind via B4, the first metal layer 460a is formed in the first blind via B3, and the second metal layer 460b is formed. In the second blind hole B4. The first metal layer 460a comprehensively covers the first blind hole B3, and the second metal layer 460b comprehensively covers the second blind hole B4, wherein the first metal layer 460a does not fill the first blind hole B3, and the second The metal layer 460b also does not fill the second blind via B4. Referring to FIG. 4C, a first barrier pattern layer 450a is formed on the first metal layer 460a, and a second barrier pattern layer 450b is formed on the second metal layer 460b. The first barrier pattern layer 450a has a first empty pattern 452a' that partially exposes the first metal layer 460a and the second barrier pattern layer 450b has a second clock pattern that partially exposes the second metal layer 460b. 26 201023701 452b. The materials and formation methods of both the first barrier pattern layer 450a and the second barrier pattern layer 450b are the same as those of the first embodiment, and therefore will not be repeatedly described. Referring to FIG. 4D, after the first barrier pattern layer 450a and the second barrier pattern layer 450b are formed, the first metal layer 460a and the second metal layer 460b are plated to form a first conductive pattern layer 430a. The first metal layer 460a partially exposed by the first hollow pattern 452a forms a second conductive pattern layer 430b in the second metal layer 460b partially exposed by the second hollow pattern 452b. Therefore, both the first conductive pattern layer 430a and the second conductive pattern ® layer 430b are formed by plating using an external current. When the first conductive pattern layer 430a and the second conductive pattern layer 430b are formed, a first conductive connection structure 440a is simultaneously formed in the first blind via B3 by electroplating, and a second conductive connection structure 440b is formed in the fourth blind. The hole B4, wherein the first conductive connection structure 440a is connected between the first conductive pattern layer 430a and the first circuit layer 212a of the substrate 210, and the second conductive connection structure 440b is connected to the second conductive pattern layer 430b and the substrate 210 Between the two circuit layers 212b. In this embodiment, the first conductive connection structure 440a and the second conductive connection structure 440b may each be a conductive blind via structure, and the conductive blind via structure is, for example, a solid conductive pillar, as shown in FIG. 4D. Both the first conductive pattern layer 430a and the second conductive pattern layer 430b can be electrically connected to the substrate 210 through the first conductive connection structure 440a and the second conductive connection structure 440b. Referring to FIG. 4D and FIG. 4E, the first barrier pattern layer 450a 27 201023701 and the second barrier pattern layer 450b are removed, so that the first metal layer 460a and the second metal layer 460b are exposed. Thereafter, a portion of the first metal layer 460a and a portion of the second metal layer 460b are removed to expose the first surface 422a and the second surface 422b' and to prevent shorting of the first conductive pattern layer 430a and the second conductive pattern layer 430b. Further, the method of removing a portion of the first metal layer 460a and the portion of the second metal layer 460b may be to etch the first metal layer 460a and the second metal layer 460b. After removing a portion of the first metal layer 460a and a portion of the second metal layer 460b ® , substantially, the substrate 210 includes a substrate 210, a first activating insulating layer 420a, a second activating insulating layer 420b, a first conductive pattern layer 430a, and a second The wiring pattern 400 of the conductive pattern layer 430b, the first conductive connection structure 440a, and the second conductive connection structure 440b has been completed. It is to be noted that the resin layers 31a, 310b in the second embodiment can be applied to the third embodiment. In detail, in other embodiments not shown, a resin layer may be formed on the upper surface 210a of the substrate 210 to form another resin layer before the first initial insulating layer and the second initial insulating layer are formed. The lower surface 210b of the substrate 210. Thereafter, a first initial insulating layer and a second initial insulating layer are formed on the resin layers. The material and formation method of the above resin layer are the same as those of the second embodiment, and therefore will not be repeatedly described. [Fourth Embodiment] Figs. 5A to 5H are views showing a process of a circuit board according to a fourth embodiment of the present invention, wherein the process of the wiring board of the fourth embodiment is similar to that of the third embodiment 28 201023701 and both are remarkable The difference is that the timing of forming blind holes is different. Differences between this embodiment and the third embodiment will be described below. Referring to FIG. 5A, after the activation process is performed, both the first activating insulating layer 520a and the second activating insulating layer 52'b are formed. The first activating insulating layer 520a and the second activating insulating layer 520b each include a high molecular weight compound 228 and a plurality of catalyst particles 226 distributed over the high molecular weight compound 228, wherein the first activating insulating layer 520a has a first surface 522a and a The second active insulating layer 520b is located on the first active region 524a of the first surface 522a, and the second activating insulating layer 520b has a second surface 522b to lie in the second active region 524b of the second surface 522b. Some of the catalyst particles 226 are activated and exposed to the first activation zone 524a and the second activation zone 524b. The first activation zone 524a encompasses the entire first surface 522a and the second activation zone 524b covers the entire second surface 522b. That is, the bare catalyst particles 226 are distributed throughout the first surface 522a and the second surface 522b, as shown in FIG. 5A, and the first active region 524a and the second activation region 524b are formed and the third embodiment. The same, so no longer repeat. Referring to FIG. 5B, a first metal layer 560a is formed on the first surface 522a, and a second metal layer 560b is formed on the second surface 522b, wherein the first metal layer 560a comprehensively covers the first surface 522a. The second metal layer 560b comprehensively covers the second surface 522b. Further, the method of forming the first metal layer 560a and the second metal layer 560b is the same as that of the third embodiment. Referring to FIG. 5C, a first blind via B5 is formed in the first activating insulating layer 520a and the first metal layer 560a to form a second blind via B6 at 29 201023701, a second active insulating layer 520b and a second metal layer. In 560b, the formation method of both the first blind hole B5 and the second blind hole B6 is the same as that of the third embodiment. The first blind via B5 partially exposes the first wiring layer 212a of the substrate 210, and the second blind via B6 partially exposes the second wiring layer 212b of the substrate 210. Referring to FIG. 5C and FIG. 5D, then, the thickness of both the first metal layer 560a and the second metal layer 560b is reduced to form a first metal layer 560a' and a second metal layer 560b', wherein the first metal layer 560a is reduced The method of thicknessing the second metal layer 560b may be a process of engraving the first metal layer 560a and the second 10 metal layer 560b. It should be noted that the above-described process of reducing the thickness of both the first metal layer 560a and the second metal layer 560b is a selective process in the embodiment, and is not a necessary process. Therefore, in other embodiments, the thickness of both the first metal layer 560a and the second metal layer 560b may not necessarily be reduced. Referring to FIG. 5E, a first plating layer 570a and a second plating layer 570b are formed. The first plating layer 570a covers the surface of the first blind via B5, and the second plating layer 570b covers the surface of the second blind via B6, wherein the first plating layer 570a connects the first metal layer 560a', and the second plating layer 570b connects the second metal layer 560b'. In the above, the first plating layer 570a and the second plating layer 570b may be formed by electroless plating, so in the process of forming the first plating layer 570a and the second plating layer 570b, the first metal layer 560a' and the second metal The thickness of layer 560b' will become thicker as shown in Figure 5E. Referring to FIG. 5F, after forming the first plating layer 570a and the second plating layer 30201023701 570b, forming a -first barrier pattern layer 55A on the first metal layer 560a' to form a second barrier pattern layer Regarding the second metal layer, the material and the forming method of the first barrier pattern layer 55A and the second barrier pattern layer 55B are the same as those of the third embodiment.
承上述，第一阻障圖案層55〇a具有一第一鎮空圖案 552a’而第二阻障圖案層55〇b具有一第二鐘空圖案挪。 第-鏤空圖案552a完全暴露第—電鐘層57〇a，並局部暴露 第-金屬層56Ga’。第二鎮空圖案552b完全暴露第二電錢 層570b，並局部暴露第二金屬層56仙，。 請參閱圖5F與圖5G，接著’對第—電鐘層57〇a與第 二電鑛層57〇b進行電鑛，以形成一第一導電圖案層憑、 -第二導電圖案層遍、一第—導電連接結構術以及 第一導電連接結構540b。第一導電圖案層53〇a形成於 第一鏤空圖案552a所局部暴露的第一金屬層56〇&，，而第 -導電圖案層53Gb是形成於第二鏤空圖案552b所局部暴 露的第二金屬層560b’。 第一導電連接結構540a形成於第一盲孔B5中，而第 二導電連接結構540b形成於第二盲孔B6中，其中第一導 電連接結構540a連接於第一導電圖案層53〇a與第一線路層 212a之間，而第二導電連接結構540b連接於第二導電圖案 層530b與第二線路層212b之間。 請參閱圖5G與圖5H，接著’移除第一阻障圖案層550a 與第二阻障圖案層550b，讓第一金屬層560a，與第二金屬 31 201023701 層5_’皆能裸露出來。之後，移除部分第一金屬層56〇a， • 與部分第二金屬層560b’，以裸露出第一表面522a與第二 • 表面522b，並且避免第一導電圖案層53〇a與第二導電圖 案層530b發生短路，其中移除部分第一金屬層56如，與部 分第二金屬層560b，的方法與第三實施例相同。 在移除部分第一金屬層560a’與部分第二金屬層56〇b， 之後，基本上，一種包括基板210、第一活化絕緣層52〇a、 第二活化絕鍊層520b、第一導電圖案層530a、第二導電圖 ® 案層530b、第一導電連接結構54〇a以及第二導電連接結 構540b的線路板500已製造完成。此外’第二實施例中的 樹脂層310a、310b皆可以應用於第四實施例中，而應用的 方法已在前述實施例中揭露，故不再重複介紹。 綜上所述’利用上述活化絕緣層（例如第一活化絕緣 層與第二活化絕緣層），本發明得以形成包括多條走線與多 個接墊的導電圖案層（例如第一導電圖案層與第二導電圖 ❿ 案層），進而製造可供多個電子元件組裝的線路板。透過本 發明的線路板，電訊號可以在這些電子元件之間傳遞，進而 讓電子裝置或電氣用品得以運作。 雖然本發明以前述實施例揭露如上，然其並非用以限 定本發明，任何熟習相像技藝者，在不脫離本發明之精神 和範圍内，所作更動與潤飾之等效替換’仍為本發明之專 利保護範圍内。 【圖式簡單說明】 32 201023701 圖1是本發明之線路板的製程的流程圖° . 圖2A至圖2G是本發明第一實施例之線路板的製程的 • 示意圖。 圖3A是本發明第二實施例之線路板的示意圖。 圖3B是圖3A中的線路板在形成樹脂層時的示意圖。 圖4A至圖4E是本發明第三實施例之線路板的製程的 . 7F意圖。 圖5A至圖5H是本發明第四實施例之線路板的製程的 ®示意圖。 【主要元件符號說明】 200、300、400、500 線路板 210 基板In the above, the first barrier pattern layer 55A has a first empty pattern 552a' and the second barrier pattern layer 55b has a second clock pattern. The first-hollow pattern 552a completely exposes the first electric clock layer 57A, and partially exposes the first metal layer 56Ga'. The second empty pattern 552b completely exposes the second electric money layer 570b and partially exposes the second metal layer 56 sen. Referring to FIG. 5F and FIG. 5G, the electric arc is performed on the first electric clock layer 57〇a and the second electric ore layer 57〇b to form a first conductive pattern layer and a second conductive pattern layer. A first conductive connection structure and a first conductive connection structure 540b. The first conductive pattern layer 53A is formed on the first metal layer 56〇& partially exposed by the first hollow pattern 552a, and the first conductive pattern layer 53Gb is formed in the second exposed portion 552b. Metal layer 560b'. The first conductive connection structure 540a is formed in the first blind via B5, and the second conductive connection structure 540b is formed in the second blind via B6, wherein the first conductive connection structure 540a is connected to the first conductive pattern layer 53A and A circuit layer 212a is connected between the second conductive pattern layer 530b and the second circuit layer 212b. Referring to FIG. 5G and FIG. 5H, the first barrier pattern layer 550a and the second barrier pattern layer 550b are removed, so that the first metal layer 560a and the second metal 31 201023701 layer 5_' can be exposed. Thereafter, a portion of the first metal layer 56A, and a portion of the second metal layer 560b' are removed to expose the first surface 522a and the second surface 522b, and the first conductive pattern layer 53A and the second are avoided. The conductive pattern layer 530b is short-circuited, and the method of removing a portion of the first metal layer 56, such as a portion of the second metal layer 560b, is the same as that of the third embodiment. After removing a portion of the first metal layer 560a' and a portion of the second metal layer 56b, substantially, one includes a substrate 210, a first activating insulating layer 52a, a second activated star layer 520b, and a first conductive The wiring board 500 of the pattern layer 530a, the second conductive pattern layer 530b, the first conductive connection structure 54A, and the second conductive connection structure 540b has been completed. Further, the resin layers 310a, 310b in the second embodiment can be applied to the fourth embodiment, and the method of application has been disclosed in the foregoing embodiments, and therefore will not be repeatedly described. In summary, the present invention enables the formation of a conductive pattern layer (eg, a first conductive pattern layer) including a plurality of traces and a plurality of pads using the above-described activated insulating layer (eg, the first activating insulating layer and the second activating insulating layer). And the second conductive pattern layer), thereby manufacturing a circuit board that can be assembled by a plurality of electronic components. With the circuit board of the present invention, electrical signals can be transmitted between these electronic components, thereby allowing electronic devices or electrical appliances to operate. While the present invention has been described above in the foregoing embodiments, it is not intended to limit the invention, and the equivalents of the modification and retouching of the present invention are still in the present invention without departing from the spirit and scope of the invention. Within the scope of patent protection. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flow chart showing the process of the circuit board of the present invention. FIG. 2A to FIG. 2G are schematic diagrams showing the process of the circuit board according to the first embodiment of the present invention. Fig. 3A is a schematic view of a wiring board according to a second embodiment of the present invention. Fig. 3B is a schematic view of the wiring board of Fig. 3A when a resin layer is formed. 4A to 4E are views showing the process of the circuit board of the third embodiment of the present invention. 5A to 5H are schematic views of the process of the wiring board of the fourth embodiment of the present invention. [Main component symbol description] 200, 300, 400, 500 circuit board 210 substrate
210a 上表面 210b 下表面 212a 第一線路層 212b 第二線路層 214 介電層 220a、320a、420a、520a 第一活化絕緣層 220a，、320aJ 第一初始絕緣廣 220b、320b、420b、520b 第二活化絕緣層 220b’、320b’ 第二初始絕緣層 222a、422a、522a 第一表面 33 201023701 222b、422b、522b 224a、424a、524a • 224b、424b、524b 226 228 230a、430a、530a 230b、430b、530b 240a、440a、540a ® 240b、440b、540b 250a、250a’、450a 250b、250b’、450b 252a、452a、552a 252b、452b、552b 310a、310b 460a、560a’ 〇 460b、560b’ 570a 570b210a upper surface 210b lower surface 212a first wiring layer 212b second wiring layer 214 dielectric layer 220a, 320a, 420a, 520a first activating insulating layer 220a, 320aJ first initial insulating width 220b, 320b, 420b, 520b second Activating insulating layer 220b', 320b' second initial insulating layer 222a, 422a, 522a first surface 33 201023701 222b, 422b, 522b 224a, 424a, 524a • 224b, 424b, 524b 226 228 230a, 430a, 530a 230b, 430b, 530b 240a, 440a, 540a ® 240b, 440b, 540b 250a, 250a', 450a 250b, 250b', 450b 252a, 452a, 552a 252b, 452b, 552b 310a, 310b 460a, 560a' 〇 460b, 560b' 570a 570b
B1、B3、B5 B2、B4、B6 D 第二表面 第一活化區 第二活化區 觸媒顆粒 高分子量化合物 第一導電圖案層 第二導電圖案層 第一導電連接結構 第二導電連接結構 • 550a第一阻障圖案層 、550b第二阻障圖案層 第一鏤空圖案 第二鏤空圖案 樹脂層 第一金屬層 第二金屬層 第一電鍍層 第二電鍍層 第一盲孔 第二盲孔 深度 34B1, B3, B5 B2, B4, B6 D Second surface First active region Second active region Catalyst particles High molecular weight compound First conductive pattern layer Second conductive pattern layer First conductive connection structure Second conductive connection structure • 550a First barrier pattern layer, 550b second barrier pattern layer first hollow pattern second hollow pattern resin layer first metal layer second metal layer first plating layer second plating layer first blind hole second blind hole depth 34