CN103517568A - Circuit board and its manufacturing method - Google Patents
Circuit board and its manufacturing method Download PDFInfo
- Publication number
- CN103517568A CN103517568A CN201210208348.0A CN201210208348A CN103517568A CN 103517568 A CN103517568 A CN 103517568A CN 201210208348 A CN201210208348 A CN 201210208348A CN 103517568 A CN103517568 A CN 103517568A
- Authority
- CN
- China
- Prior art keywords
- layer
- conductive layer
- dielectric layer
- dielectric
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention discloses a circuit board and its manufacturing method. The method comprises the following steps: firstly, a dielectric layer which contains multiple activated particles is formed on a dielectric substrate; secondly, surface treatment is carried out on the surface of the dielectric layer so as to activate the activated particles positioned on the surface of the dielectric layer; thirdly, a first conducting layer is formed on the activated surface of the dielectric layer; fourthly, a conducting hole is formed in the dielectric substrate and the dielectric layer; fifthly, a patterning mask layer is formed on the first conducting layer and lets the conducting hole and part of the first conducting layer be exposed; sixthly, a second conducting layer is formed on the first conducting layer and the conducting hole which are exposed by the patterning mask layer; and finally, the patterning mask layer and the first conducting layer positioned below the patterning mask layer are removed.
Description
Technical field
The present invention relates to a kind of wiring board and preparation method thereof, and particularly relate to a kind of wiring board that increases the adhesive force between copper layer and dielectric layer in Improvement type half addition manufacture craft by the active particle in dielectric layer and preparation method thereof.
Background technology
In recent years, along with making rapid progress of electronic technology, coming out one after another of high-tech electronic industry, constantly weeds out the old and bring forth the new electronic product more humane, with better function, and towards light, thin, short, little trend design.In these electronic products, conventionally can configure the wiring board with conducting wire.
In order to improve the wiring density in wiring board, can to utilize, subtract into manufacture craft (substrative process) and the line layer in wiring board is made as to the live width having more than 40 μ m.Yet, for the live width below 40 μ m, utilize to subtract into manufacture craft and make line layer and will cause product yield to reduce.Therefore, all take at present half addition manufacture craft (semi-additive process, SAP) or Improvement type half addition manufacture craft (modified semi-additive process, MSAP) makes the line layer of live width below 40 μ m.
Yet, the copper clad laminate using for Improvement type half addition manufacture craft, ultra-thin copper sheet and the dielectric substrate pressing of its copper layer used thickness 3 μ m, because thickness is very thin and conventionally have low roughness (center line average roughness (Ra) and 10 mean roughness (Rz)), make the adhesive force between line layer and dielectric layer bad.Therefore,, if copper sheet thickness will be continued to reduction, can in manufacture process, cause copper layer easily from dielectric substrate, to be peeled off, thereby reduce the reliability of wiring board.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of wiring board, it increases the adhesive force between line layer and dielectric layer by the active particle in dielectric layer.
Another object of the present invention is to provide a kind of wiring board, between its line layer and dielectric layer, by the active particle in dielectric layer, increases adhesive force.
For reaching above-mentioned purpose, the present invention proposes a kind of manufacture method of wiring board, and the method is prior to forming dielectric layer on dielectric substrate, contains a plurality of activation particles in its dielectric layer.Then, surface treatment is carried out in the surface of dielectric layer, to expose part activation particle.Then, on the surface of dielectric layer, form the first conductive layer.Then, in dielectric substrate and dielectric layer, form via.Then, on the first conductive layer, form patterned mask layer, this patterned mask layer exposes via and this first conductive layer of part.Subsequently, on the first conductive layer exposing in patterned mask layer and via, form the second conductive layer.Afterwards, remove patterned mask layer and the first conductive layer that is positioned at patterned mask layer below.
According to the manufacture method of the wiring board described in the embodiment of the present invention, the material of above-mentioned activation particle is for example metal complex.
According to the manufacture method of the wiring board described in the embodiment of the present invention, above-mentioned surface treatment is for example that plasma surface treatment or chemical solution cleans are processed.
According to the manufacture method of the wiring board described in the embodiment of the present invention, the formation method of the first above-mentioned conductive layer is for example pressing method, rubbing method or spraying process.
According to the manufacture method of the wiring board described in the embodiment of the present invention, the thickness of the first above-mentioned conductive layer is for example less than the thickness of the second conductive layer.
According to the manufacture method of the wiring board described in the embodiment of the present invention, the surperficial roughness towards dielectric layer of the first above-mentioned conductive layer is for example less than or equal to 3 μ m.
According to the manufacture method of the wiring board described in the embodiment of the present invention, the surperficial center line average roughness towards dielectric layer of the first above-mentioned conductive layer and 10 mean roughness are for example less than or equal to 3 μ m.
A kind of wiring board of the another proposition of the present invention, it comprises dielectric substrate, dielectric layer, via and line layer.Dielectric layer is disposed on dielectric substrate.In dielectric layer, contain a plurality of activation particles, and the surface of dielectric layer exposes part activation particle.Via is disposed in dielectric substrate and dielectric layer.Line layer is disposed on the surface of dielectric layer, and is connected with via.
According to the wiring board described in the embodiment of the present invention, the material of above-mentioned activation particle is for example metal complex.
According to the wiring board described in the embodiment of the present invention, above-mentioned line layer comprises the first conductive layer and is positioned at the second conductive layer on the first conductive layer, the first conductive layer is disposed on the surface of dielectric layer, and the thickness of the first conductive layer is for example less than the thickness of the second conductive layer.
According to the wiring board described in the embodiment of the present invention, the surperficial roughness towards dielectric layer of the first above-mentioned conductive layer is for example less than or equal to 3 μ m.
According to the wiring board described in the embodiment of the present invention, the surperficial center line average roughness towards dielectric layer of the first above-mentioned conductive layer and 10 mean roughness are for example less than or equal to 3 μ m.
Based on above-mentioned, in the present invention, the first conductive layer is attached on dielectric layer effectively by the activation particle in dielectric layer, and therefore the first conductive layer can have thinner thickness and roughness and can not peel off from dielectric layer.Thus, the live width of the line layer in the present invention also can reduce further, to meet the demand of high wiring density.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate appended accompanying drawing to be described in detail below.
Accompanying drawing explanation
The making flow process cutaway view that Figure 1A to Fig. 1 E is the wiring board that illustrates according to one embodiment of the invention.
Main element symbol description
10: wiring board
100: dielectric substrate
102: dielectric layer
102a: activation particle
104: surface treatment
106: the first conductive layers
108: via
108a: perforate
110: patterned mask layer
112: the second conductive layers
114: line layer
Embodiment
The making flow process cutaway view that Figure 1A to Fig. 1 E is the wiring board that illustrates according to the embodiment of the present invention.First, please refer to Figure 1A, on dielectric substrate 100, form dielectric layer 102.The material of dielectric substrate 100 is to be for example selected from epoxy resin, the epoxy resin of upgrading, polyester (polyester), acrylate, fluorine element polymer (fluoro-polymer), polyphenylene oxide (polyphenylene oxide), polyimides (polyimide), phenolic resins (phenolicresin), polysulfones (polysulfone), silicon element polymer (silicone polymer), two maleic acid-triazine resins (bismaleimide triazinemodified epoxy, i.e. so-called BT resin), cyanic acid polyester (cyanate ester), polyethylene (polyethylene), polycarbonate resin (polycarbonate, PC), propylene-butadiene-styrene copolymer compound (acrylonitrile-butadiene-styrene copolymer, ABS copolymer), polyethylene terephthalate resin (polyethylene terephthalate, PET), polybutylene terephthalate resin (polybutylene terephthalate, PBT), liquid crystal polymer (liquid crystal polymers, LCP), polyamide 6 (polyamide 6, and PA 6), nylon (Nylon), kematal (polyoxymethylene, POM), polyphenylene sulfide (polyphenylene sulde, PPS), the combination in any of cyclic olefin copolymerized macromolecule (cyclic olefin copolymer, COC) or these materials.The material of dielectric layer 102 is to be for example selected from epoxy resin, the epoxy resin of upgrading, polyester, acrylate, fluorine element polymer, polyphenylene oxide, polyimides, phenolic resins, polysulfones, silicon element polymer, two maleic acid-triazine resins, cyanic acid polyester, polyethylene, polycarbonate resin, propylene-butadiene-styrene copolymer compound, polyethylene terephthalate resin, polybutylene terephthalate resin, liquid crystal polymer, polyamide 6, nylon, kematal, polyphenylene sulfide, the combination in any of cyclic olefin copolymerized macromolecule or these materials.。In addition, in dielectric layer 102, contain activation particle 102a.Activation particle 102a is scattered in dielectric layer 102 equably.The material of activation particle 102a is for example metal complex.For the follow-up metal material being formed on dielectric layer 102, activation particle 102a can improve the adhesive force between dielectric layer 102 and metal material.Specifically, activation particle 102a can be the combination in any of metal oxide, metal nitride, metal misfit thing, metallo-chelate or these compounds.For instance, activation particle 102a is for example aluminium nitride, cupric oxide, titanium nitride, cobalt molybdenum bimetallic nitride (Co
2mo
3n
x) particle or palladium metal particle.
Then, please refer to Figure 1B, surface treatment 104 is carried out in the surface of dielectric layer 102, to expose part activation particle 102a.Surface treatment 104 is for example that plasma surface treatment or chemical solution cleans are processed.In detail, surface treatment 104 can be carried out etching slightly to the surface of dielectric layer 102, so that the surperficial activation particle 102a of adjacent dielectric layers 102 is come out.
Then, please refer to Fig. 1 C, on the surface of dielectric layer 102, form the first conductive layer 106.The material of the first conductive layer 106 is for example copper, silver or aluminium.The formation method of the first conductive layer 106 is for example pressing method, rubbing method or spraying process.Because the surface of dielectric layer 102 exposes activation particle 102a, therefore the first conductive layer 106 can be attached on dielectric layer 102 effectively.Special one carries, and because the first conductive layer 106 can be attached on dielectric layer 102 effectively by activation particle 102a, therefore the first conductive layer 106 can have thinner thickness and lower roughness, is beneficial to the making on fine rule road.The thickness of the first conductive layer 106 is for example between 2 μ m to 5 μ m.In addition, the surperficial roughness towards dielectric layer 102 of the first conductive layer 106 is for example less than or equal to 3 μ m.For example, the surperficial center line average roughness (Ra) towards dielectric layer 102 of the first conductive layer 106 is for example all less than or equal to 3 μ m with 10 mean roughness (Rz).Definition and method for measurement about above-mentioned roughness can be with reference to the contents of the JIS B of Japanese Industrial Standards 0601.
Continue referring to Fig. 1 C, in dielectric substrate 100 and dielectric layer 102, form via 108.The formation method of via 108 is for example first to carry out laser drill manufacture craft, in the first conductive layer 106, dielectric layer 102 and dielectric substrate 100, forms perforate 108a.Then, to electroplate or other modes are inserted electric conducting material in perforate 108a.
Then, please refer to Fig. 1 D, on the first conductive layer 106, form patterned mask layer 110.The material of patterned mask layer 110 is for example photoresist.Patterned mask layer 110 exposes via 108 and part the first conductive layer 106, that is exposes the region of prescribed route.Then on the first conductive layer 106, exposing in patterned mask layer 110 and via 108, form the second conductive layer 112.The material of the second conductive layer 112 is for example copper, silver or aluminium.The formation method of the second conductive layer 112 is for example galvanoplastic.The thickness of the second conductive layer 112 is for example greater than the thickness of the first conductive layer 106.
Afterwards, please refer to Fig. 1 E, remove patterned mask layer 110.Then, remove the first conductive layer 106 of patterned mask layer 110 belows, to complete the making of wiring board 10.In the present embodiment, be for example to remove the first conductive layer 106 in etched mode.After the first conductive layer 106 below removing patterned mask layer 110, the second conductive layer 112 and the first conductive layer 106 that is positioned at its below form the line layer 114 being connected with via 108.
The step of above-mentioned Fig. 1 D to Fig. 1 E is commonly referred to as Improvement type half addition manufacture craft (modified semi-additive process, MSAP).With the formed line layer 114 of MSAP, can there is the live width below 40 μ m, therefore can meet the demand of high wiring density.In addition, in the present embodiment, because the first conductive layer 106 is attached on dielectric layer 102 effectively by the activation particle 102a in dielectric layer 102, therefore the first conductive layer 106 can have compared with thin thickness and can not produce with roughness the problem that the first conductive layer 106 is peeled off from dielectric layer 102, and so the live width of line layer 114 can be reduced to further in the scope of 15 μ m to 25 μ m.In one embodiment, through tensile test, the adhesive force between the first conductive layer 106 and dielectric layer 102 can reach 1kgf/cm
2above.In other words, the reliability of the wiring board 10 of the present embodiment can not reduce because line layer 114 has compared with little live width.
Although disclosed the present invention in conjunction with above embodiment; yet it is not in order to limit the present invention; under any, in technical field, be familiar with this operator; without departing from the spirit and scope of the present invention; can do a little change and retouching, thus protection scope of the present invention should with enclose claim was defined is as the criterion.
Claims (12)
1. a manufacture method for wiring board, comprising:
One dielectric substrate is provided;
On this dielectric substrate, form a dielectric layer, wherein in this dielectric layer, contain a plurality of activation particles;
A surface treatment is carried out in the surface of this dielectric layer, to activate those activation particles that are positioned at this dielectric layer surface;
On the activated surface of this dielectric layer, form one first conductive layer;
In this dielectric substrate and this dielectric layer, form a via;
On this first conductive layer, form a patterned mask layer, this patterned mask layer exposes this via and this first conductive layer of part;
On this first conductive layer exposing in this patterned mask layer and this via, form one second conductive layer; And
Remove this patterned mask layer and this first conductive layer that is positioned at this patterned mask layer below.
2. the manufacture method of wiring board as claimed in claim 1, wherein materials of those activation particles comprise metal complex.
3. the manufacture method of wiring board as claimed in claim 1, wherein this surface treatment comprises that plasma surface treatment or chemical solution cleans process.
4. the manufacture method of wiring board as claimed in claim 1, wherein the formation method of this first conductive layer comprises pressing method, rubbing method or spraying process.
5. the manufacture method of wiring board as claimed in claim 1, wherein the thickness of this first conductive layer is less than the thickness of this second conductive layer.
6. the manufacture method of wiring board as claimed in claim 1, wherein this surperficial roughness towards this dielectric layer of this first conductive layer is less than or equal to 3 μ m.
7. the manufacture method of wiring board as claimed in claim 5, wherein this surperficial center line average roughness towards this dielectric layer of this first conductive layer and 10 mean roughness are less than or equal to 3 μ m.
8. a wiring board, comprising:
Dielectric substrate;
Dielectric layer, is disposed on this dielectric substrate, contains a plurality of activation particles in this dielectric layer, and a surface of this dielectric layer exposes those activation particles of part;
Via, is disposed in this dielectric substrate and this dielectric layer; And
Line layer, is disposed on this surface of this dielectric layer, and is connected with this via.
9. wiring board as claimed in claim 8, wherein materials of those activation particles comprise metal complex.
10. wiring board as claimed in claim 8, wherein this line layer comprises the first conductive layer and is positioned at the second conductive layer on this first conductive layer, this first conductive layer is disposed on this surface of this dielectric layer, and the thickness of this first conductive layer is less than the thickness of this second conductive layer.
11. wiring boards as claimed in claim 10, wherein this surperficial roughness towards this dielectric layer of this first conductive layer is less than or equal to 3 μ m.
12. wiring boards as claimed in claim 11, wherein this surperficial center line average roughness towards this dielectric layer of this first conductive layer and 10 mean roughness are less than or equal to 3 μ m.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210208348.0A CN103517568B (en) | 2012-06-19 | 2012-06-19 | Wiring board and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210208348.0A CN103517568B (en) | 2012-06-19 | 2012-06-19 | Wiring board and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103517568A true CN103517568A (en) | 2014-01-15 |
| CN103517568B CN103517568B (en) | 2016-12-21 |
Family
ID=49899325
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210208348.0A Active CN103517568B (en) | 2012-06-19 | 2012-06-19 | Wiring board and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103517568B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5869899A (en) * | 1996-03-18 | 1999-02-09 | Motorola, Inc. | High density interconnect substrate and method of manufacturing same |
| CN1799293A (en) * | 2003-06-05 | 2006-07-05 | 詹诺普蒂克自动化技术有限公司 | Method for the structured metal-coating of polymeric and ceramic support materials, and compound that can be activated and is used in said method |
| US20090309202A1 (en) * | 2008-06-13 | 2009-12-17 | Phoenix Precision Technology Corporation | Package substrate having embedded semiconductor chip and fabrication method thereof |
| TW201023701A (en) * | 2008-12-08 | 2010-06-16 | Unimicron Technology Corp | Wiring board and fabrication process thereof |
-
2012
- 2012-06-19 CN CN201210208348.0A patent/CN103517568B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5869899A (en) * | 1996-03-18 | 1999-02-09 | Motorola, Inc. | High density interconnect substrate and method of manufacturing same |
| CN1799293A (en) * | 2003-06-05 | 2006-07-05 | 詹诺普蒂克自动化技术有限公司 | Method for the structured metal-coating of polymeric and ceramic support materials, and compound that can be activated and is used in said method |
| US20090309202A1 (en) * | 2008-06-13 | 2009-12-17 | Phoenix Precision Technology Corporation | Package substrate having embedded semiconductor chip and fabrication method thereof |
| TW201023701A (en) * | 2008-12-08 | 2010-06-16 | Unimicron Technology Corp | Wiring board and fabrication process thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103517568B (en) | 2016-12-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10993331B2 (en) | High-speed interconnects for printed circuit boards | |
| JP5117455B2 (en) | Method for forming a conductive pattern on a composite structure | |
| US20060060558A1 (en) | Method of fabricating package substrate using electroless nickel plating | |
| US9572250B2 (en) | Printed circuit board and method for manufacturing the same | |
| US8574444B2 (en) | Fabricating method for multilayer printed circuit board | |
| US8365401B2 (en) | Circuit board and manufacturing method thereof | |
| US10134666B2 (en) | Package substrate, method for fabricating the same, and package device including the package substrate | |
| US20150342062A1 (en) | Semi-Finished Product for the Production of a Printed Circuit Board, Method for Producing a Printed Circuit Board and Printed Circuit Board | |
| CN110402020B (en) | Flexible printed circuit board and manufacturing method thereof | |
| TW201347628A (en) | Printed circuit board having embedded capacitor and method of manufacturing the same | |
| US8963019B2 (en) | Manufacturing method of circuit board | |
| CN104902696A (en) | Method of manufacturing copper column on printed circuit board based on wire embedding structure | |
| KR101896555B1 (en) | Printed circuit board and manufacturing method for printed circuit board | |
| US20100051329A1 (en) | Printed circuit board and method of manufacturing the same | |
| US20120124830A1 (en) | Process for fabricating circuit board | |
| CN108156763B (en) | Transparent circuit board and manufacturing method thereof | |
| US9549465B2 (en) | Printed circuit board and method of manufacturing the same | |
| CN102111964A (en) | Method for manufacturing circuit board | |
| TWI494037B (en) | Wiring bord and method for fabricating the same | |
| CN103517568A (en) | Circuit board and its manufacturing method | |
| CN110876239B (en) | Circuit board and manufacturing method thereof | |
| KR101555014B1 (en) | Printed circuit board for forming fine wiring and method for manufacturing the same | |
| CN111343802B (en) | Circuit board and manufacturing method thereof | |
| JP2013162007A (en) | Production method of fine wiring pattern | |
| US20120160556A1 (en) | Circuit board and method of manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |