TW201021137A - Semiconductor process, and silicon substrtae and chip package strucutre applying the same - Google Patents

Abstract

A semiconductor process is provided. First, a silicon substrate is provided. Next, a surface of the silicon substrate is exposed in part and at least a stair-structure is formed on the silicon substrate by etching the surface of the silicon substrate. The stair-structure has a first notch with a first depth and a second notch with a second depth, wherein the first depth is smaller than the second depth, and the diameter of the first notch is larger than that of the second notch. A final insulating layer and a metal seed layer are formed on the stair-structure in order. A patterned photoresist layer is formed on the metal seed layer. A circuit layer coving the exposed portion of the metal seed layer located above the first notch is formed. Finally, the patterned photoresist layer and the portion of the metal seed layer below the patterned photoresist layer are removed.

Description

B/50twf.doc/n 201021137 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體製程，且特別是有關於一 種應用此半導體製程所形成之矽基板及晶片封裝結構。 【先前技術】 現今半導體科技發達’積體電路晶片（IC chip)具有 大里且南聲度排列的電晶體( transistor )及許多配置在晶 片表面的訊號接墊（pad)。為了能封裝這些晶片，這些晶 片通常安裝在一晶片封裝載板上，以形成一晶片封襞（chip package)結構，其中晶片可藉由封裝製程來獲得足夠的訊 號路徑、散熱路徑及結構保護。 目Η，隨著封裝脑销的改良，各式晶#封裝結構 不斷地推陳出新，例如：晶片黏著至晶片墊或導線架（_ 之内引腳上，以形成薄型小尺寸縣（Ts〇p)體， 至印刷電路板上，以形成球狀栅格陣列 以薄型小尺寸封裝（TS〇p)結構而言， 晶片墊或導線架之内引腳上，且此 :片黏者至 結構的侧邊具衫細崎外t 、封裝（TS0P) 此外U腳異*认电注運接的外引腳。由於這 ς卜引腳暴路於封袭膠體之外， 界環境的辟，或㈣㈣度丨腳易叉到外 號的傳遞。 、负而易折岍，進而影響訊 以球格陣列式（bga) 丁戒、、。構而^，常見以有機基 201021137/50twfd〇c/n ，晶片之承載器（carrier)，而晶片配置於承載器之後， 晶片之電子訊號可藉由承載器之内部線路而向下繞線 (_tmg )至承載器之底面，最後經由承載器之銲球（solder ball)而傳遞至外界的電子裝置。由於銲球是以面陣列的 方式形成於承载器之底面，因此一直是高腳位（ffigh pin count)半導體元件f用的封裝結構。然而，球格陣列式 jBGA)封裝結構整體的高度約為1.0〜1.4mm，無法達到 薄型化（低於〇.5mm)之需求。 【發明内容】 本發明提供一種半導體製程，用以製作一矽基板來作 為打線接合之晶片的承載器。 本發明提供-财基板，㈣作為打線接合之晶片的 承載器。 本發明提供一種晶片封裝結構，具有較薄之封裝厚 W 度。 本發明長：出一種半導體製程。首先，提供一石夕美好。 接著，局部暴露矽基材的一表面，並蝕刻矽基材的此1面， 以使矽基材形成有至少一階梯狀結構。階梯狀結構具有— 第一深度的一第一凹口以及〜第二深度的一第二凹口，其 中第一深度小於第二深度，且第一凹口的孔徑大於第二凹 口的孔徑。形成一最終絕緣層於階梯狀結構。形成一金屬 種子層於最終絕緣層上。形成一圖案化光阻層於金屬種子 6 ^/50twf.doc/n 201021137 化ί阻：!覆蓋於預定形成-線路層-之外的 層。再形成線if預定形成線路層的部份金屬種子 案化光阻屬種子層上。移除圖 • 層。 口茱化先阻層底下之部份金屬種子 驟，3:月，—實施例中’上述之形成階梯狀結構的步 ΐ-第—絕緣層於蝴上。接著，形成- ❹.幕為蝕列ϋ幕於絕緣層。以第-圖案化光阻罩 -絕二，，暴露於第—圖案化光阻罩幕之外的第 芦為二除ΐ—圖案化光阻罩幕。以圖案化第一絕緣 圖案化第-絕緣層的_， π成一第二絕緣層於第-凹口，其中第二絕:層覆: ^凹"。形成—第二_化光阻罩幕於第二絕緣層上。 化光罩幕，侧祕於第二圖案 _ 綦之卜的第一{緣層。移除第二圖案化光阻罩 ^=圖案化第二絕緣層為侧罩幕，爛暴露於圖案化 =、、€緣層⑽基材，以於絲材上形成第二深度的第二 之後’移除第一絕緣層，而形成階梯狀結構。 括氧===實施例中，上述之第—絕緣層的材質包 括氧實施例中’上述之第二糊的材質包 金 在本發明之一實施例中，上述之線路層包括一第一 7 5 /50twf.doc/n 201021137 屬層與-第二金屬層。-第一金屬層覆蓋顯露於第 方的部份金屬種子層上。第二金屬層覆蓋第一金屬層。 在本發明之-實施财，上述之第—金^ 層，第二金屬層為一金層。 、、鎳 在本^月之-實施例中，上述之移除圖案化光阻 及位於圖案化光阻層底下之部份金屬種子層之後的步ς， 百先，放置至少一晶片於第二凹口内，其中晶片的上 低於位於第一凹口内的線路層的第二金屬層。接著’進— =打線接合製程’使晶片透過純導線連接至線路層的$ 二金屬層上。填人-封歸體於階梯狀結構，其中 體包覆最，絕緣層、線路層、該金屬種子層、晶片及二 導線。接著，薄化部份封裝膠體與部份線路層，以& 膠體與第-金屬層實質上切齊。之後，薄化絲材及晶^ 以暴露出晶片的下表面。最後，形成至少一金屬接塾 路層的第一金屬層上。 上述之金屬接墊的材質包括 上述之最終絕緣層的材質包 上述之形成金屬種子層的方 在本發明之一實施例中 ❷ 金。 在本發明之一實施例中 括氧化矽。 在本發明之一實施例中 法包括物理氣相沉積。 在本發明之一實施例中，上述之金屬種子層為一則 複合層。 本發明提出一種以上述之半導體製程所形成的矽運 201021137j<50twfdoc/n 板，其中最終絕緣層覆蓋階梯狀結構，線路層覆蓋第—凹 口上方的部份導電層，且第二凹口用以放置—晶片。 f本發明之-實施例中，上述之晶片透過多條 電性連接至線路層。 本發明提出-種晶片封裝結構，其包括—石夕基材、一 ，緣層、-金屬種子層、—線路層、—晶片、—封装膠體B/50twf.doc/n 201021137 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor process, and more particularly to a germanium substrate and a chip package structure formed by the application of the semiconductor process. [Prior Art] Today's semiconductor technology developed IC chip has a large and south-aligned transistor and a number of signal pads disposed on the surface of the wafer. In order to package these wafers, the wafers are typically mounted on a wafer package carrier to form a chip package structure in which the wafer can be packaged to obtain sufficient signal path, thermal path and structural protection. It is witnessed that with the improvement of the package brain pin, various types of package structure are constantly being introduced, for example, the wafer is adhered to the wafer pad or the lead frame (in the pin of _ to form a thin small-sized county (Ts〇p). Body, onto the printed circuit board, to form a spherical grid array in a thin small package (TS〇p) structure, on the inner pad of the wafer pad or lead frame, and this: the sheet sticks to the side of the structure The outer side of the outer shirt, the package (TS0P), and the outer pin of the U-pin, which is the same as the external pin. Because the pin is violently in the outer layer of the sealant, the boundary of the environment, or (4) (four) degree 丨The foot is easy to fork to the transmission of the nickname. It is negative and easy to fold, which in turn affects the ball grid array (bga), and the structure is common. The organic base 201021137/50twfd〇c/n, the wafer After the carrier is placed on the carrier, the electronic signal of the chip can be wound down (_tmg) to the bottom surface of the carrier by the internal line of the carrier, and finally the solder ball through the carrier (solder ball) And the electronic device that is transmitted to the outside world. Since the solder balls are formed in a planar array The bottom surface of the carrier is always a package structure for the ffigh pin count semiconductor device f. However, the overall height of the ball grid array jBGA package structure is about 1.0 to 1.4 mm, which cannot be thinned (low Yu Yu. 5mm) demand. SUMMARY OF THE INVENTION The present invention provides a semiconductor process for fabricating a substrate as a carrier for wire bonding wafers. The present invention provides a financial substrate, and (4) a carrier for wire bonding. The present invention provides a wafer package structure having a thin package thickness W. The invention is long: a semiconductor process. First of all, provide a good night. Next, a surface of the tantalum substrate is partially exposed, and the one side of the tantalum substrate is etched so that the tantalum substrate is formed with at least one stepped structure. The stepped structure has a first recess of a first depth and a second recess of a second depth, wherein the first depth is less than the second depth and the aperture of the first recess is greater than the aperture of the second recess. A final insulating layer is formed in the stepped structure. A metal seed layer is formed on the final insulating layer. A patterned photoresist layer is formed on the metal seed 6 ^ / 50 twf.doc / n 201021137 :: covering the layer outside the predetermined formation - circuit layer -. A portion of the metal seed, which is intended to form a wiring layer, is formed on the seed layer. Remove the layer • layer. A portion of the metal seed underneath the first resist layer, 3: month, in the embodiment, the step-first insulating layer forming the stepped structure is on the butterfly. Next, the - ❹. curtain is etched into the insulating layer. In the first-patterned photoresist mask - the second, the second reed that is exposed outside the first patterned photoresist mask is a two-defective-patterned photoresist mask. Patterning the first insulating pattern of the first insulating layer _, π into a second insulating layer in the first-notch, wherein the second: layer: ^ concave ". Forming a second etched photoresist mask on the second insulating layer. The mask is smudged to the side of the second pattern _ 綦 卜 的 的 第一 第一 第一 第一 第一 第一. Removing the second patterned photoresist mask ^=patterning the second insulating layer as a side mask, rottenly exposed to the patterned layer, and the edge layer (10) substrate to form a second depth on the wire after the second 'The first insulating layer is removed to form a stepped structure. Oxygen === In the embodiment, the material of the first insulating layer includes the material of the second paste in the oxygen embodiment. In one embodiment of the present invention, the circuit layer includes a first 7 5 /50twf.doc/n 201021137 Dependent layer and - second metal layer. - The first metal layer covers a portion of the metal seed layer that is exposed on the first side. The second metal layer covers the first metal layer. In the present invention, the second metal layer is a gold layer. In the embodiment of the present invention, the step of removing the patterned photoresist and the portion of the metal seed layer under the patterned photoresist layer is as described above, and at least one wafer is placed in the second step. Within the recess, wherein the upper surface of the wafer is lower than the second metal layer of the wiring layer located within the first recess. Next, the 'in--wire bonding process' causes the wafer to be connected to the $2 metal layer of the wiring layer through a pure wire. The filling-sealing body is in a stepped structure in which the body is covered most, the insulating layer, the wiring layer, the metal seed layer, the wafer, and the two wires. Next, a portion of the encapsulant and a portion of the wiring layer are thinned, and the & colloid is substantially aligned with the first metal layer. Thereafter, the wire and the crystal are thinned to expose the lower surface of the wafer. Finally, a first metal layer of at least one metal interface layer is formed. The material of the metal pad described above includes the material of the final insulating layer described above, and the metal seed layer is formed as described above. In one embodiment of the invention, the metal is used. In one embodiment of the invention, ruthenium oxide is included. In one embodiment of the invention the method comprises physical vapor deposition. In an embodiment of the invention, the metal seed layer is a composite layer. The invention provides a 2010201021137j<50 twfdoc/n board formed by the above semiconductor process, wherein the final insulating layer covers the stepped structure, the circuit layer covers a part of the conductive layer above the first recess, and the second recess is used To place the wafer. In the embodiment of the invention, the wafer is electrically connected to the wiring layer through a plurality of wires. The invention provides a chip package structure, which comprises: a stone substrate, a layer, a metal seed layer, a circuit layer, a wafer, a package colloid

金屬触。⑦基材具有—階梯狀結構1梯狀結 構八有一弟一深度的一第一凹口以及一第二深度的一第二 2:其中第―深度小於第二深度，且第—凹口的孔徑大 '—凹口的孔徑。絕緣層配置於矽基材上且覆蓋第一Metal touch. 7 substrate has a stepped structure 1 ladder structure eight has a first depth of a first recess and a second depth of a second 2: wherein the first depth is less than the second depth, and the aperture of the first recess Large '-nozzle aperture. The insulating layer is disposed on the germanium substrate and covers the first

二1二凹D。金屬種子層覆蓋位於第_凹。上二J i於Ϊ路層覆蓋位於第一凹口上方的金屬種子層。晶片配 节、；1 —凹口内’其中晶片的上表面低於線路層，且晶片 ，夕條導線與祕層雜連接。封裝賴包覆絕緣層、 战-種子層、線路層、晶片以及這些導線，其中封裝膠體 二線路層實質上切齊^金屬接墊配置於線路層上，並顯露 於封裝膠體外。 •’ 化石夕在本發明之一實施例中’上述之絕緣層的材質包括氧 複合ί本發明之—實施例中上述之金4種子層為一飲錄 在本發明之一實施例中，上述之線路層包括一第一金 與-第二金屬層’第—金屬層覆蓋金屬種子層，而第 …屬層覆蓋該第―金屬層。上述之第—金屬層為一鎳 /50twf.doc/n 201021137 * 層，第一金屬層為一金層。 在本發明之一實施例中，上述之金屬接墊的材質包括 金。 絲上所述，本發明之半導體製程所形成之矽基板，其 具有一階梯狀結構，因此當晶片放入階梯狀結構之第二凹 口内，且經由打線接合製程與矽基板電性連接，並以封裝 膠體將晶片加以包覆，以形成晶片封裝結構後，再薄化石夕 H 基材及晶片，如此晶片封裝結構具有較薄之封裝厚度。 *為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉實施例’並配合所附圖式作詳細說明如下。 【實施方式】 圖1 A至圖1P為本發明之—實施例之一種半導體製 ^剖面示意圖。就參考圖1A，_本實施例的半導體 衣程’首S，提供-梦基材11G，其切基材nG上形成Two one two concave D. The metal seed layer is covered in the first recess. The upper two J i covers the metal seed layer above the first recess in the layer of the road. The wafer is flanked, and the inner surface of the wafer is lower than the circuit layer, and the wafer, the spur wire is connected to the secret layer. The package is covered with an insulating layer, a war-seed layer, a circuit layer, a wafer, and the wires, wherein the encapsulating colloid two circuit layers are substantially aligned and the metal pads are disposed on the circuit layer and exposed outside the encapsulant. • 'In addition to the embodiment of the present invention, the material of the insulating layer described above includes an oxygen compound. The gold 4 seed layer described above in the embodiment is one of the embodiments of the present invention. The circuit layer includes a first gold and a second metal layer 'the first metal layer covers the metal seed layer, and the first layer covers the first metal layer. The first metal layer is a nickel/50twf.doc/n 201021137* layer, and the first metal layer is a gold layer. In an embodiment of the invention, the material of the metal pad comprises gold. As described above, the germanium substrate formed by the semiconductor process of the present invention has a stepped structure, so that when the wafer is placed in the second recess of the stepped structure, and electrically connected to the germanium substrate via the wire bonding process, After the wafer is coated with the encapsulant to form the wafer package structure, the substrate and the wafer are thinned, and the chip package structure has a thin package thickness. The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the appended claims. [Embodiment] Figs. 1A to 1P are schematic cross-sectional views showing a semiconductor device according to an embodiment of the present invention. Referring to Fig. 1A, the semiconductor package "head S of the present embodiment" provides a dream substrate 11G which is formed on the cut substrate nG.

:第-絕緣層12〇。在本實施例中，第—絕緣層m的材 質包括氧化矽及氮化矽。 請參考圖1B，接著，於第一絕緣層12〇形成一第一 圖案化光阻罩幕130a。接著，於矽基材11〇上形 請參考圖1L)。詳細而言’形成階梯狀 構14〇的步驟如下，請同時參考圖1C與圖1D，首先， 以第一圖案化光阻罩幕13仙為蝕刻罩幕， ， 圖案化光阻卿a之外的第一絕緣層12〇，=^ 案化第一絕緣層120a。接著，移除第—圖案化光阻罩幕 201021137.50twf,oc/n l3〇a’以暴露出第一圖案化光阻罩幕丨 -絕緣们施。請參考圖1E，接著，以圖案化 幕’侧暴露於圖案化第-絕緣層120a 之外的魏材11G，崎魏材UG上形成至少— 第-深度di的第-凹σ 142(圖m僅示意地繪示二個 本實施般_濕絲_料，透聽減_ (κ 為姓刻液，侧暴露於第-絕緣層⑽底下的錄材ιι〇。: The first insulating layer 12 〇. In the present embodiment, the material of the first insulating layer m includes hafnium oxide and tantalum nitride. Referring to FIG. 1B, a first patterned photoresist mask 130a is formed on the first insulating layer 12''. Next, refer to Fig. 1L) on the substrate 11〇. In detail, the steps of forming the stepped structure 14 are as follows. Please refer to FIG. 1C and FIG. 1D at the same time. First, the first patterned photoresist mask 13 is used as an etching mask, and the patterned photoresist is used. The first insulating layer 12 is 〇, and the first insulating layer 120a is formed. Next, the first patterned photoresist mask 201021137.50twf, oc/n l3〇a' is removed to expose the first patterned photoresist mask 绝缘-insulation. Referring to FIG. 1E, next, the first concave σ 142 of at least the first-depth di is formed on the Wei material 11G, which is exposed on the side of the patterned screen-insulation layer 120a. Only two embodiments of the present invention are shown in the figure: the κ is the surname engraving, and the side is exposed to the recording material ιι 底 under the first insulating layer (10).

明參考圖1F ’接著’移除第—絕緣層12()，以暴露出 石夕基材110。請參考圖1G，接著，形成—第二絕緣層⑽ 於這些第-凹π M2’其中第二絕緣層15〇覆蓋這些第一 凹口 142。在本實施例巾，第二絕緣層15()的材質與第一 絕緣層120的材質實質上相同，例如是氛化石夕或氧化石夕， 且第二絕緣層15G的形成方式與第—絕緣層⑽的形成方 式實質上相同。 —s月參相1H’接著’形成—第二圖案化光阻罩幕13仙 於第二絕緣層150上。請同時參考圖u與圖1：F，首先，以 第二圖案化光阻罩幕13Gb為银刻罩幕’侧暴露於第二圖 案，光阻罩幕130b之外的第二絕緣層15〇，以形成一圖案 化第二絕緣層l50a。接著，移除第二圖案化光阻罩幕 l3〇b，以暴露第二圖案化光阻罩幕底下關案化第二 絕緣層150a。請同時參考圖1K與圖1L，，接著，以圖案 化第二絕緣層15Ga為侧罩幕，_暴露於圖案化第二絕 緣層150a之外的矽基材110,以於矽基材n〇上形成至少 —具有一第二深度d2的第二凹口 144 (圖1K僅示意地繪 11 /50twf.doc/n 201021137 示二個）。接著’移除爾案化第二絕緣層150a，而形成階 梯狀結構。 詳細而言’在本實施例中’這些第二凹口 144分別連 通於這些第一凹口 142,且第一深度（11小於第二深度d2， 這些第一凹口 142的孔徑分別大於這些第二凹口 144的孔 徑。也就是說’這些第二凹口 144相較於這些第一凹口 142 具有較小的孔徑與較大的深度。在本實施例中，蝕刻暴露 於第二圖案化光阻罩幕130b之外的第二絕緣層150及第二 絕緣層150底下的石夕基材ho的方式與圖lc與圖戊之麵 刻暴露於第一圖案化光阻罩幕130a之外的第一絕緣層12〇 與第一絕緣層120底下的矽基材11〇的方式相同，皆是採 用濕式蝕刻的方式並以氫氧化鉀（K〇H)為蝕刻液。 請再參考圖1L，在本實施例中，移除第二絕緣層15〇 而形成至少一階梯狀結構140(圖1Lf僅是繪示兩;）， 其中移除第一絕緣層12〇及第二絕緣層15〇的方法例如是 ❹ 濕式钱刻製矛呈。至此’以於石夕基材11〇上完成這些階梯狀 結構14 0。 請參考圖1M，接著，形成一最終絕緣層16〇於這此 P皆梯狀結構14G上，其巾最終絕緣層⑽覆蓋這些第一= 口 142與這些第二凹口 144’以達成石夕基材11〇絕緣之目 的三在本實施例中，最終絕緣層160的材質包括氧化矽， 且最終絕緣層160的形成方式例如是加熱矽基材ιι〇， 使砍基材110的表面產生氧化’ &氧化的部 終絕緣層160。 厅明的最 12 201021137 '50twf.ii〇c/n 請參考圖IN，接菩，κ 士、 絕緣層廳上。在本屬種子層170於最終 仕尽貫施例中，金屬種子声n 鈦鎳（Ti/Ni)複合層，且來成曰170例如疋一 麟法或物喊相沉積。7、’ “7()的方法包括 睛參考圖10，接著，报# 屬種子層m 絲·層180於金 , 、圖案化光阻層180覆蓋在預定取士 ❹ 一線路層190之外的部份金屬種子只17〇上，^巧成 形成線路層190的部份金屬 曰 、顯路預定 190包括-第-金屬層192與—第二金屬# 194U=層 例中’第一金屬層192例如是一鋅_在本實把 194例如是一金（Αϊ〇層。_(Nl)層’弟二金屬層 明參考圖1Ρ，之後，移除圖案 180 位於堤些弟二凹口 144 Ϊ· 士 AA时八FI 暴路出 實施例中，移除ί的部份最終絕緣層160。在本 ===子層17。的方式』 完成:絲=:二由半導體製程而於伽⑴上 於簡Γ之’本實施例之石夕基板100是採用半導製程來制 作’以第-_化総轉13Ga及第 ^末製 ^ _罩幕’形成對發基材i i G進行餘刻製程:= 弟—絕緣層120與圖案化第二絕緣層150,藉由圖案化 13 201021137, 750twf.doc/n 第一絕緣層120與圖案化第二絕緣層150為蝕刻罩幕，以 形成這些具有第一深度dl之這些第一凹口 142與第二深度 d2之這些第二凹口 144的階梯狀結構140，之後，再形成 最終絕緣層160、金屬種子層170、及線路層190於矽基材 110上，以構成具有這些階梯狀結構140的矽基板1〇〇。 此外’由於本實施例所形成之這些階梯狀結構140, 其這些第一凹口 142的第一深度dl小於這些第二凹口 144 的第二深度d2’因此當矽基板1〇〇作為打線接合之晶片（未 繪示）的承載器時，可運用這些階梯狀結構14〇的這些第 二凹口 144的空間來放置多個晶片，且這些晶片可透過打 線接合製程與位於這些第一凹口 142内之線路層190電性 連接’可細小體積並可縮短碎基板1〇〇與這些晶片之間的 打線接合距離。 圖2A至圖2G為圖1P之半導體製程所形成之矽基板 對一晶片進行封裝製程的剖面示意圖。圖2H為圖2G之晶 片封裝結構的俯視示意圖。在此必須說明的是，為了方便 說明起見，圖2H省略部份結構。在本實施例中，半導體 製程所形成之碎基板1〇〇適於承載一晶片21〇。 詳細而言，在石夕基板1〇〇的後續製程中，請參考圖 2A，首先，放置至少一晶片21〇 (圖2A中僅示意地續；示 二個）於階梯狀結構140之這些第二凹口 144内，其中這 些晶片210的上表面210a分別低於這些位於第一凹口 142 内之線路層190的第二金屬層194。 明參考圖2B，接著，進行一打線接合製程，使這些 201021137 50twfH 7 > / 50twf.doc/n 晶片210透過多條導線22〇連接至線路層19〇的第二 層194上。也就是說，在本實施例中，這些晶片。八 別透過這些導線220而與線路層19〇的第二金 : 性連接。 ⑺4電 請參考圖2c ’接著’填入—封歸體2sg 結構140 ’其中封裝膠體23()包覆線路層19〇、金屬種 170、最終絕緣層160、晶片21〇及這些導線22〇。請參^ m 圖2D，接著，薄化部份封I膠體230與部份線路層， 以使封裴膠體230與第一金屬層192實質上切齊。在本 施例中’薄化封裝膠體230與線路層190的方法包括研磨。 請參考圖2E’接著，薄化矽基材n〇的背面，以暴露 出這些晶片210的下表面鳩，以達成封褒體薄型化需 求，其中薄化矽基材11〇的方法包括研磨或蝕刻製程。請 參考圖2F，接著，形成至少一金屬接墊24〇 (圖2F僅^ 意地繪示四個）於線路層190的第一金屬層192上，並顯 魯 露於封裝膠體230外，其中形成這些金屬接墊24〇的方‘式 例如是無電電鍍法（electr〇lessplating)。在本實施例中， 每一金屬接墊240的厚度約為〇j微米（#1)。請同時 參考圖2G與圖2H，之後，進行一切割程序，藉由切割刀 具沿著預定路徑將矽基板100切割而分離，以形成多個各 自獨立的晶片封裝結構200 (圖2G僅示意地續·示二個）。 簡言之，由於本實施例晶片封裝結構2〇〇的製程，其 藉由半導體製程所形成之矽基板1〇〇作為這些晶片21〇 ^ 承載益，且這些晶片210分別藉由打線接合的方式電性連 15 /JOtwf.doc/n 201021137 上之雜層190 ’並經由填膠製程將這此 阳片210禮封於封裝膠體23〇中，以構成這些 二 ^⑽是分職置料細梯狀結^ =所形狀這些晶片封裝結構，具有較薄之封^ ❹ 馨 綜上所述，本發明之半導體製程所形成之矽基板，发 階禅狀結構之第—凹讀第—深度小於第二凹口的第二^ 度，且第一凹口的孔徑大於第二凹口的孔徑，所以當將曰曰 =„合製程與矽基板電性連接以形成晶片：裝： 守精矽基材與晶片背面同時作研磨， 二=晶片封裝結構能具有較薄之封裝厚度：化: 發明忐有效縮減封裝厚度。 本翻已以實施_露如上，财並賴以限定 太^明何所屬技術領域巾具有通常知識者，在不脫離 砷和範圍内’當可作些許之更動與潤飾，故本 χ 保濩乾圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 1 Α至圖1Ρ為本發明之一實施例之一種半導體製 私的剖面示意圖。 一曰，2Α至圖2G為圖1]?半導體製程所形成之矽基板對 一日曰片進行封裝製程的剖面示意圖。 圖2Η為圖2G之晶片封裝結構的俯視示意圖。 16 201021137/50twfdoc/n 【主要元伴’符號說明】 100 :矽基板 110 :矽基材 120:第一絕緣層 120a ··圖案化第一絕緣層Referring to Figure 1F', then the first insulating layer 12() is removed to expose the stone substrate 110. Referring to FIG. 1G, next, a second insulating layer (10) is formed over the first recess π M2' wherein the second insulating layer 15 〇 covers the first recesses 142. In the towel of the embodiment, the material of the second insulating layer 15 () is substantially the same as the material of the first insulating layer 120, such as a fossilized or oxidized stone, and the second insulating layer 15G is formed and insulated. The formation of layer (10) is substantially the same. The s month phase 1H' is then formed - the second patterned photoresist mask 13 is on the second insulating layer 150. Referring to FIG. 9 and FIG. 1 : F, first, the second patterned photoresist mask 13Gb is exposed to the second pattern on the side of the silver mask, and the second insulating layer 15 outside the photoresist mask 130b To form a patterned second insulating layer 150a. Next, the second patterned photoresist mask l3〇b is removed to expose the second insulating layer 150a under the second patterned photoresist mask. Referring to FIG. 1K and FIG. 1L at the same time, then, the second insulating layer 15Ga is patterned as a side mask, and the germanium substrate 110 is exposed outside the patterned second insulating layer 150a, so as to be the germanium substrate. A second recess 144 having at least a second depth d2 is formed thereon (Fig. 1K only schematically shows 11 / 50 twf. doc / n 201021137 shows two). Next, the second insulating layer 150a is removed to form a stepped structure. In detail, in the present embodiment, the second notches 144 are respectively connected to the first notches 142, and the first depth (11 is smaller than the second depth d2, and the apertures of the first notches 142 are larger than these The apertures of the two recesses 144. That is, the second recesses 144 have a smaller aperture and a greater depth than the first recesses 142. In this embodiment, the etching is exposed to the second patterning. The second insulating layer 150 outside the photoresist mask 130b and the manner of the base substrate ho under the second insulating layer 150 are exposed to the surface of the first patterned photoresist mask 130a. The first insulating layer 12 is the same as the underlying substrate 11 底 under the first insulating layer 120, and is formed by wet etching and using potassium hydroxide (K〇H) as an etching solution. 1L, in the embodiment, the second insulating layer 15 is removed to form at least one stepped structure 140 (only two are shown in FIG. 1Lf), wherein the first insulating layer 12 and the second insulating layer 15 are removed. The method of sputum is, for example, ❹ 式 钱 刻 刻 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Stepped structure 140. Referring to FIG. 1M, a final insulating layer 16 is formed on the P-shaped ladder structure 14G, and the final insulating layer (10) of the towel covers the first and second openings 142 and the second notches. 144' is to achieve the purpose of the 11th insulation of the stone substrate. In the embodiment, the material of the final insulation layer 160 includes ruthenium oxide, and the final insulation layer 160 is formed by, for example, heating the substrate ιι 〇 The surface of the material 110 is oxidized and the oxidized portion of the final insulating layer 160. The most 12 of the halls of the Ming Dynasty 201021137 '50twf.ii〇c/n Please refer to Figure IN, connect the Bodhisattva, Kappa, and the insulation hall. The seed layer 170 is in the final application example, the metal seed acoustic n-titanium-nickel (Ti/Ni) composite layer, and is deposited into a 曰 170, for example, a 麟 麟 或 method or a material shouting phase. 7, '7 () The method includes the method of referring to FIG. 10, and then, the seed layer m of the seed layer is deposited on the gold, and the patterned photoresist layer 180 covers only a portion of the metal seed outside the predetermined layer 190. , a portion of the metal ruthenium forming the circuit layer 190, the 190 road includes a --metal layer 192 and a second属# 194U=In the layer case, the first metal layer 192 is, for example, a zinc _ in the actual case 194, for example, a gold (Αϊ〇 layer. _(Nl) layer 'di two metal layer is shown in Fig. 1 Ρ, after that, In addition to the pattern 180 located in the embankment two dimples 144 Ϊ 士 AA, the eight FI violent out of the embodiment, remove the ί part of the final insulating layer 160. In this === sub-layer 17. The way to complete: Wire =: two by the semiconductor process and gamma (1) on the simple one 'the Shishi substrate 100 of the present embodiment is made by a semi-conductive process' to the first - _ turn 13 13Ga and the first ^ ^ _ mask 'Formation of the base substrate ii G for the engraving process: = brother - insulating layer 120 and patterned second insulating layer 150, by patterning 13 201021137, 750twf.doc / n first insulating layer 120 and patterned second The insulating layer 150 is an etching mask to form the stepped structures 140 of the second recesses 144 having the first recesses 142 and the second depth d2 of the first depth dl, and then forming the final insulating layer 160, The metal seed layer 170 and the wiring layer 190 are on the tantalum substrate 110 to constitute a tantalum substrate 1 having these stepped structures 140. In addition, due to the stepped structures 140 formed in this embodiment, the first depth dl of the first notches 142 is smaller than the second depth d2' of the second notches 144. Therefore, when the substrate 1 is bonded as a wire bonding When the carrier of the wafer (not shown) is used, the space of the second recesses 144 of the stepped structures 14 可 can be used to place a plurality of wafers, and the wafers can be through the wire bonding process and located in the first notches. The wiring layer 190 in 142 is electrically connected to 'small volume and can shorten the wire bonding distance between the chip substrate 1 and the wafers. 2A to 2G are schematic cross-sectional views showing a process of packaging a wafer by a germanium substrate formed by the semiconductor process of FIG. 1P. 2H is a top plan view of the wafer package structure of FIG. 2G. It must be noted here that, for convenience of explanation, a part of the structure is omitted in Fig. 2H. In the present embodiment, the chip substrate 1 formed by the semiconductor process is adapted to carry a wafer 21A. In detail, in the subsequent process of the 夕 基板 substrate, please refer to FIG. 2A. First, at least one wafer 21 〇 (only schematically shown in FIG. 2A; two) is shown in the stepped structure 140. Within the two recesses 144, the upper surface 210a of the wafers 210 are respectively lower than the second metal layers 194 of the circuit layers 190 located in the first recesses 142. Referring to Figure 2B, next, a wire bonding process is performed to connect these 201021137 50twfH 7 > / 50twf.doc/n wafers 210 through a plurality of wires 22 to the second layer 194 of the wiring layer 19A. That is, in the present embodiment, these wafers. Eight through the wires 220 are connected to the second gold of the circuit layer 19〇. (7) 4 power Please refer to Fig. 2c' to subsequently fill in the sealed 2sg structure 140' wherein the encapsulant 23() covers the wiring layer 19, the metal species 170, the final insulating layer 160, the wafer 21 and the wires 22A. Referring to FIG. 2D, the portion of the I-colloid 230 and the portion of the wiring layer are thinned to substantially seal the sealing paste 230 with the first metal layer 192. The method of thinning the encapsulant 230 and the wiring layer 190 in this embodiment includes grinding. Please refer to FIG. 2E'. Next, the back surface of the germanium substrate is thinned to expose the lower surface of the wafer 210 to achieve the thinning requirements of the package, wherein the method of thinning the substrate 11 includes grinding or Etching process. Referring to FIG. 2F, at least one metal pad 24A (FIG. 2F is only shown in FIG. 2F) is formed on the first metal layer 192 of the circuit layer 190, and is exposed to the outside of the encapsulant 230. The square of these metal pads 24 is, for example, electr〇less plating. In this embodiment, each metal pad 240 has a thickness of approximately 微米j microns (#1). Please refer to FIG. 2G and FIG. 2H at the same time. Thereafter, a cutting process is performed to separate the germanium substrate 100 by cutting the cutting tool along the predetermined path to form a plurality of independent wafer package structures 200 (FIG. 2G is only schematically continued). · Show two). In short, due to the process of the chip package structure of the present embodiment, the substrate 1 formed by the semiconductor process is used as the substrate 21, and the wafers 210 are respectively bonded by wire bonding. Electrically connected to the miscellaneous layer 190' on the 15/JOtwf.doc/n 201021137 and sealed this positive film 210 in the encapsulant 23〇 through the filling process to form these two (10) is the sub-reservoir The shape of the chip package structure has a thinner package. As described above, the semiconductor substrate formed by the semiconductor process of the present invention has a first-inferior read depth of the zen-like structure. The second recess of the two notches, and the aperture of the first recess is larger than the aperture of the second recess, so when the 曰曰=„ combination process is electrically connected to the 矽 substrate to form a wafer: 装: 善矽矽 substrate Simultaneous grinding with the back side of the wafer, the second = chip package structure can have a thin package thickness: Chemical: Invented 忐 Effectively reduce the package thickness. This has been implemented _ _ _ _ _ _ _ _ _ _ _ The towel has the usual knowledge, not leaving Within the scope of arsenic and within the scope of the invention, it is possible to make some changes and refinements. Therefore, the scope of the patent application scope of the patent application is subject to the definition of patent application. [Simplified illustration] 1 Α to Figure 1Ρ A cross-sectional view of a semiconductor manufacturing process according to an embodiment. A 曰, 2 Α to 2G is a cross-sectional view of a dicing substrate formed by a semiconductor process on a one-day slab. FIG. 2 is a wafer of FIG. 2G. Schematic diagram of the package structure. 16 201021137/50twfdoc/n [Major element companion' symbol description] 100: 矽 substrate 110: 矽 substrate 120: first insulating layer 120a · · patterned first insulating layer

130a :第一圖案化光阻罩幕 130b :第二圖案化光阻罩幕 142 :第一凹口 150 160 180 第二絕緣層 最終絕緣層 圖案化光阻層 150a 170 ： 140 :階梯狀結構 144 :第二凹口 圖案化第二絕緣層 金屬種子層 190 194 210 線路層 第二金屬層 晶片 210b :下表面 230 :封裝膠體 dl :第一深度 192 :第一金屬層 200 :晶片封裝結構 210a :上表面 220 :導線 240 :金屬接墊 d2 :第二深度130a: first patterned photoresist mask 130b: second patterned photoresist mask 142: first recess 150 160 180 second insulating layer final insulating layer patterned photoresist layer 150a 170: 140: stepped structure 144 : second notch patterned second insulating layer metal seed layer 190 194 210 wiring layer second metal layer wafer 210b: lower surface 230: encapsulant dl: first depth 192: first metal layer 200: wafer package structure 210a: Upper surface 220: wire 240: metal pad d2: second depth

1717

Claims (1)

201021137/50twfdoc/n 十、申請專利範圍： 1. 一種半導體製程，包括： 提供一矽基材； 局部暴露該矽基材的一表面，並蝕刻該矽基材的該表 面，以使該矽基材形成有至少一階梯狀結構，該階梯狀結 構具有一第一深度的一第一凹口以及一第二深度的一第二 凹口，5亥弟一深度小於該第二深度，且該第一凹口的孔徑 大於该弟二凹口的孔徑； ® 域-最終絕緣層於該階梯狀結構以及形成一金屬 種子層於該最終絕緣層上； ，形成一圖案化光阻層於該金屬種子層上，其中該圖案 化光阻層復蓋預疋形成一線路層之外的部份該金屬種子 層，亚顯露預定形成該線路層的部份該金屬種子層； 形成該線路層，覆蓋顯露的部份該金屬種子層上；以 及 移除戎圖案化光阻層以及位於該圖案化光阻層底下 參 之部份該金屬種子層。 、2.如申請專利範圍第1項所述之半導體製程，其中形 成該階梯狀結構的步驟，包括： 形成一第一絕緣層於該矽基材上； 形成一第一圖案化光阻罩幕於該第一絕緣層； 以該第-圖案化光阻罩幕為餘刻罩幕，钱刻暴露於該 第一圖案化光阻罩幕之外的該第一絕緣層； 移除該第一圖案化光阻罩幕； 18 f50twf.doc/n 201021137 以圖案化該第-絕緣層為侧罩幕， 化該第一絕緣層的該石夕基材，以於_基材上 深度的該第一凹口； 弟 移除該第一絕緣層； 一形成一第二絕緣層於該第一凹口，其中該第二 覆蓋該第一凹口； 一 形成一第二_化光阻罩幕於該第二絕緣層上. ❹ 第，幕為崎幕，“暴露於該 弟-圖案化先阻罩幕之外的該第二絕緣層； 移除該第二圖案化光阻罩幕； 以該圖案化的該第二絕緣層為钱 圖案化該第二絕緣芦的兮歆I从 平夺蚀幻暴路於 第二深度的該第==材’以w基材上形成該 移除該第二絕緣層，而形成該階梯狀結構。 笛一二專利範圍第2項所述之半導體製程，1中該 第一、、、巴緣層的材質包括氧化矽或氮化矽。 ’、^ 第-申清專利範圍第2項所述之半導體製程，其令該 第一、、、邑緣層的材質包括氧化矽或氧化矽。 βΛ 姐申請專利範圍第1項所述之半導體製程，盆中今 包括一第一金屬層與—第二金屬層，該第一金 第一凹口上方的部份該金屬種子層上，4 一金屬層覆蓋該第一金屬層。 °亥第 第L如^專利範圍第5項所述之半導體製程，並中， 第—金屬層為—鎳層’該第二金屬層為-金層。亥 19 50twf.doc/n 201021137 3 / 7.如申清專利範圍第.5項所述之半 ===於該嶋光阻層底二二移 於位=、二 表面低 進仃一打線接合製程，使該晶片透過多條導 該線路層⑽第二金屬層上； 深連接至 ❿ 填入封裝膝體於該階梯狀結構，其中該封裝牌 覆該最終絕緣層、線路層、該金屬種子層、該晶片^該些 導線； 一 薄化部份該封装膠體與部份該線路層，以使該封裝膠 體與該第一金屬層實質上切齊； 乂 薄化該矽基材及晶片，以暴露出該晶片的下表面；以 及 形成至少一金屬接墊於該線路層的該第一金屬層上。 8. 如申請專利範圍第7項所述之半導體製程，^中詼 ❹ 接墊的材質包括金。 、^ 9. 如申請專利範圍第丨項所述之半導體製程，复 最終絕緣層的材質包括氧化， 、中該 ,1〇.如申請專利範圍第1項所述之半導體製程，其中 形成該金屬種子層的方法包括物理氣相沉積。 H.如申請專利範圍第丨項所述之半導體製程’其中 該金屬種子層為一鈇鎳複合層。 12.—種以申請專利範圍第丨項所述之半導體製程所 20 201021137 50twf.doc/n 形成的梦基板’其中該悬玖绍绝&amp; β 綠也當 ^取、〜、、邑緣層覆蓋該階梯狀結構，該 口用以放置一晶片 線Ϊ層覆ί_ΐα上方的部份該導電層，麟第二凹 13. 曰曰 1•如申請專利範圍第12項所述 片透過多條導線而電性連接至該線路層。彳-中該 14. 一種晶片封裴結構，包括：201021137/50twfdoc/n X. Patent Application Range: 1. A semiconductor process comprising: providing a substrate; partially exposing a surface of the substrate and etching the surface of the substrate to make the substrate The material is formed with at least one stepped structure having a first recess of a first depth and a second recess of a second depth, wherein the depth is less than the second depth, and the a notch having a larger aperture than the second notch; a domain - a final insulating layer on the stepped structure and forming a metal seed layer on the final insulating layer; forming a patterned photoresist layer on the metal seed a layer, wherein the patterned photoresist layer covers a portion of the metal seed layer formed outside the circuit layer, and a portion of the metal seed layer is formed to form a portion of the circuit layer; forming the circuit layer, covering the exposed layer a portion of the metal seed layer; and removing the germanium patterned photoresist layer and a portion of the metal seed layer located under the patterned photoresist layer. 2. The semiconductor process of claim 1, wherein the step of forming the stepped structure comprises: forming a first insulating layer on the germanium substrate; forming a first patterned photoresist mask The first insulating layer; the first patterned photoresist mask is a residual mask, and the first insulating layer is exposed outside the first patterned photoresist mask; Patterned photoresist mask; 18 f50twf.doc/n 201021137 to pattern the first insulating layer as a side mask, and to etch the first insulating layer of the first insulating layer to the depth of the substrate a recess; the first insulating layer is removed; a second insulating layer is formed on the first recess, wherein the second covers the first recess; and a second photoresist is formed on the mask On the second insulating layer, ❹, the curtain is a nasa, "exposed to the second insulating layer outside the patterned-first mask; removing the second patterned photoresist mask; The patterned second insulating layer is a pattern of the second insulating reed of the second insulating reed The first =, the material is formed on the w substrate to remove the second insulating layer to form the stepped structure. The semiconductor process described in the second paragraph of the flute patent, the first, The material of the rim layer includes yttrium oxide or tantalum nitride. ', ^ The semiconductor process described in the second paragraph of the patent scope of the present invention, which makes the material of the first, and rim layer include ruthenium oxide or ruthenium oxide. The semiconductor process described in the first aspect of the patent application, the basin includes a first metal layer and a second metal layer, and the portion above the first gold first recess is on the metal seed layer, 4 A metal layer covers the first metal layer. The method of claim 5, wherein the first metal layer is a nickel layer.亥 19 50twf.doc/n 201021137 3 / 7. If the application of the patent scope of the fifth paragraph of the scope of the fifth paragraph === at the bottom of the 嶋 photoresist layer 22 moved to the position =, two surface low into the first line of wire bonding a process of passing the wafer through a plurality of layers of the second metal layer of the wiring layer (10); deep connection to the 膝 filling the package knee body The stepped structure, wherein the package card covers the final insulating layer, the circuit layer, the metal seed layer, the wire, and the thinned portion of the encapsulant and a portion of the circuit layer to make the encapsulant Substantially aligned with the first metal layer; thinning the germanium substrate and the wafer to expose the lower surface of the wafer; and forming at least one metal pad on the first metal layer of the wiring layer. In the semiconductor process described in claim 7, the material of the 诙❹ 接 pad includes gold. 。 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. 9. The semiconductor process of claim 1, wherein the method of forming the metal seed layer comprises physical vapor deposition. H. The semiconductor process of claim </RTI> wherein the metal seed layer is a nickel-nickel composite layer. 12. A kind of dream substrate formed by the semiconductor process institute 20 201021137 50twf.doc/n described in the scope of the patent application scope, wherein the suspension is removed and the β green is also taken, the ~, and the edge layer Covering the stepped structure, the port is used for placing a portion of the conductive layer above the lining layer of the wafer, and the second recess is 13. 曰曰1• The film is permeable to the plurality of wires according to the scope of claim 12 It is electrically connected to the circuit layer.彳-中中 14. A wafer sealing structure comprising: 一矽基材，具有—階梯狀結構，該階梯狀結構具有一 第-深度的-第—凹口以及一第二深度的一第二凹口，該 第-冰度小於該第二深度，且該第―凹口的孔徑大於該第 二凹口的孔徑； 一絕緣層，配置於該矽基材上，且覆蓋該第一凹口與 該第二凹口； 一金屬種子層，覆蓋位於該第一凹口上方的該絕緣 層； 一線路層，覆蓋位於該第一凹口上方的該金屬種子 層； 一晶片，配置於該第二凹口内，其中該晶片的上表面 低於該線路層，且該晶片透過多條導線與該線路層電性連 接； 一封裝膠體，包覆該絕緣層、該金屬種子層、該線路 層、該晶片以及該些導線，其中該封裝膠體與該線路層實 質上切齊；以及 至少一金屬接墊，配置於該線路層上，並顯露於該封 裝膠體外。 21 201021137 50twf.d〇c/n 15. 如中請相範_ 14顧述之_晶 中該絕緣層的材質包括氧化石夕。 衣〜構’其 16. 如申請專利範圍第14項所述之晶 中該金屬種子層為一鈦鎳複合層。 衣〜構，其 17. 如申請專利範圍第14項所述之晶片封裝社 中該線路層包括一第—金屬層與一第二金屬層，議3 ，其 屬層覆蓋該金屬種子層，而該第二金屬層覆蓋^〜金 層。 μ眾—金屬a substrate having a stepped structure having a first-depth-first recess and a second recess having a second depth, the first ice is less than the second depth, and The first recess has a larger aperture than the second recess; an insulating layer disposed on the base material and covering the first recess and the second recess; a metal seed layer covering the The insulating layer above the first recess; a wiring layer covering the metal seed layer above the first recess; a wafer disposed in the second recess, wherein an upper surface of the wafer is lower than the circuit layer And the chip is electrically connected to the circuit layer through a plurality of wires; an encapsulant covering the insulating layer, the metal seed layer, the circuit layer, the wafer and the wires, wherein the encapsulant and the circuit layer Substantially aligned; and at least one metal pad disposed on the circuit layer and exposed outside the encapsulant. 21 201021137 50twf.d〇c/n 15. If you are in the same state _ 14 Gu Shuzhi _ crystal The material of the insulation layer includes oxidized stone eve. The coating of the metal seed layer is a titanium-nickel composite layer as described in claim 14 of the patent application. 17. The wafer package according to claim 14, wherein the circuit layer comprises a first metal layer and a second metal layer, and the genus layer covers the metal seed layer, and The second metal layer covers the gold layer. μ public - metal 18.如申請專利範圍第17項所述之晶片封裝結 中該第一金屬層為一鎳層，該第二金屬層為—金、層°。構’其 19·如申請專利範圍第14項所述之晶片封事^ 中該金屬接墊的材質包括金。 冓，其18. The wafer package according to claim 17, wherein the first metal layer is a nickel layer, and the second metal layer is - gold, layer. The material of the metal pad in the wafer sealing device described in claim 14 includes gold. Oh, its 22twenty two