201014488 九、發明說明： 【發明所屬之技術領域】 本發明關於一種電路板，特別關於一種多層電路板 【先前技術】 印刷電路板（Printed Circuit Board)為搭栽電子元件 並連通電路之載板，以提供一個安穩的電敗 ^ ^ 叫工作環境。而201014488 IX. Description of the Invention: [Technical Field] The present invention relates to a circuit board, and more particularly to a multilayer circuit board. [Prior Art] A Printed Circuit Board is a carrier board for arranging electronic components and connecting the circuits. To provide a stable electrical defeat ^ ^ called the working environment. and
依電路配置的型態可概分為單面板、雙面板及多層板 中，多層板為在較複雜的應用需求時，番放°其 兒塔可以被佛戶^袁 多層的結構並疊合在一起’並在層間佈建通孔電路連通各 層電路。 請參照圖1所示’習知的一種多層電路板丨包含複數 電路層111〜114及複數絕緣層12。電袼層ηι〜114與絕 緣層12交錯相疊設置。於此’電路層Hi〜114分別為一 訊號層、一接地層、一電源層及另一訊號層。電路層111 及電路層114可設置電子元件及訊號走線，電路層112可 ❹提供接地訊號，電路層Π3可提供電源訊號。其中，電路 層111及電路層114為多層電路板1之外層線路，電路層 112及電路層113則為内層線路。 如圖1所示’靜電防護單元13設置於電路層111以將 電路之突波雜訊導出而達到保護電子元件之功效。然而， - 由於靜電防護單元13及其餘的電路層111〜114皆具有金 屬材質，以致靜電防護單元13與電路層111〜114之間產 生寄生電容效應，進而造成例如阻抗不匹配及高頻信號的 201014488 反射問題，而無法通過產品認證。且隨著產品薄型化的市 場趨勢，多層電路板1的厚度越來越小，造成寄生電容效 應越來越大，所產生的問題也越嚴重。而習知技術為解決 此問題可選用昂貴、低容值的靜電防護元件，或是將此寄 生電容考慮至電路設置内，然而這樣會增加成本及電路設 ' 計的複雜度。 因此，如何提供一種多層電路板及其製造方法，可降 低靜電防護單元與金屬層間之寄生電容效應，使電路元件 ❹ 通過認證，且不需使用高單價之靜電防護元件或考慮電路 設計以減低生產成本。 【發明内容】 有鑑於上述課題，本發明之目的為提供一種多層電路 板及其製造方法，可降低靜電防護單元與金屬層間之寄生 電容效應，使電路元件通過認證，並減低生產成本。 為達上述目的，依據本發明之一種多層電路板包含複 ❿ 數電路層、複數絕緣層以及一靜電防護單元。該等絕緣層 與該等電路層交錯相疊設置。靜電防護單元係設置於該等 電路層之一。其中，與設置靜電防護單元之電路層相鄰的 至少一電路層具有一非金屬區，非金屬區與靜電防護單元 相對設置。 為達上述目的，依據本發明之一種多層電路板之製造 方法，該多層電路板包含複數電路層、複數絕緣層及一靜 電防護單元，該等絕緣層與該等電路層交錯相疊設置，靜 201014488 電防護單元係設置於該等電路層之一，製造方法的技術特 徵在於：在與設置靜電防護單元之電路層相鄰的至少一電 路層形成一非金屬區，且非金屬區與靜電防護單元相對設 置。 承上所述，依據本發明之一種多層電路板及其製造方 ' 法，藉由在與設置靜電防護單元之電路層相鄰的電路層設 置一非金屬區，且非金屬區與靜電防護單元相對設置，進 而增加靜電防護單元與相對設置之金屬之間的距離，甚至 ❹ 靜電防護單元不與任何金屬相對設置，使得寄生電容效應 大幅減低，進而解決高頻元件阻抗不匹配而影響高頻信號 反射之問題，且不需使用習知之低容值而高單價之靜電防 護元件及考慮電路設計以減低生產成本。 【實施方式】 以下將參照相關圖式，說明依本發明較佳實施例之多 層電路板及其製造方法，其中相同的元件將以相同的參照 ❹符號加以說明。 第一實施例 請參照圖2所示，本發明第一實施例之多層電路板2 .包含複數電路層211〜214、複數絕緣層22以及至少一靜 電防護單元23。於本實施例中，多層電路板2係以四層電 路層211〜214、四層絕緣層22及二個靜電防護單元為例； 當然，多層電路板2可因不同需求，而設計為其他數量的 電路層及絕緣層，例如二層疊層、六層疊層或八層疊層 201014488 等。在本實施例中’多層電路板2之厚度係小於2釐米。 電路層211〜214與絕緣層22交錯相疊。在本實施例 中，電路層211〜214分別以一訊號層、一接地層、一電 源層及另一訊號層為例。其中’電路層211及電路層214 為多層電路板2之外層電路’可設置電子元件（例如晶片、 . 主動元件及被動元件等）及訊號走線。電路層212及電路 層213則為多層電路板2之内層電路，其中電路層212可 提供一接地訊號，電路層213可提供一電源訊號。當然， 〇 電路層211〜214之佈局位置亦可因電路板需求而變更設 計，例如電路層211〜214皆為訊號層，或接地層及電源 層的位置變更。 在本實施例中’絕緣層22可包含一絕緣基板或一介 電層，並設置於該等電路層211〜214之間以形成電性隔 離。 靜電防護單元23係設置於該等電路層211〜214之 一，本實施例係例如將靜電防護單元23設置於電路層 ❹ 211。靜電防護單元23用以將電路之突波雜訊導出而達到 保護電子元件（例如晶片）之功效。在本實施例中’靜電 防護單元23可包含一齊納二極體、一壓敏電阻 (VARISTOR )或一瞬態電壓抑制二極體（Transient Voltage Suppressor, TVS) 0 " 需注意的是，與設置靜電防護單元23之電路層211 相鄰的至少一電路層具有一非金屬區A1，且非金屬區A1 與靜電防護單元23相對設置。更詳細的說，非金屬區A1 201014488 與靜電防護單元23之投影位置重疊，本實施例以電路層 212具有非金屬區A1為例說明，當然，電路層213及214 皆可具有非金屬區A卜電路層212具有非金屬區A1係指 電路層在非金屬區A1的範圍内不具有金屬或導電物質。 在本實施例中，非金屬區A1之形狀與靜電防護單元23之 ' 形狀實質上相等。 另外，靜電防護單元23可與電路層212 (以接地層為 例）電性連接。如此一來，靜電防護單元23不僅可利用 ❹ 電路層212上的非金屬區A1而降低靜電防護單元23與其 他電路層的寄生電容效應，更可將雜訊突波導地。 第二實施例 請參照圖3所示，本發明第二實施例之多層電路板3 包含複數電路層311〜314、複數絕緣層32以及複數靜電 防護單元33。該等絕緣層32與該等電路層311〜314交錯 相疊設置。本實施例之電路層311〜314之層數與佈局及 靜電防護單元33之構成與上述第一實施例之電路層211 ® 〜214及靜電防護單元23等同，於此不再贅述。 於本實施例中，靜電防護單元33包含一靜電防護元 件331及複數個連接墊332，且靜電防護元件331電性連 結於該等連接墊332，並經由連接墊332與電路層311電 性連接。電路層312具有一非金屬區A2，非金屬區A2與 靜電防護元件331相對、重疊設置，且其形狀與靜電防護 單元33的靜電防護元件331實質相同。於此是以電路層 312具有非金屬區A2為例；當然，電路層313及314亦可 201014488 具有非金屬區，以降低靜電防護單元33與其他電路層的 寄生電容效應。 第三實施例 請參照圖4所示，本發明第三實施例之多層電路板4 包含複數電路層411〜414、複數絕緣層42以及複數靜電防 護單元43。電路層411〜414與該等絕緣層42交錯相疊。 本實施例之電路層411〜414之層數與佈局及靜電防護單 元43之構成與上述第一實施例之電路層211〜214及靜電 ❿ 防護單元23等同，於此不再贅述。 於本實施例中，屬於内層佈局之電路層412及電路層 413分別具有一非金屬區A3及一非金屬區B3。需注意的 是，非金屬區A3及非金屬區B3與連接墊432相對、重疊 設置，且非金屬區A3及非金屬區B3之形狀與靜電防護單 元43的連接墊432實質相同。於此是以電路層412及413 具有非金屬區A3及B3為例；當然，電路層414亦可具有 非金屬區，以降低靜電防護單元43與其他電路層的寄生 ®電容效應。 本發明之較佳實施例之一種多層電路板之製造方 法，用以製造一多層電路板，多層電路板包含複數電路 層、複數絕緣層及一靜電防護單元，該等絕緣層與該等電 路層交錯相疊設置，靜電防護單元係設置於該等電路層之 一。多層電路板之製造方法的特徵在於：在與設置靜電防 護單元之電路層相鄰的至少一電路層形成一非金屬區，且 非金屬區與靜電防護單元對應設置。於此，多層電路板例 201014488 如是上述實施例之多層電路板2〜4其中之一，或其組合。 由於多層電路板的結構已詳述於上述實施例，故於此不再 贅述。 以下舉例說明如何形成非金屬區。非金屬區可藉由減 去法（subtractive method )形成，所謂減去法即在原有的 ‘ 電路層上將部分金屬（例如銅）去除以形成非金屬區。減 去法包含光阻蝕刻製程、絲網印刷製程或刻印製程。 光阻蝕刻製程以一光阻密合貼附電路層上，經過紫外 〇 線曝光，而將膠片上的線路圖案移轉到光阻上。然後進行 顯影以將光阻未受光照的部分（即非金屬區的區域）去 除，再進行一蝕刻步驟以將裸露出來的電路層腐蝕去除而 形成非金屬區。當然，膠片上的線路圖案需依據非金屬區 的位置及形狀作設計，以致非金屬區能夠相對靜電防護單 元設置。 絲網印刷製程為把預先設計好的電路圖案製成遮 罩，放到電路層上面，並於絲網塗覆保護劑，把電路板放 ❿ 到腐蝕液中，沒有被保護劑遮住的部份（非金屬區的區域） 便會被飩走，最後把保護劑清理。上述遮罩亦可用電路圖 案化後的膠片代替。 刻印製程為利用銑床或雷射彫刻機直接把電路層圖 案不需要的部份除去，以形成非金屬區。 ' 綜上所述，依據本發明之一種多層電路板及其製造方 法，藉由在與設置靜電防護單元之電路層相鄰的電路層設 置一非金屬區，且非金屬區與靜電防護單元相對設置，進 11 201014488 而增加靜電防護單元與相對設置之金屬之間的距離，甚至 靜電防護單元不與任何金屬相對設置，使得寄生電容效應 大幅減低，進而解決高頻元件阻抗不匹配而影響高頻信號 反射之問題，且不需使用習知之低容值而高單價之靜電防 護元件及考慮電路設計以減低生產成本。 ‘ 以上所述僅為舉例性，而非為限制性者。任何未脫離 本發明之精神與範疇，而對其進行之等效修改或變更，均 應包含於後附之申請專利範圍中。 〇 【圖式簡單說明】 圖1為一種習知之多層電路板的示意圖； 圖2為依據本發明第一實施例之多層電路板的示意 圖； 圖3為依據本發明第二實施例之多層電路板的示意 圖；以及 圖4為依據本發明第三實施例之多層電路板的示意 ❹圖。 【主要元件符號說明】 1〜4 :多層電路板 111〜114、211 〜214、311 〜314、411 〜414 :電路層 12、 22、32、42 :絕緣層 13、 23、33、43 :靜電防護單元 331、431 :靜電防護元件 12 201014488 332、432 :連接墊According to the configuration of the circuit, it can be divided into single-panel, double-panel and multi-layer boards. When the multi-layer board is needed in more complicated applications, the tower can be stacked by the Buddha multi-layer structure. Together, a through-hole circuit is connected between the layers to connect the circuits of the layers. Referring to Fig. 1, a conventional multilayer circuit board includes a plurality of circuit layers 111 to 114 and a plurality of insulating layers 12. The electrode layers ηι to 114 are arranged in a staggered manner with the insulating layer 12. The circuit layers Hi to 114 are respectively a signal layer, a ground layer, a power supply layer and another signal layer. The circuit layer 111 and the circuit layer 114 can be provided with electronic components and signal traces, the circuit layer 112 can provide a ground signal, and the circuit layer 3 can provide a power signal. The circuit layer 111 and the circuit layer 114 are the outer layer circuits of the multilayer circuit board 1, and the circuit layer 112 and the circuit layer 113 are the inner layer lines. As shown in Fig. 1, the ESD protection unit 13 is disposed on the circuit layer 111 to derive the surge noise of the circuit to protect the electronic components. However, since the ESD protection unit 13 and the remaining circuit layers 111 to 114 are all made of a metal material, a parasitic capacitance effect is generated between the ESD protection unit 13 and the circuit layers 111 to 114, thereby causing, for example, impedance mismatch and high frequency signals. 201014488 Reflection problem, but cannot pass product certification. With the market trend of thin products, the thickness of the multilayer circuit board 1 is getting smaller and smaller, causing the parasitic capacitance effect to become larger and larger, and the problems generated are more serious. In order to solve this problem, conventional techniques may use expensive, low-capacity ESD protection components or consider the parasitic capacitance into the circuit arrangement. However, this increases the cost and complexity of the circuit design. Therefore, how to provide a multilayer circuit board and a manufacturing method thereof can reduce the parasitic capacitance effect between the ESD protection unit and the metal layer, enable the circuit component to pass the certification, and do not need to use a high unit price of the ESD protection component or consider the circuit design to reduce the production. cost. SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a multilayer circuit board and a method of manufacturing the same, which can reduce the parasitic capacitance effect between the ESD protection unit and the metal layer, pass the circuit component certification, and reduce the production cost. To achieve the above object, a multilayer circuit board according to the present invention comprises a plurality of circuit layers, a plurality of insulating layers, and an electrostatic protection unit. The insulating layers are interleaved with the circuit layers. The ESD protection unit is disposed in one of the circuit layers. Wherein, at least one circuit layer adjacent to the circuit layer on which the electrostatic protection unit is disposed has a non-metal region, and the non-metal region is disposed opposite to the static electricity protection unit. In order to achieve the above object, in accordance with the method for fabricating a multilayer circuit board of the present invention, the multilayer circuit board includes a plurality of circuit layers, a plurality of insulating layers, and an electrostatic protection unit, and the insulating layers are interleaved with the circuit layers to form a static 201014488 The electric protection unit is disposed in one of the circuit layers, and the manufacturing method is characterized in that a non-metal area is formed on at least one circuit layer adjacent to the circuit layer on which the electrostatic protection unit is disposed, and the non-metal area and the static electricity protection Unit relative settings. According to the present invention, a multilayer circuit board and a method of manufacturing the same according to the present invention provide a non-metallic region and a non-metal region and an electrostatic protection unit by a circuit layer adjacent to a circuit layer on which the electrostatic protection unit is disposed. The relative arrangement increases the distance between the ESD protection unit and the oppositely disposed metal, and even the ESD protection unit is not disposed opposite any metal, so that the parasitic capacitance effect is greatly reduced, thereby solving the high frequency component impedance mismatch and affecting the high frequency signal. The problem of reflection, and the need to use conventional low capacitance values and high unit price of ESD components and consideration of circuit design to reduce production costs. [Embodiment] Hereinafter, a multi-layer circuit board and a method of manufacturing the same according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings, wherein the same elements will be described with the same reference numerals. First Embodiment Referring to Figure 2, a multilayer circuit board 2 according to a first embodiment of the present invention includes a plurality of circuit layers 211 to 214, a plurality of insulating layers 22, and at least one static electricity protection unit 23. In this embodiment, the multi-layer circuit board 2 is exemplified by four circuit layers 211 to 214, four insulating layers 22, and two electrostatic protection units. Of course, the multilayer circuit board 2 can be designed as other quantities according to different requirements. The circuit layer and the insulating layer, for example, a two-layer layer, a six-layer layer or an eight-layer layer 201014488. In the present embodiment, the thickness of the multilayer circuit board 2 is less than 2 cm. The circuit layers 211 to 214 are alternately stacked with the insulating layer 22. In this embodiment, the circuit layers 211 to 214 are respectively exemplified by a signal layer, a ground layer, a power source layer and another signal layer. The circuit layer 211 and the circuit layer 214 are the outer layer circuits of the multilayer circuit board 2, and electronic components (for example, wafers, active components, passive components, etc.) and signal traces can be disposed. The circuit layer 212 and the circuit layer 213 are the inner layer circuits of the multilayer circuit board 2. The circuit layer 212 can provide a ground signal, and the circuit layer 213 can provide a power signal. Of course, the layout positions of the circuit layers 211 to 214 may also be changed according to the requirements of the circuit board. For example, the circuit layers 211 to 214 are all signal layers, or the ground layer and the power layer are changed in position. In the present embodiment, the insulating layer 22 may include an insulating substrate or a dielectric layer and is disposed between the circuit layers 211 to 214 to form an electrical isolation. The electrostatic protection unit 23 is disposed in one of the circuit layers 211 to 214. In this embodiment, for example, the electrostatic protection unit 23 is disposed on the circuit layer 211. The electrostatic protection unit 23 is used to derive the surge noise of the circuit to protect the electronic components (such as a wafer). In this embodiment, the 'electrostatic protection unit 23 may include a Zener diode, a varistor (VARISTOR) or a Transient Voltage Suppressor (TVS) 0 " Note that, and settings At least one circuit layer adjacent to the circuit layer 211 of the ESD protection unit 23 has a non-metal region A1, and the non-metal region A1 is disposed opposite to the ESD protection unit 23. In more detail, the non-metallic area A1 201014488 overlaps with the projection position of the electrostatic protection unit 23. In this embodiment, the circuit layer 212 has a non-metal area A1 as an example. Of course, the circuit layers 213 and 214 may have a non-metal area A. The circuit layer 212 having the non-metal region A1 means that the circuit layer does not have a metal or a conductive substance in the range of the non-metal region A1. In the present embodiment, the shape of the non-metallic region A1 is substantially equal to the shape of the electrostatic protection unit 23. In addition, the ESD protection unit 23 can be electrically connected to the circuit layer 212 (which is exemplified by a ground layer). In this way, the ESD protection unit 23 can reduce the parasitic capacitance effect of the ESD protection unit 23 and other circuit layers by using the non-metal area A1 on the 电路 circuit layer 212, and can also transmit the noise. SECOND EMBODIMENT Referring to Fig. 3, a multilayer circuit board 3 according to a second embodiment of the present invention includes a plurality of circuit layers 311 to 314, a plurality of insulating layers 32, and a plurality of electrostatic protection units 33. The insulating layers 32 are arranged in a staggered manner with the circuit layers 311 to 314. The number of layers and layout of the circuit layers 311 to 314 of the present embodiment and the configuration of the electrostatic protection unit 33 are the same as those of the circuit layers 211 to 214 and the electrostatic protection unit 23 of the first embodiment, and will not be described again. In the present embodiment, the ESD protection unit 33 includes an ESD protection component 331 and a plurality of connection pads 332. The ESD protection component 331 is electrically connected to the connection pads 332 and electrically connected to the circuit layer 311 via the connection pads 332. . The circuit layer 312 has a non-metallic region A2 which is disposed opposite to the electrostatic protection element 331 and which is substantially identical in shape to the electrostatic protection element 331 of the electrostatic protection unit 33. Here, the circuit layer 312 has a non-metal region A2 as an example; of course, the circuit layers 313 and 314 may also have a non-metal region 201014488 to reduce the parasitic capacitance effect of the ESD protection unit 33 and other circuit layers. THIRD EMBODIMENT Referring to Fig. 4, a multilayer circuit board 4 according to a third embodiment of the present invention includes a plurality of circuit layers 411 to 414, a plurality of insulating layers 42, and a plurality of electrostatic protection units 43. The circuit layers 411 to 414 are alternately stacked with the insulating layers 42. The number of layers and layout of the circuit layers 411 to 414 of the present embodiment and the configuration of the electrostatic protection unit 43 are the same as those of the circuit layers 211 to 214 and the electrostatic protection unit 23 of the first embodiment, and will not be described again. In this embodiment, the circuit layer 412 and the circuit layer 413 belonging to the inner layer layout respectively have a non-metal region A3 and a non-metal region B3. It should be noted that the non-metal region A3 and the non-metal region B3 are opposite to and overlap with the connection pad 432, and the shapes of the non-metal region A3 and the non-metal region B3 are substantially the same as the connection pads 432 of the static electricity protection unit 43. Here, the circuit layers 412 and 413 have non-metal regions A3 and B3 as an example; of course, the circuit layer 414 may also have a non-metal region to reduce the parasitic capacitance effect of the electrostatic protection unit 43 and other circuit layers. A method of fabricating a multilayer circuit board for manufacturing a multilayer circuit board comprising a plurality of circuit layers, a plurality of insulating layers, and an electrostatic protection unit, the insulating layers and the circuits The layers are staggered and stacked, and the electrostatic protection unit is disposed in one of the circuit layers. The method of manufacturing a multilayer circuit board is characterized in that a non-metal region is formed in at least one circuit layer adjacent to a circuit layer on which the electrostatic protection unit is disposed, and the non-metal region is disposed corresponding to the electrostatic protection unit. Here, the multilayer circuit board example 201014488 is one of the multilayer circuit boards 2 to 4 of the above embodiment, or a combination thereof. Since the structure of the multilayer circuit board has been described in detail in the above embodiments, it will not be described again. The following examples illustrate how to form a non-metallic zone. The non-metallic regions can be formed by a subtractive method that removes a portion of the metal (e.g., copper) on the original 'circuit layer to form a non-metallic region. The subtractive method includes a photoresist etching process, a screen printing process, or an imprint process. The photoresist etch process is adhered to the circuit layer by a photoresist, exposed to the ultraviolet ray line, and the line pattern on the film is transferred to the photoresist. Development is then carried out to remove the unexposed portion of the photoresist (i.e., the region of the non-metallic region), and an etching step is performed to etch away the exposed circuit layer to form a non-metallic region. Of course, the line pattern on the film needs to be designed according to the position and shape of the non-metallic area, so that the non-metal area can be set relative to the electrostatic protection unit. The screen printing process is to make a pre-designed circuit pattern into a mask, put it on the circuit layer, and apply a protective agent on the screen, and put the circuit board into the corrosive liquid, without being covered by the protective agent. Parts (areas of non-metallic areas) will be taken away and the protective agent will be cleaned up. The mask can also be replaced by a circuit patterned film. The imprinting process removes portions of the circuit layer pattern that are not required by a milling machine or a laser engraving machine to form a non-metallic region. In summary, a multilayer circuit board and a method of fabricating the same according to the present invention provide a non-metallic region by a circuit layer adjacent to a circuit layer on which the electrostatic protection unit is disposed, and the non-metal region is opposite to the electrostatic protection unit Set, enter 11 201014488 and increase the distance between the ESD protection unit and the oppositely disposed metal. Even the ESD protection unit is not placed opposite to any metal, so that the parasitic capacitance effect is greatly reduced, thereby solving the high frequency component impedance mismatch and affecting the high frequency. The problem of signal reflection, and the need to use conventional low capacitance values and high unit price of ESD components and consideration of circuit design to reduce production costs. The above description is for illustrative purposes only and is not a limitation. Any equivalent modifications or alterations to the spirit and scope of the present invention are intended to be included in the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view of a conventional multilayer circuit board; FIG. 2 is a schematic view of a multilayer circuit board according to a first embodiment of the present invention; FIG. 3 is a multilayer circuit board according to a second embodiment of the present invention. FIG. 4 is a schematic diagram of a multilayer circuit board in accordance with a third embodiment of the present invention. [Description of main component symbols] 1 to 4: multilayer circuit boards 111 to 114, 211 to 214, 311 to 314, 411 to 414: circuit layers 12, 22, 32, 42: insulating layers 13, 23, 33, 43: static electricity Protection unit 331, 431: electrostatic protection element 12 201014488 332, 432: connection pad
Al、A2、A3、B3 :非金屬區Al, A2, A3, B3: non-metallic zone
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